Formation method of semiconductor structure
By heat treatment and cleaning the surface of the fin, the gap problem caused by the adhesion of water molecular clusters is solved, and the performance and reliability of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202410111514.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-25
- Publication Date
- 2025-07-29
AI Technical Summary
In semiconductor processes, Si-H chemical bonds formed on the surface of the fin easily lead to adhesion of water molecular groups after cleaning, increasing the risk of gaps between the gate structure and the surface of the fin, and affecting the performance of the semiconductor structure.
The first heat treatment is performed on the surface of the fin to release the adsorbed H bond, followed by a cleaning treatment to reduce the probability of water molecular clusters adhesion, and the remaining water molecular clusters are further consumed through the second heat treatment, ensuring that the surface of the fin remains hydrophilic and reducing the risk of loosening the oxide layer and gaps.
The performance of the semiconductor structure is improved, the gap risk between the gate structure and the fin surface is reduced, and the reliability and yield of the device is enhanced.
Smart Images
Figure CN120390415A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art
[0002] With the gradual development of semiconductor process technology, semiconductor process nodes continue to decrease following Moore's Law. To adapt to the reduction of process nodes, it is necessary to continuously shorten the channel length of MOSFET field-effect transistors. However, as the device channel length is shortened, the distance between the source and drain of the device is also shortened, so the gate's control ability over the channel becomes worse, making the subthreshold leakage phenomenon, namely the so-called short-channel effects (SCE), more likely to occur.
[0003] Therefore, in order to better meet the requirements of device size scaling, non-planar MOS transistors have emerged, such as gate-all-around (GAA) transistors or fin field-effect transistors (FinFETs). In FinFETs, the gate can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFET devices, the gate has stronger control ability over the channel and can well suppress short-channel effects; and FinFETs have better compatibility with existing integrated circuit manufacturing compared with other devices. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improving the performance of the semiconductor structure.
[0005] To solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate, the substrate including a substrate and fins protruding from the substrate; performing a first heat treatment on the surface of the fins; after performing the first heat treatment, performing a cleaning treatment on the surface of the fins; after performing the cleaning treatment, forming a gate structure on the top of the substrate across the top and part of the sidewalls of the fins; forming source-drain doping layers in the substrate on both sides of the gate structure.
[0006] Optionally, the process of performing the first heat treatment on the surface of the fins includes a heating and drying process.
[0007] Optionally, the process parameters of performing the first heat treatment on the surface of the fins include: the heating temperature range is 100°C to 1000°C; the heating time range is 0.1 h to 5 h; the process gas includes one or both of N2 and He.
[0008] Optionally, the step of cleaning the surface of the fin portion includes: cleaning the surface of the fin portion; after performing the cleaning process, drying the surface of the fin portion.
[0009] Optionally, the process of cleaning the surface of the fin portion includes a wet cleaning process.
[0010] Optionally, the cleaning solution used in the wet cleaning process includes deionized water.
[0011] Optionally, the step of drying the surface of the fin portion includes: drying the surface of the fin portion using a desiccant.
[0012] Optionally, the desiccant includes isopropyl alcohol.
[0013] Optionally, after performing the cleaning process and before forming the gate structure, it further includes: performing a second heat treatment on the surface of the fin portion.
[0014] Optionally, the process of performing the second heat treatment on the surface of the fin portion includes a heat drying process.
[0015] Optionally, the process parameters of performing the second heat treatment on the surface of the fin portion include: the heating temperature range is 100°C to 200°C; the heating time range is 0.1 h to 1 h; the process gas includes one or both of N2 and He.
[0016] Optionally, the step of forming the gate structure includes: forming a gate oxide layer covering the sidewalls and the top of the fin portion on the top of the substrate; forming a gate layer across a part of the top and a part of the sidewalls of the fin portion on the top of the substrate, and the gate layer covers a part of the top and a part of the sidewalls of the gate oxide layer.
[0017] Optionally, after forming the source-drain doping layer, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer covering the sidewalls of the gate structure and the top of the source-drain doping layer on the top of the substrate; removing the gate structure and forming a gate opening in the interlayer dielectric layer; forming a device gate structure in the gate opening.
[0018] Optionally, the process of removing the gate structure includes a wet etching process.
[0019] Optionally, the etching solution used in the wet etching process includes tetramethylammonium hydroxide.
[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0021] An embodiment of the present invention provides a method for forming a semiconductor structure. A substrate is provided, which includes a substrate and fins protruding from the substrate. A first heat treatment is performed on the surface of the fins. After the first heat treatment, the surface of the fins is cleaned. Compared with the solution of directly cleaning the surface of the fins after forming the fins, in the embodiment of the present invention, before cleaning the surface of the fins, a first heat treatment is first performed on the surface of the fins to release the H bonds adsorbed on the surface of the fins, reduce the number of H bonds adsorbed on the surface of the fins, so that the surface of the fins can maintain hydrophilicity. During the subsequent cleaning process of the surface of the fins, the probability of water clusters adhering to the surface of the fins can be reduced. Correspondingly, the risk of a loose oxide layer appearing on the surface of the fins due to water clusters is also reduced. During the subsequent process of forming the gate structure, the risk of a gap appearing between the gate structure and the surface of the fins is reduced, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figures 1 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0023] Currently, during the process of forming the fins using a dry etching process, hydrogen fluoride (HF) reaction gas is used. After forming the fins, a large number of Si-H chemical bonds will be formed on the surface of the fins. Immediately afterwards, deionized water is used to clean the surface of the fins. After the cleaning process, the H bonds on the surface of the fins are likely to cause water clusters to appear on the surface of the fins. During the subsequent contact between the fins and the air environment, the risk of a loose oxide layer appearing on the surface of the fins due to water clusters is increased. During the subsequent process of forming the gate structure, the risk of a gap appearing between the gate structure and the surface of the fins is increased, thereby affecting the performance of the semiconductor structure.
[0024] To solve the technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, which includes a substrate and fins protruding from the substrate; performing a first heat treatment on the surface of the fins; after the first heat treatment, cleaning the surface of the fins; after the cleaning process, forming a gate structure across the top of a part of the fins and part of the sidewalls on the top of the substrate; forming source-drain doping layers in the substrate on both sides of the gate structure.
[0025] An embodiment of the present invention provides a method for forming a semiconductor structure. A substrate is provided, and the substrate includes a substrate and fins protruding from the substrate. The surface of the fins is subjected to a first heat treatment. After the first heat treatment, the surface of the fins is cleaned. Compared with the solution of directly cleaning the surface of the fins after forming the fins, in the embodiment of the present invention, before cleaning the surface of the fins, the surface of the fins is first subjected to a first heat treatment to release the H bonds adsorbed on the surface of the fins, reduce the number of H bonds adsorbed on the surface of the fins, so that the surface of the fins can maintain hydrophilicity. During the subsequent cleaning process of the surface of the fins, the probability of water clusters adhering to the surface of the fins can be reduced. Correspondingly, the risk of a loose oxide layer appearing on the surface of the fins due to water clusters is also reduced. During the subsequent process of forming the gate structure, the risk of a gap appearing between the gate structure and the surface of the fins is reduced, thereby improving the performance of the semiconductor structure.
[0026] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.
[0027] Among them, Figures 1 to 9 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
[0028] Refer to Figure 1 , a substrate 102 is provided, and the substrate 102 includes a substrate 100 and fins 101 protruding from the substrate 100.
[0029] The substrate 102 provides a process platform for the subsequent semiconductor structure formation process.
[0030] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0031] In this embodiment, the fins 101 are made of the same material as the substrate 100, and the material of the fins 101 is silicon. In other embodiments, the material of the fins can also be other semiconductor materials suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the material of the fins can also be different from the material of the substrate.
[0032] In this embodiment, the steps of forming the fin 101 include: providing a substrate material layer (not shown in the figure); forming a patterned mask layer (not shown in the figure) on the top of the substrate material layer; patterning a part of the thickness of the substrate material layer with the patterned mask layer as a mask, using the remaining thickness of the substrate material layer as the substrate 100, and using the remaining substrate material layer protruding from the top of the substrate 100 as the fin 101.
[0033] As an example, the process of patterning a part of the thickness of the substrate material layer with the patterned mask layer as a mask includes a dry etching process.
[0034] It should be noted that the dry etching process has a high pattern transfer accuracy, can improve the topography quality of the sidewalls of the fin 101, and reduces the process difficulty of depositing a gate oxide layer on the sidewalls of the fin 101 subsequently.
[0035] It should also be noted that after forming the fin 101, the method for forming the semiconductor structure further includes: forming an isolation layer (not shown in the figure) covering a part of the sidewalls of the fin 101 on the top of the substrate 100.
[0036] The isolation layer is used to electrically isolate adjacent devices.
[0037] As an example, the material of the isolation layer includes silicon oxide.
[0038] In this embodiment, the steps of forming the isolation layer include: forming an isolation material layer (not shown in the figure) on the top of the substrate 100, the isolation material layer covering the sidewalls of the fin 101; performing an etch-back process on the isolation material layer to remove a part of the thickness of the isolation material layer, and using the remaining isolation material layer as the isolation layer.
[0039] In this embodiment, the process of performing an etch-back process on the isolation material layer includes a dry etching process.
[0040] As an example, the etching gas used in the dry etching process includes HF (hydrogen fluoride).
[0041] It should be noted that after performing an etch-back process on the isolation material layer using the dry etching process, a large number of Si-H chemical bonds will be formed on the surface of the fin 101.
[0042] Refer to Figure 2 , and perform a first heat treatment 105 on the surface of the fin 101.
[0043] Specifically, a first heat treatment 105 is performed on the surface of the fin 101 to release the H bonds adsorbed on the surface of the fin 101, reducing the number of H bonds adsorbed on the surface of the fin 101, so that the surface of the fin 101 can maintain hydrophilicity. During the subsequent cleaning process of the surface of the fin 101, the probability of water clusters adhering to the surface of the fin 101 can be reduced. Correspondingly, the risk of a loose oxide layer appearing on the surface of the fin 101 due to water clusters is also reduced. During the subsequent formation process of the gate structure, the risk of a gap appearing between the gate structure and the surface of the fin 101 is reduced, thereby improving the performance of the semiconductor structure.
[0044] As an example, the process of performing the first heat treatment 105 on the surface of the fin 101 includes a heating and drying process.
[0045] The heating and drying process can consume the H bonds adsorbed on the surface of the fin 101, releasing the H bonds attached to the surface of the fin 101, so that the surface of the fin 101 can maintain hydrophilicity and keep the surface of the fin 101 dry. The probability of water clusters adhering to the surface of the fin 101 during the subsequent semiconductor structure formation process is reduced, thereby improving the performance of the semiconductor structure.
[0046] It should be noted that during the process of performing the first heat treatment 105 on the surface of the fin 101, the heating temperature range should not be too large or too small. If the heating temperature is too high, the residual ions on the surface of the fin 101 will diffuse, affecting the product yield of the semiconductor structure; if the heating temperature is too low, it is likely that the H bonds adsorbed on the surface of the fin 101 cannot be consumed. That is to say, a large number of H bonds still adhere to the surface of the fin 101. Correspondingly, during the subsequent cleaning process of the surface of the fin 101, the probability of water clusters adhering to the surface of the fin 101 increases, and the risk of a loose oxide layer appearing on the surface of the fin 101 due to water clusters also increases. During the subsequent formation process of the gate structure, the risk of a gap appearing between the gate structure and the surface of the fin 101 increases, thereby improving the performance of the semiconductor structure. Therefore, in this embodiment, during the process of performing the first heat treatment 105 on the surface of the fin 101, the heating temperature range is 100°C to 1000°C.
[0047] It should also be noted that during the first heat treatment 105 of the surface of the fin portion 101, the heating time should not be too long or too short. If the heating time is too long, the ions remaining on the surface of the fin portion 101 will diffuse, affecting the product yield of the semiconductor structure; if the heating time is too short, it is likely that the H bonds adsorbed on the surface of the fin portion 101 cannot be consumed. That is to say, a large number of H bonds still adhere to the surface of the fin portion 101. Correspondingly, during the subsequent cleaning process of the surface of the fin portion 101, the probability of water molecular clusters adhering to the surface of the fin portion 101 increases, and the risk of a loose oxide layer appearing on the surface of the fin portion 101 due to the water molecular clusters also increases. During the subsequent formation of the gate structure, the risk of a gap appearing between the gate structure and the surface of the fin portion 101 increases, thereby improving the performance of the semiconductor structure. Therefore, in this embodiment, during the first heat treatment 105 of the surface of the fin portion 101, the heating time range is 0.1 h to 5 h.
[0048] As an example, during the first heat treatment 105 of the surface of the fin portion 101, the process gas includes one or both of N2 and He.
[0049] Specifically, both N2 and He are inert gases, which can ensure that the ambient gas will not react with the surface material of the fin to cause other problems. At the same time, the inert gas also has the function of removing the residual HF gas.
[0050] Reference Figure 3 , after performing the first heat treatment 105, the surface of the fin portion 101 is subjected to a cleaning process 107.
[0051] It should be noted that the cleaning process 107 for the surface of the fin portion 101 is used to remove the particulate matter and impurities adhering to the surface of the fin portion 101 during the formation of the fin portion 101, so as to improve the cleanliness and flatness of the surface of the fin portion 101.
[0052] In this embodiment, the steps of the cleaning process 107 for the surface of the fin portion 101 include: performing a cleaning process on the surface of the fin portion 101; after performing the cleaning process, performing a drying process on the surface of the fin portion 101.
[0053] Specifically, the cleaning process for the surface of the fin portion 101 removes the particulate matter and impurities adhering to the surface of the fin portion 101.
[0054] As an example, the process for cleaning the surface of the fin portion 101 includes a wet cleaning process.
[0055] The wet cleaning process is a commonly used process for cleaning the surface of the fin portion 101, which has the characteristics of low process cost and is suitable for large-scale use.
[0056] In this embodiment, the wet cleaning process includes using a cleaning solution that includes deionized water (DIW, De-Ionzied Water).
[0057] Specifically, deionized water is used to remove residual ions on the surface of the fin 101, reducing the probability of residual ions remaining on the surface of the fin 101, thereby reducing the probability that the resistivity of the semiconductor structure is affected by the residual ions and improving the performance of the semiconductor structure.
[0058] It should be noted that compared with the existing cleaning process 107 that only includes the cleaning step, the cleaning process 107 in this embodiment further includes: after the cleaning process, drying the surface of the fin 101.
[0059] Specifically, drying the surface of the fin 101 is used to remove the water molecular clusters remaining on the surface of the fin 101 during the cleaning process, further keeping the surface of the fin 101 dry, thereby reducing the risk of a loose oxide layer appearing on the surface of the fin 101 due to the water molecular clusters. During the subsequent formation of the gate structure, the risk of a gap appearing between the gate structure and the surface of the fin 101 is reduced, thus improving the performance of the semiconductor structure.
[0060] As an example, the step of drying the surface of the fin 101 includes: using a desiccant to dry the surface of the fin 101.
[0061] It should be noted that during the drying process, by utilizing the volatility and surface tension of the desiccant, when the desiccant is sprayed onto the surface of the fin 101, the desiccant will quickly volatilize, consuming the water molecular clusters remaining on the surface of the fin 10, further keeping the surface of the fin 101 dry, thereby reducing the risk of a loose oxide layer appearing on the surface of the fin 101 due to the water molecular clusters.
[0062] It should also be noted that during the drying process, the surface tension of the desiccant will form a protective film on the surface of the fin 101, thereby further preventing the probability of the surface of the fin 101 from being contaminated again.
[0063] As an example, the desiccant includes isopropyl alcohol.
[0064] Specifically, isopropyl alcohol is a commonly used desiccant in the formation process of semiconductor structures, with the characteristic of low process cost and is suitable for mass production.
[0065] Reference Figure 4 , after performing the cleaning process 107 and before forming the gate structure subsequently, it further includes: performing a second heat treatment 110 on the surface of the fin 101.
[0066] Specifically, a second heat treatment 110 is performed on the surface of the fin 101 to further consume the water molecular clusters remaining on the surface of the fin 101, minimizing the probability of water molecular clusters remaining on the surface of the fin 101. Correspondingly, the risk of a loose oxide layer appearing on the surface of the fin 101 due to water molecular clusters can be minimized. During the subsequent formation of the gate structure, the risk of a gap appearing between the gate structure and the surface of the fin 101 is reduced, thereby improving the performance of the semiconductor structure.
[0067] As an example, the process of performing the second heat treatment 110 on the surface of the fin 101 includes a heating and drying process.
[0068] The heating and drying process can consume the water molecular clusters adsorbed on the surface of the fin 101, release the water molecular clusters attached to the surface of the fin 101, and minimize the probability of water molecular clusters remaining on the surface of the fin 101.
[0069] It should be noted that during the process of performing the second heat treatment 110 on the surface of the fin 101, the heating temperature range should not be too large or too small. If the heating temperature is too high, the ions remaining on the surface of the fin 101 will diffuse, affecting the product yield of the semiconductor structure; if the heating temperature is too low, it is easy for water molecular clusters to still remain on the surface of the fin 101, increasing the risk of a loose oxide layer appearing on the surface of the fin 101 due to water molecular clusters. During the subsequent formation of the gate structure, the risk of a gap appearing between the gate structure and the surface of the fin 101 is reduced, thereby improving the performance of the semiconductor structure. Therefore, in this embodiment, during the process of performing the second heat treatment 110 on the surface of the fin 101, the heating temperature range is 100 °C to 200 °C.
[0070] It should also be noted that during the process of performing the second heat treatment 110 on the surface of the fin 101, the heating time should not be too long or too short. If the heating time is too long, the ions remaining on the surface of the fin 101 will diffuse, affecting the product yield of the semiconductor structure; if the heating time is too short, it is easy for water molecular clusters to still remain on the surface of the fin 101, increasing the risk of a loose oxide layer appearing on the surface of the fin 101 due to water molecular clusters. During the subsequent formation of the gate structure, the risk of a gap appearing between the gate structure and the surface of the fin 101 is reduced, thereby improving the performance of the semiconductor structure. Therefore, in this embodiment, during the process of performing the second heat treatment 110 on the surface of the fin 101, the heating time range is 0.1 h to 0 h.
[0071] As an example, during the process of performing the second heat treatment 110 on the surface of the fin 101, the process gas includes one or both of N2 and He.
[0072] Specifically, both N2 and He are inert gases, which can ensure that the ambient gas does not react with the fin surface material to cause other problems. At the same time, the inert gas also has the function of removing the residual HF gas.
[0073] Reference Figure 5 , after performing the cleaning process 107, a gate structure 126 is formed on top of the substrate 102 across the top and part of the sidewalls of the fin 101.
[0074] Specifically, the gate structure 126 occupies a spatial position in advance for the subsequent formation of the device gate structure.
[0075] In this embodiment, the gate structure 126 is a dummy gate structure.
[0076] As an example, the steps of forming the gate structure 126 include: forming a gate oxide layer 122 covering the sidewalls and the top of the fin 101 on top of the substrate 102; forming a gate layer 120 across the top and part of the sidewalls of the fin 101 on top of the substrate 102, and the gate layer 120 covers part of the top and part of the sidewalls of the gate oxide layer 122.
[0077] It should be noted that the gate oxide layer 122 is used for electrical isolation between the fin 101 and the gate layer 120. At the same time, during the process of forming the gate layer 120, the gate oxide layer 122 is also used to protect the top and sidewalls of the fin 101, reducing the probability of damage to the fin 101 caused by the etching process of forming the gate layer 120.
[0078] It should also be noted that since the probability of water molecule clusters remaining on the surface of the fin 101 is minimized, in the deposition process of forming the gate oxide layer 122, the gate oxide layer 122 can closely adhere to the surface of the fin 101, reducing the probability of a loose oxide layer on the surface of the fin 101 caused by water molecule clusters. Correspondingly, during the subsequent process of removing the gate structure 126, the probability of damage to the source-drain doping layer through the gaps on the surface of the fin 101 during the process of removing the gate structure 126 is reduced, thereby improving the performance of the semiconductor structure.
[0079] In this embodiment, the material of the gate layer 120 includes polysilicon.
[0080] Reference Figure 6 , source-drain doping layers 130 are formed in the substrate 102 on both sides of the gate structure 126.
[0081] The source-drain doping layers 130 are used as the source region or the drain region of the semiconductor structure.
[0082] In this embodiment, the source / drain doping layer 130 is formed by an epitaxial process.
[0083] When forming an NMOS transistor, the source / drain doping layer 130 includes a stress layer doped with N-type ions.
[0084] Specifically, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress to the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor. Among them, the N-type ions are P ions, As ions or Sb ions.
[0085] When forming a PMOS transistor, the source / drain doping layer 130 includes a stress layer doped with P-type ions.
[0086] Specifically, the material of the stress layer is Si or SiGe, and the stress layer provides a compressive stress to the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor. Among them, the P-type ions are B ions, Ga ions or In ions.
[0087] Reference Figures 7 to 9 After forming the source / drain doping layer 130, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 150 covering the sidewalls of the gate structure 126 and the top of the source / drain doping layer 130 on the top of the substrate 102; removing the gate structure 126 and forming a gate opening 158 in the interlayer dielectric layer 150; and forming a device gate structure 166 in the gate opening 158.
[0088] Specifically, the interlayer dielectric layer 150 provides a process basis for forming the device gate structure 166. At the same time, the interlayer dielectric layer 150 also plays an electrical isolation role for the subsequently formed device gate structure 166.
[0089] Among them, the material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride and silicon carbon oxynitride. As an example, the material of the interlayer dielectric layer 150 is silicon oxide.
[0090] In this embodiment, the interlayer dielectric layer 150 is formed by a deposition process and a planarization process (for example: chemical mechanical polishing process) performed in sequence.
[0091] Specifically, removing the gate structure 126 provides a spatial position for the subsequent formation of the device gate structure 166.
[0092] It should be noted that removing the gate structure 126 includes only removing the gate layer 120.
[0093] It should also be noted that since the probability of water molecule clusters remaining on the surface of the fin 101 is minimized, in the deposition process of forming the gate oxide layer 122, the gate oxide layer 122 can closely adhere to the surface of the fin 101, reducing the probability of a loose oxide layer (i.e., voids appearing in the gate oxide layer 122 on the surface of the fin 101) on the surface of the fin 101 due to water molecule clusters. Correspondingly, in the process of removing the gate layer 120, the probability that the etching solution of the gate layer 120 enters the source / drain doping layer 130 through the voids in the gate oxide layer 122 can be reduced, thereby reducing the probability of damage to the source / drain doping layer 130, and further improving the performance of the semiconductor structure.
[0094] In this embodiment, the process of removing the gate structure 126 includes a wet etching process.
[0095] Specifically, the wet etching process is an isotropic etching process, and its lateral etching rate is close to the longitudinal etching rate, so that the gate layer 120 can be removed completely in both the lateral and longitudinal directions, reducing the probability of residual gate layer 120. At the same time, a relatively high etching selectivity can be selected in the wet etching process, and the probability of damage to other film layers (such as the fin 101) can be reduced while the gate layer 120 is being removed completely.
[0096] As an example, the etching solution used in the wet etching process includes tetramethylammonium hydroxide.
[0097] The gate opening 158 provides a spatial position for forming the device gate structure 166.
[0098] The device gate structure 166 is used to control the opening and closing of the conductive channel when the device is working.
[0099] Specifically, the device gate structure 166 is a metal gate structure.
[0100] In this embodiment, the device gate structure 166 includes a gate dielectric layer (not shown in the figure) that surrounds and covers the fin 101, and a gate electrode layer (not shown in the figure) that covers the gate dielectric layer.
[0101] Specifically, the gate dielectric layer includes a high-k gate dielectric layer. Among them, the material of the high-k gate dielectric layer is a high-k dielectric material, and the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than that of silicon oxide.
[0102] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.
[0103] The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may only include a work function layer.
[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a substrate and fins protruding from the substrate; Performing a first heat treatment on the surface of the fins; After performing the first heat treatment, performing a cleaning treatment on the surface of the fins; After performing the cleaning treatment, forming a gate structure on top of the substrate, spanning a part of the top and part of the sidewalls of the fins; Forming source / drain doping layers in the substrate on both sides of the gate structure.
2. The method for forming a semiconductor structure according to claim 1, wherein, The process of performing the first heat treatment on the surface of the fins includes a heating and drying process.
3. The method for forming a semiconductor structure according to claim 1, wherein, The process parameters for performing the first heat treatment on the surface of the fins include: the heating temperature range is 100°C to 1000°C; the heating time range is 0.1 h to 5 h; the process gas includes one or both of N2 and He.
4. The method for forming a semiconductor structure according to claim 1, wherein, The steps of performing the cleaning treatment on the surface of the fins include: performing a cleaning process on the surface of the fins; after performing the cleaning process, performing a drying process on the surface of the fins.
5. The method for forming a semiconductor structure according to claim 4, wherein, The process of performing the cleaning process on the surface of the fins includes a wet cleaning process.
6. The method for forming a semiconductor structure according to claim 5, wherein The cleaning solution used in the wet cleaning process includes deionized water.
7. The method for forming a semiconductor structure according to claim 4, wherein The steps of performing the drying process on the surface of the fins include: using a desiccant to dry the surface of the fins.
8. The method for forming a semiconductor structure according to claim 7, wherein, The desiccant includes isopropyl alcohol.
9. The method for forming a semiconductor structure according to claim 1, wherein, After performing the cleaning treatment and before forming the gate structure, it further includes: performing a second heat treatment on the surface of the fins.
10. The method for forming a semiconductor structure according to claim 9, wherein, The process of performing the second heat treatment on the surface of the fins includes a heating and drying process.
11. The method for forming a semiconductor structure according to claim 9, wherein The process parameters for performing the second heat treatment on the surface of the fins include: the heating temperature range is 100°C to 200°C; the heating time range is 0.1 h to 1 h; the process gas includes one or both of N2 and He.
12. The method for forming a semiconductor structure according to claim 1, wherein The steps of forming the gate structure include: forming a gate oxide layer covering the sidewalls and the top of the fins on top of the substrate; forming a gate layer spanning a part of the top and part of the sidewalls of the fins on top of the substrate, the gate layer covering a part of the top and part of the sidewalls of the gate oxide layer.
13. The method for forming a semiconductor structure as claimed in claim 1, wherein After forming the source / drain doping layers, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer covering the sidewalls of the gate structure and the top of the source / drain doping layers on top of the substrate; removing the gate structure and forming a gate opening in the interlayer dielectric layer; forming a device gate structure in the gate opening.
14. The method for forming a semiconductor structure according to claim 13, wherein, The process of removing the gate structure includes a wet etching process.
15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The etching solution used in the wet etching process includes tetramethylammonium hydroxide.