Method for protecting side wall in gallium nitride deep trench process and integrated circuit using same

Abstract

The invention relates to a method for protecting a side wall in a gallium nitride deep trench process and an integrated circuit using the same. The method for sealing and protecting the side wall in the gallium nitride deep trench process comprises the following steps of: performing gallium nitride epitaxy on a semiconductor substrate; sequentially manufacturing a plurality of layer structures; performing a deep trench process on the multi-layer structure to penetrate through the multi-layer structure so as to form a deep trench; performing a deposition process, and covering the side wall of the deep trench with an anti-etching and anti-permeation material; and performing a wet etching.

Description

Technical Field

[0001] The present invention relates to a technology of semiconductor processes, and particularly to a method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process and an integrated circuit manufactured by a gallium nitride process using the same. Background Art

[0002] Shaped components. However, this process faces some challenges. One of the main problems is that the etching liquid penetrates through the multi-layer structure, resulting in leakage, which in turn causes structural collapse and ultimately defects. Deep trench etching plays a crucial role in the gallium nitride process. Its main purposes include defining component structures, forming structural features, and improving component performance.

[0003] However, although deep trench etching is a necessary step in manufacturing high-performance components, during the deep trench etching process, the etching liquid usually needs to penetrate through the multi-layer structure to reach the part to be etched for etching. This penetration process may cause the etching liquid to leak into areas that should not be affected, leading to structural collapse. Summary of the Invention

[0004] The present invention provides a method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process and a device manufactured by a gallium nitride process using the same, so as to protect the multi-layer structure in the gallium nitride (GaN) deep trench process, avoid the etching liquid from penetrating into the multi-layer structure during etching, damage the internal structure in the semiconductor process, and increase the product yield.

[0005] An embodiment of the present invention provides a method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process. The method for sealing and protecting sidewalls in the gallium nitride (GaN) deep trench process includes: performing gallium nitride epitaxy on a semiconductor substrate; sequentially fabricating a plurality of layer structures; performing a deep trench process on the plurality of layer structures to penetrate the plurality of layer structures to form a deep trench; performing a deposition process to cover the sidewalls of the deep trench with an anti-etching and anti-permeation material; and performing a wet etching.

[0006] Another embodiment of the present invention provides an integrated circuit manufactured by a gallium nitride process. The integrated circuit manufactured by the gallium nitride process includes a semiconductor substrate, polycrystalline gallium nitride, and a plurality of layer structures. The polycrystalline gallium nitride surrounds a low-pressure deposited nitride (LP nitride). There is a wet etching cavity between the polycrystalline gallium nitride and the semiconductor substrate. The plurality of layer structures are disposed on the polycrystalline gallium nitride. A deep trench penetrating the plurality of layer structures is provided on the sidewalls of the plurality of layer structures. The sidewalls of the deep trench are covered with an anti-etching and anti-permeation material.

[0007] A method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention, and an apparatus manufactured by a gallium nitride process using the same. In this method, for the step of covering the sidewalls of the deep trench with an etch-resistant and anti-permeation material during a deposition process, a chemical vapor deposition process is performed to cover the sidewalls of the deep trench with a silicon nitride.

[0008] A method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention, and an apparatus manufactured by a gallium nitride process using the same. On a semiconductor substrate, during gallium nitride epitaxy, the following steps are further included: depositing a low-pressure deposited nitride (LP nitride); configuring a polycrystalline gallium nitride (poly). In addition, for the step of sequentially fabricating a plurality of layer structures, the following steps are included: depositing the low-pressure deposited nitride on the polycrystalline gallium nitride; covering a borophosphosilicate glass (BPSG) as a pre-metal deposition dielectric layer (PMD); fabricating a contact window in the pre-metal deposition dielectric layer; configuring a first metal layer on the pre-metal deposition dielectric layer; covering a first inter-metal dielectric layer (IMD); fabricating a metal via in the first inter-metal dielectric layer; configuring a second metal layer on the first inter-metal dielectric layer; and configuring a second inter-metal dielectric layer on the second metal layer.

[0009] A method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention, and an apparatus manufactured by a gallium nitride process using the same. For the step of performing the deep trench process on the above-mentioned plurality of layer structures to penetrate the plurality of layer structures to form the deep trench, the following steps are included: performing the deep trench process to penetrate the plurality of layer structures until the semiconductor substrate. In a preferred embodiment, for the step of performing wet etching, a tetramethylammonium hydroxide is used to etch the semiconductor substrate in the deep trench to isolate the polycrystalline gallium nitride from the semiconductor substrate.

[0010] In summary, in the embodiments of the present invention, an etch-resistant and anti-permeation material is configured in the deep trench portion beside the plurality of layer structures. By doing so, during subsequent wet etching, leakage of the etching liquid between layers can be prevented from entering and causing damage to the internal circuit and even possible structural collapse. Therefore, the embodiments of the present invention can increase the product yield and product reliability.

[0011] To further understand the technology, means, and effects of the present invention, the following detailed description and drawings can be referred to, so as to thoroughly and specifically understand the purpose, features, and concepts of the present invention. However, the following detailed description and drawings are only used for reference and illustration of the implementation manner of the present invention, and are not used to limit the present invention. Description of the Drawings

[0012] The accompanying drawings are provided to enable those skilled in the art to further understand the present invention and are incorporated into and constitute a part of the specification of the present invention. The drawings illustrate exemplary embodiments of the present invention and are used together with the specification of the present invention to explain the principles of the present invention.

[0013] Figure 1A A cross-sectional schematic view of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0014] Figure 1B Another cross-sectional schematic view of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0015] Figure 1C A top view schematic view of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0016] Figure 2 A flowchart of a manufacturing method for polycrystalline gallium nitride 102 and a multi-layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0017] Figure 3A A schematic view of step S202 of a manufacturing method for polycrystalline gallium nitride 102 and a multi-layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0018] Figure 3B A schematic view of step S203 of a manufacturing method for polycrystalline gallium nitride 102 and a multi-layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0019] Figure 3C A schematic view of step S204 of a manufacturing method for polycrystalline gallium nitride 102 and a multi-layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0020] Figure 3D A schematic view of step S205 of a manufacturing method for polycrystalline gallium nitride 102 and a multi-layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0021] Figure 3E A schematic view of step S206 of a manufacturing method for polycrystalline gallium nitride 102 and a multi-layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention is shown.

[0022] Figure 3FSchematic diagram of step S207 of the manufacturing method of polycrystalline gallium nitride 102 and multiple layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention.

[0023] Figure 3G Schematic diagram of step S208 of the manufacturing method of polycrystalline gallium nitride 102 and multiple layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention.

[0024] Figure 3H Schematic diagram of step S209 of the manufacturing method of polycrystalline gallium nitride 102 and multiple layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention.

[0025] Figure 3I Schematic diagram of step S210 of the manufacturing method of polycrystalline gallium nitride 102 and multiple layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention.

[0026] Figure 3J Schematic diagram of step S211 of the manufacturing method of polycrystalline gallium nitride 102 and multiple layer structure 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention.

[0027] Figure 4 Flowchart of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0028] Figure 5A Schematic diagram of step S42 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0029] Figure 5B Schematic diagram of step S431 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0030] Figure 5C Schematic diagram of step S432 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0031] Figure 5D Schematic diagram of step S441 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0032] Figure 5E Schematic diagram of step S442 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0033] Figure 5F Schematic diagram of step S443 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0034] Figure 5G Schematic diagram of step S444 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0035] Figure 5H Schematic diagram of step S445 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0036] Figure 5I Schematic diagram of step S45 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention.

[0037] Symbol description:

[0038] 101 Semiconductor substrate;

[0039] 102 Polycrystalline gallium nitride;

[0040] 103 Majority layer structure;

[0041] 104 Low-pressure deposited nitride;

[0042] 131 Metal deposition pre-dielectric layer;

[0043] 132 Contact window;

[0044] 133 First metal layer;

[0045] 134 First dielectric layer;

[0046] 135 Metal via;

[0047] 136 Second metal layer;

[0048] 137 Second dielectric layer;

[0049] 105 Etched deep trench;

[0050] 106 Wet etching cavity;

[0051] 107 Temperature sensor;

[0052] 108 Suspension arm;

[0053] S201~S211 Flow steps of the manufacturing method of the polycrystalline gallium nitride 102 and the majority layer structure 103 of an integrated circuit manufactured by a gallium nitride process according to a preferred embodiment of the present invention;

[0054] 301 Nitride

[0055] 302 Gallium nitride polycrystal;

[0056] 303 Low-pressure deposited nitride;

[0057] 304 Dielectric layer before metal deposition;

[0058] 305 Contact window;

[0059] 306 First metal layer;

[0060] 307 First inter-metal dielectric layer;

[0061] 308 Metal via;

[0062] 309 Second metal layer;

[0063] 310 Second inter-metal dielectric layer;

[0064] 51 Silicon nitride thin film;

[0065] S41 - S45 Flow steps of the method for sealing and protecting sidewalls in the gallium nitride (GaN) deep trench process of a preferred embodiment of the present invention;

[0066] S431 - S435 Sub-steps of step S43 of the method for sealing and protecting sidewalls in the gallium nitride (GaN) deep trench process of a preferred embodiment of the present invention;

[0067] S441 - S445 Sub-steps of step S44 of the method for sealing and protecting sidewalls in the gallium nitride (GaN) deep trench process of a preferred embodiment of the present invention. Detailed implementation manners

[0068] Now, reference will be made in detail to the exemplary embodiments of the present invention, and the exemplary embodiments will be illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or similar parts. Additionally, the practices of the exemplary embodiments are only one of the implementation manners of the design concept of the present invention, and the following examples are not used to limit the present invention.

[0069] Figure 1A It is a cross-sectional schematic view of an integrated circuit manufactured by a gallium nitride process according to a preferred embodiment of the present invention. Please refer to Figure 1A, the integrated circuit fabricated by this gallium nitride process includes a semiconductor substrate 101, a polycrystalline gallium nitride 102, and a plurality of layer structures 103. The polycrystalline gallium nitride 102 surrounds a low-pressure deposited nitride 104. The plurality of layer structures 103 in this example includes a pre-metal dielectric layer (PMD, generally implemented with borophosphosilicate glass (BPSG)) 131, contact windows 132, a first metal layer 133, a first inter-metal dielectric layer (IMD) 134, metal vias 135, a second metal layer 136, and a second dielectric layer 137. Additionally, there is an etched deep trench 105 on one side of the plurality of layer structures 103. Additionally, the cross-sectional schematic diagram of this embodiment is only for illustration and does not show the true scale. The same applies hereinafter.

[0070] Figure 1B Shown is another cross-sectional schematic diagram of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention. Please refer to Figure 1B , in this embodiment, the above-mentioned deep trench 105 is marked. This deep trench 105 is mainly used for wet etching to generate the following wet etching cavity 106 to isolate the substrate of the semiconductor substrate 101 from the temperature sensor.

[0071] Figure 1C Shown is a top view schematic diagram of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention. Please refer to Figure 1C , this embodiment shows the top view of the above-mentioned temperature sensor. In this embodiment, it shows that the periphery of the temperature sensor 107 is wet-etched through the deep trench 105 to etch the substrate below the temperature sensor 107 to form the above-mentioned wet etching cavity 106. Additionally, this temperature sensor 107 is supported by four polycrystalline gallium nitride suspension arms 108.

[0072] Figure 2 Shown is a flowchart of a manufacturing method for the polycrystalline gallium nitride 102 and the plurality of layer structures 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention. Please refer to Figure 2 , this manufacturing method includes the following steps:

[0073] Step S201: Start.

[0074] Step S202: Deposit a low-pressure deposited nitride (LP nitride). Figure 3A Shown is a schematic diagram of step S202 of a manufacturing method for the polycrystalline gallium nitride 102 and the plurality of layer structures 103 of an integrated circuit fabricated by a gallium nitride process according to a preferred embodiment of the present invention. As Figure 3A shown, the nitride 301 is deposited on the substrate of the semiconductor substrate 101 by low-pressure chemical vapor deposition.

[0075] Step S203: Configure a polycrystalline gallium nitride (poly). Figure 3B FIG. is a schematic diagram of step S203 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of the integrated circuit manufactured by the gallium nitride process according to a preferred embodiment of the present invention. As Figure 3B shown, on the nitride 301, a polycrystalline gallium nitride 302 is configured.

[0076] Step S204: Deposit a low-pressure deposited nitride on the polycrystalline gallium nitride. Figure 3C FIG. is a schematic diagram of step S204 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of the integrated circuit manufactured by the gallium nitride process according to a preferred embodiment of the present invention. As Figure 3C shown, by depositing a low-pressure deposited nitride 303, the above polycrystalline gallium nitride 302 is surrounded.

[0077] Step S205: Cover a borophosphosilicate glass (BPSG) as a pre-metal deposition dielectric layer (PMD). Figure 3D FIG. is a schematic diagram of step S205 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of the integrated circuit manufactured by the gallium nitride process according to a preferred embodiment of the present invention. As Figure 3D shown, the polycrystalline gallium nitride 302 is covered with a chemically vapor-deposited borophosphosilicate glass as the pre-metal deposition dielectric layer 304.

[0078] Step S206: Fabricate a contact window in the pre-metal deposition dielectric layer. Figure 3E FIG. is a schematic diagram of step S205 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of the integrated circuit manufactured by the gallium nitride process according to a preferred embodiment of the present invention. As Figure 3E shown, generally, the contact window 305 is formed by exposure, development, and etching to configure the metal for an ohmic contact to electrically connect to the subsequent metal layer.

[0079] Step S207: Configure a first metal layer on the pre-metal deposition dielectric layer. Figure 3F FIG. is a schematic diagram of step S207 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of the integrated circuit manufactured by the gallium nitride process according to a preferred embodiment of the present invention. As Figure 3F shown, the first metal layer 306 is configured on the pre-metal deposition dielectric layer 304 to electrically connect the above polycrystalline gallium nitride 302.

[0080] Step S208: Cover a first inter-metal dielectric layer (IMD). Figure 3GSchematic diagram of step S208 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of an integrated circuit manufactured by a gallium nitride process according to a preferred embodiment of the present invention. As Figure 3G shown, a first metal interlayer dielectric layer 307 is disposed on the first metal layer 306.

[0081] Step S209: Fabricate a metal via in the first metal interlayer dielectric layer. Figure 3H Schematic diagram of step S209 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of an integrated circuit manufactured by a gallium nitride process according to a preferred embodiment of the present invention. As Figure 3H shown, similarly, the first metal interlayer dielectric layer 307 is etched to obtain a metal via (VIA) 308 as an electrical connection interface between the first metal layer 306 and the subsequent metal layer.

[0082] Step S210: Dispose a second metal layer on the first metal interlayer dielectric layer. Figure 3I Schematic diagram of step S210 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of an integrated circuit manufactured by a gallium nitride process according to a preferred embodiment of the present invention. As Figure 3I shown, a second metal layer 309 is disposed on the first metal interlayer dielectric layer 307.

[0083] Step S211: Dispose a second metal interlayer dielectric layer on the second metal layer. Figure 3J Schematic diagram of step S203 of the manufacturing method of the polycrystalline gallium nitride 102 and the multi-layer structure 103 of an integrated circuit manufactured by a gallium nitride process according to a preferred embodiment of the present invention. As Figure 3J shown, a second metal interlayer dielectric layer 310 is disposed on the second metal layer 309.

[0084] Figure 4 Flowchart of a method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 4 , this method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process includes the following steps:

[0085] Step S41: Start.

[0086] Step S42: Perform gallium nitride epitaxy on a semiconductor substrate and sequentially fabricate a multi-layer structure. Figure 5A Schematic diagram of step S42 of a method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5A, carried out as in the above steps S201 to S211 to obtain a gallium nitride epitaxy and a multi-layer structure 501. Since each layer fabricated in the above steps S201 to S211 is a stack and not homogeneous, there may be gaps between the interfaces of the two materials during the manufacturing process.

[0087] Step S43: Perform a deep trench process on the above multi-layer structure to penetrate the multi-layer structure to form a deep trench. This step includes the following sub-steps:

[0088] Step S431: Perform an exposure and development process to shape a photoresist to define the position of the deep trench. Figure 5B Schematic diagram of step S431 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5B , using the photoresist 502 and the exposure and development process, define the position 503 to be etched.

[0089] Step S432: Perform a dry etching to construct the deep trench and remove the photoresist. Figure 5C Schematic diagram of step S432 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5C , perform a dry etching on the above etched position 503 to penetrate the above multi-layer structure 501 until the semiconductor substrate, and then remove the photoresist.

[0090] Step S44: Perform a deposition process to cover the sidewalls of the deep trench with an anti-etching and anti-permeation material. This step includes the following sub-steps:

[0091] Step S441: Perform a deposition process of the anti-etching and anti-permeation material. Figure 5D Schematic diagram of step S441 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5D , in this embodiment, for example, silicon nitride chemical vapor deposition is used. Let silicon nitride form a silicon nitride film 51 on the surface, in the deep trench, and on the substrate.

[0092] Step S442: Perform an exposure and development process to shape the photoresist to define the position of the deep trench. Figure 5E Schematic diagram of step S442 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5E , in this embodiment, for example, use the exposure and development process to define the position of the deep trench for subsequent etching.

[0093] Step S443: Perform an etching on the position of the deep trench to remove the anti-etching and anti-permeation material at the bottom of the deep trench. Figure 5FSchematic diagram of step S443 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5F , remove the silicon nitride at the bottom of the above-mentioned deep trench by etching.

[0094] Step S444: Etch the semiconductor substrate base at the position of the deep trench. Figure 5G Schematic diagram of step S444 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5G , further etch the bottom of the above-mentioned deep trench by etching.

[0095] Step S445: Perform dry etching. Figure 5H Schematic diagram of step S445 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5H , define the position of the suspension arm by dry etching.

[0096] Step S45: Perform a wet etching. Figure 5I Schematic diagram of step S45 of the method for sealing and protecting sidewalls in a gallium nitride (GaN) deep trench process according to a preferred embodiment of the present invention. Please refer to Figure 5I , this wet etching process is, for example, used in tetramethylammonium hydroxide (TMAH) to etch the semiconductor substrate in the deep trench to form Figure 5I a cavity. Since there is silicon nitride on the surface of the sidewalls, tetramethylammonium hydroxide will not penetrate into the interface of the multi-layer structure. Therefore, the internal circuit is protected and the structure collapse is prevented.

[0097] In summary, the embodiments of the present invention adopt the configuration of anti-etching and anti-permeation materials in the deep trench part beside the multi-layer structure. Thereby, when performing subsequent wet etching, it is possible to prevent the etching liquid between layers from leaking in and causing damage to the internal circuit and even possible structure collapse. Therefore, the embodiments of the present invention can increase the product yield and product reliability.

[0098] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereof will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A method for protecting sidewalls in a gallium nitride deep trench process, characterized in that, Comprising: On a semiconductor substrate, gallium nitride epitaxy is performed. A plurality of layer structures are sequentially fabricated. On the plurality of layer structures, a deep trench process is performed to penetrate the plurality of layer structures to form a deep trench. A deposition process is performed to cover the sidewalls of the deep trench with an etch-resistant and anti-permeation material. And A wet etching is performed.

2. The method for protecting sidewalls in a gallium nitride deep trench process according to claim 1, wherein Performing the deposition process to cover the sidewalls of the deep trench with the etch-resistant and anti-permeation material includes performing a chemical vapor deposition process to cover the sidewalls of the deep trench with silicon nitride.

3. The method for protecting sidewalls in a gallium nitride deep trench process according to claim 1, wherein On a semiconductor substrate, performing gallium nitride epitaxy further includes: Depositing a low-pressure deposited nitride. Configuring a polycrystalline gallium nitride. Wherein, sequentially fabricating a plurality of layer structures further includes: On the polycrystalline gallium nitride, depositing the low-pressure deposited nitride. Covering a borophosphosilicate glass as a pre-metal deposition dielectric layer. On the pre-metal deposition dielectric layer, fabricating a contact window. On the pre-metal deposition dielectric layer, configuring a first metal layer. Covering a first inter-metal dielectric layer. On the first inter-metal dielectric layer, fabricating a metal via. On the first inter-metal dielectric layer, configuring a second metal layer; and On the second metal layer, configuring a second inter-metal dielectric layer.

4. The method for protecting sidewalls in a gallium nitride deep trench process according to claim 1, wherein Performing the deep trench process on the above-mentioned plurality of layer structures to penetrate the plurality of layer structures to form the deep trench includes: performing the deep trench process to penetrate the plurality of layer structures until the semiconductor substrate.

5. The method for protecting sidewalls in a gallium nitride deep trench process according to claim 1, wherein, Performing the wet etching includes: Etching the semiconductor substrate in the deep trench with a tetramethylammonium hydroxide to isolate the polycrystalline gallium nitride from the semiconductor substrate.

6. The method for protecting sidewalls in a gallium nitride deep trench process according to claim 1, wherein Performing the deep trench process on the above-mentioned plurality of layer structures to penetrate the plurality of layer structures to form the deep trench includes: Performing an exposure and development to shape a photoresist to define the position of the deep trench. Performing a dry etching to construct the deep trench. Removing the photoresist.

7. The method for protecting sidewalls in a gallium nitride deep trench process according to claim 6, wherein Performing the deposition process to cover the sidewalls of the deep trench with the etch-resistant and anti-permeation material includes: Performing the deposition process of the etch-resistant and anti-permeation material. Performing the exposure and development to shape the photoresist to define the position of the deep trench. Performing an etching on the position of the deep trench to remove the etch-resistant and anti-permeation at the bottom of the deep trench.

8. An integrated circuit manufactured by a gallium nitride process, wherein A semiconductor substrate; A polycrystalline gallium nitride, wherein the polycrystalline gallium nitride surrounds a low-pressure deposited nitride, and there is a wet etching cavity between the polycrystalline gallium nitride and the semiconductor substrate; and A plurality of layer structures are configured on the polycrystalline gallium nitride; Wherein, the sidewalls of the plurality of layer structures have a deep trench penetrating the plurality of layer structures; Wherein, the sidewall of the deep trench is covered with an etching-resistant and anti-permeation material.

9. The integrated circuit manufactured by the gallium nitride process according to claim 8, wherein, The sidewall of the deep trench is covered with the etching-resistant and anti-permeation material, including: a silicon nitride material.

10. The integrated circuit manufactured by the gallium nitride process according to claim 8, characterized in that, The above-mentioned multiple-layer structure further includes: a low-pressure deposited nitride disposed on the polycrystalline gallium nitride; a borophosphosilicate glass disposed on the low-pressure deposited nitride as a pre-metal deposition dielectric layer, wherein the pre-metal deposition dielectric layer has a contact window; a first metal layer disposed on this pre-metal deposition dielectric layer; a first inter-metal dielectric layer disposed on the first metal layer, wherein the first inter-metal dielectric layer includes a metal via; a second metal layer disposed on the first inter-metal dielectric layer; and a second inter-metal dielectric layer disposed on the second metal layer.

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