Epitaxial partition integrated radio frequency front-end chip and manufacturing method thereof

Abstract

The invention relates to the field of semiconductor chip substrate materials and manufacturing, and discloses an epitaxial partition integrated radio frequency front-end chip and a manufacturing method thereof.The radio frequency front-end chip comprises a substrate layer, a buffer layer and an epitaxial layer, and the epitaxial layer comprises a plurality of epitaxial partitions; the radio frequency front-end chip is at least integrated with a power amplifier, a low-noise amplifier, a radio frequency switch and a piezoelectric filter, the buffer layer is arranged on the substrate layer, the epitaxial layer is arranged on the buffer layer, the epitaxial partitions are randomly arranged on the epitaxial layer, and the lower surfaces of the epitaxial partitions are connected with the upper surface of the buffer layer; the power amplifier, the low-noise amplifier and the piezoelectric filter are located in different epitaxial partitions respectively, the low-noise amplifier and the radio frequency switch are located in the same epitaxial partition, and the epitaxial partitions where the power amplifier, the low-noise amplifier and the piezoelectric filter are located are made of different materials. According to the technical scheme provided by one or more embodiments of the invention, high integration of the radio frequency front-end chip can be realized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip packaging, and in particular, to a radio frequency front-end chip with epitaxial partition integration and a manufacturing method thereof. Background Art

[0002] With the continuous development of wireless communication technology and the trend of miniaturization and diversification of mobile terminals, as a key component for wireless signal transmission and reception in a communication system, the radio frequency front-end currently has an increasingly high requirement for integration.

[0003] In practical applications, the radio frequency front-end system usually appears in the form of a module containing multiple radio frequency devices in an integrated circuit. Each radio frequency device is respectively mounted or packaged on the surface of the main board to form a radio frequency front-end module, but its integration is still low and it is difficult to meet the current high-integration requirements for radio frequency front-end modules.

[0004] In view of this, how to achieve high integration of radio frequency front-end chips is an urgent problem to be solved. Summary of the Invention

[0005] The present application provides a radio frequency front-end chip with epitaxial partition integration and a manufacturing method thereof, which can achieve high integration of radio frequency front-end chips.

[0006] In a first aspect of the present application, a radio frequency front-end chip with epitaxial partition integration is provided. The radio frequency front-end chip includes a substrate layer, a buffer layer, and an epitaxial layer. The epitaxial layer includes multiple epitaxial partitions. The radio frequency front-end chip integrates at least a power amplifier, a low-noise amplifier, a radio frequency switch, and a piezoelectric filter. Among them: the buffer layer is disposed on the substrate layer, the epitaxial layer is disposed on the buffer layer, and each of the epitaxial partitions is arranged arbitrarily on the epitaxial layer, and the lower surface of the epitaxial partition is in contact with the upper surface of the buffer layer; the power amplifier, the low-noise amplifier, and the piezoelectric filter are respectively located in different epitaxial partitions, the low-noise amplifier and the radio frequency switch are located in the same epitaxial partition, and the materials of the epitaxial partitions where the power amplifier, the low-noise amplifier, and the piezoelectric filter are located are different.

[0007] In a possible implementation manner, the epitaxial partition includes gallium arsenide epitaxy, single-crystal silicon epitaxy, and piezoelectric epitaxy. Among them: the power amplifier is located in the gallium arsenide epitaxy, the low-noise amplifier and the radio frequency switch are located in the single-crystal silicon epitaxy, and the piezoelectric filter is located in the piezoelectric epitaxy.

[0008] In a possible implementation manner, the radio frequency front-end chip further integrates a duplexer, and among them, the duplexer is located in the piezoelectric epitaxy.

[0009] In a possible implementation, the gallium arsenide epitaxy includes a collector, an emitter, a base, and a buffer material.

[0010] In a possible implementation, the material of the single-crystal silicon epitaxy is single-crystal silicon, and the material of the piezoelectric epitaxy is any one of lithium tantalate, lithium niobate, or aluminum nitride.

[0011] In a possible implementation, the RF front-end chip further includes pads and a substrate, where: the pads are located on the surface of the epitaxial partition, and the pads are electrically connected to the epitaxial partition and the substrate respectively.

[0012] The second aspect of the present application provides a method for manufacturing an RF front-end chip with integrated epitaxial partitions. The method includes: using a silicon substrate as a substrate layer, growing silicon dioxide on the substrate layer to form a layer of silicon dioxide layer, and using the silicon dioxide layer as a buffer layer; respectively using gallium arsenide material, single-crystal silicon material, and piezoelectric material to grow at different positions on the buffer layer to form multiple epitaxial partitions, where the epitaxial partitions include gallium arsenide epitaxy, single-crystal silicon epitaxy, and piezoelectric epitaxy; depositing a metal layer on each of the epitaxial partitions, and coating a photoresist layer with a specific shape on the metal layer, and etching corresponding metal devices and interconnection networks on the metal layer of each of the epitaxial partitions based on the photoresist layer.

[0013] In a possible implementation, after etching specific-shaped metal devices and interconnection networks on the metal layer of each of the epitaxial partitions based on the photoresist layer, the method further includes: cleaning the metal layer to remove the photoresist layer and metal impurities on the upper surface of the metal layer, and annealing the cleaned metal layer.

[0014] In a possible implementation, the metal devices at least include a power amplifier, a low-noise amplifier, an RF switch, and a piezoelectric filter; coating a photoresist layer with a specific shape on the metal layer, and etching specific-shaped metal devices and interconnection networks on the metal layer of each of the epitaxial partitions based on the photoresist layer includes: coating photoresist on the upper surface of the metal layer, exposing and developing the metal layer coated with photoresist to form a photoresist layer with a specific shape on the surface of the metal layer; according to the specific shape of the photoresist layer, etching the transistor and interconnection metal structure of the power amplifier on the gallium arsenide epitaxy in sequence, etching the transistor and interconnection metal structure of the low-noise amplifier and the electrode and interconnection metal structure of the RF switch on the single-crystal silicon epitaxy, etching the electrode and interconnection metal structure of the piezoelectric filter on the piezoelectric epitaxy, and etching one or more passive devices and interconnection metal structures on each epitaxial partition.

[0015] In a possible implementation, the metal device further includes a duplexer; etching a metal device and an interconnection network with a specific shape on the metal layer in each of the epitaxial partitions based on the photoresist layer further includes: etching electrodes and an interconnection metal structure of the duplexer on the piezoelectric epitaxy according to the specific shape of the photoresist layer.

[0016] The technical solutions provided by one or more embodiments of the present application integrate radio frequency devices with different epitaxial layers on the same chip to improve the integration of radio frequency front-end chips. Specifically, each device of the radio frequency front-end module is integrated into gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy according to its respective functions, and the gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy are integrated on the same substrate to achieve high integration of the radio frequency front-end chip. At the same time, in the process of manufacturing the radio frequency front-end chip, since each device is integrated on the same substrate in different epitaxial forms, a single photomask can be used synchronously during lithography, simplifying the process flow of the radio frequency front-end chip and thus improving the production efficiency of the radio frequency front-end chip.

[0017] It can be seen that the technical solutions provided by the present application can achieve high integration of the radio frequency front-end chip, and at the same time, also improve the production efficiency of the radio frequency front-end chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 FIG. 1 is a schematic structural diagram of a radio frequency front-end chip with epitaxial partition integration provided by an embodiment of the present application;

[0020] FIGS. 2(a) and 2(b) are schematic structural diagrams of an existing radio frequency front-end chip and module provided by an embodiment of the present application;

[0021] Figure 3 FIG. 3 is a schematic structural diagram of a radio frequency front-end chip with epitaxial partition integration provided by an embodiment of the present application;

[0022] Figure 4 FIG. 4 is a structural step diagram of a radio frequency front-end chip with epitaxial partition integration provided by another embodiment of the present application;

[0023] Figure 5 FIG. 5 is a method step diagram for manufacturing a radio frequency front-end chip with epitaxial partition integration provided by an embodiment of the present application;

[0024] Figure 6 The figure shows the manufacturing method steps of different devices of the RF front-end chip provided by an embodiment of the present application.

[0025] Description of the reference numerals

[0026] 10 - Substrate layer, 11 - Buffer layer, 12 - Epitaxial layer, 102 - Epitaxial partition, 1021 - Epitaxial partition, 1022 - Epitaxial partition, 1023 - Epitaxial partition, 13 - Pad, 14 - Metal connection layer, 15 - Substrate, 105 - Through hole. Specific embodiments

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0028] In addition, the descriptions involving "first", "second", etc. in the present application are only for descriptive purposes, and cannot be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, the use of "based on" or "in accordance with" means open and inclusive, because a process, step, calculation, or other action based on one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.

[0029] In recent years, RF front-end chips and modules, as key components for wireless signal transmission and reception in communication systems, have shown a trend of diversification and high integration in the market with the wide application of 5G technology and the continuous change of communication requirements. Generally, RF front-end chips and modules appear in the form of modules containing multiple RF devices in integrated circuits. The above-mentioned RF devices usually include RF power amplifiers, RF switches, duplexers, low-noise amplifiers, filters, and other devices. Exemplarily, in the signal transmission link and signal reception link of wireless terminal devices, the RF front-end chip is applied in the form of a module integrating the aforementioned different devices, such as the RF power amplifier module in the signal transmission link and the receiving-end module in the signal reception link.

[0030] In the related art, usually, lithography, development, etching, film coating, cleaning and other etching processes need to be carried out separately for each radio frequency device to fabricate multiple radio frequency chips. Each of the above radio frequency devices needs to be made into different chips through different substrates according to their respective functions, and are respectively mounted on the surface of the main board to form a radio frequency front-end module. The integration degree of the radio frequency front-end module in the integrated circuit is relatively low. Moreover, when manufacturing the radio frequency front-end module as described above, lithography needs to be carried out separately for each radio frequency device, and its process flow is relatively cumbersome, resulting in a low production efficiency of the radio frequency front-end module.

[0031] Currently, passive filters can be used in radio frequency front-end chips and modules. The above passive filters can be fabricated together with the above power amplifiers in the form of capacitors and inductors to reduce the occupancy of the radio frequency front-end module in the integrated circuit. The above passive filters are only applicable to application scenarios with low performance requirements, and their application scenarios are few. Therefore, piezoelectric filters are usually used as the radio frequency filters of the radio frequency front-end module to ensure the performance of the radio frequency front-end module in multi-band and interference environments. However, piezoelectric filters can only be fabricated based on piezoelectric materials as the substrate, resulting in relatively low integration degree and production efficiency of the radio frequency front-end chips and modules in the integrated circuit.

[0032] In view of this, one or more embodiments of the present application provide an epitaxial partition integrated radio frequency front-end chip and its manufacturing method, which can solve the above problems and achieve high integration of the radio frequency front-end chip.

[0033] Please refer to Figure 1 , one embodiment of the present application provides an epitaxial partition integrated radio frequency front-end chip. The radio frequency front-end chip includes a substrate layer 10, a buffer layer 11 and an epitaxial layer 12. The epitaxial layer 12 includes a plurality of epitaxial partitions 102. The radio frequency front-end chip is at least integrated with a power amplifier, a low-noise amplifier, a radio frequency switch and a piezoelectric filter, wherein:

[0034] The buffer layer 11 is disposed on the substrate layer 10, the epitaxial layer 12 is disposed on the buffer layer 11, and each of the epitaxial partitions 102 is arranged arbitrarily on the epitaxial layer 12. The lower surface of the epitaxial partition 102 is in contact with the upper surface of the buffer layer 11. The power amplifier, the low-noise amplifier and the piezoelectric filter are respectively located in different epitaxial partitions 102. The low-noise amplifier and the radio frequency switch are located in the same epitaxial partition 102, and the materials of the epitaxial partitions 102 where the power amplifier, the low-noise amplifier and the piezoelectric filter are located are different.

[0035] In this embodiment, the structural layers of the above radio frequency front-end chip from bottom to top are a substrate layer 10, a buffer layer 11, and an epitaxial layer 12 respectively. Each device of the above radio frequency front-end chip shares the same substrate layer 10, and a buffer layer 11 is provided on the substrate layer 10. Different epitaxial materials are grown at different positions on the above buffer layer 11 as epitaxial partitions 102, and the above multiple epitaxial partitions 102 constitute the epitaxial layer 12 provided on the buffer layer 11. Among them, the material of the above substrate layer 10 is silicon, the material of the above buffer layer 11 is silicon dioxide, and the material of the above epitaxial layer 12 is determined according to different radio frequency devices, and the epitaxial materials of each radio frequency device may be different. It should be noted that the above epitaxial partitions 102 of the epitaxial layer 12 can be randomly arranged at different positions. Preferably, closely connecting each epitaxial partition 102 can reduce the area of the radio frequency front-end chip and further improve the integration degree of the radio frequency front-end chip.

[0036] In this embodiment, the above radio frequency front-end chip can be integrated with a variety of radio frequency devices, including a radio frequency power amplifier, a radio frequency switch, an antenna tuning switch, a duplexer, a low-noise amplifier, a piezoelectric filter, and other devices, and there may be one or more of each device. Among them, the above power amplifier is used for signal amplification in the transmission channel, the above piezoelectric filter is used to retain signals in a specific frequency band and filter out signals in other frequency bands, the above low-noise amplifier is used for signal amplification in the receiving channel, the above radio frequency switch is used to switch radio frequency signals between receiving and transmitting and between different frequency bands, and the above duplexer is used to ensure signal isolation between transmission and reception. In addition, in the design scenario of the radio frequency front-end of some terminals, a diplexer and a connector are also added to optimize the signal processing after the antenna tuning switch.

[0037] In the production of traditional radio frequency front-end chips and modules, please refer to FIGS. 2(a) and 2(b). FIGS. 2(a) and 2(b) show part of the production process of traditional radio frequency front-end chips and modules. Generally speaking, as shown in FIG. 2(a), the above devices are respectively lithographically fabricated using different wafer materials to form multiple chips. As shown in FIG. 2(b), each chip is mounted on a substrate to form a radio frequency front-end module. Exemplarily, the wafer material of the above power amplifier is a multi-layer structure including a gallium arsenide substrate, an emitter, a base, a collector, etc., the wafer materials of the above low-noise amplifier and radio frequency switch are multi-layer structures including a silicon substrate, an oxide layer, and a single-crystalline silicon layer, and the wafer material of the above piezoelectric filter is a multi-layer structure including a silicon substrate, an oxide layer, and a piezoelectric material layer. Fabricating each of the above radio frequency devices into chips and mounting them to form a radio frequency front-end module is difficult to meet the requirements of integrated circuits for miniaturization and portability.

[0038] In this embodiment, each of the above devices is fabricated using different epitaxial materials according to the required wafer material and is disposed in different epitaxial partitions to be integrated into the same substrate layer 10. Exemplarily, please refer to Figure 3 , and gallium arsenide layer structures such as emitter, base, collector, and buffer materials are used as the epitaxial material for the power amplifier to form an epitaxial partition 1021, a single-crystalline silicon layer is used as the epitaxial material for the low-noise amplifier to form an epitaxial partition 1022, and a piezoelectric material is used as the epitaxial material to form an epitaxial partition 1023. The plane where the above three epitaxial partitions are located is used as the epitaxial layer 12 and disposed on the buffer layer 11. The above buffer layer 11 can be understood as the oxide layer in the original wafer material, and silicon dioxide can be selected as the buffer layer material to isolate electricity and provide certain structural support, thereby improving the stability of the RF front-end chip.

[0039] Furthermore, a plurality of RF devices are fabricated on each of the above epitaxial partitions to integrate each RF device into one chip, eliminating the need to fabricate multiple different chips, greatly improving the integration degree of the RF front-end chip and making it easier to meet the requirement of the integrated circuit for the miniaturization of the RF front-end chip.

[0040] Based on the above description, the technical solution provided by the embodiment of the present application integrates RF devices with different epitaxial layers on the same substrate to improve the integration degree of the RF front-end chip. Specifically, each device of the RF front-end module is respectively integrated into gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy according to their respective functions, and the gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy are integrated on the same substrate to integrate each RF device into the same chip, eliminating the need to fabricate multiple chips for template packaging, thereby achieving high integration of the RF front-end chip.

[0041] In one embodiment, the epitaxial partitions of the above RF front-end chip include gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy. The above RF front-end chip may further include a duplexer. Since the wafer materials of the RF switch and the low-noise amplifier are the same, and the wafer materials of the duplexer and the piezoelectric filter are the same, the above power amplifier is located in the gallium arsenide epitaxy, the above low-noise amplifier and RF switch are both located in the single-crystalline silicon epitaxy, and the above piezoelectric filter and duplexer are both located in the piezoelectric epitaxy. It should be noted that according to actual requirements, each of the above types of epitaxial partitions may include one or more, and the RF devices with the same wafer material may be located in different epitaxial partitions.

[0042] Preferably, the epitaxial layer of the above radio frequency front-end chip includes three epitaxial partitions, namely a gallium arsenide epitaxy, a single-crystalline silicon epitaxy, and a piezoelectric epitaxy. Multiple power amplifiers can be integrated on one gallium arsenide epitaxy, multiple low-noise amplifiers and multiple radio frequency switches can be integrated on one single-crystalline silicon epitaxy, and multiple piezoelectric filters and multiple duplexers can be integrated on one piezoelectric epitaxy. This way can further improve the integration of the radio frequency front-end chip.

[0043] Exemplarily, the epitaxial layer of the above radio frequency front-end chip includes more than three epitaxial partitions, such as one gallium arsenide epitaxy, two single-crystalline silicon epitaxies, and two piezoelectric epitaxies. Among them, power amplifiers can be integrated on the gallium arsenide epitaxy, low-noise amplifiers and radio frequency switches are respectively integrated on different single-crystalline silicon epitaxies, and piezoelectric filters and duplexers can be integrated on different piezoelectric epitaxies. This way can provide convenience for the fabrication of the radio frequency front-end chip.

[0044] In one embodiment, the material for fabricating the gallium arsenide epitaxy is a gallium arsenide layer structure, the material for fabricating the single-crystalline silicon epitaxy is single-crystalline silicon, and the material for fabricating the above piezoelectric epitaxy is any one of piezoelectric materials such as lithium tantalate, lithium niobate, or aluminum nitride. Among them, the above gallium arsenide layer structure may include an emitter cap, a P-type gallium arsenide base region, an n-type indium gallium phosphide emitter, an n-type gallium arsenide collector, and a gallium arsenide substrate. The above gallium arsenide layer structure as the gallium arsenide epitaxy can achieve high efficiency, high stability, and low noise of the power amplifier, ensuring the performance of the radio frequency front-end chip.

[0045] In one embodiment, please refer to Figure 4 , the above radio frequency front-end chip further includes a plurality of pads 13 and a substrate 15. The above pads 13 are located on the surface of the epitaxial layer 12, one end is electrically connected to the epitaxial layer 12, and the other end is used for electrical connection with a plurality of through holes 105 of the substrate 15. The through holes 105 of the substrate 15 are used for grounding to realize the electrical path of the radio frequency front-end chip. The above substrate 15 is used to provide structural support and electrical path for the radio frequency front-end chip. Optionally, a metal connection layer 14 is provided between the above pads 13 and the substrate 15. The above metal connection layer 14 is used to provide good conductivity and support for the chip and the substrate, and the material of the above metal connection layer 14 is preferably copper.

[0046] Please refer to Figure 5 , the present application also provides a method for fabricating an epitaxial partition integrated radio frequency front-end chip, and the method includes the following steps:

[0047] S1: Using a silicon substrate as a substrate layer, growing silicon dioxide on the substrate layer to form a layer of silicon dioxide layer, and using the silicon dioxide layer as a buffer layer.

[0048] S3: Use gallium arsenide material, single-crystalline silicon material, and piezoelectric material respectively to grow at different positions on the buffer layer to form multiple epitaxial regions, where the epitaxial regions include gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy.

[0049] S5: Deposit a metal layer on each of the epitaxial regions, and coat a photoresist layer with a specific shape on the metal layer. Based on the photoresist layer, corresponding metal devices and interconnection networks are etched on the metal layer of each of the epitaxial regions.

[0050] In this embodiment, a buffer layer and an epitaxial layer are sequentially grown on a silicon substrate. Specifically, a silicon dioxide layer can be grown on the silicon substrate as the buffer layer by thermal oxidation or oxygen implantation isolation, and by controlling the thickness of the buffer layer, good insulation performance can be ensured. Further, different epitaxial regions are grown at different positions above the buffer layer to achieve heterogeneous integration and regional epitaxy. For example, gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy are grown in different regions respectively. The above-mentioned gallium arsenide epitaxy can be grown in a specific region according to chemical vapor deposition by controlling parameters such as gas flow rate, pressure, and temperature. The above-mentioned single-crystalline silicon epitaxy can be grown in a specific region according to molecular beam epitaxy technology by controlling the molecular beam flow rate and growth temperature. The above-mentioned piezoelectric epitaxy can also be grown in a specific region by chemical vapor deposition. During the growth process, the growth situation of the epitaxial layer can be monitored in real time to ensure that the thickness and quality of the epitaxial layer meet the requirements.

[0051] Further, metal copper is coated on each epitaxial region of the epitaxial layer to form a metal layer, and a specific mask pattern is formed on the metal layer by photolithography. Photolithography is performed through a set of photomasks to ensure that the mask patterns of different epitaxial regions are accurately aligned with the epitaxial regions. By defining the shapes and positions to be etched in each epitaxial region in the form of a specific mask pattern, the metal etching and deposition of subsequent related devices are completed. Further, pads can be etched on the epitaxial regions, and through wire bonding or flip-chip technology, the pads of the chip are connected to the wiring on the substrate to achieve the electrical connection between the chip and the substrate.

[0052] In one embodiment, after the above S5 step, the metal layer is cleaned to remove the photoresist layer and metal impurities on the upper surface of the metal layer, and the cleaned metal layer is annealed to make the metal layer in close contact with the epitaxial region, improving the reliability and conductivity of the metal connection. Optionally, the substrate on the back of the chip can also be processed, including thinning, polishing, or etching, etc., to enhance device isolation and improve the performance and reliability of the chip.

[0053] In one embodiment, the metal devices at least include a power amplifier, a low-noise amplifier, a radio frequency switch, and a piezoelectric filter. Please refer toFigure 6 , on the basis of the above step S5, it includes step S51 and step S53:

[0054] S51: Coating photoresist on the upper surface of the metal layer, exposing and developing the metal layer coated with photoresist to form a photoresist layer with a specific shape on the surface of the metal layer;

[0055] S53: According to the specific shape of the photoresist layer, sequentially etch out the transistors and interconnection metal structures of the power amplifier on the gallium arsenide epitaxy, etch out the transistors and interconnection metal structures of the low-noise amplifier and the electrodes and interconnection metal structures of the radio frequency switch on the single-crystalline silicon epitaxy, etch out the electrodes and interconnection metal structures of the piezoelectric filter on the piezoelectric epitaxy, and etch out one or more passive devices and interconnection metal structures on each epitaxial partition.

[0056] In this embodiment, a photoresist layer is coated on the upper surface of the metal layer, and a specific pattern is exposed on the photosensitive layer, and a photoresist layer with a specific pattern is formed as a mask pattern through the steps of developing and cleaning. Among them, after the photolithography step, part of the area of the metal layer is exposed on the surface and removed by etching, while the area of the metal layer not covered is retained to form a radio frequency device with a specific pattern. The above specific pattern can be understood as the pattern of the metal structure required for each metal device to be formed.

[0057] In this embodiment, the design of the photomask needs to precisely match the metal structures of the devices in each epitaxial partition. For example, the above power amplifier needs to define the transistors and interconnection metal patterns of the emitter, base, and collector, the above low-noise amplifier needs to define the pattern of the transistors and interconnection metal structures of the low-noise amplifier, the above radio frequency switch needs to define the electrodes and interconnection metal structures of the radio frequency switch, and the above piezoelectric filter needs to define the pattern of the electrodes and interconnection metal of the piezoelectric filter.

[0058] Furthermore, etch each epitaxial partition separately. For example, etch out the emitter, base, collector, and interconnection network of the power amplifier on the metal layer and part of the gallium arsenide epitaxy of the gallium arsenide epitaxy. The above emitter, base, and collector are sequentially etched into the emitter material, base material, and collector material of the gallium arsenide epitaxy. And, etch out the input and output network and transistors such as gates, drains, and sources and interconnection metal paths on the single-crystalline silicon epitaxy. And, etch out the metal electrodes and interconnection metal paths on the piezoelectric epitaxy.

[0059] Based on the above embodiments, the specific shape further includes the patterns of the electrodes of the duplexer and the interconnection metal structure. The metal device further includes a duplexer. The step S53 further includes etching the electrodes and the interconnection metal structure of the RF switch on the single-crystalline silicon epitaxy according to the specific shape of the photoresist layer, including the control electrode, the ground electrode, and the interconnection metal path, and etching the electrodes and the interconnection metal structure of the duplexer on the piezoelectric epitaxy, including the filter electrodes, the common terminal contacts, the receiving-end circuit, the transmitting-end circuit, and other interconnection metal structures. In addition, it is also necessary to etch one or more passive devices such as capacitors and inductors required in each epitaxial partition, as well as the interconnection metal structures required for each passive device.

[0060] Based on the above description, while achieving the high integration of the RF front-end chip, the production efficiency of the RF front-end chip can also be improved. Specifically, in the process of manufacturing the RF front-end chip, since each device is integrated on the same substrate in different epitaxial forms, a single photomask can be used synchronously during photolithography, while in the manufacture of traditional RF front-end chips, a separate RF chip is fabricated for each RF device, and each RF chip uses a separate photomask. Therefore, the technical solution provided by the embodiments of the present application simplifies the process flow of the RF front-end chip, thereby improving the production efficiency of the RF front-end chip.

[0061] The chip described above can be implemented by a product with a certain function. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0062] It should be noted that the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, commodity or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, commodity or device including said element.

[0063] It should be noted that in this application, unless otherwise clearly specified and limited, when the first feature is "or" the second feature, it may be that the first feature is in direct contact with the second feature, or the first feature and the second feature are in indirect contact through an intermediate medium. Moreover, when the first feature is "above", "over" or "on" the second feature, it may be that the first feature is directly above or obliquely below the second feature, or it merely means that the horizontal height of the first feature is higher than that of the second feature. When the first feature is "under", "below" or "beneath" the second feature, it may be that the first feature is directly below or obliquely below the second feature, or it merely means that the horizontal height of the first feature is less than that of the second feature.

[0064] It should be noted that an element is referred to as being "fixed to" or "disposed on" another element, and it can be directly on the other element or there may also be an intermediate element. An element is considered to be "connected to" another element, and it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are only for the purpose of illustration and do not represent the only implementation manner.

[0065] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. The key point of each embodiment is to illustrate the differences from other embodiments. For the relevant parts, reference can be made to the partial descriptions of other embodiments. The multiple embodiments provided in this application are used to illustrate the implementation manners of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments.

[0066] It should be noted that the diagrams provided in the above embodiments only illustrate the basic concept of this application in a schematic manner. The diagrams only show the elements related to this application and are not drawn according to the number, shape and size of the elements in actual implementation. The type, quantity and proportion of each element in its actual implementation can be arbitrarily changed, and the element layout type may also be more complex.

[0067] The above are only the embodiments of this application and are not used to limit this application. For those skilled in the art, various changes and modifications can be made to this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application should be included within the protection scope of this application.

[0068] Although the embodiments of this application are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An epitaxial partition integrated radio frequency front-end chip, characterized in that The radio frequency front-end chip includes a substrate layer, a buffer layer, and an epitaxial layer. The epitaxial layer includes a plurality of epitaxial partitions. The radio frequency front-end chip integrates at least a power amplifier, a low-noise amplifier, a radio frequency switch, and a piezoelectric filter. Among them: The buffer layer is disposed on the substrate layer, the epitaxial layer is disposed on the buffer layer, and each of the epitaxial partitions is arranged arbitrarily on the epitaxial layer. The lower surface of the epitaxial partition is in contact with the upper surface of the buffer layer; The power amplifier, the low-noise amplifier, and the piezoelectric filter are respectively located in different epitaxial partitions. The low-noise amplifier and the radio frequency switch are located in the same epitaxial partition, and the materials of the epitaxial partitions where the power amplifier, the low-noise amplifier, and the piezoelectric filter are located are different.

2. The radio frequency front-end chip according to claim 1, wherein The epitaxial partition includes gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy. Among them: The power amplifier is located in the gallium arsenide epitaxy, the low-noise amplifier and the radio frequency switch are located in the single-crystalline silicon epitaxy, and the piezoelectric filter is located in the piezoelectric epitaxy.

3. The radio frequency front-end chip according to claim 2, wherein The radio frequency front-end chip also integrates a duplexer. Among them, the duplexer is located in the piezoelectric epitaxy.

4. The radio frequency front-end chip according to claim 2, wherein The gallium arsenide epitaxy includes a collector, an emitter, a base, and a buffer material.

5. The radio frequency front-end chip according to claim 2, characterized in that The material of the single-crystalline silicon epitaxy is single-crystalline silicon, and the material of the piezoelectric epitaxy is any one of lithium tantalate, lithium niobate, or aluminum nitride.

6. The radio frequency front-end chip according to claim 1, characterized in that The radio frequency front-end chip also includes bonding pads and a substrate. Among them: The bonding pads are located on the surface of the epitaxial partition, and the bonding pads are electrically connected to the epitaxial partition and the substrate respectively.

7. A manufacturing method of a radio frequency front-end chip with epitaxial partition integration, characterized in that, The method includes: Using a silicon substrate as the substrate layer, growing silicon dioxide on the substrate layer to form a layer of silicon dioxide layer, and using the silicon dioxide layer as the buffer layer; Respectively using gallium arsenide material, single-crystalline silicon material, and piezoelectric material to grow at different positions on the buffer layer to form a plurality of epitaxial partitions, and the epitaxial partitions include gallium arsenide epitaxy, single-crystalline silicon epitaxy, and piezoelectric epitaxy; Depositing a metal layer on each of the epitaxial partitions, and coating a photoresist layer with a specific shape on the metal layer. Based on the photoresist layer, corresponding metal devices and interconnection networks are etched on the metal layer of each of the epitaxial partitions.

8. The method according to claim 7, wherein After etching specific-shaped metal devices and interconnection networks on the metal layer of each of the epitaxial partitions based on the photoresist layer, the method further includes: Cleaning the metal layer to remove the photoresist layer and metal impurities on the upper surface of the metal layer, and annealing the cleaned metal layer.

9. The method according to claim 7, wherein The metal devices at least include a power amplifier, a low-noise amplifier, a radio frequency switch, and a piezoelectric filter; coating a photoresist layer with a specific shape on the metal layer, and etching specific-shaped metal devices and interconnection networks on the metal layer of each of the epitaxial partitions based on the photoresist layer includes: Coating photoresist on the upper surface of the metal layer, exposing and developing the metal layer coated with photoresist to form a photoresist layer with a specific shape on the surface of the metal layer; According to the specific shape of the photoresist layer, transistors and interconnection metal structures of the power amplifier are etched out on the gallium arsenide epitaxy in sequence, transistors and interconnection metal structures of the low-noise amplifier and electrodes and interconnection metal structures of the radio frequency switch are etched out on the single-crystalline silicon epitaxy, electrodes and interconnection metal structures of the piezoelectric filter are etched out on the piezoelectric epitaxy, and one or more passive devices and interconnection metal structures are etched out on each epitaxial partition.

10. The method according to claim 7 or 9, characterized in that, The metal device further includes a duplexer; etching out metal devices and interconnection networks with specific shapes on the metal layers of each of the epitaxial partitions based on the photoresist layer further includes: According to the specific shape of the photoresist layer, electrodes and interconnection metal structures of the duplexer are etched out on the piezoelectric epitaxy.

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