Semiconductor device and electronic system including the same

Abstract

A semiconductor device includes a semiconductor substrate, a transistor, a first interlayer insulating layer, a plurality of contacts, and a separation insulator. The transistor is on the semiconductor substrate. The transistor includes a gate structure, a source region, and a drain region. A first interlayer insulating layer is on the gate structure and the source and drain regions of the transistor. A plurality of contacts pass through the first interlayer insulating layer and are electrically connected to the source region and the drain region of the transistor. A separation insulator passes through the first interlayer insulating layer and extends to an interior of the semiconductor substrate at the transistor boundary. The plurality of contacts includes adjacent contacts adjacent to the separation insulator and spaced apart from the gate structure. The first interlayer insulating layer is interposed between the adjacent contact and the gate structure.

Description

Cross - reference to Related Applications

[0001] This application claims priority to Korean Patent Application No. 10 - 2024 - 0013290, filed with the Korean Intellectual Property Office on January 29, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device and an electronic system including the semiconductor device. Background Art

[0003] Semiconductor devices can perform various functions while having a small size, and thus are widely used in various electronic industries. The integration degree of semiconductor devices can be improved by reducing the distance between circuit elements (e.g., transistors) included in the semiconductor device. A shallow trench isolation (STI) region may exist between adjacent transistors to prevent electrical interference and leakage that may negatively affect performance and reliability. However, the STI region needs to maintain a certain distance from the transistors to prevent it from affecting the electrical characteristics of the transistors. Therefore, there is a limit to how much the distance can be reduced.

[0004] Accordingly, there is a need for a semiconductor device that allows transistors to be placed closer together to increase the integration degree without degrading performance. Summary of the Invention

[0005] The present disclosure attempts to provide a semiconductor device with a reduced size and a higher integration degree, and an electronic system including the semiconductor device.

[0006] A semiconductor device according to an embodiment includes a semiconductor substrate, a transistor, a first interlayer insulating layer, a plurality of contact parts, and a separation insulator. The transistor is disposed on the semiconductor substrate. The transistor includes a gate structure, and a source region and a drain region on opposite sides of the gate structure. The first interlayer insulating layer is disposed on the gate structure of the transistor and the source region and the drain region. The plurality of contact parts penetrate the first interlayer insulating layer. Each contact part is electrically connected to a corresponding one of the source region and the drain region. The separation insulator penetrates the first interlayer insulating layer and extends into the interior of the semiconductor substrate at the transistor boundary. The plurality of contact parts includes adjacent contact parts adjacent to the separation insulator and spaced apart from the gate structure. The first interlayer insulating layer is interposed between the adjacent contact parts and the gate structure.

[0007] A semiconductor device according to an embodiment includes a semiconductor substrate, a first transistor and a second transistor, a device isolation body, a first interlayer insulating layer, and a separation insulator. The first transistor and the second transistor are disposed on the semiconductor substrate. Each transistor includes a gate structure, and a source region and a drain region on opposite sides of the gate structure. The device isolation body is disposed in a portion of the semiconductor substrate. The first interlayer insulating layer is disposed on the gate structure, the source region and the drain region of each transistor, and the device isolation body. The separation insulator penetrates the first interlayer insulating layer and extends into the interior of the semiconductor substrate. The second transistor has an operating voltage higher than that of the first transistor. The device isolation body and the separation insulator are disposed at the boundary of the first transistor, and the device isolation body is disposed at the boundary of the second transistor.

[0008] An electronic system according to an embodiment includes a main substrate, a semiconductor device disposed on the main substrate, and a controller electrically disposed on the main substrate to be connected to the semiconductor device. The semiconductor device includes a semiconductor substrate, transistors, a first interlayer insulating layer, a plurality of contacts, and a separation insulator. The transistors are disposed on the semiconductor substrate. Each transistor includes a gate structure, and a source region and a drain region on opposite sides of the gate structure. The first interlayer insulating layer is disposed on the gate structure of the transistors and the source region and the drain region. The plurality of contacts penetrate the first interlayer insulating layer. Each contact is electrically connected to a corresponding one of the source region and the drain region of the transistor. The separation insulator penetrates the first interlayer insulating layer and extends into the interior of the semiconductor substrate at the transistor boundary. The plurality of contacts includes adjacent contacts adjacent to the separation insulator and spaced apart from the gate structure. The first interlayer insulating layer is interposed between the adjacent contacts and the gate structure.

[0009] According to an embodiment, a plurality of contacts (e.g., adjacent contacts) can be formed by using self-alignment with a separation insulator, and thus the margin for forming the plurality of contacts can be reduced. Accordingly, the distance between a plurality of transistors can be reduced, and thus, the circuit area or the size of the semiconductor device can be reduced, and the integration degree can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a partial cross-sectional view schematically showing a semiconductor device according to an embodiment.

[0011] Figure 2 shows Figure 1 an enlarged cross-sectional view of an example of a channel structure included in the semiconductor device shown in

[0012] Figure 3 is schematically showing Figure 1 a cross-sectional view of a circuit area included in the semiconductor device shown in

[0013] Figure 4 schematically shows Figure 1 a partial plan view of a circuit region included in the semiconductor device shown in

[0014] Figure 5 is a schematic cross-sectional view taken along Figure 4 lines B-B' and C-C' of

[0015] Figures 6 to 13 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment.

[0016] Figure 14 schematically shows a partial cross-sectional view of a circuit region included in a semiconductor device according to an embodiment.

[0017] Figure 15 schematically shows a partial cross-sectional view of a circuit region included in a semiconductor device according to an embodiment.

[0018] Figure 16 schematically shows a cross-sectional view of a semiconductor device according to an embodiment.

[0019] Figure 17 schematically shows a diagram of an electronic system including a semiconductor device according to an embodiment.

[0020] Figure 18 schematically shows a diagram of an electronic system including a semiconductor device according to an embodiment.

[0021] Figure 19 schematically shows a perspective view of a semiconductor package including a semiconductor device according to an embodiment.

[0022] Figure 20 schematically shows a perspective view of a semiconductor package including a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can practice the present disclosure. However, the present disclosure may be implemented in various different forms and is not limited to the embodiments provided herein.

[0024] Throughout the present specification, the same or similar components are denoted by the same reference numerals.

[0025] Although specific dimensions and thicknesses of parts, regions, components, units, layers, films, etc. shown in the drawings are shown for better understanding and facilitation of explanation, the present disclosure is not limited to the dimensions and thicknesses shown.

[0026] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

[0027] Furthermore, throughout the specification, the phrases "in a plane", "in the plane", "on a plan view", or "in a plan view" may indicate a situation of observing a part from above or the top, and the phrases "in a cross-section" or "in a cross-sectional view" may indicate a situation of observing a cross-section taken along a vertical direction from the side.

[0028] Hereinafter, reference will be made to Figures 1 to 13 describe in detail a semiconductor device according to an embodiment and a method of manufacturing the semiconductor device.

[0029] Figure 1 is a partial cross-sectional view schematically showing a semiconductor device according to an embodiment. Figure 2 shows Figure 1 an enlarged cross-sectional view of an example of a channel structure included in the semiconductor device shown in Figure 1 In Figure 1 a cross-sectional view of the circuit region 200 is shown, in which a gate structure 222g (see Figure 3 ), and a source region 222s and a drain region 222d (see Figure 3 ), are positioned together regardless of the extending direction D2 of the gate line 130.

[0030] Referring to Figure 1 and Figure 2 a semiconductor device 10 according to an embodiment includes a cell region 100 including a memory cell structure and a circuit region 200 including a peripheral circuit structure for controlling operations of the memory cell structure. For example, the circuit region 200 and the cell region 100 may respectively correspond to Figure 17 the first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 shown in Figure 19 For example, the circuit region 200 and the cell region 100 may be respectively parts of the first structure 3100 and the second structure 3200 of the semiconductor chip 2200 shown in

[0031] In an embodiment, the circuit region 200 includes peripheral circuit structures disposed on a first substrate 210, and the cell region 100 includes a gate stack structure 120 and a channel structure CH disposed on a second substrate 110 as a memory cell structure. In an embodiment, the circuit region 200 includes a first wiring portion 230, and the cell region 100 includes a second wiring portion 180 electrically connected to the memory cell structure.

[0032] In an embodiment, the cell region 100 is disposed on the circuit region 200. For example, the cell region 100 may be stacked on top of the circuit region 200. Accordingly, an area corresponding to the circuit region 200 does not need to be secured separately from the cell region 100. Thus, the area of the semiconductor device 10 can be reduced. However, the embodiment is not limited thereto. For example, the circuit region 200 may be disposed beside the cell region 100.

[0033] In an embodiment, the cell region 100 includes a cell array region 102 and a connection region 104. The gate stack structure 120 and the channel structure CH may be disposed on the second substrate 110 in the cell array region 102. Structures connecting the gate stack structure 120 and / or the channel structure CH in the cell array region 102 to the circuit region 200 or an external circuit may be disposed in the cell array region 102 and / or the connection region 104.

[0034] In an embodiment, the second substrate 110 includes a semiconductor layer containing a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate containing or formed of a semiconductor material, or may be a semiconductor substrate having a semiconductor layer disposed on a base substrate. For example, the second substrate 110 may include silicon, germanium, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI), or may be formed of silicon, germanium, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI). The semiconductor layer included in the second substrate 110 may be doped with a p-type dopant or an n-type dopant. The p-type dopant may include boron (B) or gallium (Ga), and the n-type dopant may include phosphorus (P) or arsenic (As). However, the embodiment is not limited to the material of the second substrate 110 or the conductivity type of the dopant doped in the semiconductor layer.

[0035] In the cell array region 102, the gate stack structure 120 and the channel structure CH may be placed. The gate stack structure 120 may include a cell insulating layer 132 and a gate line 130 alternately stacked on a first surface (e.g., a front surface or an upper surface) of the second substrate 110. The channel structure CH may extend in a direction (Z-axis direction in the figure) crossing the second substrate 110 while passing through or penetrating the gate stack structure 120.

[0036] In an embodiment, the horizontal conductive layers 112 and 114 are disposed between the second substrate 110 and the gate stack structure 120 in the cell array region 102. The horizontal conductive layers 112 and 114 may electrically connect (e.g., directly connect) the channel structure CH and the second substrate 110. The horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 and / or a second horizontal conductive layer 114 disposed in sequence on the second substrate 110. The first horizontal conductive layer 112 may be used as part of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 combined with the second substrate 110 may be used as the common source line.

[0037] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may include a semiconductor material (e.g., polysilicon), or be formed of a semiconductor material (e.g., polysilicon). For example, the first horizontal conductive layer 112 may include a polysilicon layer containing a dopant, or be formed of a polysilicon layer containing a dopant. However, the embodiment is not limited thereto. In the embodiment, the second horizontal conductive layer 114 includes a material different from that of the first horizontal conductive layer 112 (e.g., an insulating material), or is formed of a material different from that of the first horizontal conductive layer 112 (e.g., an insulating material). In another embodiment, the second horizontal conductive layer 114 is omitted.

[0038] The gate stack structure 120 may be disposed on the second substrate 110 (e.g., on the first horizontal conductive layer 112 and the second horizontal conductive layer 114 on the second substrate 110). The gate stack structure 120 may include a cell insulating layer 132 and a gate line 130 stacked alternately with each other.

[0039] The gate line 130 may include any one of various conductive materials. For example, the gate line 130 may include the following materials or be formed of the following materials: a metal material (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), polysilicon, a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)). As Figure 2 shown in the enlarged view, a partial portion (e.g., the first barrier layer 156a) including an insulating material or formed of an insulating material may be disposed outside the gate line 130. The cell insulating layer 132 may include any one of various insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than that of silicon oxide, or a combination thereof.

[0040] In the embodiment, there is a channel structure CH. The channel structure CH may extend in a direction intersecting the second substrate 110 (e.g., a vertical direction perpendicular to the second substrate 110, or the Z-axis direction in the figure) to pass through the gate stack structure 120.

[0041] In an embodiment, the channel structure CH includes a channel layer 140 and a gate dielectric layer 150 disposed on the channel layer 140 between the gate line 130 and the channel layer 140. As Figure 2 shown, the channel structure CH may further include a core insulating layer 142 disposed inside the channel layer 140. In some embodiments, the core insulating layer 142 is omitted. The channel structure CH may further include a channel pad 144 disposed on the channel layer 140 and / or the gate dielectric layer 150. In an embodiment, the gate dielectric layer 150 between the gate line 130 and the channel layer 140 includes a tunneling layer 152, a charge storage layer 154, and a blocking layer 156 sequentially disposed on the channel layer 140.

[0042] Each channel structure CH may form a memory cell string, and a plurality of channel structures CH may be spaced apart from each other in a plan view while forming rows and columns. For example, a plurality of channel structures CH may be arranged to form any one of various shapes (e.g., a lattice shape or a zigzag shape) in a plan view. The channel structure CH may have a columnar shape. For example, the channel structure CH may have an inclined side surface such that the width of the channel structure CH decreases toward the second substrate 110 due to the aspect ratio. However, the embodiment is not limited thereto, and various modifications may be made to the arrangement, structure, shape, etc. of the channel structure CH.

[0043] The channel layer 140 may include a semiconductor material (e.g., polysilicon). The core insulating layer 142 may include or may be any one of various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0044] In an embodiment, the tunneling layer 152 includes an insulating material capable of tunneling charges (e.g., silicon oxide or silicon oxynitride). The charge storage layer 154 may be used as a data storage region, and the charge storage layer 154 may include or may be polysilicon or silicon nitride. In an embodiment, the blocking layer 156 includes an insulating material capable of preventing unwanted charges from flowing into the gate line 130. The blocking layer 156 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a dielectric constant higher than that of silicon oxide, or a combination thereof. In an embodiment, the blocking layer 156 includes a first blocking layer 156a including a portion horizontally extending on the gate line 130 and a second blocking layer 156b vertically extending between the first blocking layer 156a and the charge storage layer 154. In an embodiment, the first blocking layer 156a includes a first horizontal portion, a second horizontal portion, and a vertical portion connecting the horizontal portions.

[0045] However, various modifications may be made to the materials, stack structures, etc. of the channel layer 140, the core insulating layer 142, and the gate dielectric layer 150, and the embodiment is not limited thereto.

[0046] The channel pad 144 may cover the upper surface of the core insulating layer 142 and be configured to be electrically connected to the channel layer 140. The channel pad 144 may include a conductive material (e.g., doped polysilicon doped with a dopant), but the embodiment is not limited thereto.

[0047] In an embodiment, the gate stack structure 120 includes a plurality of gate stack structures 120a and 120b stacked in sequence. Then, the number of stacked gate lines 130 may be increased, and thus the number of memory cells may be increased in a stable structure. In Figure 1 FIG., the gate stack structure 120 including the first gate stack structure 120a and the second gate stack structure 120b is shown as an example. In some embodiments, the gate stack structure 120 includes a single gate stack structure, or three or more gate stack structures.

[0048] When the plurality of gate stack structures 120a and 120b are arranged as described above, the channel structure CH may include a plurality of channel structures CH1 and CH2 respectively passing through the plurality of gate stack structures 120a and 120b. The plurality of channel structures CH1 and CH2 may have a shape in which the plurality of channel structures CH1 and CH2 are connected to each other. In a cross-sectional view, each of the plurality of channel structures CH1 and CH2 may have an inclined side surface such that the width of each of the plurality of channel structures CH1 and CH2 decreases according to the aspect ratio toward the second substrate 110. A bent portion caused by the width difference of the plurality of channel structures CH1 and CH2 may be provided at the connection portion of the plurality of channel structures CH1 and CH2. In some embodiments, the plurality of channel structures CH1 and CH2 have inclined side surfaces that continuously extend without having a bent portion. In Figure 2 FIG., an example in which the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel structures CH1 and CH2 continuously extend to have an integrated structure is shown. However, in some embodiments, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel structures CH1 and CH2 are separately formed and electrically connected to each other. In some embodiments, a separate channel pad is additionally provided at the connection portion of the plurality of channel structures CH1 and CH2. Therefore, the embodiment is not limited to the shape of the plurality of channel structures CH1 and CH2 shown here.

[0049] In an embodiment, the gate stack structure 120 is divided into a plurality of parts in a plan view by a separation structure 146 that extends in a direction (e.g., a vertical direction or the Z-axis direction in the figure) intersecting the second substrate 110 and passes through the gate stack structure 120. The upper separation region 148 may be provided at a portion adjacent to the upper part of the gate stack structure 120. In a plan view, the plurality of separation structures 146 and / or the plurality of upper separation regions 148 may extend in the extension direction D2 of the gate line 130 and be spaced apart from each other at a predetermined interval in the lateral direction D1 of the gate line 130.

[0050] The separation structure 146 and / or the upper separation region 148 may be filled with any one of various insulating materials. For example, the separation structure 146 or the upper separation region 148 may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). However, the embodiment is not limited thereto, and various modifications may be made to the structure, shape, material, etc. of the separation structure 146 or the upper separation region 148.

[0051] The connection region 104 and the second wiring part 180 may be used to connect the gate stack structure 120 and the channel structure CH in the cell array region 102 to the circuit region 200 or an external circuit. The connection region 104 may be provided at the periphery of the cell array region 102, and a partial portion of the second wiring part 180 may be provided in the connection region 104.

[0052] The second wiring part 180 may include members that electrically connect the gate line 130, the channel structure CH, the horizontal conductive layers 112 and 114, and / or the second substrate 110 to the circuit region 200 or an external circuit. For example, the second wiring part 180 may include a bit line 182, a gate contact part 184, a source contact part 186, a via plug 188, a contact via 180a, and a connection wiring 190. The contact via 180a may connect to each of the bit line 182, the gate contact part 184, the source contact part 186, and / or the via plug 188. The connection wiring 190 may electrically connect the bit line 182, the gate contact part 184, the source contact part 186, the via plug 188, and / or the contact via 180a.

[0053] The bit line 182 may extend in a lateral direction D1 that is transverse to the extension direction D2 of the gate line 130. The bit line 182 may be electrically connected to the channel structure CH (e.g., the channel pad 144) through a contact via 180a (e.g., a bit line contact via).

[0054] In the connection region 104, a plurality of gate contact portions 184 may penetrate the cell insulating layer 132 to be electrically connected to a plurality of gate lines 130 extending to the connection region 104, respectively. In the figure, as an example, a plurality of gate lines 130 are shown to have a stepped or stepped shape in one or more directions in the connection region 104, but the embodiment is not limited thereto. In the connection region 104, a source contact portion 186 may penetrate the cell insulating layer 132 to be electrically connected to the horizontal conductive layers 112 and 114 and / or the second substrate 110. The via plug 188 may penetrate the gate stack structure 120 or may be disposed outside the gate stack structure 120 to be electrically connected to the first wiring portion 230 of the circuit region 200.

[0055] In Figure 1 it, the following example is shown: In a cross-sectional view, each of the gate contact portion 184, the source contact portion 186, and / or the via plug 188 has an inclined side surface such that the width of each of the gate contact portion 184, the source contact portion 186, and / or the via plug 188 decreases toward the second substrate 110 due to the aspect ratio, and a bent portion is provided at a boundary portion between the plurality of gate stack structures 120a and 120b. However, the embodiment is not limited thereto. In some embodiments, the gate contact portion 184, the source contact portion 186, and / or the via plug 188 may not include a bent portion at a boundary portion between the plurality of gate stack structures 120a and 120b.

[0056] In Figure 1 it, the following example is shown: The connection wiring 190 is a single layer on the same plane as the bit line 182, and the second insulating layer 192 is provided at portions other than the second wiring portion 180. However, the embodiment is not limited thereto. To be electrically connected to the bit line 182, the gate contact portion 184, the source contact portion 186, and / or the via plug 188, the connection wiring 190 may include a plurality of wiring layers and may also include contact vias.

[0057] Due to the second wiring portion 180 and the first wiring portion 230, the bit line 182, the gate line 130, the horizontal conductive layers 112 and 114, and / or the second substrate 110 connected to the channel structure CH may be electrically connected to the circuit element 220 of the circuit region 200.

[0058] The circuit region 200 may include a first substrate 210, and circuit elements 220 and a first wiring portion 230 provided on the first substrate 210.

[0059] The first substrate 210 may be a semiconductor substrate including a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate including or formed of a semiconductor material, or may also be a semiconductor substrate in which a semiconductor layer is disposed on a base substrate. For example, the first substrate 210 may include single-crystalline or polycrystalline silicon, epitaxial silicon, germanium, silicon germanium, silicon-on-insulator, or germanium-on-insulator.

[0060] The circuit elements 220 disposed on the first substrate 210 may include various circuit elements that control the operation of the memory cell structure in the control unit region 100. For example, the circuit elements 220 may constitute peripheral circuit structures such as a decoder circuit 1110 (see Figure 17 ), a page buffer 1120 (see Figure 17 ), or a logic circuit 1130 (see Figure 17 ). [[ID=Ill]]

[0061] The circuit elements 220 may include, for example, a plurality of transistors 222, but the embodiments are not limited thereto. In an embodiment, the plurality of transistors 222 includes a first transistor 222a and a second transistor 222b. This will be described in more detail later. The circuit elements 220 may include not only active elements such as transistors 222 but also passive elements such as capacitors, resistors, or inductors.

[0062] The first wiring portion 230 disposed on the first substrate 210 may be electrically connected to the circuit elements 220. In an embodiment, the first wiring portion 230 includes a plurality of wiring layers 236 that are spaced apart from each other while a first insulating layer 232 is inserted therebetween and are electrically connected through contact vias 234 to form a desired path. The wiring layer 236 or the contact via 234 may include any one of various conductive materials, and the first insulating layer 232 may include any one of various insulating materials. For example, among the plurality of wiring layers 236, the wiring layer 236 at the uppermost portion adjacent to the cell region 100 may include or constitute a pad portion connected to the gate contact portion 184, the source contact portion 186, or the through plug 188.

[0063] Refer to Figure 3 and Figure 1 and Figure 2 , and the circuit region 200 including the plurality of transistors 222 and the contact portions (e.g., the gate contact portion 234g and the plurality of contact portions 2341) connected to the plurality of transistors 222 will be described in more detail.

[0064] Figure 3 is a schematic cross-sectional view showing Figure 1 the circuit region 200 included in the semiconductor device 10 shown in Figure 4 is a schematic illustration ofFigure 1 A partial plan view of a circuit region 200 included in the semiconductor device 10 shown in Figure 5 is a schematic cross-sectional view taken along line B-B' and line C-C' of Figure 4

[0065] Figure 3 A cross-sectional view of the circuit region 200 is shown, in which the gate structure 222g, the source region 222s, and the drain region 222d are positioned together. In the Figure 3 left portion of Figure 3 a first transistor region A1 in which the first transistor 222a is provided is shown. In the Figure 3 right portion of Figure 4 a second transistor region A2 in which the second transistor 222b is provided is shown. Figure 3 The left portion of Figure 4 is a cross-sectional view taken along line A-A' of Figure 4 is a plan view of the first transistor region A1 in which the first transistor 222a is provided. For ease of illustration and clear understanding, Figure 4 mainly shown in

[0066] are the gate structure 222g, the source region 222s, and the drain region 222d, the gate contact portion 234g connected to the gate structure 222g, and a plurality of contact portions 2341 connected to the source region 222s and the drain region 222d.

[0066] Refer to Figures 1 to 5 , in an embodiment, a plurality of transistors 222 are provided at or on the first substrate 210. In this example, each of the plurality of transistors 222 may include a gate structure 222g on the first substrate 210, and a source region 222s and a drain region 222d. The gate structure 222g may include a gate insulating layer 224, a gate electrode 226, a gate capping layer 228, and a gate spacer 229.

[0067] In an embodiment, each transistor 222 has a planar structure. That is, the gate insulating layer 224 may horizontally extend on the surface of the first substrate 210, and the gate electrode 226 may horizontally extend on the gate insulating layer 224. In a plan view, the source region 222s and the drain region 222d may be provided on both sides of the gate structure 222g. The transistor 222 having a planar type can be stably applied to a memory device (e.g., a flash memory device) including a plurality of transistors 222 having various operating voltages or performing various functions.

[0068] The gate capping layer 228 may be disposed on the gate electrode 226, and the gate spacer 229 may be disposed on the side surface of the gate electrode 226. The gate capping layer 228 may be used as a mask layer when forming the gate insulating layer 224 and the gate electrode 226. The gate spacer 229 may separate the gate structure 222g from the source region 222s and the drain region 222d. For example, the gate spacer 229 may extend in the first direction (the X direction in the figure) on both sides in the second direction (the Y direction in the figure) transverse to the first direction. The first direction may be parallel to the extending direction of the gate structure 222g, and the second direction may be the direction in which the gate structure 222g and the source region 222s and the drain region 222d are located together.

[0069] In the drawings, as an example, the gate spacer 229 is shown disposed on the side surface of the gate capping layer 228. In some embodiments, the gate capping layer 228 may be disposed on the gate spacer 229.

[0070] The gate insulating layer 224 may include at least one of an oxide, a nitride, an oxynitride, a high-k material having a dielectric constant higher than that of silicon oxide, or a low-k material having a dielectric constant lower than that of silicon oxide. For example, the first gate insulating layer 224 may include at least one of silicon oxide, silicon nitride, oxynitride, hafnium oxide, aluminum oxide, or tantalum oxide. The gate insulating layer 224 may include a single insulating layer or may include a plurality of insulating layers.

[0071] The gate electrode 226 may include or may be a conductive material. For example, the gate electrode 226 may include at least one of a metal, a metal alloy, a metal nitride, a metal silicide, or a doped semiconductor material. Here, the metal or metal alloy included in the gate electrode 266 may include at least one of titanium, tungsten, molybdenum, aluminum, copper, cobalt, tantalum, or ruthenium. The metal nitride included in the gate electrode 266 may include at least one of titanium nitride, tungsten nitride, molybdenum nitride, or tantalum nitride. The gate electrode 266 may also include a metal oxide or a metal oxynitride in which the above materials are oxidized. The doped semiconductor material may include a semiconductor material doped with an n-type dopant or a p-type dopant (e.g., a polycrystalline semiconductor material).

[0072] Although an example in which the gate electrode 226 includes a first electrode layer 226a including a semiconductor layer and a second electrode layer 226b including a metal-containing layer containing a metal has been discussed, the embodiments are not limited thereto. For example, various modifications may be made to the material, stack structure, etc. of the gate electrode 226.

[0073] The gate capping layer 228 may include any one of various insulating materials (e.g., oxide, nitride, or oxynitride). For example, the gate capping layer 228 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride, or may be formed of at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0074] The gate spacer 229 may include any one of various insulating materials (e.g., oxide, nitride, oxynitride, or low-k material). For example, the gate spacer 229 may include or be formed of the following: a material containing at least one of silicon oxide, silicon nitride, or silicon oxynitride, or a material additionally including carbon in the above materials. The gate spacer 229 may include a single insulating layer or may include multiple insulating layers.

[0075] The source region 222s and the drain region 222d may include a doped region formed by doping a local portion of the first substrate 210, or may be formed of a doped region formed by doping a local portion of the first substrate 210. For example, the source region 222s and the drain region 222d may be portions formed by doping an n-type dopant or a p-type dopant into a local portion of the first substrate 210. In this case, the conductivity type of the dopant included in the source region 222s and the drain region 222d may be opposite to the conductivity type of the dopant included in the first substrate 210.

[0076] However, the embodiments are not limited thereto. In some embodiments, the gate insulating layer 224, the gate electrode 226, the gate capping layer 228, the gate spacer 229, and / or the source region 222s and the drain region 222d may have any one of various materials, structures, etc.

[0077] In an embodiment, the plurality of transistors 222 includes a first transistor 222a and a second transistor 222b having different operating voltages. For example, the first transistor 222a may be a low-voltage (LV) transistor having a relatively low operating voltage, and the second transistor 222b may be a high-voltage (HV) transistor having an operating voltage higher than or greater than the operating voltage of the first transistor 222a.

[0078] For example, the operating voltage range of the first transistor 222a may be from about 0.1 V to about 10 V, and the operating voltage of the second transistor 222b may be greater than the operating voltage of the first transistor 222a and may range from about 10 V to about 100 V. However, the embodiments are not limited to these ranges of supply voltages.

[0079] The first transistor 222a, being a low-voltage transistor, can have high-speed operation characteristics and excellent reliability, and thus can be applied in embodiments that require high-speed operation. The second transistor 222b, being a high-voltage transistor, can be applied in embodiments that require generating or transmitting high voltage. For example, at least a part of the transistors included in the page buffer 1120 (see Figure 17 ), can be the first transistor 222a, and at least a part of the transistors included in the decoder circuit 1110 (see Figure 17 ) can be the second transistor 222b.

[0080] In an embodiment, the thickness of the gate insulating layer 224 in the first transistor 222a is less than the thickness of the gate insulating layer 224 in the second transistor 222b. The channel length (the distance between the source region 222s and the drain region 222d) in the first transistor 222a can be less than the channel length (the distance between the source region 222s and the drain region 222d) in the second transistor 222b. The width of the gate electrode 226 of the first transistor 222a in the second direction (the Y direction in the figure) can be less than the width of the gate electrode 226 of the second transistor 222b in the second direction. Thus, the second transistor 222b, being a high-voltage transistor, can stably withstand the high potential difference between the gate electrode 226 and the source region 222s and the drain region 222d.

[0081] For example, the lower surface of the gate insulating layer 224 included in the first transistor 222a can be higher than the lower surface of the gate insulating layer 224 included in the second transistor 222b, and the upper surface of the gate insulating layer 224 included in the first transistor 222a and the upper surface of the gate insulating layer 224 included in the second transistor 222b can be in the same plane. In some embodiments, the lower surface of the gate insulating layer 224 included in the first transistor 222a and the lower surface of the gate insulating layer 224 included in the second transistor 222b are in the same plane, and the upper surface of the gate insulating layer 224 included in the second transistor 222b is higher than the upper surface of the gate insulating layer 224 included in the first transistor 222a.

[0082] In Figure 1In this case, the following examples are shown: A plurality of first transistors 222a or a first transistor region A1 are disposed below the cell array region 102, and a plurality of second transistors 222b or a second transistor region A2 are disposed below the connection region 104. However, the embodiments are not limited thereto. At least one of the first transistor 222a and the second transistor 222b may be disposed below the cell array region 102, or at least one of the first transistor region A1 or the second transistor region A2 may be disposed below the cell array region 102. At least one of the first transistor 222a and the second transistor 222b may be disposed below the connection region 104, or at least one of the first transistor region A1 or the second transistor region A2 may be disposed below the connection region 104. In addition, various modifications can be made to the positions of the first transistor 222a and the second transistor 222b.

[0083] The capping layer 244 may cover the gate structure 222g on the first surface 2101 (e.g., the front surface or the upper surface) of the first substrate 210. The capping layer 244 may be entirely on the first surface 2101 of the first substrate 210, as well as the upper surface and the side surfaces of the gate structure 222g in a region except for the gate contact portion 234g and the plurality of contact portions 2341. The capping layer 244 may be a layer that prevents an undesired diffusion of dopants doped in the source region 222s and the drain region 222d. According to an embodiment, a buffer layer 242 may also be disposed between the first surface 2101 of the first substrate 210 and the capping layer 244. The buffer layer 242 may be a layer for compensating for the lattice constant difference between the first substrate 210 and the capping layer 244.

[0084] For example, the capping layer 244 may include silicon nitride or silicon oxynitride, and the buffer layer 242 may include silicon oxide. However, the embodiments are not limited thereto. The capping layer 244 or the buffer layer 242 may include any one of various materials. In some embodiments, the buffer layer 242 is omitted.

[0085] The first interlayer insulating layer 232m may be disposed on the gate structure 222g and the capping layer 244 on the first substrate 210. The first interlayer insulating layer 232m may be entirely on the first surface 2101 of the first substrate 210 and on the capping layer 244 on the upper surface and side surfaces of the gate structure 222g in a region other than the gate contact portion 234g and the plurality of contact portions 2341. In this case, the first interlayer insulating layer 232m may include an upper portion 232u disposed on the gate structure 222g, and a side portion 232l disposed on the source region 222s and the drain region 222d on one side of the first surface 2101 of the first substrate 210. The side portion 232l may be disposed on the side surface of the gate structure 222g (more specifically, the side surface of the capping layer 244 on the side surface of the gate structure 222g) in a region where the gate structure 222g is not located. The side portion 232l may fill the space between adjacent gate structures 222g (more specifically, the space between the capping layers 244 on the side surfaces of adjacent gate structures 222g), or fill the space between the gate structure 222g and the isolation insulator 214 adjacent to each other (more specifically, the space between the capping layer 244 on the side surface of the gate structure 222g adjacent to each other and the isolation insulator 214).

[0086] The gate contact portion 234g and the plurality of contact portions 2341 may pass through or penetrate the first interlayer insulating layer 232m, the capping layer 244, and / or the buffer layer 242. For example, the gate contact portion 234g may pass through the first interlayer insulating layer 232m, the capping layer 244, and the gate capping layer 228 to be electrically connected to the gate electrode 226. The plurality of contact portions 2341 may include a source contact portion 234s connected to the source region 222s and a drain contact portion 234d connected to the drain region 222d. The source contact portion 234s and the drain contact portion 234d may pass through the first interlayer insulating layer 232m, the capping layer 244, and the buffer layer 242. The first wiring layer 2361 connected to the gate contact portion 234g and the plurality of contact portions 2341 connected to the second transistor 222b may be disposed on the first interlayer insulating layer 232m. One or more second interlayer insulating layers 232n and one or more second wiring layers 2362 may also be disposed on the first wiring layer 2361.

[0087] In an embodiment, the device isolation body 212 and the isolation insulator 214 are disposed on one side of the first surface 2101 of the first substrate 210. The device isolation body 212 and the isolation insulator 214 may be disposed at one or more boundaries of the plurality of transistors 222 to isolate the active regions of the plurality of transistors 222 on one side of the first surface 2101 of the first substrate 210.

[0088] More specifically, the device isolation body 212 may be disposed at a local portion of the boundary of the first transistor 222a, and the isolation insulator 214 may be disposed at another local portion of the boundary of the first transistor 222a.

[0089] For example, in the first transistor region A1, the device isolation body 212 may be disposed at one or more boundaries on one or both sides of the first transistor 222a in the first direction (the X direction in the figure) and may extend in the second direction (the Y direction in the figure). Thus, the device isolation body 212 may separate the active regions of a plurality of transistors 222 adjacent to each other in the first direction on one side of the first surface 2101 of the first substrate 210. In the first transistor region A1, the isolation insulator 214 may be disposed at one or more boundaries on one or both sides of the first transistor 222a in the second direction (the Y direction in the figure) and may extend in the first direction (the X direction in the figure). For example, the isolation insulator 214 may separate the source regions 222s and the drain regions 222d of the plurality of transistors 222 on one side of the first surface 2101 of the first substrate 210. For example, the isolation insulator 214 may be disposed to space the source region 222s and the drain region 222d apart from each other by a certain distance.

[0090] In the first direction (the X direction in the figure), that is, in the extending direction of the gate structure 222g, the interval between the first transistors 222a may be relatively large to ensure the insulation characteristics. For example, the first interval of the first transistors 222a in the first direction (the X direction in the figure) may be greater than the second interval of the first transistors 222a in the second direction (the Y direction in the figure). Accordingly, the isolation insulator 214 may be formed at the boundaries of the first transistors 222a having a relatively small interval to reduce the interval between the plurality of contact portions 2341. However, the embodiment is not limited thereto. For example, various modifications may be made to the position of the isolation insulator 214.

[0091] In the embodiment, the device isolation body 212 is disposed at the boundary of the second transistor 222b, and the isolation insulator 214 may not be at the boundary of the second transistor 222b. More specifically, in the second transistor region A2, the device isolation body 212 may include a portion extending in the second direction (the Y direction in the figure) at one or more boundaries on one or both sides of the second transistor 222b in the first direction (the X direction in the figure), and another portion extending in the first direction and at one or more boundaries on one or both sides of the second transistor 222b in the second direction.

[0092] Since the second transistor 222b is a high-voltage transistor having a relatively large operating voltage, the pitch between the second transistors 222b in the second direction (the Y direction in the figure) can be greater than the second pitch between the first transistors 222a in the second direction. Accordingly, the isolation insulator 214 for reducing the pitch between the plurality of contact portions 2341 may not be formed at the boundary of the second transistors 222b. However, the embodiments are not limited thereto. For example, the isolation insulator 214 may be provided at at least a part of the boundary of the second transistors 222.

[0093] In an embodiment, the width of the device isolation 212 extending in the second direction (the Y direction in the figure) at the boundary of the first transistors 222a is smaller than the width of the device isolation 212 extending in the second direction at the boundary of the second transistors 222b. Here, the width of the device isolation 212 may refer to the width in a direction transverse to the extending direction of the device isolation 212 (e.g., the maximum width of the device isolation 212). This is because the operating voltage of the second transistors 222b is greater than the operating voltage of the first transistors 222a. However, the embodiments are not limited thereto. For example, the width of the device isolation 212 extending in the second direction at the boundary of the first transistors 222a may be equal to or greater than the width of the device isolation 212 extending in the second direction at the boundary of the second transistors 222b.

[0094] In an embodiment, the width of the isolation insulator 214 extending in the first direction (the X direction in the figure) at the boundary of the first transistors 222a is smaller than the width of the device isolation 212 extending in the first direction at the boundary of the second transistors 222b. Here, the width of the isolation insulator 214 may refer to the width in a direction transverse to the extending direction of the isolation insulator 214 (e.g., the maximum width of the isolation insulator 214). This is because the operating voltage of the second transistors 222b is greater than the operating voltage of the first transistors 222a. However, the embodiments are not limited thereto. For example, the width of the isolation insulator 214 extending in the first direction at the boundary of the first transistors 222a may be equal to or greater than the width of the device isolation 212 extending in the first direction at the boundary of the second transistors 222b.

[0095] In an embodiment, the device isolation 212 and the isolation insulator 214 may be formed by different processes and may be at different positions, have different structures, or include different materials or be formed of different materials.

[0096] For example, the device isolation body 212 may be an insulator having a shallow trench isolation (STI) structure for isolating the active regions of the first transistor 222a and the second transistor 222b. The device isolation body 212 may penetrate a local portion of the first substrate 210. For example, the device isolation body 212 may extend from the upper surface of the first substrate 210 into the interior of the first substrate 210. Accordingly, the surface (e.g., the upper surface) of the device isolation body 212 (adjacent to the surface of the first interlayer insulating layer 232m opposite to the first substrate 210) may be in the same plane as or adjacent to the first surface 2101 of the first substrate 210. Here, the phrase "two surfaces are in the same plane" may include the case where the two surfaces are exactly in the same plane, and the case where the two surfaces are formed by the same process (e.g., a forming process, an etching process, a polishing process, etc.) and are thus close to or adjacent to each other. Another surface (e.g., the lower surface) of the device isolation body 212 inside the first substrate 210 may be between the first surface 2101 of the first substrate 210 and the second surface 2102 (e.g., the lower surface) of the first substrate 210.

[0097] In a cross-sectional view (the YZ plane in the figure) perpendicular to the first direction (the X direction in the figure), the side surface of the device isolation body 212 may include an inclined surface or be formed by an inclined surface such that the width of the device isolation body 212 gradually decreases from the first surface 2101 of the first substrate 210 toward the second surface 2102 of the first substrate 210. The side surface of the device isolation body 212 may have an inclined surface by forming a trench for the device isolation body 212 via an etching process performed at the side surface of the first surface 2101 of the first substrate 210. However, the embodiments are not limited thereto. In some embodiments, the side surface of the device isolation body 212 may include a vertical surface perpendicular to the first substrate 210 or be formed by a vertical surface perpendicular to the first substrate 210.

[0098] The isolation insulator 214 may be an insulator having a trench isolation structure for isolating the active region of the first transistor 222a. The isolation insulator 214 may be a self-aligned insulator for self-aligning a plurality of contact portions 2341 for connecting to the source region 222s and the drain region 222d. It will be described in more detail below.

[0099] The isolation insulator 214 can pass through the first interlayer insulating layer 232m and a partial portion of the first substrate 210. More specifically, the isolation insulator 214 can pass through the first interlayer insulating layer 232m, the capping layer 244, and the buffer layer 242, and extend into the interior of the first substrate 210. That is to say, the isolation insulator 214 can include a first portion 214a and a second portion 214b. The first portion 214a can pass through the first interlayer insulating layer 232m, the capping layer 244, and the buffer layer 242. The second portion 214b can be disposed inside the first substrate 210.

[0100] For example, one surface (e.g., the upper surface) of the isolation insulator 214 (adjacent to the surface of the first interlayer insulating layer 232m opposite to the first substrate 210) can be disposed in the same plane as, or adjacent to, the surface of the first interlayer insulating layer 232m (i.e., the interface between the first interlayer insulating layer 232m and the first wiring layer 2361). Another surface (e.g., the lower surface) of the isolation insulator 214 in the first substrate 210 can be disposed between the first surface 2101 and the second surface 2102 of the first substrate 210.

[0101] Therefore, one surface (e.g., the upper surface) of the device isolation body 212 and one surface (e.g., the lower surface) of the isolation insulator 214 (adjacent to the surface of the first interlayer insulating layer 232m opposite to the first substrate 210) can be disposed at different heights or levels.

[0102] In an embodiment, another surface (e.g., the lower surface) of the device isolation body 212 in the first substrate 210 and another surface (e.g., the lower surface) of the isolation insulator 214 can be disposed at different heights or levels. In Figure 5 it, it is shown as an example that another surface of the isolation insulator 214 is higher than another surface of the device isolation body 212. This can prevent the height of the isolation insulator 214 from increasing excessively, but the embodiment is not limited thereto. In some embodiments, another surface of the isolation insulator 214 and another surface of the device isolation body 212 are in the same plane or level, or can be lower than another surface of the device isolation body 212.

[0103] In a cross-sectional view (the YZ plane in the figure) perpendicular to the first direction (the X direction in the figure), the recessed portion 214r may be provided on a side surface of the first portion 214a of the isolation insulator 214. The recessed portion 214r may be provided on one side of a surface (e.g., the upper surface) of the isolation insulator 214 (adjacent to the surface of the first interlayer insulating layer 232m opposite to the first substrate 210). The recessed portion 214r may be provided on both sides of the isolation insulator 214 in the second direction (the Y direction in the figure), and may have a concave circular surface, and may extend longitudinally in the first direction (i.e., the extending direction of the isolation insulator 214, the X direction in the figure). In a cross-sectional view (the YZ plane in the figure) perpendicular to the first direction (the X direction in the figure), a side surface of another portion of the isolation insulator 214 may have an inclined surface such that the width of the isolation insulator 214 gradually decreases toward the second surface 2102 of the first substrate 210.

[0104] The recessed portion 214r of the isolation insulator 214 may be formed in an etching process for forming third through-holes 232a and 232b (see Figure 10 ) for a plurality of contact portions 2341 (more specifically, a first adjacent contact portion 234a and a second adjacent contact portion 234b) provided on both sides of the isolation insulator 214. The isolation trench 214t (see Figure 7 ) for forming the isolation insulator 214 may be formed by an etching process performed on one side of a surface (e.g., the upper surface) of the first interlayer insulating layer 232m opposite to the first substrate 210. Accordingly, a side surface of another portion of the isolation insulator 214 may have an inclined surface. However, the embodiment is not limited thereto. In some embodiments, a side surface of another portion of the isolation insulator 214 may have a vertical surface perpendicular to the first substrate 210.

[0105] In an embodiment, an isolation buffer layer 216 having a material different from that of the isolation insulator 214 is provided between the first substrate 210 and the isolation insulator 214 (more specifically, between the first substrate 210 and the second portion 214b of the isolation insulator 214). The isolation buffer layer 216 may be a layer for compensating for the difference in lattice constants between the first substrate 210 and the isolation insulator 214. However, the embodiment is not limited thereto. In an embodiment, the isolation buffer layer 216 is omitted.

[0106] In an embodiment, the isolation insulator 214 includes a material different from that of the device isolation body 212 or is formed of a material different from that of the device isolation body 212. This is because the isolation insulator 214 can be formed by a process different from the process for forming the device isolation body 212 and can perform a function different from that of the device isolation body 212. The isolation insulator 214 may include a material different from that of the first insulating layer 232 (e.g., the first interlayer insulating layer 232m) or be formed of a material different from that of the first insulating layer 232 (e.g., the first interlayer insulating layer 232m). For example, the isolation insulator 214 and the first interlayer insulating layer 232m may include materials having different etching selectivities. Accordingly, in the process of forming the through-holes 232g, 232e, 232a, and 232b (see Figure 10 ) for forming the gate contact portion 234g and the plurality of contact portions 2341 by etching a partial portion of the first interlayer insulating layer 232m, the isolation insulator 214 can be prevented from being completely removed.

[0107] For example, the first insulating layer 232 (e.g., the first interlayer insulating layer 232m) or the device isolation body 212 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material or be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material, and the isolation insulator 214 may include a material different from that of the first interlayer insulating layer 232m and at least one of silicon nitride, silicon oxynitride, silicon oxide, or silicon carbide or be formed of a material different from that of the first interlayer insulating layer 232m and at least one of silicon nitride, silicon oxynitride, silicon oxide, or silicon carbide. Here, the low-k material may be a material having a dielectric constant lower than that of silicon oxide.

[0108] For example, the first insulating layer 232 (e.g., the first interlayer insulating layer 232m) or the device isolation body 212 may include silicon oxide or be formed of silicon oxide, and the isolation insulator 214 may include silicon nitride or be formed of silicon nitride. The isolation buffer layer 216 may include silicon oxide or be formed of silicon oxide. However, the embodiment is not limited thereto. In some embodiments, the first insulating layer 232, the device isolation body 212, the isolation insulator 214, or the isolation buffer layer 216 may include or be formed of any one of various materials.

[0109] In an embodiment, as Figure 4 shown, the plurality of contact portions 2341 include adjacent contact portions 234a and 234b adjacent to (e.g., in contact with) the isolation insulator 214. The adjacent contact portion 234a or 234b may be a self-aligned contact portion formed to be in contact with the isolation insulator 214 and thus self-aligned through the isolation insulator 214.

[0110] In this case, the adjacent contact portions 234a or 234b may include a contact surface S1 in contact with the isolation insulator 214, and a covering surface S2 spaced apart from the isolation insulator 214 and surrounded by the first interlayer insulating layer 232m. That is, the adjacent contact portions 234a or 234b may be spaced apart from the gate structure 222g while being inserted into an upper portion of the gate structure 222g covered by the first interlayer insulating layer 232m and / or a partial portion of the capping layer 244 (more specifically, a side portion 232l of the first interlayer insulating layer 232m). More specifically, in a cross-sectional view (the YZ plane in the figure) perpendicular to the first direction (the X direction in the figure), the side portion 232l of the first interlayer insulating layer 232m may be disposed between the covering surface S2 of the adjacent contact portions 234a or 234b and a side surface of the gate structure 222g (more specifically, a side surface of the capping layer 244 on the side surface of the gate structure 222g).

[0111] When the side portion 232l is disposed between the gate structure 222g and the adjacent contact portions 234a or 234b, it is possible to prevent the adjacent contact portions 234a or 234b from having an adverse effect on the gate structure 222g during the process of forming the adjacent contact portions 234a or 234b. For example, during the process of forming the third through portions 232a and 232b (see Figure 10 ) for forming the adjacent contact portions 234a and 234b, damage or collapse of the gate structure 222g can be prevented. The height or thickness of the gate structure 222g may be independent of the adjacent contact portions 234a or 234b. For example, the height or thickness of the gate structure 222g may be less than the height of the adjacent contact portions 234a or 234b.

[0112] In the first transistor 222a having a planar structure, a sufficient distance between the adjacent contact portions 234a or 234b and the gate structure 222g can be ensured, thereby enhancing stability. In an embodiment including a plurality of transistors 222 driven by different operating voltages, the distance between the adjacent contact portions 234a or 234b and the gate structure 222g can be freely changed by using the side portion 232l.

[0113] In an embodiment, the isolation insulator 214 may have a shape extending in the first direction (the X direction in the figure). The adjacent contact portions 234a and 234b may include a first adjacent contact portion 234a and a second adjacent contact portion 234b. The first adjacent contact portion 234a may be disposed on a first side of the isolation insulator 214 in the second direction (the Y direction in the figure) (for example, Figure 4 the right side). The second adjacent contact portion 234b may be disposed on a second side of the isolation insulator 214 opposite to the first side of the isolation insulator 214 in the second direction (for example, Figure 4to the left side).

[0114] Third through-holes 232a and 232b for forming a first adjacent contact portion 234a and a second adjacent contact portion 234b into which a separation insulator 214 is inserted (see Figure 10 ) can be formed by using an opening 214n (more specifically, a third opening) that exposes a separation insulator 214 and includes portions on both sides of the separation insulator 214. The first adjacent contact portion 234a and the second adjacent contact portion 234b into which a separation insulator 214 is inserted can be disposed at the same position in a first direction (the X direction in the figure). In this case, the first adjacent contact portion 234a and the second adjacent contact portion 234b into which a separation insulator 214 is inserted can be self-aligned through the separation insulator 214.

[0115] In an embodiment, the plurality of contact portions 2341 further includes a separation contact portion 234e spaced apart from the separation insulator 214. The entire portion of the side surface of the separation contact portion 234e can be formed by a covering surface surrounded by the first interlayer insulating layer 232m. That is, the separation contact portion 234e can be spaced apart from the gate structure 222g while inserting an upper portion of the covering gate structure 222g of the first interlayer insulating layer 232m and / or a portion of the capping layer 244 (more specifically, a side portion 232l of the first interlayer insulating layer 232m). For example, a portion of the first interlayer insulating layer 232m can be inserted between the separation contact portion 234e and the gate structure 222g. More specifically, in a cross-sectional view (the YZ plane in the figure) perpendicular to the first direction (the X direction in the figure), the side portion 232l of the first interlayer insulating layer 232m can be disposed between the covering surface of the separation contact portion 234e and the side surface of the gate structure 222g (more specifically, the side surface of the capping layer 244 on the side surface of the gate structure 222g).

[0116] For example, the first adjacent contact portion 234a, the separation contact portion 234e, and the second adjacent contact portion 234b between two adjacent separation insulators 214 can be a drain contact portion 234d, a source contact portion 234s, and another drain contact portion 234d, respectively. That is, the source region 222s or the source contact portion 234s can be shared in two adjacent first transistors 222a. However, the embodiment is not limited thereto. In some embodiments, the first adjacent contact portion 234a, the separation contact portion 234e, or the second adjacent contact portion 234b can be one of the source contact portion 234s and the drain contact portion 234d. That is, the plurality of contact portions 2341 between two adjacent separation insulators 214 can have various arrangements.

[0117] In an embodiment, the surfaces (e.g., upper surfaces) of the plurality of contact portions 2341 (e.g., adjacent contact portions 234a and 234b and separated contact portion 234e) may be disposed in the same plane as, or adjacent to, one surface (e.g., the upper surface) of the separation insulator 214.

[0118] In an embodiment, the height of the separation insulator 214 is greater than the width W of the separation insulator 214. For example, the height H of the second portion 214b of the separation insulator 214 may be greater than the width W of the separation insulator 214. The height H of the second portion 214b may be measured in the thickness direction of the first substrate 210 (the Z-axis direction in the figure), and for example, is the maximum height of the second portion 214b. The width W of the separation insulator 214 may be measured in a second direction (the Y-axis direction in the figure) transverse to the extending direction of the separation insulator 214, and for example, is the maximum width of the separation insulator 214. In an embodiment, the height H of the second portion 214b of the separation insulator 214 is greater than the thickness T of the gate structure 222g. The thickness T of the gate structure 222g may be measured in the thickness direction of the first substrate 210 (the Z-axis direction in the figure), and for example, is the maximum thickness of the gate structure 222g (e.g., the gate structure 222g of the first transistor 222a).

[0119] Since the height of the separation insulator 214 is relatively large, the physical distance of carriers can be increased, and thus the active regions of the transistors 222 can be stably separated. However, the embodiment is not limited thereto.

[0120] According to an embodiment, the plurality of contact portions 2341 are formed by self-alignment using the separation insulator 214, and thus the margin for forming the plurality of contact portions 2341 can be reduced. That is, the adjacent contact portions 234a and 234b can be formed in a state where the adjacent contact portions 234a and 234b are in contact with the separation insulator 214, and thus, the margin for misalignment between the adjacent contact portions 234a and 234b and the separation insulator 214 does not need to be considered. The first adjacent contact portion 234a and the second adjacent contact portion 234b can be spaced apart from each other by the separation insulator 214, and thus, the margin for misalignment between the first adjacent contact portion 234a and the second adjacent contact portion 234b does not need to be considered. By reducing the margin for forming the plurality of contact portions 2341 (e.g., adjacent contact portions 234a and 234b), the distance between the plurality of transistors 222 (e.g., the first transistor 222a) can be reduced. Accordingly, the size of the circuit region 200 can be reduced, and the integration degree can be improved.

[0121] The semiconductor device 10 including the circuit region 200 may be a flash memory device. In the flash memory device including a plurality of transistors 222 to which various voltages are applied, the integration degree can be effectively increased. According to the present embodiment, in the flash memory device including a large number of gate lines 130 and transistors 222 to increase the data storage capacity, the integration degree can be greatly increased.

[0122] In the present embodiment, the isolation insulator 214 is provided at the boundary of the first transistor 222a or the low-voltage transistor, but does not have to be at the boundary of the second transistor 222b or the high-voltage transistor. However, the embodiment is not limited thereto. In some embodiments, the isolation insulator 214 may be provided at the boundary of the second transistor 222b or the high-voltage transistor, and may or may not be at the boundary of the first transistor 222a or the low-voltage transistor. In the present embodiment, each of the first transistor 222a and the second transistor 222b has a planar structure. However, the embodiment is not limited thereto. For example, at least one of the first transistor 222a and the second transistor 222b may have a structure different from the planar structure (e.g., a vertical structure or a three-dimensional structure). That is, the isolation insulator 214 according to the embodiment may be formed to correspond to various transistors 222.

[0123] The following will refer to Figures 6 to 13 and Figures 1 to 5 to describe in more detail an example of a method of manufacturing the semiconductor device 10 having the above structure. If an element is not described in detail below, it can be understood that the element is at least similar to the corresponding element described elsewhere in the present disclosure.

[0124] Figures 6 to 13 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment. In Figure 6 and Figure 13 is shown a part corresponding to Figure 3 The following will mainly describe the method of manufacturing the semiconductor device 10 based on the circuit region 200 (e.g., the transistor 222).

[0125] As Figure 6 shown, a plurality of transistors 222 including the first transistor 222a and the second transistor 222b are formed in the first transistor region A1 and the second transistor region A2. That is, a plurality of transistors 222 are formed, each transistor 222 including a gate structure 222g and a source region 222s and a drain region 222d. For example, the transistors 222 may be formed on the first substrate 210. A buffer layer 242, a capping layer 244, and a first interlayer insulating layer 232m may be formed.

[0126] A gate insulating layer 224, a gate electrode 226, and a gate capping layer 228 may be formed on a first surface 2101 of a first substrate 210, and then the gate insulating layer 224 and the gate electrode 226 may be patterned by using the gate capping layer 228 as a mask. A gate spacer 229 may be formed on side surfaces of the gate electrode 226, and then source regions 222s and drain regions 222d may be formed by using the gate capping layer 228 and the gate spacer 229 as masks.

[0127] The gate insulating layer 224, the gate electrode 226, the gate capping layer 228, or the gate spacer 229 may be formed by any one of various methods (e.g., deposition, etc.). The source regions 222s and the drain regions 222d may be formed by any one of various methods (e.g., an ion implantation process, etc.). The process of forming the plurality of transistors 222 may apply any one of various processes.

[0128] Before, between, or after the process of forming the plurality of transistors 222, a device isolation body 212 and various circuit elements 220 may be further formed together with the plurality of transistors 222. The process of forming the device isolation body 212 and the circuit elements 220 may apply any one of various processes. The device isolation body 212 may be formed by etching a trench at one side of the first surface 2101 of the first substrate 210 and filling the trench with an insulating material. For example, a part of the first substrate 210 may be removed to form a trench.

[0129] For example, in a first transistor region A1, the device isolation body 212 may be formed at one or more boundaries on one side or both sides of a first transistor 222a in a first direction (the X direction in the figure) and may extend in a second direction (the Y direction in the figure). In a second transistor region A2, the device isolation body 212 may include a part extending in a second direction (the Y direction in the figure) at one or more boundaries on one side or both sides of a second transistor 222b in a first direction (the X direction in the figure), and another part extending in the first direction and at one or more boundaries on one side or both sides of the second transistor 222b in the second direction.

[0130] A buffer layer 242 may be formed on the first surface 2101 of the first substrate 210 at a portion where the gate structure 222g is not located. For example, the buffer layer 242 may be formed by any one of various processes (e.g., a deposition or oxidation process). However, the embodiments are not limited thereto. In some embodiments, the buffer layer 242 may be formed by a subsequent heat treatment process, or the buffer layer 242 may not be formed.

[0131] The capping layer 244 may be entirely on the first surface 2101 of the first substrate 210 (e.g., on the buffer layer 242) to cover the gate structure 222g. The first interlayer insulating layer 232m may be entirely on the first surface 210 and the gate structure 222g (e.g., on the capping layer 244 on the first substrate 210 and the gate structure 222g). The first interlayer insulating layer 232m may include an upper portion 232u on the gate structure 222g and a side portion 232l disposed on the source region 222s and the drain region 222d on one side of the first surface 2101 of the first substrate 210.

[0132] The capping layer 244 or the first interlayer insulating layer 232m may be formed by any one of various methods (e.g., deposition).

[0133] Subsequently, as Figure 7 shown, a separation trench 214t is formed through a partial portion of the first interlayer insulating layer 232m and a partial portion of the first substrate 210. A separation buffer layer 216 may be formed on the surface of the first substrate 210 exposed by the separation trench 214t.

[0134] The separation trench 214t through a partial portion of the first interlayer insulating layer 232m and a partial portion of the first substrate 210 may be formed by an etching process performed on one side of the surface of the first interlayer insulating layer 232m opposite to the first substrate 210 (e.g., the upper surface). For example, the separation trench 214t may be formed by an etching process (e.g., dry etching) or a photolithography process using a mask layer. For example, the separation trench 214t may be formed by removing a partial portion of the first interlayer insulating layer 232m and the first substrate 210. However, the embodiments are not limited thereto, and the separation trench 214t may be formed by any one of various methods.

[0135] In an embodiment, in a cross-sectional view (the YZ plane in the figure) perpendicular to the first direction (the X direction in the figure), the side surface of the separation trench 214t may include an inclined surface or be formed by an inclined surface such that the width of the separation trench 214t gradually decreases toward the second surface 2102 (e.g., the lower surface) of the first substrate 210. In some embodiments, the side surface of the device isolation 212 may include a vertical surface perpendicular to the first substrate 210 or be formed by a vertical surface perpendicular to the first substrate 210.

[0136] In the first transistor region A1, the separation insulator 214 may be disposed at one or more boundaries on one side or both sides of the first transistor 222a in the second direction (the Y direction in the figure) and may extend in the first direction (the X direction in the figure).

[0137] In an embodiment, when forming the preliminary insulating layer 214s (seeFigure 8 Prior to that, a separation buffer layer 216 may be formed on the surface of the separation trench 214t that may be formed at the first substrate 210. For example, the separation buffer layer 216 may be formed by any one of various processes (e.g., a deposition process or an oxidation process). However, the embodiments are not limited thereto. In some embodiments, the separation buffer layer 216 may be formed by a subsequent heat treatment process, or the separation buffer layer 216 may not be formed.

[0138] Subsequently, as Figure 8 shown, a preliminary insulating layer 214s that fills the separation trench 214t is formed. The preliminary insulating layer 214s may be formed by forming an insulating material on the first interlayer insulating layer 232m to fill the separation trench 214t.

[0139] The preliminary insulating layer 214s may include a preliminary separation insulator 214p that fills the separation trench 214t, and a mask portion 214m disposed on the preliminary separation insulator 214p and the first interlayer insulating layer 232m. The mask portion 214m may be used as a mask layer for forming through-holes 232g, 232e, 232a, 232b (see Figure 10 )) at the first interlayer insulating layer 232m after patterning. According to an embodiment, the preliminary insulating layer 214s that fills the separation trench 214t includes the mask portion 214m, and thus, the process of forming an additional mask layer may be omitted.

[0140] Subsequently, as Figure 9 shown, an opening 214n is formed at the mask portion 214m. The opening 214n may include a plurality of openings respectively corresponding to a plurality of contact portions 2341 (see Figure 12 ) and a gate contact portion 234g (see Figure 12 ). In this case, the opening 214n may include a first opening, a second opening, and a third opening. The first opening may be at a position corresponding to the gate contact portion 234g. The second opening may be at a position corresponding to the separation contact portion 234e (see Figure 12 ). The third opening may be at a position corresponding to the first adjacent contact portion 234a and the second adjacent contact portion 234b (see Figure 12 ) and the preliminary separation insulator 214p. In a plan view, the third opening may straddle the preliminary separation insulator 214p and extend to both sides of the preliminary separation insulator 214p in a second direction (the Y direction in the figure) transverse to the preliminary separation insulator 214p.

[0141] The opening 214n can be formed by an etching process (e.g., dry etching) using a mask layer or a photolithography process. In this case, the opening 214n can be formed at the preliminary insulating layer 214s (see Figure 8 ) by using an etching material capable of selectively etching the preliminary insulating layer 214s or adjusting the etching thickness.

[0142] Subsequently, as Figure 10 shown, via holes 232g, 232e, 232a, and 232b are formed at the first interlayer insulating layer 232m by using the mask portion 214m as a mask.

[0143] In this case, the via holes 232g, 232e, 232a, and 232b may include a first via hole 232g, a second via hole 232e, and third via holes 232a and 232b. The first via hole 232g may be formed at a position corresponding to the first opening or the gate contact portion 234g. The second via hole 232e may be formed at a position corresponding to the second opening or the isolation contact portion 234e. The third via holes 232a and 232b may be formed at positions corresponding to partial portions of the third opening, or the first adjacent contact portion 234a and the second adjacent contact portion 234b, respectively.

[0144] For example, the first via hole 232g may pass through the first interlayer insulating layer 232m, the capping layer 244, and the gate capping layer 228. The second via hole 232e and the third via holes 232a and 232b may pass through the first interlayer insulating layer 232m, the capping layer 244, and the buffer layer 242.

[0145] The via holes 232g, 232e, 232a, and 232b can be formed by a dry etching process capable of selectively etching the first interlayer insulating layer 232m. In the process of forming the via holes 232g, 232e, 232a, 232b, when selectively etching the first interlayer insulating layer 232m, the preliminary isolation insulator 214p (see Figure 9 ) or a partial portion of the isolation insulator 214 (e.g., the upper part at the side surface) can be etched together. Thereby, a recessed portion 214r can be formed at a partial portion of the isolation insulator 214 (e.g., the upper part of the side surface).

[0146] Subsequently, as Figure 11 shown, a preliminary contact layer 234p can be formed by filling a conductive material in the via holes 232g, 232e, 232a, and 232b (see Figure 10 ). For example, the via holes 232g, 232e, 232a, and 232b can be filled with a conductive material to form the preliminary contact layer 234p.

[0147] The preliminary contact layer 234p can be formed by any one of various processes (e.g., a deposition process). The preliminary contact layer 234p (gate contact portion 234g and multiple contact portions 2341) can include or be formed of any one of various conductive materials. For example, the preliminary contact layer 234p (gate contact portion 234g and multiple contact portions 2341) can include or be formed of at least one of the following: a metal material (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), polysilicon, a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a combination thereof.

[0148] In Figure 11 FIG., an example is shown in which the preliminary contact layer 234p is formed at a portion where the through portions 232g, 232e, 232a, and 232b are formed, but the embodiments are not limited thereto. In some embodiments, the preliminary contact layer 234p can also include a portion disposed on the upper surface of the mask portion 214m.

[0149] Subsequently, as Figure 12 shown, the multiple contact portions 2341 and the gate contact portion 234g can be formed by removing the mask portion 214m (see Figure 11 ). In this case, the mask portion 214m and a local portion of the preliminary contact layer 234p (see Figure 11 ) can be removed such that the upper surface of the first interlayer insulating layer 232m and the upper surfaces of the multiple contact portions 2341 and the gate contact portion 234g are in the same plane. For example, the process of removing the mask portion 214m and the local portion of the preliminary contact layer 234p can be performed by a chemical mechanical polishing process.

[0150] Subsequently, as Figure 13 shown, one or more second interlayer insulating layers 232n and one or more second wiring layers 2362 are further formed on the first wiring layer 2361 to form the first wiring portion 230.

[0151] According to one embodiment, a circuit region 200 or a semiconductor device 10 with increased integration can be formed by the manufacturing process described herein.

[0152] Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment will be described in more detail with reference to Figures 14 to 16 . If a certain element is not described in detail below, it can be understood that the element is at least similar to the corresponding element described elsewhere in the present disclosure.

[0153] Figure 14 is a partial cross-sectional view schematically showing a circuit region included in a semiconductor device according to an embodiment. InFigure 14 In [reference], a part corresponding to Figure 3 is shown.

[0154] Referring to Figure 14 , in a cross-sectional view (the YZ plane in the figure) perpendicular to the first direction (the X direction in the figure), the side surface of the entire separation insulator 214 may have an inclined surface such that the width of the separation insulator 214 gradually decreases toward the second surface 2102 of the first substrate 210. In some embodiments, the side surface of the entire separation insulator 214 may have a vertical surface perpendicular to the first substrate 210. As described above, in an embodiment, the recessed portion 214r (refer to Figure 3 ) may not be formed on the side surface or the upper portion of the separation insulator 214.

[0155] The separation insulator 214 that does not include the recessed portion 214r may be formed by adjusting process conditions such that the recessed portion 214r is not formed, or by removing the recessed portion 214r in the process of removing the mask portion 214m (see Figure 11 ).

[0156] Figure 15 is a schematic partial cross-sectional view showing a circuit region included in a semiconductor device according to an embodiment. In Figure 15 , a part corresponding to Figure 4 is shown.

[0157] Referring to Figure 15 , in an embodiment, the plurality of contact portions 2341 may include adjacent contact portions 234a and 234b adjacent to the separation insulator 214. The separated contact portion 234e (see Figure 4 ) spaced apart from the separation insulator 214 may not be provided. According to the electrical connection structure of the plurality of transistors 222, embodiments referring to Figure 4 and embodiments referring to Figure 15 may be included simultaneously. Various other modifications are also possible.

[0158] Figure 16 is a schematic cross-sectional view showing a semiconductor device 20 according to an embodiment.

[0159] Referring to Figure 16 , the semiconductor device 20 according to an embodiment has a chip-to-chip (C2C) structure joined by a wafer bonding type. That is, a lower chip including a circuit region 200a including a peripheral circuit structure formed on a first substrate 210 may be manufactured, an upper chip including a memory cell structure on a second substrate 110a may be manufactured, and then the lower chip and the upper chip may be joined to each other to manufacture the semiconductor device 20.

[0160] The circuit region 200a may include a first substrate 210, circuit elements 220, a first wiring portion 230, and a first bonding structure 240 electrically connected to the first wiring portion 230 at a surface facing the cell region 100a. A region other than the first bonding structure 240 at the surface facing the cell region 100a may be covered with a first bonding insulating layer 250.

[0161] The cell region 100a may include a second substrate 110a, a gate stack structure 120, a channel structure CH, a second wiring portion 180, and a second bonding structure 194 electrically connected to the second wiring portion 180 at a surface facing the circuit region 200a. A region other than the second bonding structure 194 may be covered with a second bonding insulating layer 196.

[0162] In an embodiment, the second substrate 110a is a semiconductor substrate including a semiconductor material. For example, the second substrate 110a may be a semiconductor substrate including or formed of a semiconductor material, or may be a semiconductor substrate having a semiconductor layer formed on a base substrate. For example, the second substrate 110a may include single-crystalline or polycrystalline silicon, germanium, silicon germanium, silicon on insulator, or germanium on insulator. In some embodiments, the second substrate 110a may be a support member including an insulating layer or insulating material. This is because the semiconductor substrate provided in the cell region 100a may be removed after bonding the cell region 100a to the circuit region 200a, and a support member including an insulating layer or insulating material may be formed.

[0163] In an embodiment, the gate stack structure 120 may be sequentially stacked on a lower portion of the second substrate 110a in the figure, and may have Figure 1 a structure in which the gate stack structure 120 shown in is provided in an upright and inverted manner. The channel structure CH passing through the gate stack structure 120 may have Figure 2 a structure in which the channel structure CH shown in is provided in an upright and inverted manner. Accordingly, in a cross-sectional view, the channel structure CH may have inclined side surfaces such that the width of the channel structure CH decreases from the circuit region 200a toward the second substrate 110a. A channel pad and the second wiring portion 180 at an upper portion of the gate stack structure 120 may be adjacent to the circuit region 200a.

[0164] For example, the first bonding structure 240 and / or the second bonding structure 194 may include aluminum, copper, tungsten, or an alloy including aluminum, copper, tungsten. For example, the first bonding structure 240 and the second bonding structure 194 may include copper such that the cell region 100a and the circuit region 200a may be bonded to each other by copper-copper bonding (e.g., direct bonding).

[0165] In Figure 16In [the figure], a gate stack structure 120 is shown including a plurality of gate stack structures 120a and 120b as an example. In some embodiments, the gate stack structure 120 may include a single gate stack structure, or three or more gate stack structures. Unless otherwise described, the references may be applied as they are. Figures 1 to 5 The descriptions of the gate stack structure 120 and the channel structure CH are applicable. In Figure 16 [the figure], the following example is shown: the electrical connection structure of the channel structure CH with the horizontal conductive layers 112 and 114 and / or the second substrate 110a is the same as Figure 1 the electrical connection structure of the channel structure CH with the horizontal conductive layers 112 and 114 and / or the second substrate 110 in [the figure]. However, the embodiments are not limited thereto, and various modifications may be made to the electrical connection structure of the channel structure CH with the horizontal conductive layers 112 and 114 and / or the second substrate 110a.

[0166] According to an embodiment, the semiconductor device 20 may include input / output pads, and vias or input / output connection wirings electrically connected to the input / output pads. The input / output connection wirings may be electrically connected to a part of the second bonding structure 194. For example, the input / output pads may be on an insulating layer 198b covering the outer surface of the second substrate 110a. In some embodiments, additional input / output pads electrically connected to the circuit region 200a may be provided.

[0167] For example, the circuit region 200a and the cell region 100a may be parts corresponding to the first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the Figure 17 illustrated electronic system 1000, respectively. For example, the circuit region 200a and the cell region 100a may be regions of the first structure 4100 and the second structure 4200 including the Figure 20 illustrated semiconductor chip 2200a, respectively.

[0168] Examples of electronic systems including semiconductor devices will be described in detail below.

[0169] Figure 17 [The figure] schematically shows an electronic system including a semiconductor device according to an embodiment.

[0170] Reference Figure 17, according to an embodiment, the electronic system 1000 includes a semiconductor device 1100 and a controller 1200 (e.g., a controller circuit) electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100, or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device including one or more semiconductor devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0171] The semiconductor device 1100 may be a non-volatile storage device, and for example, may be a NAND flash memory device described in Figures 1 to 16 The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including bit lines BL, a common source line CSL, word lines WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit lines BL and the common source line CSL.

[0172] In the second structure 1100S, each memory cell string CSTR may include: lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit lines BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. Various modifications may be made to the number of the lower transistors LT1 and LT2, and the number of the upper transistors UT1 and UT2 according to embodiments.

[0173] In an embodiment, the lower transistors LT1 and LT2 may include ground selection transistors, and the upper transistors UT1 and UT2 may include string selection transistors. The first lower gate line LL1 and the second lower gate line LL2 may be the gate lines of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate line of the memory cell transistors MCT, and the upper gate lines UL1 and UL2 may be the gate lines of the upper transistors UT1 and UT2, respectively.

[0174] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 through the first connection wiring 1115 extending into the second structure 1100S within the first structure 1100F. The bit line BL can be electrically connected to the page buffer 1120 through the second connection wiring 1125 extending into the second structure 1100S within the first structure 1100F.

[0175] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations for at least one memory cell transistor selected from a plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through the input / output connection wiring 1135 extending into the second structure 1100S within the first structure 1100F.

[0176] The controller 1200 can include a processor 1210, a NAND controller 1220 (e.g., a controller circuit), and a host interface 1230 (e.g., an interface circuit). According to an embodiment, the electronic system 1000 can include a plurality of semiconductor devices 1100, and in this case, the controller 1200 can control the plurality of semiconductor devices 1100.

[0177] The processor 1210 can control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 can operate according to a predetermined firmware and can access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 can include a NAND interface (I / F) 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written into the memory cell transistors MCT of the semiconductor device 1100, and data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. can be sent through the NAND interface 1221. The host interface (I / F) 1230 can provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0178] Figure 18 is a perspective view schematically showing an electronic system including a semiconductor device according to an embodiment.

[0179] ReferenceFigure 18 According to an embodiment, the electronic system 2000 may include a main substrate 2001, a controller 2002 (e.g., a controller circuit) disposed on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 at the main substrate 2001.

[0180] The main substrate 2001 may include a connector 2006, and the connector 2006 includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. In an embodiment, the electronic system 2000 may communicate with an external host according to any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an embodiment, the electronic system 2000 may be operated by power supplied from an external host via the connector 2006. The electronic system 2000 may also include a Power Management Integrated Circuit (PMIC) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0181] The controller 2002 may write data into the semiconductor package 2003 or may read data from the semiconductor package 2003, and may increase the operation speed of the electronic system 2000.

[0182] The DRAM 2004 may be a buffer memory for alleviating or buffering the speed difference between the semiconductor package 2003 as a data storage space and the external host. The DRAM 2004 included in the electronic system 2000 may also be a cache memory, and may also provide a space for temporarily storing data in the control operation for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0183] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 at the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 on the package substrate 2100 covering the semiconductor chips 2200 and the connection structure 2400.

[0184] The package substrate 2100 may be a printed circuit board including package upper pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to Figure 17 the input / output pads 1101. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. The semiconductor chip 2200 may include the semiconductor device described above with reference to Figures 1 to 16 description.

[0185] In an embodiment, the connection structure 2400 may be bonding wirings that electrically connect the input / output pads 2210 and the package upper pads 2130. Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using bonding wiring type, and the semiconductor chips 2200 may be electrically connected to the package upper pads 2130 of the package substrate 2100. According to an embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including through-silicon vias (TSVs) instead of using the connection structure 2400 of the bonding wiring type.

[0186] In an embodiment, the controller 2002 and the semiconductor chips 2200 may be included in one package. For example, the controller 2002 and the semiconductor chips 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chips 2200 may be connected to each other through wirings at the interposer substrate.

[0187] Figure 19 and Figure 20 are respectively schematic cross-sectional views showing a semiconductor package according to an embodiment. Figure 19 and Figure 20 respectively show Figure 18An embodiment of the semiconductor package 2003, and conceptually shows the area obtained by cutting along line I-I'. Figure 18 of the semiconductor package 2003.

[0188] Referring Figure 19 , in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate main body portion 2120, a package upper pad 2130 on the upper surface of the package substrate main body portion 2120, a package lower pad 2125 disposed on the lower surface of the package substrate main body portion 2120 or exposed through the lower surface of the package substrate main body portion 2120, and an internal wiring 2135 within the package substrate main body portion 2120 for electrically connecting the package upper pad 2130 and the package lower pad 2125. The package upper pad 2130 may be electrically connected to the connection structure 2400. The package lower pad 2125 may be connected to the wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 as shown in Figure 18 .

[0189] The semiconductor chip 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 stacked in sequence on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including peripheral wirings 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 passing through the gate stack structure 3210 and a separation structure 3230, a bit line 3240 electrically connected to the channel structure 3220, and a gate connection wiring electrically connected to the gate stack structure 3210 and the word line WL (see Figure 17 ).

[0190] In the semiconductor chip 2200 or the semiconductor device according to the embodiment, due to the separation insulator 214 and the adjacent contact portions 234a and 234b in contact with the separation insulator 214, the integration degree of the semiconductor chip 2200 or the semiconductor device according to the embodiment can be improved.

[0191] Each semiconductor chip 2200 may include a through-wiring 3245 electrically connected to the peripheral wirings 3110 of the first structure 3100 and extending into the second structure 3200. The through-wiring 3245 may pass through the gate stack structure 3210 and may be further disposed outside the gate stack structure 3210. Each semiconductor chip 2200 may further include an input / output connection wiring 3265 electrically connected to the peripheral wirings 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connection wiring 3265.

[0192] In an embodiment, in semiconductor package 2003, a plurality of semiconductor chips 2200 may be electrically connected to each other through a connection structure 2400 having a bonding wiring type. In some embodiments, the plurality of semiconductor chips 2200 or a plurality of portions constituting the plurality of semiconductor chips 2200 may be electrically connected through a connection structure including through-silicon vias (TSVs).

[0193] Reference Figure 20 , in semiconductor package 2003A, each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding type.

[0194] The first structure 4100 may include a peripheral circuit region including peripheral wirings 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 passing through the gate stack structure 4210 and a separation structure 4230, and a second bonding structure 4250 electrically connected to the channel structure 4220 and the gate stack structure 4210 and to a word line WL (see Figure 17 ). For example, the second bonding structure 4250 may be electrically connected to the channel structure 4220 and the word line WL through a bit line 4240 electrically connected to the channel structure 4220 and a gate connection wiring electrically connected to the word line WL. The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 may be in contact with each other and bonded to each other. For example, a portion where the first bonding structure 4150 and the second bonding structure 4250 are bonded to each other among the first bonding structure 4150 and the second bonding structure 4250 may include copper (Cu).

[0195] In the semiconductor chip 2200a or a semiconductor device according to an embodiment, the integration degree of the semiconductor chip 2200a or a semiconductor device according to an embodiment may be improved by a separation insulator (e.g., 214) and adjacent contact portions (e.g., 234a and 234b) in contact with the separation insulator.

[0196] Each semiconductor chip 2200a may further include input / output pads 2210 and input / output connection wirings 4265 at a lower portion of the input / output pads 2210. The input / output connection wirings 4265 may be electrically connected to a part of the second bonding structure 4250.

[0197] In an embodiment, in a semiconductor package 2003A, a plurality of semiconductor chips 2200a may be electrically connected to each other through a connection structure 2400 having a bonding wiring type. In some embodiments, a plurality of semiconductor chips 2200a or a plurality of portions constituting the plurality of semiconductor chips 2200a may be electrically connected through a connection structure including through-silicon vias (TSVs).

[0198] Although some examples have been described in connection with some embodiments, it should be understood that the present disclosure is not limited to these embodiments, and the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A semiconductor substrate; A transistor disposed on the semiconductor substrate, the transistor including a gate structure, and a source region and a drain region disposed on opposite sides of the gate structure; A first interlayer insulating layer disposed on the gate structure of the transistor and the source region and the drain region; A plurality of contact portions passing through the first interlayer insulating layer, wherein each contact portion is electrically connected to a corresponding one of the source region and the drain region; and A separation insulator passing through the first interlayer insulating layer and extending into the interior of the semiconductor substrate at the boundary of the transistor, Wherein the plurality of contact portions include adjacent contact portions adjacent to the separation insulator and spaced apart from the gate structure, and the first interlayer insulating layer is interposed between the adjacent contact portions and the gate structure.

2. The semiconductor device according to claim 1, wherein, In a plan view, the separation insulator extends in a first direction, and The adjacent contact portions include a first contact portion and a second contact portion, the first contact portion being disposed on a first side of the separation insulator in a second direction transverse to the first direction, and the second contact portion being disposed on a second side of the separation insulator opposite to the first side of the separation insulator in the second direction.

3. The semiconductor device according to claim 1, further comprising a plurality of transistors, the plurality of transistors including the transistor, and The separation insulator separates the source region and the drain region included in one transistor among the plurality of transistors from the source region and the drain region included in another transistor among the plurality of transistors.

4. The semiconductor device according to claim 1, wherein, The adjacent contact portions include self-aligned contact portions self-aligned through the separation insulator.

5. The semiconductor device according to claim 1, wherein, The plurality of contact portions further include separation contact portions, and Side surfaces of the separation contact portions are surrounded by the first interlayer insulating layer to be spaced apart from the separation insulator.

6. The semiconductor device according to claim 1, wherein, The separation insulator includes a material different from that of the first interlayer insulating layer.

7. The semiconductor device according to claim 1, further comprising: A device isolation body disposed at the boundary of the transistor on one side of a surface of the semiconductor substrate adjacent to the first interlayer insulating layer, Wherein the separation insulator includes a material different from that of the device isolation body.

8. The semiconductor device according to claim 7, wherein, The first interlayer insulating layer or the device isolation body includes silicon oxide, and The separation insulator includes silicon nitride.

9. The semiconductor device according to claim 1, further comprising: A device isolation body disposed at the boundary of the transistor on one side of a surface of the semiconductor substrate adjacent to the first interlayer insulating layer, Wherein one surface of the device isolation body and one surface of the separation insulator are at different heights, the one surface of the device isolation body and the one surface of the separation insulator are closest to a surface of the first interlayer insulating layer opposite to the semiconductor substrate, or Another surface of the device isolation body and another surface of the separation insulator inside the semiconductor substrate are at different heights.

10. The semiconductor device according to claim 1, wherein, The isolation insulator includes a first portion passing through the first interlayer insulating layer and a second portion inside the semiconductor substrate, and the height of the second portion is greater than the width of the isolation insulator.

11. The semiconductor device according to claim 1, wherein, The isolation insulator includes a first portion passing through the first interlayer insulating layer and a second portion inside the semiconductor substrate, and the height of the second portion is greater than the thickness of the gate structure.

12. The semiconductor device according to claim 1, wherein, The isolation insulator includes a recessed portion at a side surface of the isolation insulator, and the side surface of the isolation insulator is adjacent to a surface of the first interlayer insulating layer opposite to the semiconductor substrate.

13. The semiconductor device according to claim 1, further comprising: a high-voltage transistor having an operating voltage higher than the operating voltage of the transistor; and a device isolation body disposed at a boundary between the transistor and the high-voltage transistor on one side of a surface of the semiconductor substrate adjacent to the first interlayer insulating layer, wherein the isolation insulator is disposed at the boundary of the transistor.

14. The semiconductor device according to claim 1, further comprising: an isolation buffer layer disposed between the isolation insulator and the semiconductor substrate, and the isolation buffer layer includes a material different from that of the isolation insulator.

15. The semiconductor device according to claim 1, wherein, The semiconductor device includes a circuit region and a cell region, the circuit region includes the semiconductor substrate and the transistor, the cell region includes a memory cell structure disposed on the circuit region, and the transistor has a planar structure.

16. A semiconductor device, comprising: a semiconductor substrate; a first transistor and a second transistor disposed on the semiconductor substrate, each of the first transistor and the second transistor includes a gate structure, and a source region and a drain region disposed on opposite sides of the gate structure; a device isolation body disposed in a portion of the semiconductor substrate; a first interlayer insulating layer disposed on the gate structure, the source region and the drain region in each of the first transistor and the second transistor, and the device isolation body; and an isolation insulator passing through the first interlayer insulating layer and extending into the semiconductor substrate, wherein the second transistor has an operating voltage higher than the operating voltage of the first transistor, and the device isolation body and the isolation insulator are disposed at the boundary of the first transistor, and the device isolation body is disposed at the boundary of the second transistor.

17. The semiconductor device according to claim 16, further comprising: a plurality of contact portions passing through the first interlayer insulating layer, wherein each contact portion is electrically connected to a corresponding one of the source region and the drain region, wherein the plurality of contact portions include adjacent contact portions adjacent to the isolation insulator and self-aligned with the isolation insulator.

18. The semiconductor device according to claim 16, wherein, The isolation insulator includes a material different from that of the device isolation body.

19. The semiconductor device according to claim 16, wherein, One surface of the device isolation body and one surface of the isolation insulator are at different heights, and the one surface of the device isolation body and the one surface of the isolation insulator are closest to one surface of the first interlayer insulating layer opposite to the semiconductor substrate, or Another surface of the device isolation body and another surface of the isolation insulator inside the semiconductor substrate are at different heights.

20. An electronic system, comprising: A main substrate; A semiconductor device disposed on the main substrate; And A controller electrically disposed on the main substrate to be connected to the semiconductor device, The semiconductor device includes: A semiconductor substrate; A transistor disposed on the semiconductor substrate, the transistor including a gate structure, and a source region and a drain region disposed on opposite sides of the gate structure; A first interlayer insulating layer disposed on the gate structure of the transistor and the source region and the drain region; A plurality of contact portions passing through the first interlayer insulating layer, wherein each contact portion is electrically connected to a corresponding one of the source region and the drain region of the transistor; and An isolation insulator passing through the first interlayer insulating layer and extending into the interior of the semiconductor substrate at the boundary of the transistor, Wherein the plurality of contact portions include adjacent contact portions adjacent to the isolation insulator and spaced apart from the gate structure, and the first interlayer insulating layer is interposed between the adjacent contact portions and the gate structure.

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