Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. According to the embodiment, the semiconductor device comprises a substrate, a buried oxide layer, a channel part comprising a semiconductor layer, a source part / drain part and a gate stack. The semiconductor layer comprises a shell part and a core part which are separated from each other at an interval and are distributed in an overlapping manner in the projection direction, the shell part is arranged above the core part, and the shell part and the core part are respectively subjected to one of p-type doping and n-type doping. The phase inverter is composed of n-type and p-type semiconductor devices which are basically symmetrical. The invention also discloses a semiconductor device having a drift portion, the drift portion including an elongated channel portion, the semiconductor device being capable of accommodating high and low voltage circuits.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a channel portion including a shell portion and a core portion and a method for manufacturing the same. Background Art

[0002] Fully depleted (FD) SOI semiconductor devices, especially oxide semiconductor field effect transistors (MOSFETs), can well control the short channel portion effect and enable further miniaturization of the devices. However, the process for manufacturing FDSOI MOSFETs is complex and costly, and the performance needs to be further improved. And such FDSOI devices are used in low-voltage logic operation applications. For FDSOI that can apply higher voltages (e.g., > 10V), a drift region is required to support the voltage, and such high-voltage devices can be called Lateral diffusion FDSOI (or LDMOS). Summary of the Invention

[0003] In view of this, an object of the present disclosure is at least partially to provide a semiconductor device and a method for manufacturing the same.

[0004] According to one aspect of the present disclosure, there is provided a semiconductor device, including:

[0005] A substrate;

[0006] A buried oxide layer on the substrate; and

[0007] A semiconductor layer stacked above the buried oxide layer;

[0008] Wherein the semiconductor device includes a first semiconductor device of a first type and a second semiconductor device of a second type, wherein the first semiconductor device includes:

[0009] A first channel portion including a first part of the semiconductor layer;

[0010] A first source / drain portion of a first doping type, disposed above the buried oxide layer and connected to opposite ends of the first channel portion; and

[0011] A first gate stack between the first source / drain portions, disposed on the first channel portion; and

[0012] The second semiconductor device includes:

[0013] A second channel portion, the second channel portion including a second part of the semiconductor layer;

[0014] A second source / drain portion of a second doping type, disposed above the buried oxide layer and connected to opposite ends of the second channel portion; and

[0015] A second gate stack between second source / drain portions, disposed over the second channel portion;

[0016] Wherein the first channel portion and the second channel portion each include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in a projection direction, and the at least one shell portion and the at least one core portion have dopings of opposite doping types;

[0017] Wherein the drain portion of the first semiconductor device and the drain portion of the second semiconductor device are electrically connected, and the first gate stack of the first semiconductor device and the second gate stack of the second semiconductor device are electrically connected.

[0018] Aspects of the present invention provide a semiconductor device including:

[0019] A substrate;

[0020] A buried oxide layer on the substrate; and

[0021] A semiconductor layer stacked over the buried oxide layer;

[0022] Wherein the semiconductor device includes a third semiconductor device portion and a drift portion, and the third semiconductor device portion includes:

[0023] A third channel portion, including a third portion of the semiconductor layer;

[0024] Third source / drain portions, disposed over the buried oxide layer and connected to opposite ends of the third channel portion; and

[0025] A third gate stack between the third source / drain portions, disposed over the third channel portion; and

[0026] The drift portion includes:

[0027] A drift portion channel, including a fourth portion of the semiconductor layer, and the length of the drift portion channel in the extending direction of the semiconductor layer is greater than that of the third channel portion;

[0028] Fourth source / drain portions, disposed over the buried oxide layer and connected to opposite ends of the drift portion channel, and the doping type of the fourth source / drain portions is the same as that of the third source / drain portions; and

[0029] An oxide layer between the fourth source / drain portions, disposed over the drift portion channel;

[0030] Wherein the third channel portion and the drift portion channel each include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in a projection direction, and the at least one shell portion and the at least one core portion have dopings of opposite doping types; and

[0031] Wherein the drain portion of the third semiconductor device portion is the source portion of the drift portion.

[0032] In one embodiment, the thickness of one of the at least one shell portion is 5 nm to 10 nm, and / or the thickness of one of the at least one core portion is 10 nm to 50 nm.

[0033] In one embodiment, the at least one core portion includes one core portion or two core portions, and / or wherein the at least one shell portion includes one shell portion or two shell portions.

[0034] In one embodiment, the shell portion and the core portion are obtained by a process of performing ion implantation on the semiconductor layer and an annealing process.

[0035] In one embodiment, the gate stack includes a work function layer and a gate metal conductive layer.

[0036] In one embodiment, the gate stack includes a first gate dielectric layer.

[0037] In one embodiment, the first semiconductor device includes a first doped type source / drain portion and a first gate dielectric layer, and the work function on the first gate dielectric layer is of the first type; the second semiconductor device includes a second doped type source / drain portion and a second gate dielectric layer, and the work function layer on the second gate dielectric layer is of the second type.

[0038] One aspect of the present invention provides a method of manufacturing a semiconductor device, including:

[0039] Forming a buried oxide layer on a substrate;

[0040] Forming a semiconductor layer on the buried oxide layer;

[0041] Forming a first sacrificial gate and a second sacrificial gate on the semiconductor layer, and respectively forming a first sacrificial gate spacer and a second sacrificial gate sidewall on the sidewalls of the first sacrificial gate and the second sacrificial gate;

[0042] Using a mask, forming a first source / drain portion of a first doped type on opposite sides of the first sacrificial gate spacer, and forming a second source / drain portion of a second doped type on opposite sides of the second sacrificial gate, and the first source / drain portion of the first doped type and the second source / drain portion of the second type overlap with the first sacrificial gate and the second sacrificial gate in the channel extension direction;

[0043] Removing the first sacrificial gate, the second sacrificial gate, and optionally removing the sidewall of the first sacrificial gate and the second sacrificial gate sidewall to release the space between the first source / drain portion and the second source / drain portion;

[0044] Forming at least one core portion and at least one shell portion in the semiconductor layer in the space;

[0045] Form a gate stack on the semiconductor layer in the space; and

[0046] Electrically connect the drain of the source / drain portion of the first doping type and the drain of the source / drain portion of the second type, and electrically connect the gate stack between the source / drain portions of the first doping type and the gate stack between the source / drain portions of the second type;

[0047] Wherein, the semiconductor layer of the channel portion of the source / drain portion of the first doping type and the channel portion between the source / drain portions of the second type includes at least one shell portion of the second doping type and at least one core portion of the first doping type, and the first type of doping and the second type of doping are opposite doping types.

[0048] One aspect of the present invention provides a method for manufacturing a semiconductor device, including:

[0049] Form a buried oxide layer on a substrate;

[0050] Form a semiconductor layer on the buried oxide layer;

[0051] Form a third sacrificial gate and a fourth sacrificial gate on the semiconductor layer, and optionally form a third sacrificial gate sidewall on the sidewall of the third sacrificial gate, wherein the width of the fourth sacrificial gate is greater than that of the third sacrificial gate;

[0052] Form source / drain portions of the same doping type on the opposite outer sides of the third sacrificial gate sidewall and the fourth sacrificial gate, and between the third sacrificial gate sidewall and the fourth sacrificial gate, and the source / drain portions overlap with the third sacrificial gate and the fourth sacrificial gate in the channel extension direction;

[0053] Remove the third sacrificial gate and the fourth sacrificial gate and optionally remove the third sacrificial gate sidewall to release the third space and the fourth space between the source / drain portions;

[0054] Form at least one core portion and at least one shell portion in the semiconductor layer in the third space and the fourth space, and the at least one shell portion is located above the at least one core portion; and

[0055] Form a gate stack on the semiconductor layer in the third space, and form an oxide layer on the semiconductor layer in the fourth space, wherein the third space corresponds to the third sacrificial gate, and the fourth space corresponds to the fourth sacrificial gate;

[0056] Wherein, the doping type of the source / drain portion is opposite to the doping type of at least one shell portion and the same as the doping type of at least one core portion.

[0057] In one embodiment, at least one core portion and at least one shell portion are formed in the semiconductor layer by ion implantation.

[0058] In one embodiment, the thickness of one of the at least one shell portion is from 5 nm to 10 nm, and / or the thickness of one of the at least one core portion is from 10 nm to 50 nm.

[0059] In one embodiment, forming the gate stack includes:

[0060] Successively forming a first gate dielectric layer, a work function layer, and a gate conductive layer on the exposed surface of the semiconductor layer.

[0061] According to an embodiment of the present disclosure, the channel portion may include a shell portion and a core portion. Thus, by changing the absolute value of the gate voltage, the charges of the shell portion and the core portion can be changed and can jointly participate in conduction, so that the electrical characteristics of the semiconductor device can be improved. In addition, the method of manufacturing a semiconductor device according to an embodiment of the present disclosure can be simpler and have lower costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] According to the following description with reference to the accompanying drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure may become clearer. In the drawings:

[0063] Figures 1 to 7 Some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated.

[0064] Figure 8 The structure of a semiconductor device (inverter) according to an embodiment of the present disclosure is schematically illustrated.

[0065] Figure 9 The structure of a semiconductor device (having a drift portion) according to an embodiment of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0066] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0067] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0068] The present disclosure can be presented in various forms, and some examples will be described below. In the following description, the selection of various materials is involved. In addition to considering its function (for example, semiconductor materials are used to form active regions, and dielectric materials are used to form electrical isolation), the etching selectivity is also considered when selecting materials. In the following description, the required etching selectivity may or may not be indicated. Those skilled in the art should be clear that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or other layers are not shown as being etched in the figures, then this etching can be selective, and the material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0069] The FDSOI technology has greatly improved the performance of devices. The application of field-effect transistors on FDSOI has been greatly developed. The junctionless field-effect transistors on FDSOI in the prior art have shown excellent advantages. And the present inventors have found that devices on FDSOI including a shell part and a core part have further improved performance, exceeding the performance of devices in the prior art, and can be combined with the current process flow at the 10nm node and below. Furthermore, it is expected to carry out the integration and innovation of device structures, materials, and processes, and has great development space.

[0070] The inventors discovered that the channel layer can be fabricated using epitaxial growth techniques. The channel layer can include a shell and a core. For example, for an n-channel field-effect transistor, the shell of the channel semiconductor layer is limited to being undoped or lightly p-type doped, while the core can be a highly n-type doped layer. The shell thickness is comparable to that of the core (e.g., the same order of magnitude), but the thicknesses of both can be adjusted as needed. The fabrication methods for the shell and core are highly reliable, and can be achieved, for example, through direct epitaxial growth or by ion implantation after the semiconductor layer is formed. FDSOI planar technology has the potential to achieve or exceed the performance of Fin field-effect transistors at the same node, making it market-competitive.

[0071] According to an embodiment of the present disclosure, a semiconductor device is provided. Specifically, the semiconductor device may include: a substrate; a buried oxide layer on the substrate; and a semiconductor layer stacked above the buried oxide layer. The semiconductor device includes a first semiconductor device of a first type (e.g., n-type or p-type) and a second semiconductor device of a second type (e.g., p-type or n-type, respectively). In the present invention, the first semiconductor device and the second semiconductor device are both located on the buried oxide layer on the substrate, and their channel portions are formed from the same semiconductor layer.

[0072] In one embodiment, a first semiconductor device includes: a first channel portion, the first channel portion including a first portion of a semiconductor layer; a first source / drain portion disposed above a buried oxide layer and connected to opposite ends of the first channel portion; and a first gate stack disposed on the first channel portion between the first source / drain portion. A second semiconductor device includes a second channel portion, the second channel portion including a second portion of the semiconductor layer; a second source / drain portion disposed above a buried oxide layer and connected to opposite ends of the second channel portion; and a second gate stack disposed on the second channel portion between the second source / drain portion. The first channel portion and the second channel portion respectively include at least one shell portion and at least one core portion spaced apart from each other and overlapping in a projection direction, wherein the at least one shell portion and the at least one core portion have opposite doping types.

[0073] In an embodiment of the present invention, Figure 8 As shown, the first semiconductor device and the second semiconductor device together constitute an inverter, wherein the drain of the first semiconductor device is electrically connected to the drain of the second semiconductor device, and the first gate stack of the first semiconductor device is electrically connected to the second gate stack of the second semiconductor device.

[0074] The first semiconductor device and the second semiconductor device may have the same structure, such as a similar channel portion, gate stack, and core and shell portion within the channel portion. The first semiconductor device and the second semiconductor device differ in having source / drain portions of opposite doping types.

[0075] In the present invention, the first and second channel portions may include portions of a semiconductor layer, such as Si. In one embodiment, the first and second channel portions may also include portions of a semiconductor layer 1005 with high mobility, such as SiGe. In other embodiments, a part of the semiconductor layer 1005 may be Si and another part may be SiGe. The semiconductor layer 1005 includes at least one shell portion 1005-1 and at least one core portion 1005-2. The shell portion 1005-1 is a partially doped region within the semiconductor layer 1005, and the core portion 1005-2 is a partially doped region within the semiconductor layer 1005. The first and second channel portions may have the same core and shell structure. However, it should be understood that the first and second channel portions may have different core and shell structures. For example, the first channel portion may have two shell portions and one core portion, and the second channel portion may have one shell portion and one core portion. Those skilled in the art can specifically set them according to the principles and meanings disclosed in the present invention.

[0076] At least one layer of the shell portion 1005-1 and at least one layer of the core portion 1005-2 means, for example, combinations such as one layer of the shell portion 1005-1 and one layer of the core portion 1005-2, two layers of the shell portion 1005-1 and one layer of the core portion 1005-2, two layers of the shell portion 1005-1 and two layers of the core portion 1005-2, one layer of the shell portion 1005-1 and two layers of the core portion 1005-2, etc. It should be understood that there may also be configurations such as three or four layers of the shell portion and / or three or four layers of the core portion. The number of the shell portion and the core portion can be set according to the required performance, the doping concentration of the shell portion and the core portion can be set, and the arrangement between the shell portion and the core portion can be set. For example, in one embodiment, one layer of the shell portion and one layer of the core portion are alternately arranged. In one embodiment, one layer of the core portion is arranged on top of one layer of the shell portion (not shown).

[0077] In Figure 7In the illustrated embodiment, by way of example only, the first semiconductor device includes a first source / drain portion 1011 and a first channel portion between the first source / drain portions 1011, wherein the first channel portion includes a part of the semiconductor layer 1005, and this part of the semiconductor layer 1005 includes two shell portions 1005-1 and one core portion 1005-2. Compared with one shell portion, the configuration of stacking two shell portions 1005-1 and one core portion 1005-2 has better uniformity and greater current under the same conditions. In this embodiment, the first gate stack is formed between the first source / drain portions 1011 and above the first channel portion; the first gate stack may include a first gate dielectric layer and / or a first work function layer 1019. In one embodiment, the first gate stack may include a first work function layer 1019, such as a metal work function layer, particularly, for example, a titanium nitride layer. In one embodiment, the first gate stack includes a first gate dielectric layer 1017, such as a hafnium oxide layer. The hafnium oxide layer may have a thickness of about 2 nm. The first gate stack may further include a gate conductive layer 1021.

[0078] In one embodiment, a spacer 1009 is formed on the sidewalls of the first gate stack, and the spacer is located between the first gate stack and the first source / drain portions 1011. In Figure 7 the embodiment, no spacer is provided. In addition, Figure 7 in the embodiment, the illustrated semiconductor device includes an interlayer dielectric layer 1013. However, in other embodiments, the semiconductor device may not include the interlayer dielectric layer 1013. It should be noted that in this embodiment, the semiconductor device further includes a second semiconductor device, which is not shown in Figure 7 and has a structure similar to that of the first semiconductor device and is formed on the buried oxide layer 1003. The second channel portion of the second semiconductor device includes a part of the semiconductor layer 1005, which includes a similar core and shell structure and will not be elaborated here. Since the second semiconductor device and the first semiconductor device have similar structures and the core and shell portions may be exactly the same, the first and second semiconductor devices do not need to be distinguished in the manufacturing process, thereby reducing the number of masks and the number of implantations.

[0079] In an embodiment of the present invention, the semiconductor layer 1005 of the first channel portion includes at least one shell portion 1005-1 and at least one core portion 1005-2. As an example, in an embodiment of an n-type semiconductor device, n-type ion implantation is performed toward the channel portion using a predetermined energy and dose (forming the core portion), and then p-type ion implantation is performed toward the channel portion of the n-type semiconductor device using a different predetermined energy and dose (forming the shell portion). In this embodiment, the p-type implantation can be performed using two different energies to form ion doping profiles at different depths in the semiconductor layer 1005, wherein the doses can be the same or different. After the ion implantation is completed, rapid laser annealing, such as nanosecond laser annealing, can be performed. Through this process, two shell portions 1005-1 and a core portion 1005-2 are formed within the semiconductor layer 1005 of the first and second channel portions. The core portion 1005-2 is located at a greater depth than the shell portion 1005-1. Thus, in a projection direction, the two shell portions 1005-1 are substantially stacked on the core portion 1005-2. The two shell portions 1005-1 and the core portion 1005-2 are spaced apart from each other. The width or extent (vertical thickness in the figure) of the shell portion 1005-1 is, for example, approximately 5-10 nm, and the width or extent (vertical thickness in the figure) of the core portion 1005-2 is, for example, approximately 10-50 nm. In the horizontal direction of the figure, the span of the shell portion 1005-1 and the core portion 1005-2 is substantially similar to the span of the channel portion. However, it should be noted that the characteristics of ion implantation determine that the ion distribution shape of the shell 1005-1 and the core 1005-2 is not necessarily rectangular, but rather generally elliptical. Other shapes can be achieved by changing the implantation process.

[0080] The present invention utilizes existing implantation technology to advantageously implement a multi-Vt solution for FDSOI devices by providing one or more shell portions in a channel portion in a very simple manner. Compared with conventional / existing methods for manufacturing FDSOI devices with multiple Vt, the process is extremely simple. In particular, when the first semiconductor device and the second semiconductor device have the same shell-core structure, the channel portion structures of the first semiconductor device and the second semiconductor device can be simultaneously formed by the same implantation method, without the need for additional circuit design and corresponding process settings, thereby greatly reducing complexity. Furthermore, the channel portions of the first and second (i.e., n and p) semiconductor devices having the same structure have the characteristic of charge balance, thereby achieving a fully depleted channel and symmetrical Vt.

[0081] In another embodiment of the present invention, the shell portion 1005 - 1 may be a non-doped portion in the semiconductor layer 1005 . In other words, the shell portion 1005 - 1 is a non-doped region in the semiconductor layer 1005 .

[0082] In one embodiment, the threshold voltage of the n-type semiconductor device and the threshold voltage of the p-type semiconductor device can be set to be substantially symmetric, which can be determined by, for example, the doping dosage and work function layer of the shell portion and the core portion. According to the embodiment, the contact resistance between the channel portion and the source / drain portion 1011 of the above semiconductor device can be lower in the on state of the semiconductor device than in the off state of the semiconductor device.

[0083] According to the embodiment, the above first semiconductor device can be an n-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (positive voltage), the space charge in the core portion 1005-2 of the n-type semiconductor device is balanced by the space charge of the shell portion 1005-1 to become fully depleted. When the absolute value of the gate voltage gradually becomes greater than the absolute value of the threshold voltage, an electron accumulation mode is first formed in the core portion 1005-2 of the n-type semiconductor device to start conducting, and then a greater gate voltage value causes the shell portion 1005-1 to form an inversion mode and jointly participate in conduction.

[0084] According to the embodiment, the above second semiconductor device can be a p-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (negative voltage), the space charge in the core portion 1005-2' is balanced by the space charge of the shell portion 1005-1' to become fully depleted. When the absolute value of the gate voltage gradually increases and becomes greater than the absolute value of the threshold voltage, a hole accumulation mode is first formed in the core portion 1005-2' to start conducting. Then a greater gate voltage value causes the shell portion 1005-1' to form an inversion mode and jointly participate in conduction.

[0085] In the present invention, the inverter is formed by connecting the first semiconductor device and the second semiconductor device, that is, the drain portion of the first semiconductor device and the drain portion of the second semiconductor device are electrically connected, and the gate stack (actually the gate conductor layer) of the first semiconductor device and the gate stack (actually the gate conductor layer) of the second semiconductor device are electrically connected. Due to the setting of the shell portion and the core portion, an improved inverting voltage can be achieved, and the noise margin can be improved.

[0086] A method for manufacturing a transistor device according to an embodiment of the present invention will be described below.

[0087] Figures 1 to 7 Some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown. For the sake of simplicity, only the manufacturing process of a first semiconductor device is shown. The second semiconductor device is formed by the same or similar process. Especially when the first semiconductor device and the second semiconductor device have the same channel portion structure, except for the source / drain portion, the formation processes of other components are exactly the same, which is also the advantage of the simple process of the present invention.

[0088] As Figure 1As shown, a buried oxide layer 1003 can be formed on a substrate 1001 (e.g., Si), or a commercially available silicon-on-insulator (SOI) substrate can be directly used. A semiconductor layer 1005 is formed on the buried oxide layer 1003. In this embodiment, the SOI substrate can be formed by, for example, an SOI preparation process such as an intelligent cutting process. The substrate 1001 can include an elemental semiconductor material such as Si or Ge, or a compound semiconductor material such as SiGe, etc. Here, taking a silicon wafer as an example, the substrate 1001 is described. The buried oxide layer 1003 can include an oxide (e.g., silicon oxide). The semiconductor layer 1005 can include an elemental semiconductor material such as Si or Ge, or a compound semiconductor material such as SiGe, etc. The thickness of the semiconductor layer 1005 can be set as needed, and the semiconductor layer 1005 can be directly grown epitaxially.

[0089] Next, as Figure 2 shown, a sacrificial gate 1007 can be formed on the semiconductor layer 1005. Here, the channel extension direction is taken as the first direction (e.g., Figure 2 the horizontal direction in the plane of the paper in Figure 2 ), and the direction intersecting (e.g., perpendicular) with the first direction is taken as the second direction (e.g., Figure 2 the direction perpendicular to the plane of the paper in Figure 2 ), and the sacrificial gate 1007 extends along the second direction. The sacrificial gate 1007 can include polysilicon. For convenience, the hard mask that may exist on the sacrificial gate 1007 is not shown. On the sidewalls of the sacrificial gate 1007, sidewalls 1009 of the sacrificial gate 1007 can be formed by a sidewall formation process. For example, the sidewalls 1009 can include a nitride (e.g., silicon nitride). As Figure 2 shown, in the third direction ( Figure 2 the vertical direction in the plane of the paper in

[0090] ), the portion of the upper surface of the semiconductor layer 1005 not covered by the sacrificial gate 1007 and the sidewalls 1009 is exposed. In the present invention, a first sacrificial gate and a second sacrificial gate can be formed. Optionally, a first sacrificial gate sidewall and a second sacrificial gate sidewall can be respectively formed on the sidewalls of the first sacrificial gate and the second sacrificial gate.

[0090] As Figure 3As shown, a source / drain portion 1011 extending in the third direction can be formed by, for example, selective epitaxial growth, using the exposed portion of the upper surface of the semiconductor layer 1005 as a seed. The source / drain portion 1011 can be formed on opposite sides of the spacer 1009 of the sacrificial gate 1007 and can overlap the sacrificial gate 1007 in the first direction. The source / drain portion 1011 can comprise various suitable semiconductor materials, such as Si for an n-type field-effect transistor and SiGe for a p-type field-effect transistor. The source / drain portion 1011 can be doped to a desired conductivity type (n-type for an n-type field-effect transistor and p-type for a p-type field-effect transistor) by, for example, in-situ doping or ion implantation. Advantageously, the height of the source / drain portion 1011 can be less than the height of the sacrificial gate 1007. For both the first and second sacrificial gates, the first source / drain portion 1011 can be formed through the first sacrificial gate using a mask, followed by the second source / drain portion formed through the second sacrificial gate. The formation process is identical.

[0091] Next, a replacement gate process may be performed.

[0092] For example, Figure 4 As shown, an interlayer dielectric layer 1013 can be formed on the semiconductor layer 1005. The interlayer dielectric layer can be an oxide layer. For example, the interlayer dielectric layer 1013 can be formed by depositing an oxide and then planarizing the deposited oxide, such as by CMP. CMP can be performed until the sacrificial gate 1007 inside the sacrificial gate spacer 1009 is exposed. In this step, the first sacrificial gate and the second sacrificial gate can be exposed simultaneously by CMP.

[0093] like Figure 5 As shown, the sacrificial gate 1007 and the sacrificial gate spacer 1009 can be removed by selective etching to release a space 1015 between the source / drain 1011, thereby forming an opening pattern. The opening pattern exposes the surface of the semiconductor layer 1005. Since the sacrificial gate spacer 1009 is removed in addition to the sacrificial gate 1007, there may be no gate spacer between the gate stack and the source / drain 1011 that is subsequently formed in the released space 1015. In another embodiment, the gate spacer may be retained.

[0094] It should be pointed out here that Figure 5 For convenience, the space 1015 is shown as having a substantially uniform width in the vertical direction. However, considering the morphology of the sacrificial gate spacer 1009, the space 1015 may have a shape in which the lower width is greater than the upper width.

[0095] Afterwards, if Figure 6As shown, ions can be implanted into the semiconductor layer 1005 with the opening pattern facing it. The process parameters of multiple ion implantation steps can be set according to the number, respective depths, and concentrations of the shell portion 1005-1 and the core portion 1005-2, so as to form ion implantation regions with different depths and concentrations in the semiconductor layer 1005, thereby providing at least one shell portion 1005-1 and at least one core portion 1005-2. For example, for an n-type field-effect transistor, n-type ions are first implanted with a predetermined energy to provide the ion distribution of the core portion 1005-2, then the implantation energy is adjusted to implant p-type ions to provide the ion distribution of the shell portion 1005-1. Subsequently, the implantation energy can be continuously reduced to implant p-type ions to provide the ion distribution of the second shell portion 1005-1.

[0096] For a p-type field-effect transistor, p-type ions are first implanted with a predetermined energy to provide the ion distribution of the core portion 1005-2, then the implantation energy is adjusted to implant n-type ions to provide the ion distribution of the shell portion 1005-1. Subsequently, the implantation energy can be continuously reduced to implant n-type ions to provide the ion distribution of the second shell portion 1005-1.

[0097] It should be noted here that Figure 6 only schematically shows the ion distribution forms of the shell portion 1005-1 and the core portion 1005-2. In the present invention, especially in the case where the channel portion structures are the same, the first and second semiconductor devices may not need to use a mask for selective etching of the first sacrificial gate and the second sacrificial gate to simultaneously remove the first sacrificial gate and the second sacrificial gate. And for the space between the first source / drain portion and the second source / drain portion obtained after removal, the core-shell structure can be formed by ion implantation and annealing without using a mask.

[0098] In the present invention, when performing ion implantation, due to the existence of the opening pattern, ions can be implanted into the portion of the semiconductor layer 1005 exposed in the opening, while the entire SOI substrate is covered with the interlayer dielectric layer 1013, and the ions are blocked when implanted into the interlayer dielectric layer 1013. Therefore, there is no need to separately provide a hard mask and an alignment process to perform the ion implantation process, thereby simplifying the manufacturing process and ensuring the accuracy of implantation.

[0099] Thereafter, as Figure 7As shown, a gate stack can be formed in the space 1015, for example, by a deposition method. For example, a first gate dielectric layer 1017, a work function layer 1019, and a gate conductor layer 1021 can be sequentially formed directly on the surface of the semiconductor layer 1005 to obtain the final gate stack. The first gate dielectric layer 1017 can be a high-k gate dielectric, such as a hafnium oxide layer, and the hafnium oxide layer can have a thickness of about 2 nm. The work function layer 1019 can be TiN. In one embodiment, the gate stack can include the gate conductor layer 1021, and the gate conductor layer 1021 can include a gate electrode metal such as tungsten (W), etc.

[0100] For an n-type field effect transistor (which can correspond to the first semiconductor device) and a p-type field effect transistor (which can correspond to the second semiconductor device), the corresponding shell part 1005-1 and core part 1005-2 or shell part 1005-1' and core part 1005-2' can be formed respectively as above, and n-type and p-type work function layers can be formed respectively (refer to Figure 8 ). In one embodiment, the threshold voltage of the n-type field effect transistor and the threshold voltage of the p-type field effect transistor can be set to be substantially symmetric, which can simplify the manufacturing process of the semiconductor device and can reduce the manufacturing cost.

[0101] As Figure 7 shown, the semiconductor device according to an embodiment can include a gate stack, and the gate stack can be between the source / drain parts 1011.

[0102] In addition, the work function layer includes a metal material, such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), etc., but not limited thereto.

[0103] Subsequently, as Figure 8 shown, the drain part 1011-1 of the first semiconductor device and the drain part 1011-2 of the second semiconductor device are electrically connected, and the gate stacks of the first semiconductor device and the second semiconductor device are electrically connected (in fact, the gate conductor layer 1021-1 of the gate stack of the first semiconductor device is electrically connected to the gate conductor layer 1021-2 of the gate stack of the second semiconductor device), forming an inverter.

[0104] One aspect of the present invention discloses a semiconductor device, including: a substrate 1001; a buried oxide layer 1003 on the substrate; and a semiconductor layer 1005 stacked above the buried oxide layer. The semiconductor device includes a third semiconductor device part 300 and a drift part 400.

[0105] In this embodiment, the third semiconductor device portion 300 includes: a third channel portion, including a third part of the semiconductor layer; a third source / drain portion 1011-3, arranged above the buried oxide layer 1005 and connected to the opposite ends of the third channel portion; and a third gate stack between the third source / drain portions 1011-3, arranged on the third channel portion.

[0106] The drift portion 400 includes a drift portion channel, comprising a fourth portion of the semiconductor layer, the drift portion channel having a greater length in the direction of extension of the semiconductor layer than the third channel portion; a fourth source / drain portion 1011-4 disposed above the buried oxide layer and connected to opposite ends of the drift portion channel; and an oxide layer 1030 disposed above the drift portion channel, between the fourth source / drain portions 1011-4. In projection, the third portion of the semiconductor layer of the third channel portion is located between the source / drain portions 1011-3, and the fourth portion of the semiconductor layer of the drift portion channel portion is located between the source / drain portions 1011-4. Although reference numerals are not used in the drawings herein to indicate these positions, their respective positions should be understood.

[0107] The third channel portion includes at least one shell portion 1005-1'' and at least one core portion 1005-2'' that are spaced apart from each other and overlapped in the projection direction, the drift portion channel includes at least one shell portion 1005-1''' and at least one core portion 1005-2'' that are spaced apart from each other and overlapped in the projection direction, the shell portions 1005-1'', 1005-1''' and the core portions 1005-2'', 1005-2''' have opposite doping types; and the drain portion 1011-3 of the third semiconductor device portion is the source portion 1011-4 of the drift portion, Figure 9 Shown as 1011-3 / 4.

[0108] In the above embodiments, Figure 9 The semiconductor device according to the present invention is described as including a third semiconductor device portion and a drift portion; however, in another embodiment of the present invention, Figure 9 The semiconductor device shown is described as including source / drain portions 1011-3, 1011-4 and transition semiconductor portions 1011-3 / 4 (eg, Figure 9 The three components have the same doping type. Those skilled in the art will understand that, although the description has changed, the arrangement of the components in the structure and their corresponding functions are the basis for achieving the overall function of the semiconductor device of the present invention.

[0109] Here, it should be understood that the third and fourth terms follow the first and second terms. For the purpose of distinction and identification, the third semiconductor device portion is not necessarily different from the first semiconductor device in the aforementioned example. On the contrary, the two may have the same structure. The structure and manufacturing process of the third semiconductor device portion can refer to the first semiconductor device in the aforementioned example.

[0110] In the present invention, the third semiconductor device portion 300 and the drift portion 400 constitute a semiconductor device that can withstand high voltage applications (e.g., 10V). For example, the third semiconductor device portion 300 is an n-type semiconductor device, and the drift portion 400 has a p-type shell portion. The drift portion 400 can be used as a charge balancing region, thereby increasing the breakdown voltage, and the shell-core structure reduces the operating resistance.

[0111] In this example, unlike the aforementioned inverter, the drift portion 400 has an oxide layer 1040 between the fourth source / drain portions and no gate stack. Furthermore, unlike the aforementioned inverter, the fourth channel portion of the drift portion 400 has a different size than the third channel portion of the third semiconductor device. The longer fourth channel portion of the drift portion 400 enables the semiconductor device to operate at high voltages.

[0112] In addition, if Figure 9 The illustrated embodiment may include a configuration having two shells and one core as in the previous embodiment, or a configuration having other numbers of shells and cores.

[0113] A method for manufacturing a semiconductor device is provided in accordance with aspects of the present invention. The method includes: forming a buried oxide layer 1003 on a substrate 1001; forming a semiconductor layer 1005 on the buried oxide layer 1003; forming a third sacrificial gate and a fourth sacrificial gate on the semiconductor layer 1005; in some embodiments, forming a third sacrificial gate spacer on a sidewall of the third sacrificial gate, wherein the fourth sacrificial gate has a greater width or length (in the channel extension direction) than the third sacrificial gate;

[0114] Source / drain portions 1011-3 and 1011-4 are formed on opposite sides of the third sacrificial gate spacer and the fourth sacrificial gate, and a source / drain portion 1011-3 / 4 of the same doping type is formed between the third sacrificial gate spacer and the fourth sacrificial gate. The third and fourth source / drain portions overlap with the third and fourth sacrificial gates in the channel extension direction.

[0115] Removing the third sacrificial gate and the fourth sacrificial gate and optionally removing the third sacrificial gate spacer to release the third space and the fourth space between the source / drain;

[0116] forming at least one core portion and at least one shell portion 1005-1", 1005-1'' in the semiconductor layer by ion implantation (and annealing) in the third space and the fourth space, wherein the at least one shell portion is located above the at least one core portion 1005-2", 1005-2''; and

[0117] forming a gate stack on the semiconductor layer 1005 in a third space, and forming an oxide layer on the semiconductor layer in a fourth space, wherein the third space corresponds to a third sacrificial gate and the fourth space corresponds to a fourth sacrificial gate;

[0118] The doping type of the source / drain is opposite to the doping type of at least one shell portion 1005 - 1 ″, 1005 - 1 ′″, and is the same as the doping type of at least one core portion 1005 - 2 ″, 1005 - 2 ′″.

[0119] In this embodiment, since the drift portion 400 is longer in size, a third sacrificial gate and a fourth sacrificial gate of different sizes are formed; based on the third and fourth sacrificial gates, source / drain portions of the same doping type are formed, for example, three source / drain portions all of which are n-type doped. The term source / drain portion is used here only for convention, and it should be understood that they are semiconductor components of the same doping type.

[0120] By removing the third sacrificial gate and the fourth sacrificial gate to form the third space and the fourth space, and by ion implantation combined with annealing doping in the third space and the fourth space, a shell-core structure is formed in the semiconductor layer 1005. The description of the above example can be referred to and will not be repeated here.

[0121] Semiconductor devices according to embodiments of the present disclosure can be applied to electronic devices operating in various voltage ranges. For example, integrated circuits (ICs) (e.g., less than 2V) can be formed based on such semiconductor devices to construct electronic devices. Such electronic devices may also include components such as higher-voltage displays (e.g., greater than 5V) that operate in conjunction with the ICs, as well as wireless transceivers that operate in conjunction with the ICs. Such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and mobile power supplies.

[0122] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0123] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A substrate; A buried oxide layer on the substrate; And A semiconductor layer stacked above the buried oxide layer; Wherein the semiconductor device includes a first semiconductor device of a first type and a second semiconductor device of a second type, wherein the first semiconductor device includes: A first channel portion, including a first portion of the semiconductor layer; A first source / drain portion of a first doping type, disposed above the buried oxide layer and connected to opposite ends of the first channel portion; and A first gate stack between the first source / drain portions, disposed on the first channel portion; and The second semiconductor device includes: A second channel portion, the second channel portion including a second portion of the semiconductor layer; A second source / drain portion of a second doping type, disposed above the buried oxide layer and connected to opposite ends of the second channel portion; and A second gate stack between the second source / drain portions, disposed on the second channel portion; Wherein the first channel portion and the second channel portion respectively include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in the projection direction, and the at least one shell portion and the at least one core portion have dopings of opposite doping types; Wherein the drain portion of the first semiconductor device and the drain portion of the second semiconductor device are electrically connected, and the first gate stack of the first semiconductor device and the second gate stack of the second semiconductor device are electrically connected.

2. A semiconductor device, comprising: A substrate; A buried oxide layer on the substrate; And A semiconductor layer stacked above the buried oxide layer; Wherein the semiconductor device includes a third semiconductor device portion and a drift portion, wherein the third semiconductor device portion includes: A third channel portion, including a third portion of the semiconductor layer; A third source / drain portion, disposed above the buried oxide layer and connected to opposite ends of the third channel portion; and A third gate stack between the third source / drain portions, disposed on the third channel portion; and The drift portion includes: A drift portion channel, including a fourth portion of the semiconductor layer, and the length of the drift portion channel in the extending direction of the semiconductor layer is greater than that of the third channel portion; A fourth source / drain portion, disposed above the buried oxide layer and connected to opposite ends of the drift portion channel, and the doping type of the fourth source / drain portion is the same as that of the third source / drain portion; and An oxide layer between the fourth source / drain portions, disposed on the drift portion channel; Wherein the third channel portion and the drift portion channel respectively include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in the projection direction, and the at least one shell portion and the at least one core portion have dopings of opposite doping types; and Wherein the drain portion of the third semiconductor device portion is the source portion of the drift portion.

3. The semiconductor device according to claim 1 or 2, wherein the thickness of one shell portion of the at least one shell portion is 5 nm to 10 nm, and / or the thickness of one core portion of the at least one core portion is 10 nm to 50 nm.

4. The semiconductor device according to claim 1 or 2, wherein the at least one core portion includes one core portion or two core portions, and / or wherein the at least one shell portion includes one shell portion or two shell portions.

5. The semiconductor device according to claim 4, wherein the shell portion and the core portion are obtained by performing an ion implantation process and an annealing process on the semiconductor layer.

6. The semiconductor device according to claim 1 or 2, wherein the gate stack includes a work function layer and a gate metal conductive layer.

7. The semiconductor device according to claim 6, wherein the gate stack includes a first gate dielectric layer.

8. The semiconductor device according to claim 1, wherein, The first semiconductor device includes a source / drain portion of a first doping type and a first gate dielectric layer, and the work function on the first gate dielectric layer is of a first type; the second semiconductor device includes a source / drain portion of a second doping type and a second gate dielectric layer, and the work function layer on the second gate dielectric layer is of a second type.

9. A method of manufacturing a semiconductor device, comprising: Forming a buried oxide layer on a substrate; Forming a semiconductor layer on the buried oxide layer; Forming a first sacrificial gate and a second sacrificial gate on the semiconductor layer, and respectively forming a first sacrificial gate spacer and a second sacrificial gate sidewall on sidewalls of the first sacrificial gate and the second sacrificial gate; Using a mask, forming a first source / drain portion of a first doping type on opposite sides of the first sacrificial gate spacer, and forming a second source / drain portion of a second doping type on opposite sides of the second sacrificial gate, wherein the first source / drain portion of the first doping type and the second source / drain portion of the second type overlap with the first sacrificial gate and the second sacrificial gate in a channel extension direction; Removing the first sacrificial gate, the second sacrificial gate, and optionally removing sidewalls of the first sacrificial gate and the second sacrificial gate sidewall to release a space between the first source / drain portion and the second source / drain portion; Forming at least one core portion and at least one shell portion in the semiconductor layer in the space; Forming a gate stack on the semiconductor layer in the space; And Electrically connecting a drain of the first source / drain portion of the first doping type and a drain of the second source / drain portion of the second type, and electrically connecting the gate stack between the first source / drain portions of the first doping type and the gate stack between the second source / drain portions of the second type; Wherein, a semiconductor layer of a channel portion of the first source / drain portion of the first doping type and a channel portion between the second source / drain portions of the second type includes at least one shell portion of a second doping type and at least one core portion of a first doping type, and the doping of the first doping type and the second doping type are opposite doping types.

10. A method of manufacturing a semiconductor device, comprising: Forming a buried oxide layer on a substrate; Forming a semiconductor layer on the buried oxide layer; Forming a third sacrificial gate and a fourth sacrificial gate on the semiconductor layer, and optionally forming a third sacrificial gate spacer on a sidewall of the third sacrificial gate, wherein a width of the fourth sacrificial gate is greater than that of the third sacrificial gate; Forming source / drain portions of the same doping type on opposite outer sides of the third sacrificial gate spacer and the fourth sacrificial gate, and between the third sacrificial gate spacer and the fourth sacrificial gate, and the source / drain portions overlap with the third sacrificial gate and the fourth sacrificial gate in a channel extension direction; Removing the third sacrificial gate and the fourth sacrificial gate and optionally removing the third sacrificial gate spacer to release a third space and a fourth space between the source / drain portions; Form at least one core portion and at least one shell portion in the semiconductor layer in the third space and the fourth space, where the at least one shell portion is located above the at least one core portion; and Form a gate stack on the semiconductor layer in the third space and form an oxide layer on the semiconductor layer in the fourth space, where the third space corresponds to a third sacrificial gate and the fourth space corresponds to a fourth sacrificial gate; wherein, the doping type of the source / drain portion is opposite to the doping type of the at least one shell portion and the same as the doping type of the at least one core portion.

11. The method according to claim 9 or 10, wherein, Form at least one core portion and at least one shell portion in the semiconductor layer by ion implantation.

12. The method according to claim 9 or 10, wherein The thickness of one shell portion of the at least one shell portion is 5 nm to 10 nm, and / or the thickness of one core portion of the at least one core portion is 10 nm to 50 nm.

13. The method according to claim 9, wherein Forming the gate stack includes: Sequentially form a first gate dielectric layer, a work function layer, and a gate conductive layer on the exposed surface of the semiconductor layer.

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