3D cell and array structure and process

Abstract

Various 3D cells, array structures, and processes are disclosed. In one embodiment, a memory cell structure is provided, comprising: a vertical bit line; an insulator surrounding a first portion of the vertical bit line; a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line; and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure further includes a first dielectric layer surrounding the extended portion of the conductor material; a first conductor layer surrounding the first dielectric layer; a second conductor layer surrounding the first conductor layer; a second dielectric layer on top surfaces of the first conductor layer and the second conductor layer; a third dielectric layer on bottom surfaces of the first and second conductor layers; a first gate on a top surface of the second dielectric layer; and a second gate on a bottom surface of the third dielectric layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority under 35 U.S.C.§119(e) to the following U.S. Provisional Patent Applications: U.S. Provisional Patent Application No. 63 / 417,535, titled "3D Cell and Array Structures", filed on October 19, 2022; U.S. Provisional Patent Application No. 63 / 417,606, titled "3D Memory Cell and Array Structures", filed on October 19, 2022; U.S. Provisional Patent Application No. 63 / 418,011, titled "3D Cell and Array Structures", filed on October 20, 2022; U.S. Provisional Patent Application No. 63 / 418,534, titled "3D Array Structures and Processes", filed on October 22, 2022; U.S. Provisional Patent Application No. 63 / 421,522, titled "3D Cell and Array Structures", filed on November 1, 2022; U.S. Provisional Patent Application No. 63 / 458,634, titled "3D Cell and Array Structures", filed on April 11, 2023; U.S. Provisional Patent Application No. 63 / 459,406, titled "3D Cell and Array Structures and Processes", filed on April 14, 2023; U.S. Provisional Patent Application No. 63 / 460,406, titled "3D Memory Cell and Array Structures", filed on April 19, 2023; U.S. Provisional Patent Application No. 63 / 463,040, titled "3D Memory Cell and Array Structures", filed on April 30, 2023; U.S. Provisional Patent Application No. 63 / 465,526, titled "3D Cell and Array Structures", filed on May 10, 2023; U.S. Provisional Patent Application No. 63 / 466,155, titled "3D Cell and Array Structures", filed on May 12, 2023; U.S. Provisional Patent Application No. 63 / 467,004, titled "3D Cell and Array Structures", filed on May 16, 2023; and U.S. Provisional Patent Application No. 63 / 542,526, titled "3D Array Structures and Processes", filed on October 5, 2023. The entire contents of all of the above applications are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to the field of memory, and more particularly to memory cell and array structures and related processes. Background Art

[0004] As the complexity and density of electronic circuits continue to increase, the size, complexity, and cost of memory become important considerations. One way to increase memory capacity is to use a three-dimensional (3D) array structure. However, a high-performance and cost-effective 3D array structure has not been fully realized. Summary of the Invention

[0005] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and related processes are disclosed. In one embodiment, aspects of the present invention can be applied to form dynamic random access memory (DRAM). In other embodiments, aspects of the present invention can be applied to form ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), and magnetoresistive random access memory (MRAM). In still other embodiments, aspects of the present invention can be applied to form memory elements called "synapses" in artificial neural networks, as well as any other memory applications.

[0006] In one exemplary embodiment, a memory cell structure is provided, including: a vertical bit line; an insulator surrounding a first portion of the vertical bit line; a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line; and an extension of a conductor material surrounding the continuous semiconductor layer. The memory cell structure further includes: a first dielectric layer surrounding the extension of the conductor material; a first conductor layer surrounding the first dielectric layer; a second conductor layer surrounding the first conductor layer; a second dielectric layer on the top surfaces of the first conductor layer and the second conductor layer; a third dielectric layer on the bottom surfaces of the first conductor layer and the second conductor layer; a first gate on the top surface of the second dielectric layer; and a second gate on the bottom surface of the third dielectric layer.

[0007] In another exemplary embodiment, a memory cell structure is provided, including: a vertical bit line; an insulator surrounding a first portion of the vertical bit line; a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line; an extension of a conductor material surrounding a portion of the continuous semiconductor layer; a first dielectric layer on the top surface of the extension of the conductor material; a second dielectric layer under the bottom surface of the extension of the conductor material; a first conductor layer on the top surface of the first dielectric layer; and a second conductor layer on the bottom surface of the second dielectric layer.

[0008] Other features and advantages of the exemplary embodiments of the present invention will become more apparent from the following detailed description, drawings, and claims. Brief Description of the Drawings

[0009] Exemplary embodiments of the present invention will be more fully understood from the following detailed description and the accompanying drawings, which illustrate various embodiments of the present invention, but should not be construed as limiting the present invention to these specific embodiments. The drawings are for explanatory and understanding purposes only.

[0010] Figure 1A FIGS. 1A to 1D illustrate an embodiment of a cell structure for a 3D array according to the present invention.

[0011] Figures 1E to 1F An embodiment of a 3D cell structure according to the present invention is shown.

[0012] Figure 1G Another embodiment of a 3D cell structure according to the present invention is shown.

[0013] FIGS. 2A to 2E respectively show the equivalent circuits of DRAM, FRAM, RRAM, PCM, and MRAM cell structures.

[0014] Figures 3A to 3B An embodiment of a 3D cell structure according to the present invention is shown.

[0015] Figures 4A to 4B An embodiment of a 3D cell structure according to the present invention is shown.

[0016] Figures 5A to 5B An embodiment of a 3D cell structure according to the present invention is shown.

[0017] Figures 6A to 6B An embodiment of a 3D cell structure according to the present invention is shown.

[0018] Figures 7A to 7H An embodiment of a brief process step configured to form a 3D cell structure according to the present invention is shown.

[0019] Figures 8A to 8I An embodiment of a 3D array structure according to the present invention is shown.

[0020] Figure 9A An embodiment of a 3D array structure according to the present invention is shown.

[0021] Figure 9B An embodiment of a 3D array structure according to the present invention is shown.

[0022] Figures 10A to 10B An embodiment of a 3D cell structure according to the present invention is shown.

[0023] Figures 10C to 10D An embodiment of a 3D cell structure according to the present invention is shown.

[0024] Figures 11A to 11BShows an embodiment of a 3D cell structure according to the present invention.

[0025] Figures 12A to 12J Shows an embodiment configured to form Figure 10A A brief process step of the 3D cell structure shown.

[0026] Figures 12K to 12N Shows an embodiment configured to form Figure 10C A brief process step of the 3D cell structure shown.

[0027] Figures 12O to 12S Shows an embodiment of a 3D cell structure according to the present invention.

[0028] Figures 13A to 13D Shows an embodiment of a 3D cell structure according to the present invention.

[0029] Figures 14A to 14B Shows an embodiment of a 3D cell structure according to the present invention.

[0030] Figure 15A Shows a side view of an embodiment of a 3D cell structure according to the present invention.

[0031] Figure 15B Shows a side view of an embodiment of a 3D cell structure according to the present invention.

[0032] Figures 15C to 15D Shows an embodiment of a 3D cell structure according to the present invention.

[0033] Figures 16A to 16B Shows an embodiment of a 3D cell structure according to the present invention.

[0034] Figures 17A to 17B Shows a side view of an embodiment of a 3D cell structure according to the present invention.

[0035] Figures 18A to 18C Shows a side view of an embodiment of a 3D cell structure according to the present invention.

[0036] Figures 19A to 19B Shows an embodiment of a cell structure with a source line configuration similar to Figure 14A and Figure 15A the cell structure shown.

[0037] Figure 20A Shows a side view of an embodiment of a 3D cell structure according to the present invention.

[0038] Figure 20B Shows a side view of an embodiment of a 3D cell structure according to the present invention.

[0039] Figure 21A A side view of an embodiment of a 3D cell structure according to the present invention is shown.

[0040] Figure 21B A side view of an embodiment of a 3D cell structure according to the present invention is shown.

[0041] Figures 22A to 22C An embodiment of a 3D cell structure according to the present invention is shown.

[0042] Figure 23 An embodiment of a 3D cell structure according to the present invention is shown. Detailed Description

[0043] Those of ordinary skill in the art will recognize that the following detailed description is exemplary and not restrictive. Other embodiments of the present invention will be apparent to those skilled in the art who benefit from the present disclosure. The implementation of exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Throughout the drawings and the following detailed description, the same reference numerals or numbers are used to refer to the same or similar components.

[0044] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and related processes are disclosed. For example, embodiments of the present invention relate to 3D NOR-type cells and array structures. However, aspects of the present invention can be applied to a variety of different memory technologies. In one embodiment, aspects of the present invention can be applied to form dynamic random access memory (DRAM). In one embodiment, aspects of the present invention can be applied to form ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), and magnetoresistive random access memory (MRAM). In another embodiment, aspects of the present invention can be applied to form memory elements called "synapses" in artificial neural networks. Additionally, aspects of the present invention can be applied to form a variety of other memory structures and applications.

[0045] Figure 1A An embodiment of a cell structure for a 3D array according to the present invention is shown.

[0046] Figure 1B Shown is Figure 1A the cell structure shown in, where gate 104a and gate dielectric layer 105a are removed to show the internal structure of the cell.

[0047] Figures 1C to 1D respectively show cross-sectional views of the cell structure taken along Figure 1A lines A-A' and B-B' in. It should be noted that in some cross-sectional views, additional materials of the structural components surrounding the bit line are shown for clarity.

[0048] The cell structure includes a vertical bit line (BL) 101 formed of a conductor material (such as metal or a heavily doped semiconductor material such as polysilicon). The cell structure also includes a semiconductor layer 102 formed of silicon, polysilicon, germanium, silicon germanium, gallium arsenide, cadmium selenide, indium gallium zinc oxide (IGZO), or other suitable semiconductor materials. The semiconductor layer 102 forms the channel of the cell transistor. In one embodiment, the semiconductor layer 102 is doped with a P-type or N-type impurity (such as boron or phosphorus) using diffusion, implantation, or in-situ doping processes, respectively.

[0049] The cell structure includes gates 104a-b formed of a conductor material (such as metal or polysilicon material). The cell structure also includes gate dielectric layers 105a-b formed of a thin oxide or high-K material (such as hafnium oxide (HfO2)). An insulator 107 formed of an insulating material such as oxide or nitride is also provided. The gates 104a-b can be connected to the word line (WL) of the memory array. The gates 104a-b, the gate dielectric layers 105a-b, and the semiconductor layer 102 form a double-gate thin-film transistor 119. The source and drain of the transistor are connected to layer 106 and the bit line 101, respectively.

[0050] Depending on the cell technology, layer 106 can be formed of different materials. In one embodiment for a dynamic random access memory (DRAM), layer 106 is a dielectric layer including a material formed of a thin oxide or high-K material (such as HfO2). The conductor layer 103 includes a material such as metal or polysilicon material. The conductor layer 103, the dielectric layer 106, and the semiconductor layer 102 form a capacitor.

[0051] In another embodiment for forming a ferroelectric random access memory (FRAM), layer 106 includes multiple layers, which include a ferroelectric layer (such as lead zirconate titanate (PZT), orthorhombic hafnium oxide (HfO2), or hafnium zirconium oxide (HfZrO2)) and a buffer layer (such as an oxide or high-K material (such as HfO2)).

[0052] In another embodiment for forming a resistive random access memory (RRAM), layer 106 includes multiple layers, which include an adjustable resistance layer (such as hafnium oxide (HfOx), titanium oxide (TiOx), and tantalum oxide (TaOx)).

[0053] In another embodiment for forming a phase change memory (PCM), layer 106 includes multiple layers, which include a phase change layer (such as chalcogenide glass, Ge2Sb2Te5 (GST)).

[0054] In another embodiment of forming a magnetoresistive random access memory (MRAM), layer 106 includes multiple layers, which include a top layer and a bottom layer formed of a ferromagnetic material (such as a nickel-iron (NiFe) or cobalt-iron (CoFe) alloy), and an intermediate tunneling barrier layer formed of a thin insulator (such as hafnium oxide (HfO2)).

[0055] It should be noted that the materials for forming layer 106 described above are only examples and not limitations, and any other suitable materials can be used to form layer 106. For ease of illustration, the following description will use a dielectric material in the embodiment, but any other suitable materials are within the scope of the present invention.

[0056] Figure 1E An embodiment of a 3D cell structure according to the present invention is shown.

[0057] Figure 1F Is shown Figure 1E The cell structure shown, in which the gate 104a and the gate dielectric layer 105a are removed to show the internal structure of the cell. This embodiment is similar to Figure 1A The embodiment shown, except that a heavily doped drain region 127 and a source region 128 are formed in the semiconductor layer 102. In one embodiment, the doping types of the drain region 127 and the source region 128 are opposite to those of the semiconductor layer 102 to form a junction transistor. In another embodiment, the doping types of the drain region 127 and the source region 128 are the same as those of the semiconductor layer 102 to form a junctionless transistor.

[0058] In one embodiment, the drain region 127 is formed by diffusing impurities into the semiconductor layer 102 by applying a diffusion process in the bit line hole for forming the bit line 101 before forming the bit line 101. The source region 128 is formed by diffusing impurities into the semiconductor layer 102 by applying a diffusion process before forming the conductor layer 103.

[0059] Figure 1G Another embodiment of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 1A The embodiment shown, except that the height of the cell is increased to increase the area of the dielectric layer 106 between the semiconductor layer 102 and the conductor layer 103. For the DRAM cell embodiment, the conductor layer 103, the dielectric layer 106, and the semiconductor layer 102 form a capacitor for charge storage. Increasing the cell height can increase the capacitance value, thereby increasing the amount of charge stored in the capacitor. Therefore, the data retention time of the DRAM cell is increased.

[0060] Figures 2A through 2E respectively illustrate equivalent circuits for DRAM, FRAM, RRAM, PCM, and MRAM cell structures. In one embodiment, the circuit of the cell structure includes a dual-gate select transistor 125 and a selected memory element (such as memory elements 126a-d). The dual-gate select transistor 125 includes gates 104a and 104b. Gates 104a and 104b are respectively connected to word lines WL1 and WL2. In another embodiment shown in Figure 2B, gates 104a and 104b are connected to the same word line (WL) to form a single-gate transistor. Memory elements 126a through 126d are formed by conductor layer 103, layer 106, and semiconductor layer 102. In another embodiment, dielectric layer 106 is formed of different materials to form various types of memory cells, such as Figure 1A described.

[0061] Figure 2A illustrates an embodiment of a DRAM cell, where memory element 126a is a capacitor. The capacitor is connected to conductor layer 103 that forms a conductor plate (also referred to as a capacitor plate (CP)). The conductor plate can provide a constant voltage, such as VDD or 1 / 2VDD.

[0062] Figure 2B illustrates an embodiment of a DRAM cell, where memory element 126a is a capacitor. This embodiment is similar to the embodiment shown in Figure 2A, except that gates 104a and 104b of the dual-gate transistor 125 are connected together.

[0063] Figure 2C illustrates an embodiment of a FRAM cell, where memory element 126b is a ferroelectric capacitor. The ferroelectric capacitor is connected to conductor layer 103 that forms a source line (SL).

[0064] Figure 2D illustrates embodiments of RRAM and PCM cells, where memory element 126c is a resistive memory element or a phase change memory element. Memory element 126c is connected to conductor layer 103 that forms a source line (SL).

[0065] Figure 2E illustrates an embodiment of an MRAM cell, where memory element 126d is a magnetoresistive memory element. The magnetoresistive memory element 126d is connected to conductor layer 103 that forms a source line (SL).

[0066] Figure 3A illustrates an embodiment of a 3D cell structure according to the present invention. This embodiment is the same as Figure 1ASimilar to the embodiments shown, the difference is that a conductor layer 109 including materials such as metals is added between the dielectric layer 106 and the semiconductor layer 102. For certain special technology types, the conductor layer 109 is formed of a specific metal material necessary for forming memory elements. For example, for the embodiment of the RRAM memory element, the conductor layer 109 is formed of titanium (Ti), platinum (Pt), copper (Cu), gold (Au) and other suitable materials therein.

[0067] Figure 3B shows Figure 3A the cell structure shown, in which the gate 104a and the gate dielectric layer 105a are removed to show the internal structure of the cell.

[0068] Figure 4A shows another embodiment of the 3D cell structure according to the present invention. This embodiment is similar to Figure 1A the embodiment shown, the difference being that the dielectric layer 106 is formed in another way. In Figure 1A it, the dielectric layer 106 is formed through the space occupied by the conductor layer 103 before forming the conductor layer 103. In Figure 4A it, the dielectric layer 106 is formed through the vertical bit line holes before forming the conductor layer 109 and the semiconductor layer 102.

[0069] Figure 4B shows Figure 4A the cell structure shown, in which the gate 104a and the gate dielectric layer 105a are removed to show the internal structure of the cell.

[0070] Figure 5A shows another embodiment of the 3D cell structure according to the present invention. This embodiment is similar to Figure 1A the embodiment shown, the difference being that the select transistor is formed as a conventional junction transistor instead of a thin film transistor. The source region 108 and the drain region 122 of the transistor are formed by heavily doped diffusion regions in the semiconductor material, and the transistor body 123 is formed by a lightly doped semiconductor material (such as lightly doped silicon material).

[0071] Figure 5B shows Figure 5A the cell structure shown, in which the gate 104a and the gate dielectric layer 105a are removed to show the internal structure of the cell. The doping types of the source region 108 and the drain region 122 are opposite to those of the body 123. For example, in one embodiment, the source region 108 and the drain region 122 are N+ type doped, and the body 123 is P- type doped; in another embodiment, the source region 108 and the drain region 122 are P+ type doped, and the body 123 is N- type doped.

[0072] Figure 6AAnother embodiment of the 3D cell structure according to the present invention is shown. This embodiment is similar to the Figure 1A embodiment shown, except that one of the gates (such as gate 104b) is removed and replaced by an insulating layer 129 formed of a material such as an oxide. This forms a single-gate transistor.

[0073] Figure 6B is shown Figure 6A the cell structure shown, in which gate 104a and gate dielectric layer 105a are removed to show the internal structure of the cell.

[0074] In one embodiment, the bottom portion of the semiconductor layer 102 is etched by the following steps: First, the insulating layer 129 is removed using an isotropic etching process (such as wet etching), and then the semiconductor layer 102 is etched using an isotropic etching process (such as wet etching). After that, an insulator such as an oxide is deposited to reform the insulating layer 129. It should be noted that this single-gate transistor structure can be applied to all other cell structure embodiments shown herein with minor modifications. These modifications and variations are all within the scope of the present invention.

[0075] Figures 7A to 7H An embodiment of the brief process steps configured to form a 3D cell structure according to the present invention is shown. To illustrate the process steps, the Figure 3A cell structure shown is taken as an example. Obviously, these process steps can be applied to form other cell structures shown herein with minor modifications. These modifications and variations are all within the scope of the present invention.

[0076] Figure 7A shows how multiple first sacrificial layers (such as layers 110a and 110b) and multiple second sacrificial layers (such as layer 111) are alternately deposited to form a stack. The first and second sacrificial layers have a high etching selectivity. For example, in one embodiment, the first sacrificial layers 110a-b are nitride layers and the second sacrificial layer 111 is an oxide layer. After forming the stack, all the layers in the stack are etched by an anisotropic etching process (such as deep trench etching) to form multiple vertical bit line holes (such as hole 112).

[0077] Figure 7B shows selective etching of the second sacrificial layer 111 by an isotropic etching process (such as wet etching) through the vertical bit line hole 112 to form a groove 113.

[0078] Figure 7CA series of operations are shown: through a deposition process such as chemical vapor deposition (CVD), the vertical bit line holes 112 and the grooves 113 are filled with a conductor material 109 (such as a metal or polysilicon material); then the conductor material in the bit line holes 112 is etched through an anisotropic etching process (such as dry etching) to form a residual conductor layer 109 in the grooves.

[0079] Figure 7D An isotropic etching process (such as wet etching) is shown to be performed through the vertical bit line holes 112 to selectively etch the conductor 109 in the grooves 113 to form the residual conductor layer 109 as shown. It should be noted that in one embodiment, to form Figure 1A the unit structure shown, the process steps shown Figures 7C to 7D can be skipped.

[0080] Figure 7E A semiconductor layer 102 (such as a silicon layer or an indium gallium zinc oxide (IGZO) layer) is shown to be formed on the sidewall surface of the vertical bit line holes 112 and the residual conductor 109 in the grooves 113 by using thin film deposition or epitaxial deposition.

[0081] Figure 7F A series of operations are shown: the vertical bit line holes 112 and the grooves 113 are filled with an insulating material 107 (such as an oxide material) through a deposition process; then an anisotropic etching process (such as dry etching) is performed to etch away the insulator 107 in the bit line holes 112, leaving only the residual insulator 107 in the grooves 113; finally, the vertical bit line holes 112 are filled with a conductor material (such as a metal or polysilicon) to form the vertical bit line 101.

[0082] Figure 7G How to remove the second sacrificial layer 111 is shown: through an isotropic etching process (such as wet etching); then a dielectric layer 106 is formed on the sidewall surface of the space previously occupied by the second sacrificial layer 111 and the residual conductor 109 through a thin film deposition process. According to the unit technology, the dielectric layer 106 can include multiple layers. In one embodiment, these multiple layers are formed by applying multiple thin film depositions. After depositing the dielectric layer 106, the space is filled with a conductor layer 103 (such as a metal or polysilicon layer) through a deposition process such as chemical vapor deposition (CVD).

[0083] Figure 7H A series of operations are shown: the first sacrificial layers 110a and 110b are removed through an isotropic etching process (such as wet etching); then a gate dielectric layer 105a - b composed of a thin oxide or high - K material is formed on the sidewall surface of the space previously occupied by the first sacrificial layers 110a - b through a thin film deposition process; finally, these spaces are filled with a conductor material (such as a metal or polysilicon) to form the gates 104a - b. Finally, Figure 3AThe unit structure shown.

[0084] Figures 8A to 8G An embodiment of a 3D array structure according to the present invention is shown. The 3D array includes a unit structure exemplified by the Figure 1A unit structure shown. It should be noted that the 3D array structure may include any other unit structure shown herein, and these modifications and variations are within the scope of the present invention.

[0085] Figure 8A Shows how multiple units (such as units 100a to 100c) are stacked to form a 3D array. Units 100a to 100c are separated by insulating layers 114a to 114c (which include materials such as oxides or nitrides). The array also includes vertical bit lines 101a to 101c, word lines 104a to 104f, and conductor layers 103a to 103c. In this embodiment, each unit (such as 100a) can be selected by connecting to two word lines (such as 104a and 104b) of the unit. In one embodiment, the two word lines (such as 104a and 104b) connected to each unit are connected to different decoder signals; in another embodiment, the two word lines (such as 104a and 104b) connected to each unit are connected to the same decoder signal.

[0086] Figure 8B Another embodiment of a 3D array structure according to the present invention is shown. This embodiment is Figure 8A similar to the embodiment shown, except that two adjacent units (such as 100a and 100b) share a word line 104b. Similarly, adjacent units (such as units 100c and 100d) share word line 104e. In one embodiment, this reduces the height of the 3D array structure. The shared word lines 104b and 104e can be grounded or provided with a 0V voltage to turn off the transistors between adjacent units. Units 100a and 100b are selected by word lines 104a and 104c respectively. Units 100c and 100d are selected by word lines 104d and 104f respectively.

[0087] Figure 8C Another embodiment of a 3D array structure according to the present invention is shown. This embodiment is Figure 8A similar to the embodiment shown, except that the word lines 104a to 104f are formed as layers instead of line patterns. In one embodiment, this reduces the chip size by reducing the horizontal space between the word lines. Figure 8C Vertical bit lines 101a to 101e are also shown. In one embodiment, the bit line selection transistors (such as Figures 8H to 8I shown) are located at the top or bottom of the array and are connected to each bit line to enable bit line selection.

[0088] Figure 8CThe 3D array structure shown is applicable to FRAM, RRAM, PCM, and MRAM applications, but not to DRAM applications. Since the read operation of DRAM cells is destructive, unselected cells connected to the selected word line layer may be turned on and cause charge sharing between the cell capacitor and the bit line capacitor, resulting in data loss. Therefore, for DRAM applications, there is provided Figure 8D the 3D array structure shown.

[0089] Figure 8D An embodiment of a 3D DRAM array structure according to the present invention is shown. In this embodiment, all layers are cut using an anisotropic etching process (such as deep trench etching) to form vertical slits (such as vertical slits 140a and 140b). The slits 140a and 140b cut the word line layer into individual word lines (such as individual word lines 104a to 104f).

[0090] Vertical bit lines (such as vertical bit lines 101a to 101c) connected to the same word line (such as word lines 104a to 104f) are connected to different horizontal bit lines 141a to 141c. In one embodiment, the horizontal bit lines 141a to 141c are formed of a conductor material (such as metal or polysilicon). The horizontal bit lines 141a to 141c may be located at the top of the 3D array (as Figure 8D shown) or at the bottom of the 3D array. By using this array structure, all cells selected by the selected word line will be coupled to the horizontal bit line to perform read and write-back (refresh) operations. Thus, the aforementioned data loss problem is solved.

[0091] Figure 8E Shows how to fill the Figure 8D vertical slits 140a and 140b shown with an insulating material 142a-b (such as an oxide) using a deposition process (such as chemical vapor deposition (CVD)).

[0092] Figure 8F Shows how to fill the Figure 8D vertical slits 140a and 140b shown with a conductor material (such as a metal material) to form vertical capacitor plates 143a and 143b. The capacitor plates 143a and 143b are connected to the conductor layer of the cell (such as layers 103a and 103b). In one embodiment, the capacitor plates 143a and 143b are connected to a constant voltage (such as VDD or ground).

[0093] In one embodiment, before forming the capacitor plates, an insulating layer (such as insulating layers 144a and 144b) is formed on the sidewalls of the word lines (such as word lines 104a to 104f) to prevent short - circuiting between the word lines and the vertical capacitor plates 143a and 143b. In one embodiment, by using an isotropic etching process (such as wet etching), the word line layers 104a to 104f are etched through the vertical slits 140a and 140b to form grooves in the word lines, and the insulating layers 144a and 144b are formed. Next, the grooves are filled with an insulator (such as an oxide insulator) to form the insulating layers 144a and 144b.

[0094] In another embodiment, a metal oxidation process is applied through the vertical slits 140a and 140b to form a metal oxide layer on the sidewalls of the word lines 104a to 104f, thereby forming the insulating layers 144a and 144b. Next, the vertical slits 140a and 140b are filled with a conductor material (such as a metal material) to form the capacitor plates 143a and 143b.

[0095] Figure 8G Another embodiment of a 3D DRAM array structure according to the present invention is shown. In this embodiment, Figure 1A The conductor layer 103 of the unit structure shown is formed of a sacrificial material (such as a nitride material) that has a high etch selectivity with respect to the word lines 104a and 104b. After forming Figure 8D the vertical slits 140a and 140b shown, an isotropic etching process (such as wet etching) is performed through the vertical slits 140a, 140b to etch the sacrificial layer to form grooves, such as grooves 146a and 146b.

[0096] Next, a thin dielectric layer 106 (such as a thin oxide or a high - K material (such as HfO2)) is formed on the sidewall surfaces of the slits 140a and 140b and the groove regions 146a and 146b by a thin - film deposition process. Next, the slits 140a and 140b and the groove regions 146a and 146b are filled with a conductor material (such as a metal) by a metal deposition process to form the capacitor plates 145a and 145b.

[0097] Figure 8H Another embodiment of a 3D DRAM array structure using the Figure 8C array structure shown according to the present invention is shown. The vertical bit lines (such as bit lines 101a to 101c) are connected to the horizontal bit lines 141a to 141c through the bit - line selection transistors 170a to 170c. The selection lines 171a to 171c are connected to the gates of the selection transistors (such as the selection transistors 170a to 170c). In one embodiment, the bit - line selection transistors 170a to 170c are vertical - channel transistors or other suitable types of transistors.

[0098] Figure 8I An embodiment is shown using a vertical channel transistor as a bit line selection transistor (such as bit line selection transistor 170a). The bit line selection transistor 170a is connected to the horizontal bit line 141a through a conductor contact 172.

[0099] Figure 9A An embodiment of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 1A the embodiment shown, except that insulating layers 114a and 114b are included between different cell layers. In this embodiment, the channel of the selection transistor is arranged in the horizontal direction (as indicated in semiconductor layer 102).

[0100] Figure 9B Another embodiment of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 9A the embodiment shown, except that the channel of the selection transistor is arranged in the vertical direction (as indicated in semiconductor layer 102). This transistor structure can be applied to all other cell structure embodiments shown herein. These modifications and variations are within the scope of the present invention.

[0101] Figure 10A Another embodiment of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 3A the embodiment shown, except that an extension portion 120 of the conductor layer 109 is added to increase the capacitance value. The extension portion 120 is formed of a conductor material (such as metal or polysilicon). The extension portion 120 is coupled to a conductor layer 121, which is formed of a material such as metal or polysilicon. The conductor layer 121 is also connected to the conductor layer 103.

[0102] Figure 10B Shows Figure 10A the cell structure shown, where the gate 104a and the gate dielectric layer 105a are removed to show the internal structure of the cell.

[0103] In one embodiment, Figures 10A to 10BThe unit structure shown includes: a vertical bit line 101; an insulator 107 surrounding a first portion of the vertical bit line 101; a continuous semiconductor layer 102 surrounding the insulator 107 and a second portion of the vertical bit line 101; an extension portion 120 of a conductor material surrounding the continuous semiconductor layer 102; and a dielectric layer 106 surrounding the extension portion 120 of the conductor material. The unit structure further includes: a conductor layer 121 surrounding the dielectric layer 106; a conductor layer 103 surrounding the conductor layer 121; a dielectric layer 105a on the top surfaces of the conductor layer 121 and the conductor layer 103; a dielectric layer 105b on the bottom surfaces of the conductor layer 121 and the conductor layer 103; a gate 104a on the top surface of the dielectric layer 105a; and a gate 104b on the bottom surface of the dielectric layer 105b.

[0104] Figure 10C Another embodiment of a 3D unit structure according to the present invention is shown. This embodiment is similar to Figure 10A the embodiment shown, except that the shape of the extension portion 120 is different from Figure 10A the shape shown. In this embodiment, the extension portion 120 is completely located inside the glove-shaped structure formed by the conductor layer 121.

[0105] Figure 10D Shown is Figure 10C the unit structure shown, where the gate 104a and the gate dielectric layer 105a are removed to show the internal structure of the unit.

[0106] Figure 11A Another embodiment of a 3D unit structure according to the present invention is shown. This embodiment is similar to Figures 10A to 10B the embodiment shown, except that the extension portion 120 is formed by an extension of the semiconductor layer 102.

[0107] Figure 11B Shown is Figure 11A the unit structure shown, where the gate 104a and the gate dielectric layer 105a are removed to show the internal structure of the unit.

[0108] Figures 12A to 12J Shown is an embodiment of a brief process step configured to form Figure 10A the 3D unit structure shown.

[0109] Figure 12A Shown is how a stack is formed by alternately depositing a plurality of first sacrificial layers 115a and 115b (including materials such as nitrides) and a plurality of second sacrificial layers 131 (including materials such as oxides). The first sacrificial layers 115a and the second sacrificial layers 115b have a high etch selectivity. Next, an anisotropic etching process (such as deep trench etching) is used to etch through all the layers of the stack to form a plurality of vertical bit line holes, such as bit line holes 117 (or openings).

[0110] Figure 12B Illustrates how to selectively etch the second sacrificial layer 131 by performing an isotropic etching process (such as wet etching) through the vertical bit line via 117 to form a groove 118.

[0111] Figure 12C Illustrates how to form a conductor layer 121 on the sidewall surfaces of the second sacrificial layer 131 and the first sacrificial layers 115a - b within the groove 118 using a thin - film deposition process. Next, fill the bit line via 117 and the groove 118 with an insulator 119 (such as an oxide or a nitride) using a deposition process. Subsequently, perform an anisotropic etching process (such as dry etching) to etch the conductor 121 to restore the bit line via 117.

[0112] Figure 12D Illustrates how to selectively etch the conductor layer 121 and the insulator 119 by performing an isotropic etching process (such as wet etching) through the vertical bit line via 117 to form the shown extended groove 130. In another embodiment, the shown structure is formed by two independent etching processes: perform a first etching process to etch only the insulator 119, and then perform a second etching process to etch the conductor layer 121 using the insulator 119 as a hard mask. Figure 12D Illustrates the steps of performing a first etching process to etch only the insulator 119, and then performing a second etching process to etch the conductor layer 121 using the insulator 119 as a hard mask.

[0113] Figure 12E Illustrates how to remove the insulator 119 by an isotropic etching process (such as wet etching). Next, form a thin dielectric layer 106 (such as a thin oxide or a high - K material) on the sidewall surfaces of the bit line via 117 and the groove 130 using a thin - film deposition process (such as atomic layer deposition (ALD)).

[0114] Figure 12F Illustrates a series of steps: deposit a conductor material 120 (such as a metal or polysilicon) to fill the bit line via 117 and the groove 130; then perform an anisotropic etching process (such as dry etching) to etch the conductor 120 in the bit line via 117, leaving the residual conductor within the groove; next, perform an isotropic etching process (such as wet etching) through the bit line via 117 to selectively etch the conductor layer 120 to form a partial groove 130. The remaining conductor layer 120 forms the Figure 10A shown extension 120. For Figures 11A to 11B the shown cell structure, the Figure 12F shown steps can be skipped.

[0115] Figure 12G Illustrates how to form a semiconductor layer 102 (including materials such as silicon, polysilicon, or IGZO) on the sidewall surfaces of the intermediate dielectric layer 106 and the conductor 120 by thin - film deposition (such as atomic layer deposition (ALD)), epitaxial growth, or epitaxial deposition through the bit line via 117.

[0116] Figure 12H shows a series of steps: filling bit line holes 117 and grooves 130 with an insulating material 107 (such as an oxide) using a deposition process (such as CVD) through the bit line holes 117; then performing an anisotropic etching process (such as dry etching) to etch away the insulator 107 in the bit line holes 117, leaving only the residual insulator in the grooves 130; and finally filling the bit line holes 117 with a conductor material 101 (such as a metal or polysilicon) to form vertical bit lines 101.

[0117] Figure 12I shows how to remove Figure 12H the second sacrificial layer 131 shown using an isotropic etching process (such as wet etching). Next, the resulting space is filled with a conductor material (such as a metal or polysilicon) to form a conductor layer 103.

[0118] Figure 12J shows how to remove the first sacrificial layers 115a and 115b using an isotropic etching process (such as wet etching). By using a thin film deposition process, gate dielectric layers 105a and 105b including materials such as a thin oxide or a high-K material are formed on the sidewall surfaces in the space previously occupied by the first sacrificial layers 115a and 115b. Next, the space is filled with a conductor material (such as a metal or polysilicon material) to form gates 104a and 104b. As a result, the Figure 10A unit structure shown is formed.

[0119] Figures 12K to 12N shows an example of a brief process step for configuring to form Figure 10C the 3D unit structure shown.

[0120] Figure 12K shows performing Figure 12E the unit structure formed after the process steps shown. The reader can refer to Figures 12A to 12E for a detailed description of the process steps performed to form Figure 12E the unit structure shown.

[0121] Figure 12L shows a series of process steps, where a conductor material 120 such as a metal or polysilicon material is deposited to fill the vertical bit line holes 117 and the grooves 130. Next, an anisotropic etching process such as dry etching is performed to etch the conductor 120 in the vertical bit line holes 117 and the conductor 120 in the grooves. Then, an isotropic etching process (such as wet etching) is performed through the vertical bit line holes 117 to selectively etch the conductor layer 120 to form the grooves 130. The residue of the conductor layer 120 forms Figure 10A the extension 120 shown. It should be noted that the shape of the conductor layer 120 is different from Figure 12FThe conductor layer shown.

[0122] Figure 12M Shows how a semiconductor layer 102 including a material such as silicon or indium gallium zinc oxide (IGZO) is formed on the surface of the dielectric layer 106 and the sidewalls of the conductor 120 by using thin film deposition or epitaxial deposition.

[0123] Figure 12N Shows a series of steps: A deposition process is performed through the bit line via 117 to fill the vertical bit line via 117 and the groove 130 with an insulating material 107 such as an oxide material. Next, an anisotropic etching process, such as dry etching, is performed to etch the insulator 107 in the vertical bit line via 117, except for the residue of the insulator 107 within the groove 130. Then, the vertical bit line via 117 is filled with a conductor material such as a metal or polysilicon material to form the vertical bit line 101. Next, the Figures 12I to 12J Process steps shown to form Figure 10C The cell structure shown.

[0124] Figure 12O Shows another embodiment of the 3D array structure according to the present invention. This embodiment is similar to Figure 8A The embodiment shown, except that the Figure 10C Cell structure shown is used as an example. For example. It should be noted that all the cell structures shown in other embodiments herein can also be applied to Figures 8A to 8I All the 3D array structures shown.

[0125] Figure 12O The embodiment shown shows how multiple cells (such as cells 100a to 100c) are stacked to form a 3D array. Cells 100a to 100c are separated by insulating layers 114a to 114c containing materials such as oxides or nitrides. The array also includes vertical bit lines 101a to 101c, word lines 104a to 104f, and conductor layers 103a to 103c.

[0126] Figure 12P Shows Figure 12O The 3D array structure shown, where the top word line 104a and part of the layer are removed to show the internal structure of the array.

[0127] Figure 12Q Shows according to the present invention Figures 12O to 12P A top view embodiment of the 3D array structure of Figure 12Q Shows cells 173a to 173h, vertical bit lines 101a to 101h, and horizontal bit lines 141a to 141h. Depending on the type of 3D array structure, the layer 174 can be a word line or a select line of a bit line select transistor. For example, when using Figure 8DWhen the 3D array structure shown is used, layer 174 forms word lines, such as word line 104a. When using Figures 8H to 8I the 3D array structure shown, layer 174 forms select lines, such as select line 171a. In one embodiment, the first row of cells 173a to 173g and the second row of cells 172b to 173h are staggered as shown. This enables the two rows of cells to be connected to one word line or select line 174.

[0128] Figure 12R Another embodiment of a top view of a 3D array structure according to the present invention is shown. Figures 12O to 12P This embodiment is similar to Figure 12Q the embodiment shown, except that four rows of cells, such as cells 173a to 173p, are staggered as shown. This enables the four rows of cells 173a to 173p to be connected to one word line or select line 174. Compared with Figure 12Q the embodiment shown, this embodiment triples the number of horizontal bit lines 141a to 141p. This will increase the "page" size used in read and write operations to improve memory performance.

[0129] Figure 12S Another embodiment of a top view of a 3D array structure according to the present invention is shown. Figures 12O to 12P This embodiment is similar to Figure 12Q the embodiment shown, except that six rows of cells 173a to 173x are staggered as shown. This enables the six rows of cells 173a to 173x to be connected to one word line or select line 174. Compared with Figure 12Q the embodiment shown, this embodiment quadruples the number of horizontal bit lines 141a to 141x. This will increase the "page" size used in read and write operations to improve memory performance.

[0130] Figures 12Q to 12S The embodiments shown are exemplary and not restrictive. In other embodiments, the cells are staggered with any other number of rows or in any other way. These variations and modifications are within the scope of the present invention.

[0131] Figures 13A to 13D An embodiment of a 3D cell structure according to the present invention is shown.

[0132] Figure 13A A side view of a 3D cell structure is shown. This embodiment of the 3D cell structure is similar to Figures 10A to 10B the embodiment shown, except that Figures 10A to 10BThe shown conductor layer 121 is divided into two conductor layers 133a and 133b formed of a metal or polysilicon material. The conductor plate 132 is formed of a metal or polysilicon material and connected to the semiconductor layer 102. The capacitor dielectric layers 106a and 106b include materials such as thin oxides or high-K materials (such as HfO2). The insulating layer 134 includes materials such as oxide or nitride materials. The conductor layers 133a and 133b, the capacitor dielectric layers 106a and 106b, and the conductor plate 132 form a capacitor.

[0133] The array further includes vertical bit lines 101 and gates 104a and 104b formed of a conductor material such as a metal or polysilicon material. The array further includes gate dielectric layers 105a and 105b that include materials such as thin oxides or high-K materials such as hafnium oxide (HfO2). The array further includes a semiconductor layer 102 that includes materials such as silicon or indium gallium zinc oxide (IGZO). The array further includes an insulator 107 that includes materials such as oxide or nitride materials. The array further includes insulating layers 114a and 114b that include materials such as oxide or nitride materials. In one embodiment, the gates 104a and 104b, the gate dielectric layers 105a and 105b, and the semiconductor layer 102 form two thin film select transistors.

[0134] Figures 13B to 13D A top view of a cross-section of the 3D cell structure taken along lines A-A', B-B', and C-C' as shown is presented. It should be noted that, Figure 13A A top view of a cross-section of the 3D cell structure taken along lines A-A', B-B', and C-C' as shown is presented. It should be noted that, Figure 13A The shown side view shows half of the cell, with the bit line 101 on the right. Figures 13B to 13D The shown top view shows the entire cell with the bit line 101 at the center.

[0135] Figures 14A to 14B An embodiment of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figures 13A to 13D the shown embodiment, except that the conductor layers 133a and 133b are replaced by a conductor layer 135. The conductor layer 135 is formed using an isotropic etching process (such as wet etching) to remove layers 133a, 133b, and 134, and then the capacitor dielectric layer 106 is formed using thin film deposition, and the conductor layer 135 is formed using a deposition process.

[0136] Figure 14B A top view of a cross-section taken along Figure 14A the line A-A' as shown is presented. The cross-sections along the lines B-B' and C-C' in Figure 14A are the same as those shown in Figures 13B to 13C It should be noted that, Figure 14AThe side view shown shows half of the cell, where the bit line 101 is on the right. Figure 14B The top view shown shows the entire cell with the bit line 101 in the center. It should be noted that Figure 13A and Figure 14A the cell structure shown can be applied to all other embodiments of the cell structure shown herein according to the present invention.

[0137] In one embodiment, Figures 14A to 14B the cell structure shown includes: a vertical bit line 101, an insulator 107 surrounding a first portion of the vertical bit line 101, a continuous semiconductor layer 102 surrounding the insulator 107 and a second portion of the vertical bit line 101, an extension of a conductor material 132 surrounding a first portion of the side surface of the continuous semiconductor layer 102, a dielectric layer 106 surrounding the extension of the conductor material 132 and a second portion of the side surface of the continuous semiconductor layer 102, and a conductor layer 135 surrounding the first dielectric layer. The cell structure further includes a dielectric layer 105a above the top surface of the conductor layer 135, a dielectric layer 105b below the bottom surface of the conductor layer 135, a conductor layer 104a on the top surface of the dielectric layer 105a, and a conductor layer 104b on the bottom surface of the dielectric layer 105b.

[0138] Figure 15A A side view showing another embodiment of the 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 14A the embodiment shown, except that the gates 104a and 104b are formed to have different shapes. In this embodiment, the channel of the select transistor as shown in FIG. 102 is in the vertical direction, while Figure 14A the channel of the select transistor shown is in the horizontal direction.

[0139] Figure 15B A side view showing another embodiment of the 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 14A the embodiment shown, except that the gates 104a and 104b are formed to have different shapes. In this embodiment, the channel of the select transistor as indicated by 102 is in the horizontal direction.

[0140] It should be noted that Figure 14A , Figure 15A and Figure 15B the gates 104a and 104b with different shapes shown in can be applied to all other embodiments of the cell structure shown herein according to the present invention.

[0141] The previous embodiments show one conductor plate 132 in the cell structure. However, according to the present invention, the cell structure can have multiple conductor plates 132.

[0142] Figure 15C A side view of an embodiment of a cell structure having two conductor plates 132a and 132b according to the present invention is shown. In other embodiments, the cell structure is configured to have any number of conductor plates.

[0143] Figure 15D A view shows along Figure 15C the line A - A’ shown in Figure 15C a cross - sectional view of the cell structure shown. Figure 15C The multi - conductor plate structure shown can be applied to all other embodiments of the cell structure shown herein according to the present invention. It should be noted that Figure 15C the side view shown shows half of the cell, with the bit line 101 on the right. Figure 15D The top view shown shows the entire cell with the bit line 101 at the center.

[0144] Figures 16A to 16B An embodiment of a 3D cell structure according to the present invention is shown. These embodiments are similar to Figures 14A to 14B the embodiment shown, except that the select transistor is formed as a conventional junction transistor instead of a thin - film transistor. As Figure 16A shown, the drain region 136 and the source region 137 are formed of a heavily doped semiconductor layer, such as a heavily doped silicon layer. The transistor body 138 is formed of a lightly doped semiconductor material such as a lightly doped silicon material. In one embodiment, the drain region 136 and the source region 137 have a doping type opposite to that of the body 137. It should be noted that Figure 16A the side view shown shows half of the cell, with the bit line 101 on the right side. Figure 16B The top view shown shows the entire cell with the bit line 101 at the center. The junction transistor structure shown in this embodiment can be applied to all other embodiments of the cell structure shown in the present invention.

[0145] Figures 17A to 17B A side view of an embodiment of a 3D cell structure according to the present invention is shown. These embodiments are similar to Figure 15B the embodiment shown, except that the conductor plate 132 is formed of a P - type semiconductor material such as silicon or polysilicon material. This allows the semiconductor plate 132 to store electric holes 150 to represent data. The holes 150 are generated by using any one of many suitable mechanisms. In one embodiment, the holes 150 are generated by using the band - to - band tunneling (BTBT) mechanism. The gates 104a and 104b are provided with a positive voltage to turn on the channel in the semiconductor layer 102, thereby transferring a suitable positive voltage (e.g., 2.5V) to the semiconductor plate 132. The semiconductor plate 132 is provided with a suitable negative voltage (e.g., - 2V). This causes the band - to - band tunneling effect to occur in the junction between the semiconductor layer 102 and the semiconductor plate 132 to inject the holes 150 into the semiconductor plate 132, asFigure 17A as indicated by the arrow in Figure 17A . When a low voltage such as 0V is provided to gates 104a and 104b to turn off the channel in semiconductor layer 102, the hole 150 is trapped within semiconductor plate 132.

[0146] Figure 17B A read operation is shown. During the read operation, the bit line 101 is precharged to an appropriate voltage. Gates 104a and 104b are provided with a positive voltage to turn on the channel in semiconductor layer 102. The hole 150 stored in semiconductor plate 132 flows through the channel towards bit line 101, as Figure 17B indicated by the arrow in Figure 17B , and causes charge sharing with the capacitance of bit line 101. This will change the voltage of bit line 101. If semiconductor plate 132 does not store a hole, the bit line 101 voltage will remain unchanged. A sense circuit (not shown) is coupled to bit line 101 to detect the voltage change to determine the data. Figures 17A to 17B The cell structure and operation shown in Figures 17A to 17B can be applied to all other embodiments of the cell structures shown herein according to the present invention.

[0147] Figures 18A to 18C A side view of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figures 17A to 17B the embodiment shown in Figures 17A to 17B , except that semiconductor plate 132 is connected to a source line 151 formed of a conductor material such as metal or heavily doped polysilicon material. Semiconductor plate 132 is formed of a P-type semiconductor material such as silicon or polysilicon material. This allows semiconductor plate 132 to store electric holes 150 to represent data. This cell structure is also referred to as a "floating body" cell structure.

[0148] Any one of many suitable mechanisms is used to generate hole 150. In one embodiment, hole 150 is generated by using the Figure 17A band-to-band tunneling (BTBT) mechanism described in Figure 17A . The reader may refer to Figure 17A for a detailed operation description.

[0149] In another embodiment, hole 150 is generated by using the "impact ionization" mechanism. Gates 104a and 104b are provided with a positive voltage to turn on the channel in semiconductor layer 102, thereby transferring an appropriate positive voltage (e.g., 2.5V) to semiconductor plate 132. Conductor layers 135a and 135b are provided with a low voltage (e.g., 0.7V to 1V) higher than the threshold voltage Vt to weakly turn on the channel in the surface of semiconductor plate 132 under conductor layers 135a and 135b. This results in the generation of hole 150 in the junction between semiconductor layer 102 and semiconductor plate 132, and hole 150 is injected into semiconductor plate 132, as Figure 18AAs shown by the arrow in []. When a low voltage such as 0V is applied to gates 104a and 104b to turn off the channel in semiconductor layer 102, holes 150 are trapped within semiconductor plate 132.

[0150] Figure 18B An operation of removing holes 150 from semiconductor plate 132 is shown. Gates 104a and 104b are supplied with a positive voltage to turn on the channel in semiconductor layer 102. Bit line 101 is supplied with a negative voltage (e.g., -1V). This causes a P-N forward bias current to occur from semiconductor plate 132 through the channel in semiconductor layer 102 to bit line 101, as Figure 18B shown by the arrow in []. The current evacuates holes 150 stored in semiconductor plate 132.

[0151] In another embodiment, bit line 101 is supplied with 0V. Conductor layers 135a and 135b are supplied with a positive voltage (e.g., 2V) to cause capacitive coupling to semiconductor plate 132. This causes the voltage of semiconductor plate 132 to be higher than the threshold voltage of the P-N junction, and causes a P-N forward current to flow from semiconductor plate 132 to bit line 101 to evacuate holes 150.

[0152] In another embodiment, a negative voltage (e.g., -1V or 0V) is applied to source line 151 instead of bit line 101. This causes a P-N forward current to occur in the junction between semiconductor plate 132 and source line 151 to evacuate holes to source line 151.

[0153] Figure 18C A read operation of the cell is shown. Bit line 101 and source line 151 are respectively supplied with different voltages (e.g., 1V and 0V). Gates 104a and 104b are supplied with a positive voltage to turn on the channel in semiconductor layer 102. Assuming that holes 150 are stored in semiconductor plate 132, holes 150 lower the threshold voltages of channels 152a and 152b in semiconductor layer 132 under conductor layers 135a and 135b. A read voltage higher than the threshold voltage is applied to conductor layers 135a and 135b. This turns on channels 152a and 152b to conduct current from bit line 101 to source line 151.

[0154] If semiconductor plate 132 does not store holes, the threshold voltages of channels 152a and 152b in semiconductor layer 152 will be higher than the read voltage applied to conductor layers 135a and 135b. Therefore, channels 152a and 152b will be turned off and will not conduct current. A sensing circuit (not shown) coupled to bit line 101 detects the current to determine the data. Figures 18A to 18C The structure and operation of source line 151 shown can be applied to all other embodiments of the cell structure shown herein according to the present invention.

[0155] Figures 19A to 19B illustrates embodiments of cell structures having a source line configuration similar to that of the source line 151 in the cell structure embodiments shown respectively in Figure 14A and Figure 15A

[0156] Figure 20A shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 15A except that additional insulating layers 160a and 160b including a material such as an oxide or a nitride are formed between the conductor layer 135 and the gates 104a and 104b. This configuration reduces the parasitic capacitance of the gates 104a and 104b to reduce the RC delay of the gates. This configuration also reduces the capacitive coupling of the gates 104a and 104b to the conductor layer 135. This feature can be applied to all other embodiments of the cell structures shown herein according to the present invention.

[0157] Figure 20B shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 20A except that the gate dielectric layers 105a and 105b are formed in different shapes. In Figure 20A , the gate dielectric layers 104a and 104b are formed to surround the gates 104a and 104b. In Figure 20B , the gate dielectric layers 104a and 104b are formed on the sidewalls of the semiconductor layer 102. This configuration of the gate dielectric layers can be applied to all other embodiments of the cell structures shown herein according to the present invention.

[0158] Figure 21A shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 15A except that additional channel regions 161a and 161b are formed in the semiconductor layer 102. In one embodiment, the channel regions 161a and 161b are formed by using an isotropic doping process (e.g., plasma doping or vapor doping) to dope the semiconductor layer 102 with a dopant of the opposite type, thereby inverting the doping type of the channel regions 161a and 161b. For example, if the semiconductor layer 102 is N+ doped, the channel regions 161a and 161b are doped with a P-type dopant such as boron to form P-channel regions. If the semiconductor layer 102 is P+ doped, the channel regions 161a and 161b are doped with an N-type dopant such as phosphorus to form N-channel regions.

[0159] In one embodiment, before forming the gates 104a and 104b and the gate dielectric layers 105a and 105b, a doping process is performed through the space occupied by the gates 104a and 104b. Figure 21A ​The features shown can be applied to all other embodiments of the cell structures shown herein according to the present invention.

[0160] Figure 21B A side view of another embodiment of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 15A the embodiment shown, except that the transistors of the cell are formed as junction transistors. The cell structure includes a semiconductor layer 163, which includes a material such as silicon or polysilicon that forms the transistor body. The semiconductor layer 163 can have P-type or N-type doping. The source region 164 is formed by using an isotropic doping process (such as plasma doping or vapor doping) to dope the semiconductor layer 163 with a dopant of the opposite type (such as an N-type or P-type dopant). In one embodiment, the doping process is applied through the space occupied by the conductor plate 132 and the conductor layer 135 before forming the conductor plate 132, the conductor layer 135, and the dielectric layer 106.

[0161] In one embodiment, the drain regions 165a and 165b are formed of a semiconductor material having a doping type opposite to that of the semiconductor layer 163. For example, in one embodiment, the semiconductor layer 163 is P-doped, and the source region 164 and the drain regions 165a and 165b are N+-doped. In another embodiment, the semiconductor layer 163 is N-doped and the source region 164 and the drain regions 165a and 165b are P+-doped.

[0162] In this embodiment, the bit line 101 is formed of a heavily doped semiconductor material such as heavily doped silicon or polysilicon material, which has a doping type opposite to that of the semiconductor layer 163. In another embodiment, if the bit line 101 is formed of metal, an insulating layer (not shown) including an oxide or a nitride is formed between the semiconductor layer 163 and the bit line 101 to prevent them from short-circuiting. Figure 21B The features shown can be applied to all other embodiments of the cell structures shown herein according to the present invention.

[0163] Figures 22A to 22C Another embodiment of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 20A the embodiment shown, except that the capacitor formed by the conductor plate 132 and the conductor layer 135 is formed in a different shape. For example, in Figure 20A it, the conductor layer 135 surrounds the conductor plate 132, while in Figure 22A it, the conductor plate 132 surrounds the conductor layer 135.

[0164] In this embodiment, the insulating layers 160a and 160b include materials such as oxide or nitride materials and are formed between the conductor plate 132 and the gates 104a and 104b. This configuration reduces the capacitive coupling from the gates 104a and 104b to the conductor plate 132. In another embodiment, the insulating layers 160a and 160b are removed to form a cell structure similar to Figure 15A the cell structure shown in the illustrated embodiment. The shape of the capacitor shown in this embodiment can be applied to all other embodiments of the cell structures shown herein according to the present invention.

[0165] Figures 22B to 22C The top cross-sectional views of the cell structure taken along lines A-A' and B-B' respectively are shown. Figure 22A The top cross-sectional view of the cell structure shown.

[0166] Figure 23 Another embodiment of a 3D cell structure according to the present invention is shown. This embodiment is similar to Figure 15A the embodiment shown, except that the gate 104b and the gate dielectric layer 105b are removed. This cell only has one gate 104a and an insulating layer 114b including materials such as oxide or nitride materials. This embodiment reduces the height of the cell. The reduced cell height allows for stacking more cells in a 3D array. This feature can be applied to all other embodiments of the cell structures shown herein according to the present invention.

[0167] Although, for purposes of illustration, Figures 20A to 23 the embodiment shown uses Figure 15A the cell structure shown, it is obvious that Figures 20A to 23 the features of the embodiment shown can also be applied to all other embodiments of the cell structures shown herein according to the present invention.

[0168] Although the exemplary embodiments of the present invention have been shown and described, it will be apparent to those of ordinary skill in the art that, based on the teachings herein, changes and modifications can be made without departing from the exemplary embodiments and their broader aspects. Accordingly, the appended claims are intended to cover all changes and modifications that are within the true spirit and scope of the exemplary embodiments of the present invention.

Claims

1. A memory cell structure, comprising: A vertical bit line; An insulator surrounding a first portion of the vertical bit line; A continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line; An extension of a conductor material surrounding the continuous semiconductor layer; A first dielectric layer surrounding the extension of the conductor material; A first conductor layer surrounding the first dielectric layer; A second conductor layer surrounding the first conductor layer; A second dielectric layer on top surfaces of the first conductor layer and the second conductor layer; A third dielectric layer on bottom surfaces of the first conductor layer and the second conductor layer; A first gate on the top surface of the second dielectric layer; and A second gate on the bottom surface of the third dielectric layer.

2. A memory cell structure, comprising: A vertical bit line; An insulator surrounding a first portion of the vertical bit line; A continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line; An extension of a conductor material surrounding a first portion of a side surface of the continuous semiconductor layer; A first dielectric layer surrounding the extension of the conductor material and a second portion of the side surface of the continuous semiconductor layer; A first conductor layer surrounding the first dielectric layer; A second dielectric layer above the top surface of the first conductor layer; A third dielectric layer below the bottom surface of the first conductor layer; A second conductor layer on the top surface of the first dielectric layer; And A third conductor layer on the bottom surface of the third dielectric layer.

Images