Post-treatment for removing dielectric surface residues

Abstract

A semiconductor structure, the semiconductor structure comprising: a first level comprising a metal layer, the metal layer being within a first dielectric layer formed on a substrate; a second level formed on the first level, the second level including an interconnect within a second dielectric layer and a barrier layer formed around the interconnect; and a metal capping layer disposed at an interface between the metal layer and the interconnect, where the metal capping layer includes tungsten (W) and has a thickness of between 20 angstroms and 40 angstroms.

Description

Background Technical Field

[0002] Embodiments herein relate to methods for use in the manufacture of electronic components, and more particularly, to a process for growing a selective tungsten (W) capping layer on tungsten (W) vias during a back-end-of-line (BEOL) process. Background Art

[0003] Tungsten (W) is widely used in the manufacture of integrated circuit (IC) components to form conductive features that are desired to have relatively low resistance and relatively high electromigration resistance. For example, tungsten can be used as a metal fill material to form source contacts, drain contacts, metal gate fills, gate contacts, interconnects (e.g., horizontal features formed in the surface of a dielectric material layer), and vias (e.g., vertical features formed to pass through a dielectric material layer to connect other interconnect features disposed above and below it). Due to the relatively low resistivity of tungsten, tungsten is also generally used to form interconnects at the M0 level of IC components, as well as bit lines and word lines, to address individual memory cells in a memory cell array of a three-dimensional NAND (3D NAND) component.

[0004] It has been found that conventional post-treatment methods for removing tungsten and chlorine residues from dielectric surfaces during component manufacturing processes can damage the dielectric surfaces.

[0005] Accordingly, a process is needed to address these issues. Summary of the Invention

[0006] Embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes: a first level including a metal layer within a first dielectric layer formed on a substrate; a second level formed on the first level, the second level including interconnects within a second dielectric layer and a barrier layer formed around the interconnects; and a metal capping layer disposed at an interface between the metal layer and the interconnects, wherein the metal capping layer includes tungsten (W) and has a thickness between 20 angstroms and 40 angstroms.

[0007] Embodiments of the present disclosure provide a method for post-treatment in a middle-of-line (MEOL) portion of a semiconductor structure. The method includes: performing a first pre-clean process to remove residues from a surface of a metal layer within a via formed in a dielectric layer; performing a first soak process including: a second pre-clean process to remove metal oxides from the surface of the metal layer within the via, and a fluoride-free tungsten (FFW) growth process to form a metal capping layer on the surface of the metal layer; and performing a second soak process to remove residues from exposed surfaces of the dielectric layer on multiple inner sidewalls of the via.

[0008] Embodiments of the present disclosure provide a method for forming a middle-of-line (MEOL) portion of a semiconductor structure. The method includes: performing a first pre-clean process to remove residues from a surface of a metal layer within a via formed in a dielectric layer; performing a first soak process including: a second pre-clean process to remove metal oxides from the surface of the metal layer within the via, and a fluorine-free tungsten (FFW) growth process to form a metal overlay on the surface of the metal layer; performing a second soak process to remove residues from multiple inner sidewalls of the via; performing a third pre-clean process to remove residues from the surface of the metal layer within the via; performing a first selective deposition process to selectively form a passivation layer on an exposed surface of the metal overlay; performing a second selective deposition process to form a barrier layer on the multiple inner sidewalls of the via; performing a removal process to remove the passivation layer from the surface of the metal layer; and performing a metal filling process to fill the via with a conductive via filling material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To enable a more particular understanding of the foregoing features of the present disclosure, reference may be made to the embodiments in which the present disclosure briefly summarized above is described in more detail, some of which are illustrated in the drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments of the present disclosure and should not be considered to limit its scope, as the present disclosure may admit other equivalent embodiments.

[0010] Figure 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure.

[0011] Figure 2A AND Figure 2B is a schematic diagram of an exemplary semiconductor structure 200. Figure 2A Illustrates a middle-of-line (MEOL) portion 200A of the semiconductor structure 200. Figure 2B Illustrates a back-end-of-line (BEOL) portion 200B of the semiconductor structure 200.

[0012] Figure 3 Depicts a method for forming a semiconductor structure having Figure 2A AND 2B the MEOL portion and the BEOL portion shown in the process flow diagram of the method.

[0013] Figure 4A 、 4B 、4C, 4D, 4E and 4F are cross-sectional views of a portion of the semiconductor structure 200 corresponding to various states of the Figure 3 method.

[0014] For ease of understanding, like reference numerals are used to denote like elements shared by the figures, where possible. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation. In the drawings and the following description, an orthogonal coordinate system including an X-axis, a Y-axis, and a Z-axis is used. For convenience, the directions indicated by the arrows in the figures are assumed to be positive. It is contemplated that elements disclosed in some embodiments may be beneficially used in other embodiments without specific recitation. Detailed Description

[0015] Embodiments herein generally relate to methods for use in the fabrication of electronic components, and more particularly, to systems and methods for depositing and growing a selective tungsten (W) capping layer on tungsten (W) vias during a back-end-of-line (BEOL) process.

[0016] The methods disclosed herein include a post-treatment (H2O soak) that significantly reduces the level of tungsten / chloride residues and better restores a tantalum nitride (TaN) barrier layer than conventional processes. Conventional post-treatment methods (e.g., remote plasma-assisted processes or capacitively coupled plasma (CCP) processes) are not as effective as the H2O soak disclosed herein for tungsten / chloride removal and do not fully restore the TaN barrier layer resistance. More importantly, conventional post-treatment methods damage the dielectric surface, and it has been found that the H2O soak disclosed herein does not cause such a situation. In the methods described herein, the H2O soak process can be performed in a chamber integrated within a multi-chamber processing system.

[0017] Example of a processing system

[0018] Figure 1 is a schematic top view of a multi-chamber processing system 100 in accordance with one or more embodiments of the present disclosure. Processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having respective transfer robots 112, 114, hold chambers 116, 118, and process chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in processing system 100 can be processed in each chamber and transferred between chambers without exposing the substrates to the surrounding environment outside of processing system 100 (e.g., an ambient atmosphere such as may exist in a semiconductor foundry). For example, substrates can be processed in each chamber maintained at a low pressure (e.g., less than or equal to about 300 torr) or a vacuum environment and transferred between chambers without disrupting the low pressure or vacuum environment between the various processes performed on the substrates in processing system 100. Thus, processing system 100 provides an integrated solution for some substrate processing.

[0019] Examples of processing systems that can be modified appropriately in accordance with the teachings provided herein include Endura ® , Producer ® or Centura ® integration processing systems or other suitable processing systems available from Applied Materials, Inc. located in Santa Clara, California, USA. It is contemplated that other processing systems (including systems from other manufacturers) may be adapted to benefit from aspects described herein.

[0020] In Figure 1 the illustrative example, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to assist in the transfer of substrates. The docking station 132 is adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed at one end of the respective factory interface robot 134, and the blade 138 is adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0021] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the hold chambers 116, 118 and respective ports 152, 154 coupled to the process chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the hold chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the process chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, slit valve openings with slit valves for passing substrates through the openings by transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, any port is open to allow the transfer of substrates through the ports. Otherwise, the ports are closed.

[0022] The load lock chambers 104, 106, transfer chambers 108, 110, hold chambers 116, 118, and process chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not shown in detail). The gas and pressure control system can include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), gas sources, various valves, and ducts fluidly coupling the chambers. In operation, the factory interface robot 134 transfers a substrate from the FOUP 136 through port 140 or 142 to the load lock chamber 104 or 106. Then, the gas and pressure control system pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the hold chambers 116, 118 in an internal low pressure or vacuum environment (which can include an inert gas). Thus, pumping down the load lock chamber 104 or 106 facilitates transferring the substrate between the atmospheric environment, such as the factory interface 102, and the low pressure or vacuum environment of the transfer chamber 108.

[0023] With the substrate in the load lock chamber 104 or 106 pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 through port 144 or 146 to the transfer chamber 108. Then, the transfer robot 112 can move the substrate to: either of the process chambers 120, 122 (for processing) through respective ports 152, 154 and either of the hold chambers 116, 118 (for holding awaiting further transfer) through respective ports 148, 150, and / or transfer between the process chamber and the hold chamber. Similarly, the transfer robot 114 can access the substrate in the hold chamber 116 or 118 through port 156 or 158, and can move the substrate to: either of the process chambers 124, 126, 128, 130 (for processing) through respective ports 160, 162, 164, 166 and either of the hold chambers 116, 118 (for holding awaiting further transfer) through respective ports 156, 158, and / or transfer between the process chamber and the hold chamber. Transfer and holding of the substrate within and between the chambers can be performed in the low pressure or vacuum environment provided by the gas and pressure control system.

[0024] The process chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing substrates. In some examples, the process chamber 120 can perform an etching process, the process chamber 122 can perform a cleaning process, and the process chambers 126, 128, 130 can perform respective epitaxial growth processes. The process chamber 120 can be a Selectra available from Applied Materials, Inc. of Santa Clara, California, USA TMEtching chamber. The processing chamber 122 can be an Aktiv chamber available from Applied Materials, Inc. of Santa Clara, California, USA TM Pre-cleaning (APC) chamber, a pre-cleaning XT (MCxT-2) chamber available from Applied Materials, Inc. of Santa Clara, California, USA, or a SiConi pre-cleaning chamber available from Applied Materials, Inc. of Santa Clara, California, USA TM Pre-cleaning chamber. The processing chambers 126, 128 or 130 can be a Centura™ Epi chamber, a Volta™ CVD / ALD chamber, an Encore™ PVD chamber, a selective tungsten deposition chamber, an ionized metal plasma physical vapor deposition (IMPPVD) chamber, a rapid thermal processing (RTP) chamber or a plasma etching (PE) chamber, each of which is available from Applied Materials, Inc. of Santa Clara, California, USA.

[0025] The system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100, or control the operation of the processing system 100 by controlling the controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data and feedback to be collected from the individual chambers to coordinate the performance of the processing system 100.

[0026] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172 and support circuitry 174. The CPU 170 can be one of any form of general-purpose processor that can be used in an industrial environment. The memory 172 or non-transitory computer-readable medium can be accessed by the CPU 170 and can be one or more of memories such as random access memory (RAM), read-only memory (ROM), disk drives, hard disks or any other form of local or remote digital storage. The support circuitry 174 is coupled to the CPU 170 and can include a cache memory, frequency circuitry, input / output subsystems, power supplies, etc. The various methods disclosed herein can generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction codes stored in the memory 172 (or the memory of a specific processing chamber), for example as software routines. When the CPU 170 executes the computer instruction codes, the CPU 170 controls the chambers to perform processes according to the various methods.

[0027] Other processing systems can present other configurations. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device in the processing system.

[0028] Exemplary semiconductor structure

[0029] Figure 2A And Figure 2B is a schematic diagram of an exemplary semiconductor structure 200. Figure 2A Illustrates the middle-of-line (MEOL) portion 200A of the semiconductor structure 200. Figure 2B Illustrates the back-end-of-line (BEOL) portion 200B of the semiconductor structure 200.

[0030] The MEOL portion 200A can include a first level L1 and a second level L2 (also referred to as the "M0 level"). The first level L1 includes a metal layer 202 (also referred to as "VD") within a first dielectric layer 204 formed on a substrate 206, and the second level L2 includes interconnects 208 within a second dielectric layer 210 formed on the first level L1. At the interface between the metal layer 202 and the interconnects 208, a metal capping layer 212 is provided to improve the contact resistance of the interconnects 208. At the second level L2, a barrier layer 214 can be formed around the interconnects 208. Between the first level L1 and the second level L2, an etch stop layer (ESL) 216 is provided.

[0031] The substrate 206 can include a heavily doped region 218 and a lightly doped region 220 (also referred to as "MD").

[0032] As used herein, the term "substrate" refers to a material layer that serves as a basis for subsequent processing operations and includes a surface to be cleaned. The substrate 206 can be a silicon-based material or any suitable insulating or conductive material as needed. The substrate 206 can include materials such as: crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0033] The metal layer 202 and the interconnects 208 can be formed of tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo).

[0034] The first dielectric layer 204 can be formed of the following materials: dielectric materials such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ); hafnium-containing materials such as hafnium oxide (HfO x , including HfO2), hafnium silicate (HfSi x O y , including HfSiO4), hafnium silicon oxynitride (HfSi x O y N z ), hafnium oxynitride (HfO x N y ), hafnium aluminate (HfAl x O y ), hafnium aluminum silicate (HfAl x Si y O z ), hafnium aluminum silicon oxynitride (HfAl w Si x O y N z ), hafnium lanthanum oxide (HfLa x O y ); zirconium-containing materials such as zirconium oxide (ZrO x , including ZrO2), zirconium silicate (ZrSi x O y , including ZrSiO4), zirconium silicon oxynitride (ZrSi x O y N z ), zirconium oxynitride (ZrO x N y ), zirconium aluminate (ZrAl x O y ), zirconium aluminum silicate (ZrAl x Si y O z ), zirconium aluminum silicon oxynitride (ZrAl w Si x O y N z ), zirconium lanthanum oxide (ZrLa x O y ); other aluminum-containing or lanthanum-containing materials such as aluminum oxide (Al2O3 or AlO x ), aluminum oxynitride (AlO x N y ), aluminum silicate (AlSi x O y ), aluminum silicon oxynitride (AlSi x O y N z ), lanthanum aluminate (LaAlx O y ), lanthanum oxide (LaO x or La2O3); other suitable materials; composite materials of the foregoing; or combinations of the foregoing. Other dielectric materials that can be used for the first dielectric layer 204 include titanium oxide (TiO x or TiO2), titanium oxynitride (TiO x N y ), tantalum oxide (TaO x or Ta2O5) and tantalum oxynitride (TaO x N y ). The second dielectric layer 210 can be formed of a low-k dielectric material such as silicon oxycarbide (SiOC).

[0035] The barrier layer 214 can be formed of titanium nitride (TiN) or tungsten (W).

[0036] The metal capping layer 212 can be formed of tungsten (W) having a thickness between about 20 angstroms and about 40 angstroms (e.g., about 20 angstroms). The ESL 216 can be formed of aluminum oxide (Al2O3).

[0037] The BEOL portion 200B can include a second level L2 and a third level L3 (also referred to as the "M1 layer"). The second level L2 includes interconnects 208 formed within the second dielectric layer 210, and the third level L3 includes a metal layer 222 formed within a third dielectric layer 224. In the third level L3, a barrier layer 226 can be formed around the metal layer 222, and a liner 228 can be formed around the barrier layer 226. The metal layer 222 can be formed of copper (Cu). The third dielectric layer 224 can be formed of a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). The barrier layer 226 can be formed of titanium (Ti) or tantalum (Ta). The liner 228 can be formed of titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W).

[0038] Post-processing of the dielectric surface

[0039] During the fabrication of the MEOL portion of a semiconductor structure, prior to depositing a barrier layer on the exposed surface of a dielectric layer, the exposed surface of the dielectric layer (e.g., the inner sidewall of a via formed in the dielectric layer) is pre-cleaned to remove residues (e.g., tungsten (W) or chlorine (Cl2)). Conventionally, the pre-cleaning is performed through plasma processing, such as a remote plasma-assisted process or a capacitively coupled plasma (CCP) process, in which the dielectric surface is damaged. The method described herein includes a water (H2O) soak process that effectively removes tungsten residues or chlorine residues from the exposed surface of the dielectric layer. The water (H2O) soak can be completed in the same processing chamber as the pre-cleaning process to pre-clean the surface of the metal layer without breaking the vacuum.

[0040] Figure 3 A process flow diagram of a method 300 for forming a semiconductor structure 200 having a MEOL portion 200A and a BEOL portion 200B as shown in accordance with one or more embodiments of the present disclosure. Figure 2A and Figure 2B illustrated. Figure 4A 、 4B 、4C, 4D, 4E, and 4F are cross-sectional views of a portion of the semiconductor structure 200 corresponding to various states of the method 300. It should be understood that Figure 4A 、 4B 、4C, 4D, 4E, and 4F illustrate schematic views of only a portion of the semiconductor structure 200, and the semiconductor structure 200 may contain any number of transistor segments and additional materials with aspects as illustrated in the figures. It should also be noted that although Figure 3 the methods shown are described in sequence, other process sequences including one or more operations that have been omitted and / or added and / or other process sequences that have been rearranged in another desired order fall within the scope of the embodiments of the present disclosure provided herein.

[0041] As Figure 4A illustrated, the MEOL portion 200A of the semiconductor structure 200 includes a first level L1 and a second level L2. The first level L1 includes a metal layer 202 (also referred to as "VD") formed in a first dielectric layer 204 on a substrate 206. The second level L2 includes a second dielectric layer 210 having a via 402 formed in the second dielectric layer 210 on the first level L1. Interconnects 208 ( Figure 4A not shown in

[0042] The metal layer 202 and the interconnect 208 can be formed of tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo). The first dielectric layer 204 and the second dielectric layer 210 can each be formed of the following materials: dielectric materials such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ); hafnium-containing materials such as hafnium oxide (HfO x , including HfO2), hafnium silicate (HfSi x O y , including HfSiO4), hafnium silicon oxynitride (HfSi x O y N z ), hafnium oxynitride (HfO x N y ), hafnium aluminate (HfAl x O y ), hafnium aluminum silicate (HfAl x Si y O z ), hafnium aluminum silicon oxynitride (HfAl w Si x O y N z ), hafnium lanthanum oxide (HfLa x O y ); zirconium-containing materials such as zirconium oxide (ZrO x , including ZrO2), zirconium silicate (ZrSi x O y , including ZrSiO4), zirconium silicon oxynitride (ZrSi x O y N z ), zirconium oxynitride (ZrO x N y ), zirconium aluminate (ZrAl x O y ), zirconium aluminum silicate (ZrAl x Si y O z ), zirconium aluminum silicon oxynitride (ZrAl w Si x O y N z ), zirconium lanthanum oxide (ZrLa x O y ); other aluminum-containing or lanthanum-containing materials such as aluminum oxide (Al2O3 or AlO x ), aluminum oxynitride (AlO x N y ), aluminum silicate (AlSi x O y), silicon aluminum oxynitride (AlSi x O y N z ), lanthanum aluminum oxide (LaAl x O y ), lanthanum oxide (LaO x or La2O3); other suitable materials; composites of the foregoing; or combinations of the foregoing. Other dielectric materials that can be used for the first dielectric layer 204 and the second dielectric layer 210 include titanium oxide (TiO x or TiO2), titanium oxynitride (TiO x N y ), tantalum oxide (TaO x or Ta2O5) and tantalum oxynitride (TaO x N y ).

[0043] The substrate 206 may include a heavily doped region 218 and a lightly doped region 220 (also referred to as "MD"). An etch stop layer (ESL) 216 is disposed between the first level L1 and the second level L2. The ESL 216 may be formed of aluminum oxide (Al2O3).

[0044] Method 300 begins at block 310, where a pre-clean process is performed to remove residues from the surface 202S of the metal layer 202 within the via 402. The pre-clean procedure can be performed in a pre-clean chamber, such as Figure 1 the processing chamber 122 shown.

[0045] During the fabrication of the second level L2, the semiconductor structure 200 may be exposed to air or other oxidizing environments, so the surface 202S of the metal layer 202 may be oxidized. Moreover, the etching process for forming the via 402 within the second dielectric layer 210 may also leave residues on the surface 202S of the metal layer 202, such as chlorine residues or fluorine residues. Therefore, before filling the via 402 from the bottom surface of the via 402 (the surface 202S of the metal layer 202) to form the interconnect 208, the surface 202S of the metal layer 202 within the via 402 is pre-cleaned.

[0046] The pre-clean process may include a plasma treatment process to remove chlorine or fluorine residues from the surface 202S of the metal layer 202. The plasma treatment process includes exposing the surface 202S of the metal layer 202 to a plasma formed by a process gas including a hydrogen-containing (H2) gas and a helium-containing (He) gas. The plasma treatment process can be a radical-based pre-cleaning technique using a remote plasma-assisted process in a processing chamber, such as Aktiv available from Applied Materials, Inc. of Santa Clara, California, USA TMPre-cleaning (APC) chamber. The plasma processing can be a capacitively coupled plasma (CCP) process performed in a processing chamber, such as the Preclean XT (MCxT-2) chamber available from Applied Materials, Santa Clara, California, USA. The plasma processing can be performed at a temperature between about 300 °C and about 400 °C (e.g., about 345 °C) and at a pressure between about 100 mTorr and about 500 mTorr (e.g., about 300 mTorr) for a duration between about 10 seconds and about 120 seconds, e.g., about 25 seconds. During the plasma processing, helium (He) gas can be supplied at a flow rate between about 300 sccm and about 500 sccm (e.g., about 380 sccm), and hydrogen (H2) gas can be supplied at a flow rate between about 10 sccm and 50 sccm (e.g., about 20 sccm).

[0047] In block 320, a first soak process is performed to selectively remove metal oxides (e.g., selectively remove metal oxides such as tungsten oxide (WO x ), or molybdenum oxide (MoO x ), where x = 2 or 3)) from the surface 202S of the metal layer 202, and then a metal overlay 212 is selectively formed on the surface 202S of the metal layer 202 within the via 402, as Figure 4B shown. The metal overlay 212 can be formed of tungsten (W) having a thickness between about 20 angstroms and about 40 angstroms, e.g., about 20 angstroms. The first soak process is performed in a processing chamber, such as Figure 1 the processing chamber 122 shown in

[0048] The first soak process can include a pre-cleaning process and a fluorine-free tungsten (FFW) growth process using chemical vapor deposition (CVD) techniques, where the surface 202S of the metal layer 202 is soaked in a precursor including tungsten chloride (WCl5) gas, which is provided to the processing chamber in a pulsed flow. In the pre-cleaning process, the surface 202S of the metal layer 202 is pre-cleaned. Subsequently, in the FFW growth process, a metal overlay 212 is selectively formed on the surface 202S of the metal layer 202 within the via 402, and its tungsten (W) is formed through the reaction of the precursor gas (e.g., WCl5) and hydrogen (H2). The first soak process is performed at a temperature between about 400 °C and about 450 °C (e.g., about 420 °C), at a pressure between about 10 Torr and about 50 Torr (e.g., about 15 Torr), for a duration between about 30 seconds and about 5 minutes, e.g., about 4 minutes.

[0049] In block 330, a second soak process is performed to remove tungsten residues and chlorine residues from the inner sidewalls of the vias 402 (e.g., the exposed surfaces of the second dielectric layer 210). The second soak process is performed in the same processing chamber as the pre-cleaning process in block 310, such as Figure 1 the processing chamber 122 shown.

[0050] In the second soak process, the surface 202S of the metal layer 202 is soaked in a precursor including water (H2O), which is provided in the processing chamber in a pulsed flow or a continuous flow. The second soak process is performed at a temperature between about 300 °C and about 450 °C (e.g., about 350 °C) and at a pressure between about 5 Torr and about 300 Torr (e.g., about 7.5 Torr) for a duration of about 30 seconds to about 300 seconds, e.g., about 120 seconds. During the second soak process, water (H2O) can be supplied at a flow rate between about 10 sccm and about 200 sccm (e.g., about 30 sccm), hydrogen (H2) can be supplied at a flow rate between about 500 sccm and 1500 sccm (e.g., about 1000 sccm), and argon (Ar) can be supplied at a flow rate between about 500 sccm and 1500 sccm (e.g., about 1000 sccm).

[0051] The inventors have found that the water (H2O) soak process can effectively remove tungsten (W) residues and chlorine residues from the dielectric surface, about 87% of the chlorine residues and about 32.5% of the tungsten residues.

[0052] The pre-cleaning process in block 310, the first soak process in block 320, and the second soak process in block 330 can be performed in the same chamber, such as Figure 1 the processing chamber 122 shown, without breaking the vacuum. After the second soak process in block 330, the semiconductor structure 200 undergoes a vacuum break for further fabrication.

[0053] In block 340, another pre-cleaning process is performed to remove impurities from the exposed surface of the metal capping layer 212. The pre-cleaning process in block 340 is the same as or similar to the pre-cleaning process in block 310.

[0054] In block 350, a first selective deposition process is performed to selectively form a passivation layer 404 on the exposed surface of the metal capping layer 212 (e.g., tungsten (W)), as Figure 4C shown. The first selective deposition process can be a soak process performed in a processing chamber (such as Figure 1 the processing chambers 124, 126, 128, or 130 shown).

[0055] The passivation layer 404 can be formed from a self-assembled monolayer (SAM) of organic molecules. In an immersion process, the semiconductor structure 200 is immersed in a gas precursor comprising an unsaturated hydrocarbon at a temperature of about 350 °C to about 400 °C, a pressure of 10 Torr to 60 Torr, for a duration between about 30 seconds to about 200 seconds, and the flow rate of the precursor is between about 300 sccm to about 600 sccm. In some embodiments, a liquid precursor is used in the immersion process. In the immersion process, the organic molecules in the precursor are only absorbed on the metal surface, such as the exposed surface of the metal overlay 212. The passivation layer 404 can act as a barrier layer to inhibit the nucleation or growth of subsequent material deposition thereon.

[0056] In block 360, a second selective deposition process is performed to form a barrier layer 214 on the inner sidewalls of the vias 402 but not on the passivation layer 404, as Figure 4D shown. The second selective deposition process can include an atomic layer deposition (ALD) process in a processing chamber (such as Figure 1 the processing chambers 124, 126, 128, or 130 shown).

[0057] The barrier layer 214 can be formed from tantalum nitride (TaN) or doped tantalum nitride (TaN), metal-doped TaN, titanium nitride (TiN), tungsten nitride (WN), or tungsten carbonitride (WCN).

[0058] In block 370, after the second selective deposition process in block 260, a removal process is performed to remove the passivation layer 404 from the surface 202S of the metal layer 202, as Figure 4E shown. The removal process can include a dry etching process in an etching chamber (such as Figure 1 the processing chamber 122 shown).

[0059] The removal process can include an anisotropic remote plasma-assisted dry etching process, such as a reactive ion etching (RIE) process, which uses a plasma formed from a gas comprising argon (Ar), helium (He), nitrogen (N2), hydrogen (H2), ammonia (NH3), or a combination of any of the foregoing. The plasma effluent directionally bombards and removes the passivation layer 404.

[0060] In block 380, a metal filling process is performed to fill the vias 402 with a conductive via filling material 406 to form an interconnect 208, as Figure 2A shown. The metal filling process can include any suitable deposition process in a processing chamber (such as Figure 1 the processing chambers 124, 126, 128, or 130 shown), such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or a wet process including electroplating.

[0061] In a metal filling process, a semiconductor structure 200 is exposed to a precursor of a conductive via filling material 406 that grows faster (e.g., about ten times faster) from an exposed surface of a metal capping layer 212 (e.g., tungsten (W)) than from an exposed surface of a barrier layer 214 (e.g., tantalum nitride (TaN)). The conductive via filling material 406 can be tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo).

[0062] In block 390, a BEOL formation process is performed to form a third tier L3 that includes a metal layer 222 formed within a third dielectric layer 224, as Figure 2B shown.

[0063] Embodiments described herein provide systems and methods for fabricating and growing a selective capping layer on a metal layer within a via during a back-end-of-line (BEOL) process. The methods disclosed herein include a post-treatment (H2O soak) that significantly reduces the level of tungsten / chloride residues on the dielectric surface and better restores a tantalum nitride (TaN) barrier layer than other conventional processes (e.g., remote plasma-assisted processes or capacitively coupled plasma (CCP) processes) without damaging the dielectric surface.

[0064] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A semiconductor structure, the semiconductor structure comprising: A first level, the first level including a metal layer, the metal layer within a first dielectric layer formed on a substrate; A second level, the second level formed on the first level, the second level including interconnects within a second dielectric layer and a barrier layer formed around the interconnects; And A metal capping layer, the metal capping layer disposed at an interface between the metal layer and the interconnects, wherein The metal capping layer includes tungsten (W) and has a thickness between 20 angstroms and 40 angstroms.

2. The semiconductor structure according to claim 1, wherein: The metal layer and the interconnects each include tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo); And The first dielectric layer and the second dielectric layer each include: silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), a hafnium-containing material, a zirconium-containing material, an aluminum-containing material, a lanthanum-containing material, or a combination of the above materials.

3. The semiconductor structure according to claim 1, wherein the barrier layer includes tantalum nitride (TaN).

4. A method for post-processing in a middle-of-the-line (MEOL) portion of a semiconductor structure manufacturing line, the method comprising: Performing a first pre-cleaning process to remove residues from a surface of a metal layer within a via formed in a dielectric layer; Performing a first soak process, the first soak process including: A second pre-cleaning process to remove metal oxides from the surface of the metal layer within the via; and A fluorine-free tungsten (FFW) growth process to form a metal capping layer on the surface of the metal layer; and Performing a second soak process to remove residues from exposed surfaces of the dielectric layer on multiple inner sidewalls of the via.

5. The method according to claim 4, wherein: The metal layer includes tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo); and The dielectric layer includes: silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), a hafnium-containing material, a zirconium-containing material, an aluminum-containing material, a lanthanum-containing material, or a combination of the above materials.

6. The method according to claim 4, wherein the first pre-cleaning process, the first soak process, and the second soak process are performed in the same processing chamber without breaking vacuum.

7. The method according to claim 4, wherein the first pre-cleaning process and the third pre-cleaning process each include a remote plasma-assisted process using a hydrogen (H2)-containing gas and a helium (He)-containing gas.

8. The method according to claim 4, wherein the first soaking process comprises: Immersing the surface of the metal layer in a precursor, the precursor including tungsten chloride (WCl5) gas, the precursor being provided in a pulsed flow form into a processing chamber.

9. The method according to claim 8, wherein the metal capping layer includes tungsten (W), the tungsten having a thickness between 20 angstroms and 40 angstroms.

10. The method according to claim 4, wherein the second soaking process comprises: Immersing the surface of the metal layer in a precursor, the precursor including water (H2O), the precursor being provided in a pulsed flow or continuous flow form into a processing chamber.

11. A method for forming a middle-of-the-line (MEOL) portion of a semiconductor structure, the method comprising: Performing a first pre-cleaning process to remove residues from a surface of a metal layer within a via formed in a dielectric layer; Performing a first soak process, the first soak process including: A second pre-cleaning process to remove metal oxides from the surface of the metal layer within the via; and A fluorine-free tungsten (FFW) growth process to form a metal capping layer on the surface of the metal layer; Perform a second soaking process to remove residues from multiple inner walls of the via; Perform a third pre-cleaning process to remove residues from the surface of the metal layer within the via; Perform a first selective deposition process to selectively form a passivation layer on the exposed surface of the metal capping layer; Perform a second selective deposition process to form a barrier layer on multiple inner walls of the via; Perform a removal process to remove the passivation layer from the surface of the metal layer; and Perform a metal filling process to fill the via with a conductive via filling material.

12. The method of claim 11, wherein: The metal layer comprises tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo); and The dielectric layer includes: silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), a hafnium-containing material, a zirconium-containing material, an aluminum-containing material, a lanthanum-containing material, or a combination of the above materials.

13. The method of claim 11, wherein each of the first pre-cleaning process and the third pre-cleaning process comprises a remote plasma-assisted process using a hydrogen (H2) gas and a helium (He) gas.

14. The method according to claim 11, wherein the first soaking process comprises: Immerse the surface of the metal layer in a precursor, the precursor comprising tungsten chloride (WCl5) gas, and the precursor is provided in a pulsed flow form into a processing chamber.

15. The method of claim 14, wherein the metal capping layer comprises tungsten (W), and the tungsten has a thickness between 20 angstroms and 40 angstroms.

16. The method according to claim 11, wherein the second soaking process comprises: Immerse the surface of the metal layer in a precursor, the precursor comprising water (H2O), and the precursor is provided in a pulsed flow or continuous flow form into a processing chamber.

17. The method of claim 11, wherein the first selective deposition process comprises a soaking process, and the passivation layer comprises a self-assembled monolayer (SAM) of organic molecules.

18. The method of claim 11, wherein the second selective deposition process comprises an atomic layer deposition (ALD) process, and the barrier layer comprises tantalum nitride (TaN).

20. The method according to claim 11, wherein the conductive via filling material comprises:

19. The method of claim 11, wherein the removal process comprises a dry etching process. Tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo).

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