Improved contact structure for power transfer on semiconductor devices

Abstract

A semiconductor structure with improved backside metal contacts includes a plurality of source / drain regions within a field effect transistor. The backside metal contact is electrically connected to at least one source / drain region of the plurality of source / drain regions. The backside metal contact includes a first tapered profile. The semiconductor structure also includes a backside power rail electrically connected to the at least one source / drain region through a backside metal contact. The backside power rail includes a second tapered profile different from the first tapered profile.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to the field of semiconductor devices, and more particularly, to power delivery for active devices.

[0002] Modern integrated circuits (ICs) are composed of transistors, capacitors, and other devices formed on a semiconductor substrate. On the substrate, these devices are initially isolated from each other, but are subsequently interconnected to form functional circuits. Typical interconnect structures include lateral interconnects such as metal wires (wiring), and vertical interconnects such as vias and contacts. Power is supplied to the integrated circuit through power rails in the metal layers of the integrated circuit. For example, the bottom metal layer (M0 or M1) may include multiple metal wires such as VDD power rails and VSS power rails.

[0003] As the size of ICs continues to scale down, backside power rails (BPRs), i.e., power rails typically formed under the transistor "fins" and on the backside of the wafer, and backside power delivery ( "backside" is under the transistor substrate), have been proposed to alleviate design challenges and enable technology scaling beyond the 5nm technology node. BPR technology can free up resources for dense logic connections that limit the performance of modern processors, enable further scaling of standard logic cells by removing the overhead in the area occupied by the power rails, and allow for the implementation of thicker low-resistance power rails with lower voltage (IR) drops. Although existing methods in semiconductor manufacturing have generally been sufficient to achieve their intended purposes, they are not entirely satisfactory in all respects. A particular area of concern includes forming metal contacts on the backside of the IC. SUMMARY OF THE INVENTION

[0004] According to an embodiment of the present disclosure, a semiconductor structure includes: a plurality of source / drain regions within a field-effect transistor; a backside metal contact electrically connected to at least one of the plurality of source / drain regions, the backside metal contact including a first tapered profile; and a backside power rail electrically connected to at least one source / drain region through the backside metal contact, the backside power rail including a second tapered profile different from the first tapered profile.

[0005] According to another embodiment of the present disclosure, a method of forming a semiconductor structure includes forming a plurality of source / drain regions within a field-effect transistor, forming a backside metal contact electrically connected to at least one of the plurality of source / drain regions, the backside metal contact including a first tapered profile, and forming a backside power rail electrically connected to at least one source / drain region through the backside metal contact, the backside power rail including a second tapered profile different from the first tapered profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following detailed description, given by way of example and not intended to be limiting of the present invention, will be best understood in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a top view of a semiconductor structure at an intermediate step during a semiconductor manufacturing process, depicting different cross-sectional views used to describe embodiments of the present disclosure;

[0008] Figure 2 is a cross-sectional view of the semiconductor structure taken along line Y1 - Y1' as shown in Figure 1 , depicting the formation of a nanosheet stack;

[0009] Figure 3 is a cross-sectional view of the semiconductor structure taken along line Y1 - Y1' as shown in Figure 1 , depicting the patterning of the nanosheet stack and the formation of nanosheet fins;

[0010] Figure 4A is a cross-sectional view of the semiconductor structure taken along line Y1 - Y1' as shown in Figure 1 , depicting the deposition of a dummy gate and a sacrificial hard mask;

[0011] Figure 4B is a cross-sectional view of the semiconductor structure taken along line Y2 - Y2' as shown in Figure 1 ;

[0012] Figure 4C is a cross-sectional view of the semiconductor structure taken along line X - X' according to an embodiment of the present disclosure;

[0013] Figure 5A is a cross-sectional view of the semiconductor structure taken along line Y1 - Y1' as shown in Figure 1 , depicting the removal of the nanosheet stack sacrificial layer;

[0014] Figure 5B is a cross-sectional view of the semiconductor structure taken along line Y2 - Y2' as shown in Figure 1 according to an embodiment of the present disclosure;

[0015] Figure 5C is a cross-sectional view of the semiconductor structure taken along line X - X' according to an embodiment of the present disclosure;

[0016] Figure 6A is a cross-sectional view of the semiconductor structure taken along Y1 - Y1' as shown in Figure 1 , depicting the formation of sidewall spacers;

[0017] Figure 6B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2' as shown in Figure 1 ;

[0018] Figure 6C is a cross-sectional view of a semiconductor structure taken along line X-X' according to an embodiment of the present disclosure;

[0019] Figure 7A is a cross-sectional view of a semiconductor structure taken along line Y1-Y1' as shown in Figure 1 according to an embodiment of the present disclosure, depicting the recessing of a nanosheet fin and the formation of an inner spacer;

[0020] Figure 7B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2' as shown in Figure 1 according to an embodiment of the present disclosure;

[0021] Figure 7C is a cross-sectional view of a semiconductor structure taken along line X-X' according to an embodiment of the present disclosure;

[0022] Figure 8A is a cross-sectional view of a semiconductor structure taken along line Y1-Y1' as shown in Figure 1 according to an embodiment of the present disclosure, depicting the formation of a spacer protection layer and the patterning of a backside contact;

[0023] Figure 8B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2' as shown in Figure 1 according to an embodiment of the present disclosure;

[0024] Figure 8C is a cross-sectional view of a semiconductor structure taken along line X-X' according to an embodiment of the present disclosure;

[0025] Figure 9A is a cross-sectional view of a semiconductor structure taken along Y1-Y1' as shown in Figure 1 according to an embodiment of the present disclosure, depicting the sigma etching of a first semiconductor layer;

[0026] Figure 9B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2' as shown in Figure 1 according to an embodiment of the present disclosure;

[0027] Figure 9C is a cross-sectional view of a semiconductor structure taken along line X-X' according to an embodiment of the present disclosure;

[0028] Figure 10A is a cross-sectional view taken along line Y1-Y1’ of a semiconductor structure according to an embodiment of the present disclosure, which depicts forming a dummy layer and removing a planarization layer; Figure 1

[0029] Figure 10B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2’ as shown in Figure 1 according to an embodiment of the present disclosure;

[0030] Figure 10C is a cross-sectional view of a semiconductor structure taken along line X-X’ according to an embodiment of the present disclosure;

[0031] Figure 11A is a cross-sectional view of a semiconductor structure taken along line Y1-Y1’ as shown in Figure 1 according to an embodiment of the present disclosure, which depicts removing a spacer protection layer and forming a BEOL interconnect level and a carrier wafer;

[0032] Figure 11B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2’ as shown in Figure 1 according to an embodiment of the present disclosure;

[0033] Figure 11C is a cross-sectional view of a semiconductor structure taken along line X-X’ according to an embodiment of the present disclosure;

[0034] Figure 12A is a cross-sectional view of a semiconductor structure taken along line Y1-Y1’ as shown in Figure 1 according to an embodiment of the present disclosure, which depicts completing front-end-of-line (FEOL) processing steps;

[0035] Figure 12B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2’ as shown in Figure 1 according to an embodiment of the present disclosure;

[0036] Figure 12C is a cross-sectional view of a semiconductor structure taken along line X-X’ according to an embodiment of the present disclosure;

[0037] Figure 13A is a cross-sectional view of a semiconductor structure taken along line Y1-Y1’ as shown in Figure 1 according to an embodiment of the present disclosure, which depicts performing a replacement metal gate process, performing middle-of-line contact patterning and metallization, and forming a BEOL interconnect level and a carrier wafer;

[0038] Figure 13B ​is a cross-sectional view of a semiconductor structure taken along line Y2-Y2’ as shown in Figure 1 in accordance with an embodiment of the present disclosure;

[0039] Figure 13C is a cross-sectional view of a semiconductor structure taken along line X-X’ in accordance with an embodiment of the present disclosure;

[0040] Figure 14A is a cross-sectional view of a semiconductor structure taken along Y1-Y1’ as shown in Figure 1 in accordance with an embodiment of the present disclosure, depicting the removal of a semiconductor substrate;

[0041] Figure 14B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2’ as shown in Figure 1 in accordance with an embodiment of the present disclosure;

[0042] Figure 14C is a cross-sectional view of a semiconductor structure taken along line X-X’ in accordance with an embodiment of the present disclosure;

[0043] Figure 15A is a cross-sectional view of a semiconductor structure taken along line Y1-Y1’ as shown in Figure 1 in accordance with an embodiment of the present disclosure, depicting the removal of a first sacrificial layer and etching of a portion of a first semiconductor layer to expose a placeholder layer;

[0044] Figure 15B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2’ as shown in Figure 1 in accordance with an embodiment of the present disclosure;

[0045] Figure 15C is a cross-sectional view of a semiconductor structure taken along line X-X’ in accordance with an embodiment of the present disclosure;

[0046] Figure 16A is a cross-sectional view of a semiconductor structure taken along Y1-Y1’ as shown in Figure 1 in accordance with an embodiment of the present disclosure, depicting the removal of a remaining Si-containing region;

[0047] Figure 16B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2’ as shown in Figure 1 in accordance with an embodiment of the present disclosure;

[0048] Figure 16C is a cross-sectional view of a semiconductor structure taken along line X-X’ in accordance with an embodiment of the present disclosure;

[0049] Figure 17A is a cross-sectional view of a semiconductor structure taken along line Y1-Y1’ as shown in Figure 1Cross-sectional view of the semiconductor structure along Y1-Y1’ as shown, depicting the formation of the first backside interlayer dielectric;

[0050] Figure 17B is a cross-sectional view of the semiconductor structure taken along Y2-Y2’ as shown in accordance with an embodiment of the present disclosure; Figure 1 Cross-sectional view of the semiconductor structure taken along Y2-Y2’ as shown;

[0051] Figure 17C is a cross-sectional view of the semiconductor structure taken along X-X’ in accordance with an embodiment of the present disclosure;

[0052] Figure 18A is a cross-sectional view of the semiconductor structure taken along Y1-Y1’ as shown in accordance with an embodiment of the present disclosure, depicting the selective removal of the dummy layer; Figure 1 Cross-sectional view of the semiconductor structure taken along Y1-Y1’ as shown, depicting the selective removal of the dummy layer;

[0053] Figure 18B is a cross-sectional view of the semiconductor structure taken along Y2-Y2’ as shown in accordance with an embodiment of the present disclosure; Figure 1 Cross-sectional view of the semiconductor structure taken along Y2-Y2’ as shown;

[0054] Figure 18C is a cross-sectional view of the semiconductor structure taken along X-X’ in accordance with an embodiment of the present disclosure;

[0055] Figure 19A is a cross-sectional view of the semiconductor structure taken along Y1-Y1’ as shown in accordance with an embodiment of the present disclosure, depicting the deposition of the backside metal; Figure 1 Cross-sectional view of the semiconductor structure taken along Y1-Y1’ as shown, depicting the deposition of the backside metal;

[0056] Figure 19B is a cross-sectional view of the semiconductor structure taken along Y2-Y2’ as shown in accordance with an embodiment of the present disclosure; Figure 1 Cross-sectional view of the semiconductor structure taken along Y2-Y2’ as shown;

[0057] Figure 19C is a cross-sectional view of the semiconductor structure taken along X-X’ in accordance with an embodiment of the present disclosure;

[0058] Figure 20A is a cross-sectional view of the semiconductor structure taken along Y1-Y1’ as shown in accordance with an embodiment of the present disclosure, depicting the patterning of the backside power rail; Figure 1 Cross-sectional view of the semiconductor structure taken along Y1-Y1’ as shown, depicting the patterning of the backside power rail;

[0059] Figure 20B is a cross-sectional view of the semiconductor structure taken along Y2-Y2’ as shown in accordance with an embodiment of the present disclosure; Figure 1 Cross-sectional view of the semiconductor structure taken along Y2-Y2’ as shown;

[0060] Figure 20Cis a cross-sectional view of a semiconductor structure taken along line X-X' according to an embodiment of the present disclosure;

[0061] Figure 21A is a cross-sectional view of a semiconductor structure taken along Y1-Y1' as shown in Figure 1 according to an embodiment of the present disclosure, which depicts the formation of a backside power delivery network;

[0062] Figure 21B is a cross-sectional view of a semiconductor structure taken along line Y2-Y2' as shown in Figure 1 according to an embodiment of the present disclosure; and

[0063] Figure 21C is a cross-sectional view of a semiconductor structure taken along line X-X' according to an embodiment of the present disclosure.

[0064] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to depict specific parameters of the present disclosure. The drawings are intended to only describe typical embodiments of the present disclosure. In the drawings, the same reference numerals denote the same elements. Detailed Description

[0065] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be implemented in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0066] For the purposes described below, terms such as "above", "below", "right", "left", "vertical", "horizontal", "top", "bottom" and derivatives thereof shall refer to the disclosed structures and methods as oriented in the drawings. Terms such as "above", "covering", "on top", "on top of", "located" or "situated on top" mean that a first element, such as a first structure, is present on a second element, such as a second structure, where an intermediate element, such as an interface structure, may be present between the first element and the second element. The term "in direct contact" refers to a connection where a first element (e.g., a first structure) and a second element (e.g., a second structure) are joined at the interface of the two elements without any intermediate conductive, insulating or semiconductor layer.

[0067] To avoid obscuring the presentation of the embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for presentation and for illustrative purposes, and in some instances may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of the various embodiments of the present invention.

[0068] It should be understood that although the disclosed embodiments include a detailed description of an exemplary nanosheet FET architecture having silicon and silicon germanium nanosheets, the implementation of the teachings described herein is not limited to the specific FET architecture described herein. Instead, embodiments of the present invention can be implemented in conjunction with any other type of FET device now known or later developed.

[0069] Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same, in which an improved backside metal contact is formed for connection to a power rail located on the backside of a wafer. The backside metal contact and the backside power rail are formed by a backside process performed after completing the BEOL process and flipping the wafer. Specifically, a sigma etch process is performed to achieve a backside contact having a first taper angle different from a second taper angle of the backside power rail. The sigma etch process and the use of a placeholder material allow for the simultaneous deposition of a conductive metal for forming the backside contact and the backside power rail in fewer processing steps, thereby simplifying the manufacturing process and increasing the contact area between the backside metal contact and the backside power rail to improve device performance and reliability.

[0070] The following will refer to Figures 1 to 21C the accompanying drawings to describe in detail embodiments of a semiconductor structure that can form an improved backside metal contact.

[0071] Now refer to Figure 1 , which depicts a top view of a semiconductor structure 100 during an intermediate step of a semiconductor manufacturing process according to an embodiment of the present disclosure. In particular, Figure depicts different cross-sectional views of the semiconductor structure 100 that will be used to describe embodiments of the present disclosure. The cross-sectional views are taken along line X-X', line Y1-Y1', and line Y2-Y2'. As shown in the accompanying drawings, line X-X' represents a cut along the nanosheet fin structure or nanosheet fin region 20 of the semiconductor structure 100, line Y1-Y1' represents a cut across the source / drain regions in the NFET region 12 and the PFET region 16 of the semiconductor structure 100, and line Y2-Y2' represents a cut along the gate structure or gate region 24 of the semiconductor structure 100.

[0072] In this embodiment, a cross-sectional view taken along line Y1-Y1' may also include a view of the NFET region 12 and / or the PFET region 16, as well as a view of the region (N-P boundary) 14 between the NFET and PFET regions 12, 16. Additionally, a cross-sectional view taken along line Y1-Y1' may include a view of the shared buried power rail (BPR) region 22.

[0073] Now refer to ​ , which depicts a cross-sectional view of a semiconductor structure 100 after forming a nanosheet stack 10 in accordance with an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 along Y1-Y1' in ​ .

[0074] In the depicted example, the semiconductor structure 100 includes a substrate 102, a first sacrificial layer 104 located above the substrate 102, and a first semiconductor layer 106 disposed above the first sacrificial layer 104. According to an embodiment, as shown, the first sacrificial layer 104 and the first semiconductor layer 106 are vertically stacked one on top of the other in a direction perpendicular to the substrate 102.

[0075] The substrate 102 may be, for example, a bulk substrate, which may be made of any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium phosphide. Generally, the substrate 102 may be approximately but not limited to a few hundred micrometers thick. In other embodiments, the substrate 102 may be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, where a buried insulator layer separates the bottom substrate from the top semiconductor layer.

[0076] Continuing to refer to ​, According to an embodiment, the first sacrificial layer 104 can be formed on the substrate 102 using an epitaxial growth process. For example, in this embodiment, the first sacrificial layer 104 is formed by epitaxially growing a SiGe layer with a germanium concentration varying from about 15 atomic percent to about 35 atomic percent. In a preferred embodiment, the first sacrificial layer 104 is made of epitaxially grown SiGe having a germanium concentration of approximately 30 atomic percent. In one or more embodiments, the first sacrificial layer 104 can act as an etch stop layer during subsequent substrate removal. Similarly, the first semiconductor layer 106 is formed by epitaxially growing an Si layer to a thickness varying from about 30 nm to about 150 nm, although other thicknesses are also within the scope contemplated by the present invention. In some embodiments, the first sacrificial layer 104 can include SiO2. In such an embodiment, the combined structure formed by the substrate 102, the first sacrificial layer 104, and the first semiconductor layer 106 can be a SOI wafer, where the first sacrificial layer 104 is a buried oxide (BOX) that includes a thickness in the range from about 20 nm to about 100 nm and ranges therebetween.

[0077] Generally, the first sacrificial layer 104 and the first semiconductor layer 106 can be formed by epitaxial growth using the substrate 102 as a seed layer. Terms such as "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of a semiconductor material on the deposition surface of a semiconductor material, where the grown semiconductor material has the same or substantially similar crystal properties as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same or substantially similar crystal properties as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for forming on a semiconductor surface and does not deposit material on a dielectric surface, such as a silicon dioxide or silicon nitride surface.

[0078] Non-limiting examples of various epitaxial growth processes include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metalorganic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). The temperature of the epitaxial deposition process can be in the range of 500 °C to 900 °C. Although higher temperatures generally result in faster deposition, faster deposition may lead to crystal defects and film cracking.

[0079] Many different precursors can be used for the epitaxial growth of the first sacrificial layer 104 and the first semiconductor layer 106. In some embodiments, the gas sources for depositing epitaxial semiconductor materials include silicon-containing gas sources, germanium-containing gas sources, or combinations thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source that includes, but is not necessarily limited to, silane, disilane, trisilane, tetrasilane, hexachloroethyldisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that includes, but is not necessarily limited to, germane, digermane, halogenated germanes, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. A combination of these gas sources can be used to form an epitaxial silicon-germanium alloy layer. A carrier gas, such as hydrogen, helium, and argon, can be used.

[0080] In the described embodiments, an alternating sequence of sacrificial semiconductor material layers and semiconductor channel material layers is vertically stacked one on top of the other in a direction perpendicular to the substrate 102 to form a nanosheet stack 10, as shown in the figures. Specifically, the alternating sequence includes a nanosheet stack sacrificial layer 108 above the first semiconductor layer 106, a second sacrificial semiconductor layer 110 above the nanosheet stack sacrificial layer 108, and a semiconductor channel layer 112 above the second sacrificial semiconductor layer 110. In the example depicted in the figures, alternating second sacrificial semiconductor layers 110 and semiconductor channel layers 112 are formed in the stack 10 above the nanosheet stack sacrificial layer 108. The term sacrificial as used herein means a layer or other structure that is removed (or a portion thereof) before the final device is completed.

[0081] For example, in the described example, portions of the second sacrificial semiconductor layer 110 will be removed from the stack in the channel region of the device to allow the semiconductor channel layer 112 to be released from the nanosheet stack 10. It is noted that while in this example the second sacrificial semiconductor layer 110 and the semiconductor channel layer 112 are made of silicon-germanium (SiGe) and silicon (Si), respectively, any combination of sacrificial and channel materials can be employed in accordance with the present technology. For example, alternatively, selective etching techniques can be employed that allow Si to be used as the sacrificial material between SiGe channel layers.

[0082] Continue to refer to ​, a first (sacrificial) layer in the stack, i.e., the nanosheet stack sacrificial layer 108, is formed on the first semiconductor layer 106 using an epitaxial growth process. For example, in the embodiment, the nanosheet stack sacrificial layer 108 is formed by epitaxially growing a SiGe layer having a higher germanium concentration varying between about 45 atomic percent and about 70 atomic percent. In a preferred embodiment, the nanosheet stack sacrificial layer 108 comprises a SiGe layer with a germanium concentration of about 55 atomic percent. The higher concentration of germanium atoms allows for the selective removal of the nanosheet stack sacrificial layer 108 relative to the remaining alternating layers of the nanosheet stack 10, as will be described in detail below. By way of example only, the nanosheet stack sacrificial layer 108 can be formed with a thickness varying from about 5 nm to about 20 nm, although thicknesses greater than 20 nm and less than 5 nm can also be used.

[0083] Generally, the layers (e.g., SiGe and Si layers) in the nanosheet stack 10 can be formed by epitaxial growth using the first semiconductor layer 106 as a seed layer. For example, the second sacrificial semiconductor layer 110 is formed by epitaxially growing a SiGe layer. In this embodiment, the germanium concentration of the second sacrificial semiconductor layer 110 can vary from about 15 atomic percent to about 35 atomic percent. In a preferred embodiment, each second sacrificial semiconductor layer 110 comprises a SiGe layer with a germanium concentration of about 30 atomic percent.

[0084] To continue building the nanosheet stack 10, the semiconductor channel layer 112 is formed by epitaxially growing a Si layer. As shown in the drawings, the second sacrificial semiconductor layer 110 and the semiconductor channel layer 112 have substantially similar or the same thickness. The nanosheet stack 10 is grown by forming the (SiGe) sacrificial semiconductor layer 110 and the (Si) semiconductor channel layer 112 in an alternating manner on the nanosheet stack sacrificial layer 108. Thus, each of the second sacrificial semiconductor layer 110 and the semiconductor channel layer 112 in the nanosheet layer stack 10 can be formed in the same manner as described above, e.g., using an epitaxial growth process, with a thickness varying from about 6 nm to about 12 nm, although other thicknesses are within the scope contemplated by the present invention.

[0085] Thus, each layer in the nanosheet stack 10 has nanoscale dimensions and can thus also be referred to as a nanosheet. Additionally, as described above, the (Si) semiconductor channel layer 112 in the nanosheet stack 10 will be used to form the channel layer of the device. Thus, the dimensions of the semiconductor channel layer 112 determine the dimensions of the channel region of the semiconductor structure 100.

[0086] As described above, the goal is to create a stack of alternating (sacrificial and channel) SiGe and Si layers on the wafer. The number of layers in the stack can depend on the specific application. Thus, the configurations depicted and described herein are merely examples intended to illustrate the technology. For example, the nanosheet stack 10 of the present invention may include more or fewer layers than shown in the figures.

[0087] The nanosheet stack 10 can be used to fabricate gate-all-around devices that include vertically stacked semiconductor channel material nanosheet layers for positive-channel field-effect transistor (hereinafter "PFET") or negative-channel field-effect transistor (hereinafter "NFET") devices.

[0088] In the illustrated embodiment, the semiconductor structure 100 further includes a hard mask layer 202 that is formed on the nanosheet stack 10 by depositing a hard mask material (e.g., silicon nitride) using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any suitable technique for dielectric deposition. By way of example only, the hard mask layer 202 can be formed to have a thickness varying from about 20 nm to about 200 nm, although thicknesses greater than 200 nm and less than 20 nm can also be used.

[0089] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after patterning the nanosheet stack 10 to form a plurality of nanosheet fins (hereinafter "nanosheet fins"). In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 of ​ along Y1 - Y1'.

[0090] After depositing ​ the hard mask layer 202 depicted in, then photolithographic patterning is performed on the deposited hard mask layer 202 to form a plurality of individual fin hard masks. According to an exemplary embodiment, reactive ion etching (RIE) can be used to etch through the nanosheet stack 10 to form the nanosheet fins 302. The etching process can continue until the upper portion of the first semiconductor layer 106 located between adjacent nanosheet fins 302 is removed, forming a plurality of trenches (not shown). Subsequently, the plurality of trenches (not illustrated) formed during the photolithographic patterning process are filled with an insulating material to form shallow trench isolation (STI) regions 310, as depicted in the figures.

[0091] The process of forming the STI region 310 is standard and well-known in the art, and typically includes depositing an insulating material to substantially fill a plurality of trenches (not shown) created after removing portions of the first semiconductor layer 106 located between adjacent nanosheet fins 302. According to an embodiment, the STI region 310 electrically isolates the nanosheet fins 302. The STI region 310 can be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the STI region 310 include silicon oxide, silicon nitride, silicon carbon oxide hydride, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics. After forming the STI region 310, the hard mask layer 202 can be removed from the semiconductor structure 100 using any suitable etching technique ( ​ ).

[0092] Now referring to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after depositing the dummy gate 410 and the sacrificial hard mask 420 according to an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1' drawn in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2', as shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X' depicted in ​ .

[0093] The dummy gate 410 and the sacrificial hard mask 420 form a sacrificial gate structure for the semiconductor structure 100. The processes of forming the dummy gate 410 and the sacrificial hard mask 420 are typical and well-known in the art. In one or more embodiments, the dummy gate 410 is formed of amorphous silicon (a-Si), and the sacrificial hard mask 420 is formed of silicon nitride (SiN), silicon oxide, an oxide / nitride stack, or similar materials and configurations.

[0094] After depositing the dummy gate 410 and the sacrificial hard mask 420 on the semiconductor structure 100, the dummy gate 410 and the sacrificial hard mask 420 are patterned as depicted in the drawings. As is known to those skilled in the art, the process of patterning the dummy gate 410 typically includes exposing a pattern on a photoresist layer (not shown) and transferring the pattern to the sacrificial hard mask 420 and the dummy gate 410 using known lithography and RIE processes, as shown in ​ . The dummy gate 410 is formed and patterned above the topmost semiconductor channel layer 112 and along the sidewalls of the nanosheet fins 302. As shown in ​As shown, patterning of the dummy gate 410 exposes portions of the topmost semiconductor channel layer 112 located between the sacrificial gate structures. As described above, ​ The cross-sectional view of ​ is taken along the line Y1 - Y1' as shown in ​ and thus does not show the sacrificial gate structures formed by the dummy gate 410 and the sacrificial hard mask 420.

[0095] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after removal of the nanosheet stack sacrificial layer 108 ( ​ ) in accordance with an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1 - Y1' depicted in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2 - Y2', as shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X - X' depicted in ​ .

[0096] As shown in the embodiment shown in ​ , removal of the nanosheet stack sacrificial layer 108 ( ​ ) creates a first opening 502 in the region of the semiconductor structure 100 from which the nanosheet stack sacrificial layer 108 ( ​ ) is removed. According to an embodiment, the nanosheet stack sacrificial layer 108 is selectively removed relative to the first semiconductor layer 106, the second sacrificial semiconductor layer 110, the semiconductor channel layer 112, the dummy gate 410, and the sacrificial hard mask 420. For example, a high-selectivity dry etching process can be used to selectively remove the nanosheet stack sacrificial layer 108 ( ​ ).

[0097] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after formation of the sidewall spacers 610. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1 - Y1' depicted in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2 - Y2', as shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X - X' depicted in ​ .

[0098] In this embodiment, a spacer material is deposited on the semiconductor structure 100. As ​ shown, the spacer material is deposited along the sidewalls of the dummy gate 410 and the sacrificial hard mask 420 to form sidewall spacers 610. The spacer material forming the sidewall spacers 610 substantially fills ​ the first opening 502 shown in. A spacer pull-down formation process can be used to form the sidewall spacers 610. The sidewall spacers 610 can also be formed using a sidewall image transfer (SIT) spacer formation process, which includes spacer material deposition followed by directional RIE of the deposited spacer material. In one or more embodiments, the spacer material deposited between the bottom surface of the nanosheet fin 302 and the substrate 102 can be referred to as the bottom dielectric isolation layer 620. In some embodiments, the bottom dielectric isolation layer 620 and the sidewall spacers 610 can be composed of different materials.

[0099] Non-limiting examples of various spacer materials for forming the sidewall spacers 610 and the bottom dielectric isolation layer 620 can include conventional low-k materials such as SiO2, SiOC, SiOCN, or SiBCN. Generally, the thickness of the sidewall spacers 610 can vary from about 5 nm to about 20 nm and vary therebetween.

[0100] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after recessing the nanosheet fin 302 and forming the inner spacer 720 according to an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1' drawn in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2', as ​ shown; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X' depicted in ​ .

[0101] As is known to those skilled in the art, the sidewall spacers 610 can be used as a mask to recess the portions of the nanosheet fin 302 that are not covered by the sidewall spacers 610 and the dummy gate 410, as ​ shown. For example, a RIE process can be used to recess the portions of the nanosheet fin 302 that are not under the sidewall spacers 610 and the dummy gate 410. According to an embodiment, the nanosheet fin 302 can be recessed until reaching the top of the bottom dielectric isolation layer 620. As ​ and 7C depicted, the recessing of the nanosheet fin 302 forms a second opening (or source / drain recess) 730 in the semiconductor structure 100.

[0102] Continue to refer to ​ , and using, for example, a selective etching process such as hydrogen chloride (HCl) gas etching, selectively recess the exterior of each second sacrificial semiconductor layer 110. Preferably, the selected etching process for recessing the second sacrificial semiconductor layer 110 is capable of etching silicon germanium without etching silicon. Inner spacers 720 may be formed within the recessed cavities (not shown) formed after etching the second sacrificial semiconductor layer 110. For example, the inner spacers 720 may be formed by conformally depositing an inner spacer dielectric material that pinches off in the recessed cavities (not shown) formed after recessing the second sacrificial semiconductor layer 110. The inner spacers 720 may be formed using any suitable dielectric material, such as silicon dioxide, silicon nitride, SiOC, SiOCN, SiBCN, and may include a single layer or multiple layers of dielectric material. An isotropic etch may then be performed to remove excess inner spacer material from other regions of the semiconductor structure 100.

[0103] As ​ shown, the outer sidewalls of the inner spacers 720 are vertically aligned with the semiconductor channel layer 112 and are thus vertically aligned with the upper portions of the sidewall spacers 610 located on the opposite sidewalls of the pseudo gate 410.

[0104] Now refer to ​ , which depicts a cross-sectional view of a semiconductor structure 100 after forming a nanosheet protection layer 802 and performing backside contact patterning according to an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1' drawn in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2', as ​ shown; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X' depicted in ​ .

[0105] According to an embodiment, as ​ and ​ shown, a nanosheet protection layer 802 is formed within second openings 730 ( ​ ) on opposite sides of the sidewall spacers 610. In an exemplary embodiment, the nanosheet protection layer 802 may be composed of SiN, TiOx, AlOx, SiO2, SiOCN, SiC, and equivalent materials. An ALD deposition process followed by an anisotropic etch process may be used to form as ​ and ​The nanosheet protection layer 802 configured therein. In particular, the nanosheet protection layer 802 is formed in such a way that only the portion of the nanosheet protection layer 802 perpendicular to the substrate 102 remains in the semiconductor structure 100. The thickness of the nanosheet protection layer 802 can vary from about 1 nm to about 3 nm and within the range therebetween. As the name implies, the nanosheet protection layer 802 can protect the integrity of the sidewall spacers 610 and the nanosheet fins 302 during subsequent etching processes.

[0106] After forming the nanosheet protection layer 802, an organic planarization layer (OPL) or simply a planarization layer 804 can be deposited on the semiconductor structure 100. The planarization layer 804 can be made of any organic planarization material capable of effectively preventing damage to the underlying layer during subsequent etching processes. The planarization layer 804 can include but is not necessarily limited to organic polymers including C, H, and N. In another embodiment, the organic planarization material can be free of silicon and fluorine (F). As defined herein, a material is free of an atomic element when the atomic element level in the material is at or below the trace level detectable by available analytical methods in the art. Non-limiting examples of organic planarization materials for forming the planarization layer 804 can include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar commercially available materials. The planarization layer 804 can be deposited by, for example, spin coating.

[0107] Continuing reference ​ , a lithography process is performed on the semiconductor structure 100, followed by an etching process for etching the planarization layer 804 and removing a portion of the first semiconductor layer 106 to form a third opening 810, as ​ and ​ shown. In some embodiments, the etching of the planarization layer 804 can be performed by, for example, OPL RIE including track point detection. The removal of the portion of the first semiconductor layer 106 can be performed by the same or different etching processes selective to the nanosheet protection layer 802, the STI region 310, and the bottom dielectric isolation layer 620.

[0108] In one or more embodiments, the position of the third opening 810 can be selected based on the desired position of the subsequent formed backside metal contact.

[0109] Now referring ​ , which depicts a cross-sectional view of the semiconductor structure 100 after sigma etching the first semiconductor layer 106 according to an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1 - Y1' drawn in ​ ; ​is a cross-sectional view of the semiconductor structure 100 taken along line Y2 - Y2', as ​ shown; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the ​ line X - X' depicted in

[0110] In the described embodiment, a sigma etching process is performed on the first semiconductor layer 106 to further increase the size of the third opening 810 and expose the top of the first sacrificial layer 104. As is known to those skilled in the art, sigma etching is synonymous with the terms "crystalline etching" and "anisotropic etching along crystal planes". Sigma etching involves the use of a chemical etchant. Examples of chemical etchants that can be used for sigma etching include, but are not limited to, potassium hydroxide, tetraethylammonium hydroxide, or an aqueous solution of ethylenediamine and catechol.

[0111] Sigma etching produces a sigma shape of the etch that cuts a portion of the first semiconductor layer 106. As ​ shown, after the sigma etching process is performed, a sigma shape 902 is formed within the first semiconductor layer 106.

[0112] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after forming the placeholder layer 1020 and removing the planarization layer 804 ( ​ ). In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the ​ line Y1 - Y1' depicted in ​ is a cross-sectional view of the semiconductor structure 100 taken along line Y2 - Y2', as ​ shown; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the ​ line X - X' depicted in

[0113] According to an embodiment, a layer of any suitable material for forming the placeholder layer 1020 can be deposited within the third opening 810. In one or more embodiments, the material for forming the placeholder layer 1020 can include, for example, SiGe, AlOx, TiOx, etc. Specifically, the material for forming the placeholder layer 1020 substantially fills the sigma-shaped third opening 810, as shown. In some embodiments, the top surface of the placeholder layer 1020 can be coplanar with the top surface of the bottom dielectric isolation layer 620. The placeholder layer 1020 serves as a placeholder for the subsequently formed backside metal contact, as the name implies.

[0114] After forming the placeholder layer 1020, the planarization layer 804 can be removed from the semiconductor structure 100. Exemplary techniques suitable for removing the planarization layer 804 from the semiconductor structure 100( ​ ) can include, but are not limited to, oxygen plasma, nitrogen plasma, hydrogen plasma, or other carbon strip or ashing processes that cause minimal or no damage to the underlying layers. Removal of the planarization layer 804 exposes the upper surfaces of the bottom dielectric isolation layer 620, the STI region 310, and the nanosheet protection layer 802.

[0115] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after removing the nanosheet protection layer 802( ​ ) in accordance with an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1 - Y1' depicted in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2 - Y2', as shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X - X' depicted in ​ .

[0116] Exemplary techniques suitable for removing the nanosheet protection layer 802 from the semiconductor structure 100( ​ ) can include, but are not limited to, selective wet or dry etching processes that can cause minimal or no damage to the underlying layers. As shown in the figures, removal of the nanosheet protection layer 802( ​ ) exposes the upper surfaces of the sidewall spacers 610, the bottom dielectric isolation layer 620, the STI region 310, the inner spacers 720, and the semiconductor channel layer 112.

[0117] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after completing the front-end-of-line (FEOL) processing steps in accordance with an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1 - Y1' depicted in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2 - Y2', as shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X - X' depicted in ​ .

[0118] Known semiconductor manufacturing operations have been used to form as ​The semiconductor structure 100 depicted therein. Accordingly, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into more comprehensive programs or processes having additional steps or functionality not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and thus, for the sake of brevity, many conventional steps will be only briefly mentioned herein or will be completely omitted without providing well-known process details.

[0119] Generally, at this step of the manufacturing process, source / drain regions 1220 may be formed in the semiconductor structure 100. As is known to those skilled in the art, source / drain regions are formed within the NFET and PFET regions 12, 16 ( ​ shown therein) of the semiconductor structure 100 using methods well known in the art. For example, source / drain regions 1220 may be formed on the exposed ends of the semiconductor channel layer 112 using an epitaxial layer growth process.

[0120] The source / drain regions 1220 may be formed on opposite sides of the nanosheet fins 302 and be in direct contact with the ends of the semiconductor channel layer 112 and the ends of the inner spacers 720. The top portion of the source / drain regions 1220 may include the result of a diamond shape with different growth rates during the epitaxial deposition process, the different growth rates being inherent to each crystalline orientation plane of the material forming the source / drain regions 1220. In other embodiments, the source / drain regions 1220 may have a shape different from ​ the diamond shape depicted therein.

[0121] After forming the source / drain regions 1220, an interlayer dielectric layer 1230 may be formed to fill the voids in the semiconductor structure 100. The interlayer dielectric layer 1230 may be formed by CVD of, for example, a dielectric material. Non-limiting examples of dielectric materials for forming the interlayer dielectric layer 1230 may include silicon oxide, silicon nitride, silicon carbon oxide hydride, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics.

[0122] As is known to those skilled in the art, after depositing the interlayer dielectric layer 1230, a planarization process (e.g., CMP) may be performed on the semiconductor structure 100. This process may expose the top surface of the dummy gate 410 to prepare for the replacement metal gate process, as will be described in detail below.

[0123] Now refer to ​, which depicts a cross-sectional view of the semiconductor structure 100 after performing a replacement metal gate process, performing middle of line (MOL) contact patterning and metallization, and forming a back end of line (BEOL) interconnect level 1320 and a carrier wafer 1322 according to an embodiment of the present disclosure. In this embodiment, ​ To follow ​ A cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1'; ​ is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2', as shown in FIG. ​ displayed; and ​ It is along ​ 1 is a cross-sectional view of the semiconductor structure 100 taken along line XX′ depicted in FIG.

[0124] According to an embodiment, the dummy gate 410 is removed from the semiconductor structure 100. As is known in the art, in a gate-last manufacturing process, the removed dummy gate 410 is then replaced by a high-k metal gate structure (i.e., replacement gate 1310). According to an embodiment, the second sacrificial semiconductor layer 110 ( ​ ), wherein the etching process includes, for example, RIE, wet etching or dry gas (HCl). Removing the sacrificial semiconductor layer 110 ( ​ ) creates a cavity (not shown) between the inner spacers 720, which will then be filled with the corresponding gate dielectric and work function metal to form a high-k metal gate structure or replacement gate 1310, as shown in FIG. ​ is displayed.

[0125] The replacement gate 1310 includes a gate dielectric such as hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium aluminum oxide (HfAlOx), hafnium lanthanum oxide g (HfLaOx), etc., and one or more work function metals, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and a conductive metal, including, for example, aluminum (Al), tungsten (W), or cobalt (Co). As shown in ​ As can be understood in the foregoing, the replacement gate 1310 surrounds the (stacked) semiconductor channel layer 112. In one or more embodiments, a gate cap (not shown) may be formed over the replacement gate 1310.

[0126] After forming the replacement gate 1310 , chemical mechanical polishing (CMP) may be performed to remove excess material and polish the upper surface of the semiconductor structure 100 .

[0127] In one or more embodiments, a gate cut process may be performed on the semiconductor structure 100 to isolate the gate structure from different CMOS cells. During this process, a gate cut region 1315 may be formed before or after the replacement metal gate (RMG), and then filled with a dielectric such as SiO2, SiN, SiBCN, SiOCN, SiOC, SiC, etc., as ​ shown.

[0128] Continuing to refer ​ , multiple conductive structures including metal contacts 1312 are formed in the semiconductor structure 100 for electrically connecting the FEOL devices to a subsequently formed metal layer. The process of forming the metal contacts 1312 is standard and well-known in the art. Generally, this process includes forming trenches (not shown) within the interlayer dielectric layer 1230 and then filling the trenches with a conductive material or a combination of conductive materials to form the metal contacts 1312. In one or more embodiments, the conductive material filling the metal contacts 1312 may include a silicide liner (e.g., titanium (Ti), nickel (Ni), nickel-platinum (NiPt) alloy, etc.), a metal adhesion liner (e.g., titanium nitride (TiN)), and a conductive metal (e.g., aluminum (Al), tungsten (W), copper (Co), ruthenium (Ru), or any combination thereof).

[0129] The conductive material may be deposited by suitable deposition processes such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the upper surface of the semiconductor structure 100. Specifically, in the depicted example, the metal contacts 1312 may include a source / drain contact (CA) extending to the uppermost surface of the source / drain region 1220 as depicted in ​ and 13C and a gate contact (CB) to the replacement gate 1310 as depicted in ​ .

[0130] According to an embodiment, the BEOL interconnect level 1320 is formed above and electrically connected to the FEOL device level 30 of the semiconductor structure 100. Although not shown in the drawings, those skilled in the art will appreciate that the BEOL interconnect level 1320 generally includes contacts, insulating layers (dielectrics), metal layers, and bonding locations for chip-to-package connections. As described above, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well-known, and thus for the sake of brevity, many conventional steps will only be briefly mentioned here or will be completely omitted without providing well-known process details.

[0131] According to an embodiment, after forming the BEOL interconnect level 1320, the semiconductor structure 100 (i.e., the semiconductor wafer) is bonded to a carrier wafer (or auxiliary substrate) 1322. The carrier wafer 1322 can be used as a reinforcement substrate to provide mechanical strength during the processing (e.g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the carrier wafer 1322 can be achieved by a conventional wafer bonding process, such as dielectric-to-dielectric bonding or Cu-to-Cu bonding.

[0132] Thus, the carrier wafer 1322 can include a silicon oxide layer or a SiCN layer, or any other layer applicable in direct bonding techniques used in existing packaging technologies. The device wafer is bonded to the carrier wafer 1322 by such known direct bonding techniques, thereby obtaining ​ the components shown in. Although not shown in the drawings, after bonding the device wafer to the carrier wafer 1322, the wafer is flipped.

[0133] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after removing the substrate 102 according to an embodiment of the present disclosure ( ​ ). In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1' drawn in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2', as shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X' depicted in ​ .

[0134] In the described embodiment, after the wafer is flipped (not shown), the substrate 102 ( ​ ) can be removed using conventional grinding, CMP, and selective etching processes including wet or dry etching techniques. In one or more embodiments, the grinding process is performed until the substrate 102 is substantially removed from the semiconductor structure 100 and only a few microns of Si remain. Subsequently, an optional CMP process can be further used to reduce thickness variations, and finally a high-selectivity Si etching process is used to remove the remaining substrate 102 from the semiconductor structure 100. In the described embodiment, the first sacrificial layer 104 serves as an etch stop layer during the high-selectivity Si removal process, preventing over-etching of Si that may damage the replacement gate 1310 and the source / drain regions 1220.

[0135] Now refer to ​, which depicts a cross-sectional view of the semiconductor structure 100 after removing the first sacrificial layer 104 and etching a portion of the first semiconductor layer 106 to expose the placeholder layer 1020. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ depicted in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’, as shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ depicted in ​ .

[0136] In the depicted embodiment, any suitable etching technique can be used to remove the first sacrificial layer 104 ( ​ ). In an embodiment where the first sacrificial layer 104 ( ​ ) is made of SiGe, thermal SC1 or dry HCl etching can be used to remove the first sacrificial layer 104. In an embodiment where the first sacrificial layer 104 ( ​ ) is made of SiO2, DHF wet cleaning can be used to remove the first sacrificial layer 104. As shown in ​ and ​ , some portions of the placeholder layer 1020 can also be etched during the removal of the sacrificial layer 104.

[0137] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after removing the remaining Si-containing region, i.e., the first semiconductor layer 106 depicted in ​ . In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ depicted in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’, as shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ depicted in ​ .

[0138] In this embodiment, a process similar to the process for removing the substrate 102 described in ​ can be performed to remove the first semiconductor layer 106 ( ​ ) from the semiconductor structure 100. The selective removal of the first semiconductor layer 106 ( ​ ) exposes the placeholder layer 1020. As shown in ​ and ​As can be observed, the first or bottom surface of the placeholder layer 1020 contacts the first or bottom surface of the source / drain region 1220.

[0139] Now refer to ​ , which depicts a cross-sectional view of the semiconductor structure 100 after forming the first backside interlayer dielectric (BILD) 1702 according to an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1', as ​ shown; ​ is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2', as ​ shown; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X' depicted in ​ .

[0140] The first BILD 1702 is formed using standard methods and materials, such as those described above with reference to ​ for forming the interlayer dielectric layer 1230. As ​ shown, the first BILD 1702 is disposed above the bottom dielectric isolation layer 620. In one embodiment, the thickness of the first BILD 1702 can vary between about 40 nm and about 300 nm, and therebetween. In one or more embodiments, after forming the first BILD 1702, a planarization process (e.g., CMP) can be performed on the semiconductor structure 100. After the planarization process, the exposed second or top surface of the placeholder layer 1020, opposite the first surface of the placeholder layer, is substantially coplanar with the first BILD 1702 and the STI region 310.

[0141] Now refer to Figures 18A to 18C , which depicts a cross-sectional view of the semiconductor structure 100 after selectively removing the placeholder layer 1020 ( Figures 17A to 17C ). In this embodiment, Figure 18A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1', as Figure 1 shown; Figure 18B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2', as Figure 1 shown; and Figure 18C is a cross-sectional view of the semiconductor structure 100 taken along the line X-X' depicted in Figure 1 .

[0142] Removal of the placeholder layer 1020 ( Figures 17A to 17C)A fourth opening 1820 is created in the semiconductor structure 100. The fourth opening 1820 (i.e., the backside contact via) exposes one or more source / drain regions 1220, as Figure 18A and 18C shown. Exemplary techniques suitable for removing the dummy layer 1020 from the semiconductor structure 100 ( Figures 17A to 17C ) may include, but are not limited to, dry HCl etching, which can cause minimal or no damage to the underlying layers.

[0143] As Figure 18A and 18C shown, at least one fourth opening 1820 exposes the top surface of a source / drain region 1220 adjacent to another source / drain region 1220, which is in electrical contact with the metal contact 1312.

[0144] Now referring to Figures 19A to 19C , which depicts a cross-sectional view of the semiconductor structure 100 after the deposition of the backside metal 1920 in accordance with an embodiment of the present disclosure. In this embodiment, Figure 19A is a cross-sectional view of the semiconductor structure 100 taken along the line Y1 - Y1' depicted in Figure 1 ; Figure 19B is a cross-sectional view of the semiconductor structure 100 taken along the line Y2 - Y2', as Figure 1 shown; and Figure 19C is a cross-sectional view of the semiconductor structure 100 taken along the line X - X' depicted in Figure 1 .

[0145] The backside metal 1920 substantially fills the fourth opening 1820 ( Figures 18A to 18C ). As shown in the figures, a layer of the backside metal 1920 is further deposited over the filled fourth opening 1820, over the first BILD 1702, and over the STI region 310. It should be noted that the backside metal 1920 that substantially fills the fourth opening 1820 ( Figures 18A to 18C ) provides a backside metal contact 1930 to the source / drain region 1220. According to an embodiment, the backside contact 1930 may electrically connect the semiconductor structure 100 to a subsequently formed backside power rail (BPR), as will be described in detail below.

[0146] The backside metal 1920 can be formed using conductive materials and deposition processes similar to those used to form the metal contacts 1102. In some embodiments, the conductive metal used to form the backside metal 1920 can be selected based on the subsequently formed backside power rail structure. In such cases, the backside metal 1920 can be formed by depositing, for example, a silicide liner such as Ti, Ni, NiPt, an adhesion metal liner such as TiN, and a low-resistance metal layer such as Ru, Co, W, or Cu.

[0147] The thickness of the backside material layer extending over the first BILD 1702 and the STI region 310 can vary from about 30 nm to about 200 nm and vary therebetween.

[0148] In one or more embodiments, a backside contact 1930 can be formed between adjacent source / drain regions 1220 within the NFET (i.e., N2N spacer) region 12 ( Figure 1 ) or the PFET (i.e., P2P spacer) region 16 ( Figure 1 ) of the semiconductor structure 100. In the described embodiments, the backside metal contact 1930 is formed to be in direct contact with the first or bottom surface of at least one source / drain region 1220.

[0149] Now refer to Figures 20A to 20C , which depicts a cross-sectional view of the semiconductor structure 100 after backside power rail patterning in accordance with an embodiment of the present disclosure. In this embodiment, Figure 20A is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ drawn in Figure 1 ; Figure 20B is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’, as shown in Figure 1 ; and Figure 20C is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ depicted in Figure 1 .

[0150] In the depicted embodiments, backside power rails (BPRs) 2010, 2012 are formed in the semiconductor structure 100 by patterning the backside metal 1920 ( Figures 19A to 19C ) using subtractive metal etching. Specifically, a hybrid damascene and subtractive metal lithography can be used to pattern the backside metal layer 1920 ( Figures 19A to 19C ) extending over the first BILD 1702 and the STI region 310 to form the BPRs 2010, 2012, as shown in the figures. Thus, this embodiment can allow for the simultaneous formation of backside metal contacts (e.g., backside contact 1930) and backside power rails (e.g., BPRs 2010, 2012).

[0151] More specifically, in an embodiment, the semiconductor structure 100 includes NFET devices. In such an embodiment, BPR2012 includes a VSS track embedded in the NFET region of the semiconductor structure 100 for electrical connection to the N-type source / drain region 1220 through a backside contact 1930 (located between adjacent N-type source / drain regions 1220). In other embodiments, the semiconductor structure 100 includes PFET devices, where BPR 2010 may include a VDD track line embedded in the PFET region of the semiconductor structure 100, and the VDD track line is electrically connected to the (P-type) source / drain region 1220 through a backside contact 1930 (located between adjacent P-type source / drain regions 1220).

[0152] It should be noted that the source / drain regions 1220 wired to the backside power rails (i.e., BPR 2010, 2012) are not connected to the BEOL interconnect level 1320. More particularly, as shown in the figures, at least one backside power rail (i.e., BPR 2010, 2012) is electrically connected to the source / drain region 1220 of the transistor through a backside contact 1930, where the bottom dielectric isolation layer 620, the first BILD 1702, and / or the STI region 310 contact the remaining source / drain regions 1220 for electrically isolating at least one backside power rail from the source / drain regions 1220 not electrically connected to the backside contact 1930.

[0153] After patterning the BPR 2010, 2012, voids within the semiconductor structure can be filled by depositing a dielectric material substantially similar to the first BILD 1702. Thus, for simplicity, another layer of the first BILD1702 is deposited within the semiconductor structure 100 to fill the remaining voids and electrically isolate the BPR 2010, 2012, as shown in the following Figures 21A to 21C figure. After depositing another layer of the first BILD 1702, a planarization process can be performed on the semiconductor structure 100.

[0154] Now referring to Figures 21A to 21C , which depicts a cross-sectional view of the semiconductor structure 100 after forming a backside power delivery network (BSPDN) 2130 according to an embodiment of the present disclosure. In this embodiment, Figure 21A is a cross-sectional view of the semiconductor structure 100 taken along the line Y1 - Y1' depicted in Figure 1 ; Figure 21B is a cross-sectional view of the semiconductor structure 100 taken along the line Y2 - Y2', as shown in Figure 1 ; and Figure 21C is a cross-sectional view of the semiconductor structure 100 taken along the line X - X' depicted in Figure 1 .

[0155] In one or more embodiments, the structure of BSPDN 2130 can be fabricated according to known techniques. Depending on the exact function of the transistor arrangement, multiple source / drain regions 1220 can be connected to the backside power and ground via backside contacts 1930. As described above, the backside contact 1930 is a metal region located between P-type source / drain regions (N 2N pitch) and between N-type source / drain regions (N 2N pitch), i.e., between source / drain regions of similar polarity. According to an embodiment, the backside contact 1930 contacts the bottom surface of BPR 2010 or 2012 (depending on the polarity of the device) and is embedded within the intermediate STI region 310 (located between regions of the same polarity).

[0156] It should be noted that the BEOL interconnect layer 1320 in the semiconductor structure 100 fabricated according to the disclosed techniques is separated from BSPDN 2130, thereby increasing the routing resources for signal routing in the BEOL layer in the semiconductor structure 100.

[0157] According to an embodiment, by performing a sigma etch process, the backside contact via and thus the backside metal contact 1930 exhibits a first (positive) conical profile including a first cone angle, according to which the first or top critical dimension (CD1) of the backside metal contact 1930 is smaller than the second or bottom critical dimension (CD2) of the backside metal contact 1930, as Figure 21C shown. Similarly, BPR 2010, 2012 are formed with a second (negative) conical profile different from the first conical profile of the backside metal contact 1930. The second conical profile includes a second cone angle, according to which the third or top critical dimension (CD3) of BPR 2010, 2012 is larger than the fourth or bottom critical dimension (CD4) of each of BPR 2010, 2012.

[0158] Thus, the previously described embodiments provide a semiconductor device including a field effect transistor (FET) and a backside contact 1930. The backside contact 1930 is electrically connected to the source / drain region 1220 of the FET and is electrically connected to the backside power rails 2010, 2012. The backside contact 1930 has a first width adjacent to the source / drain region 1220 and a second width adjacent to the backside power rails 2010, 2012. The second width of the backside contact 1930 is larger than the first width of the backside contact 1930. According to one embodiment, the backside power rails 2010, 2012 have a third width adjacent to the backside contact 1930 and a fourth width at the opposite side of the backside contact 1930. The third width of the backside power rails 2010, 2012 is larger than the fourth width of the backside power rails 2010, 2012.

[0159] The above method is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in the form of a raw wafer (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with one or both of surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to high-end computer products with a display, keyboard, or other input devices and a central processing unit.

[0160] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" refers to an event or circumstance that may or may not occur subsequently, and the description includes instances where the event occurs and instances where it does not.

[0161] For ease of description, spatial relative terms such as "inner", "outer", "below", "above", "over", "top", "bottom", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is flipped, an element described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "below" can include both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptions used herein are to be interpreted accordingly.

[0162] As used throughout the specification and claims of this document, approximating language may be applied to modify any quantitative representation that admits of variation without resulting in a change in its associated basic function. Thus, values modified by one or more terms such as "about," "approximately," and "substantially" are not limited to the precise values specified. In at least some instances, the approximating language may correspond to the precision of the instrument used to measure the value. Herein, as well as throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges being identified and including all the sub-ranges contained therein, unless the context or language indicates otherwise. The "about" applied to a particular value of a range applies to both values and may indicate + / - 10% of the stated value, unless otherwise dependent on the precision of the instrument used to measure the value.

[0163] The description of the various embodiments of the invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or an improvement upon the technology found in the marketplace, or to enable other ordinary skilled artisans in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: multiple source / drain regions within a field effect transistor; a backside metal contact electrically connected to at least one of the multiple source / drain regions, the backside metal contact including a first tapered profile; and a backside power rail electrically connected to the at least one source / drain region through the backside metal contact, the backside power rail including a second tapered profile different from the first tapered profile.

2. The semiconductor structure according to claim 1, further comprising: a front-end process tier including the field effect transistor, the front-end process tier being electrically connected to a back-end process interconnect tier located on a first side of the front-end process tier; multiple shallow trench isolation regions located between adjacent field effect transistors; a backside interlayer dielectric surrounding the backside power rail and located on a second side of the front-end process tier opposite to the first side of the front-end process tier; and a metal contact within an interlayer dielectric layer, the metal contact being in electrical contact with a bottom portion of at least another source / drain region.

3. The semiconductor structure according to claim 1, wherein the first tapered profile of the backside metal contact includes a first critical dimension of the backside metal contact, the first critical dimension being smaller than a second critical dimension of the backside metal contact.

4. The semiconductor structure according to claim 3, wherein the first critical dimension is a top critical dimension of the backside metal contact, and the second critical dimension is a bottom critical dimension of the backside metal contact.

5. The semiconductor structure according to claim 1, wherein the second tapered profile includes a third critical dimension of the backside power rail, the third critical dimension being larger than a fourth critical dimension of the backside power rail.

6. The semiconductor structure according to claim 5, wherein the third critical dimension is a top critical dimension of the backside power rail, and the fourth critical dimension is a bottom critical dimension of the backside power rail.

7. The semiconductor structure according to claim 1, wherein the backside metal contact and the backside power rail are made of a conductive material including at least one of Ru, Cu, Co, W, and Al.

8. The semiconductor structure according to claim 1, further comprising: a power delivery network located above the backside power rail and in electrical contact with the backside power rail.

9. The semiconductor structure according to claim 2, further comprising: a carrier wafer in contact with a surface of the back-end process tier opposite to the multiple source / drain regions and the metal contact.

10. The semiconductor structure according to claim 1, wherein the field effect transistor includes at least one of a P-type field effect transistor and an N-type field effect transistor, and wherein the field effect transistor includes a nanosheet field effect transistor.

11. A method of forming a semiconductor structure, comprising: forming multiple source / drain regions within a field effect transistor; Forming a backside metal contact that is electrically connected to at least one of the plurality of source / drain regions, the backside metal contact including a first tapered profile; and Forming a backside power rail that is electrically connected to the at least one source / drain region via the backside metal contact, the backside power rail including a second tapered profile that is different from the first tapered profile.

12. The method according to claim 11, further comprising: Forming a front-end process level including the field effect transistor, the front-end process level being electrically connected to a back-end process interconnect level located on a first side of the front-end process level; Forming a plurality of shallow trench isolation regions between adjacent field effect transistors; Forming a backside interlayer dielectric that surrounds the backside power rail and is on a second side of the front-end process level that is opposite the first side of the front-end process level; and Forming a metal contact within the interlayer dielectric layer that is in electrical contact with a bottom portion of at least another source / drain region.

13. The method according to claim 11, wherein the first tapered profile of the backside metal contact includes a first critical dimension of the backside metal contact, the first critical dimension being less than a second critical dimension of the backside metal contact.

14. The method according to claim 13, wherein the first critical dimension is a top critical dimension of the backside metal contact, and the second critical dimension is a bottom critical dimension of the backside metal contact.

15. The method according to claim 11, wherein the second tapered profile includes a third critical dimension of the backside power rail, the third critical dimension being greater than a fourth critical dimension of the backside power rail.

16. The method according to claim 15, wherein the third critical dimension is a top critical dimension of the backside power rail, and the fourth critical dimension is a bottom critical dimension of the backside power rail.

17. The method according to claim 11, wherein the backside metal contact and the backside power rail are composed of a conductive material including at least one of Ru, Cu, Co, W, and Al.

18. The method according to claim 11, further comprising: Forming a power delivery network that is above the backside power rail and in electrical contact with the backside power rail.

19. The method according to claim 12, further comprising: Forming a carrier wafer that contacts a surface of the back-end process level that is opposite the plurality of source / drain regions and the metal contact.

20. The method according to claim 11, wherein the field effect transistor includes at least one of a P-type field effect transistor and an N-type field effect transistor, and wherein the field effect transistor includes a nanosheet field effect transistor.

21. A computer program, the computer program including program code that, when the program is run on a computer, is adapted to perform the method steps of any one of claims 11 to 20.

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