SoC chip pin multiplexing function test circuit and test method

Abstract

The invention provides a SoC chip pin multiplexing function test circuit and test method. The test circuit comprises a test output unit, a multiplexer unit, a test detection unit and a result output unit. The test output unit generates a plurality of different types of test signals and imports the test signals into the pin multiplexing module; the multiplexer unit selects the corresponding test detection unit and the result output unit according to the configured multiplexing channel; and the test detection unit is used for testing the multiplexing channels under each type of test signals, traversing tests of all the multiplexing channels and generating test results. The test circuit is arranged in the Soc chip, multiple types of test signals are generated through the test circuit, the pin multiplexing working mode in practical application is simulated, multiple types of test signals are adopted to directly test the pin multiplexing channel, the test program only runs on the chip on the basis of a simple test environment, and the test efficiency is greatly improved. And the pin multiplexing function is comprehensively tested.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and more particularly, to a test circuit and a test method for the pin multiplexing function of an SoC chip. Background Art

[0002] An SoC (System On Chip) chip integrates rich peripheral interface functions, and multiple peripheral functions are mapped to different pins through the pin multiplexing function. The pin multiplexing function makes the SoC pins highly flexible, and users select pins according to the actual application requirements and the SoC mapping relationship table during the development stage.

[0003] During the chip retest stage, assuming that the chip pin multiplexing mode has at most N(n) mapping modes, the main steps of the existing chip pin multiplexing function test are as follows:

[0004] Step1: The test program configures the pin multiplexing mapping mode mode1, and then uses the off-chip test circuit corresponding to the set mapping relationship and the test detection instrument connection mode 1 to complete the multiplexing function mode1 test.

[0005] Step2: The test program configures the pin multiplexing mapping mode mode2, and then uses the off-chip test circuit corresponding to the set mapping relationship and the test detection instrument connection mode 2 to complete a multiplexing function mode2 test. ...............

[0007] Stepn: The test program configures the pin multiplexing mapping mode modeN, and then uses the off-chip test circuit corresponding to the set mapping relationship and the test detection instrument connection mode N to complete the multiplexing function modeN test.

[0008] To complete the test of N multiplexing function modes of all functional pins of the chip with the above test method and test process, it is necessary for test engineers to frequently adjust the off-chip test circuit and test detection instrument according to the pin multiplexing mapping relationship. Completing the multiplexing function test of all functional pins requires a long test cycle. Since the traditional test method requires frequent manual operations, it is also easy to introduce human operation errors and there is also a problem of incomplete test coverage. Therefore, to solve the situation in SoC chip testing where the test circuit needs to be frequently adjusted, test signals need to flow between multiple hardware, the test efficiency is low, and the test workload is large, a more efficient and accurate automated test method for pin multiplexing functions is needed to reduce the test cost. Summary of the Invention

[0009] The present invention addresses the technical problems existing in the prior art and provides a test circuit and a test method for the pin multiplexing function of an SoC chip, so as to solve the problems of insufficient testing, frequent manual modification of the test environment, low test efficiency, and the need for multiple test instruments when testing the pin multiplexing function in the existing test solutions.

[0010] According to the first aspect of the present invention, there is provided a test circuit for the pin multiplexing function of an SoC chip. The test circuit is built into the SoC chip and includes a test output unit, a multiplexer unit, a test detection unit, and a result output unit.

[0011] The test output unit is used to generate various different types of test signals and import the generated different types of test signals into the pin multiplexing module of the SoC chip through register configuration based on a test program.

[0012] The multiplexer unit is used to select the corresponding test detection unit and result output unit according to the configured multiplexing channel (n, m), where n represents the pin number and m represents the pin multiplexing function number.

[0013] The test detection unit is used to test the corresponding multiplexing channel under each type of test signal and traverse the tests of all multiplexing channels to obtain the test results of each multiplexing channel under each type of test signal.

[0014] The result output unit is used to output the test results.

[0015] According to the second aspect of the present invention, there is provided a test method for the pin multiplexing function of an SoC chip, including:

[0016] Step 1: Enter the power-on initialization state S0, load the test program, and the test program initializes and enables the test circuit for the pin multiplexing function. After completion, enter state S1, and state S1 is the test state.

[0017] Step 2: In state S1, record the pin number n to be tested and the pin multiplexing function number m to be tested. In state S1, the test program determines whether the current multiplexing channel (n, m) exists. If the corresponding pin multiplexing function m of pin n does not exist, the pin multiplexing function number m is incremented by 1 until the corresponding pin multiplexing function number m of pin number n is configurable or all multiplexing channels of pin number n are traversed. After completion, enter state S2; if there are no untested reusable channels for pin number n, enter state S7.

[0018] Step 3: In state S2, the test program enables the configuration of the multiplexing channel (n, m), configures the multiplexer unit, connects the currently tested multiplexing channel (n, m) to the corresponding test detection unit and test output unit, and enters state S3 after the configuration is completed;

[0019] Step 4: In state S3, the test program configures a test item (n, m, i) by combining a test signal with the multiplexing path (n, m), where i represents the type of the test signal, tests the test item (n, m, i), activates the test detection unit and the result output unit, and enters state S4 after starting the channel test;

[0020] Step 5: In state S4, the test program waits for the test circuit to complete the test of the current test item (n, m, i), records and outputs the detection result of the current test item (n, m, i), and enters state S5;

[0021] Step 6: In state S5, the test program checks whether all the multiple test signal types i configured for the multiplexing channel (n, m) have passed the test. If all are completed, it enters state S6. If not, it modifies the value of i to switch to the next untested test signal type, and then enters state S4;

[0022] Step 7: In state S6, the test program determines whether all the multiplexing functions m of the pin number n have been traversed and tested. If completed, it enters state S7; if not, it increments the pin multiplexing function number m by 1 and enters state S1;

[0023] Step 8: In state S7, the test program determines whether all the pins have been traversed and tested. If traversed and tested, it enters state S8; if not, it increments the pin number n by 1, sets the pin multiplexing function number m to 1, and enters state S1;

[0024] Step 9: State S8 is the end state. In state S8, the test program records the test results and configures the multiplexing channel to the non-test state, and shuts down the test circuit.

[0025] A test circuit and test method for the pin multiplexing function of an SoC chip provided by the present invention are fully implemented inside the chip. When using this test circuit to test the pin multiplexing function, no hardware circuit board, test instrument, or device other than the single board of the chip under test is required. When using this test method to test the pin multiplexing function, only the test signal needs to interact inside the chip test board, and it is not interfered by the external test environment of the chip. Since the test is only completed inside the chip, this test method only requires developing a test program inside the chip. Description of the Drawings

[0026] Figure 1Schematic diagram of a test circuit for the pin multiplexing function of an SoC chip provided by an embodiment of the present invention;

[0027] Figure 2 Flowchart of a test method for the pin multiplexing function of an SoC chip provided by an embodiment of the present invention. Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. In addition, the technical features in each embodiment or a single embodiment provided by the present invention can be combined with each other arbitrarily to form a feasible technical solution. This combination is not restricted by the order of steps and / or the pattern of structural composition, but must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions conflicts with each other or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0029] Figure 1 A test circuit for the pin multiplexing function of an SoC chip provided by an embodiment of the present invention, as Figure 1 shown. Refer to Figure 1 . This test circuit is built into the SoC chip. The test circuit includes a test output unit, a multiplexer unit, a test detection unit, and a result output unit. In addition to the above parts, the test circuit also includes the enable control, reset control, module clock switch selection, and their configuration registers corresponding to the above respective units. [[ID=1�]]

[0030] Among them, each functional peripheral is connected to the test circuit in the SoC chip. The test circuit is connected to the pin multiplexing module and the pin input / output unit. Here, the pin input / output unit is connected to an external device.

[0031] Among them, the function of the test output unit is to generate various types of test signals, such as test signals of the level type, flip type, and coding type. The test signal of the level type refers to high and low level signals. The test signal of the flip type refers to a flip signal with double-edge transitions (the number of cycles can be configured by a register, and the generated period is controllable). The test signal of the coding type refers to a coding signal (a coding signal with a configurable coding clock period, such as a pseudo-random coding signal PRBS3, PRBS7, etc.).

[0032] The function of the multiplexer is as follows: The test program can import the test signals generated by the test output unit into the pin multiplexing module through register configuration, and send the test signals of the pin multiplexing module to the test detection unit through the multiplexer unit.

[0033] The function of the test detection unit is as follows: The test detection unit detects the test signals of the level signal, flip signal, and encoding type and latches the detection results. Level detection: Detect the high and low levels of the digital signal. Flip signal detection: Detect the single / double edges of the signal under test and count the edges. Encoding type signal detection: Decoding and verification detection of the class encoding signal (the clock cycle is the same as the encoding clock cycle).

[0034] Result output unit: After this unit is enabled, it will query the current test status (whether the test is enabled: the test is enabled or not; the test timeout counting status: the count is not timed out or timed out, the test result: pass, fail, timeout), and output the test status to the register.

[0035] See Figure 2 , which provides a method for testing the pin multiplexing function of an SoC chip based on the SoC chip pin multiplexing function test circuit provided in the above embodiment. The specific implementation and working process are as follows:

[0036] Step 1, enter the power-on initialization state S0, load the test program, and the test program initializes and enables the test pin multiplexing function test circuit. After completion, enter state S1, and state S1 is the test state.

[0037] Step 2, in state S1, record the pin number n to be tested and the pin multiplexing function number m to be tested. In state S1, the test program determines whether the current multiplexing channel (n, m) exists. If the corresponding multiplexing function m of pin n does not exist, the pin multiplexing function number m is incremented by 1 until the corresponding pin multiplexing function number m of pin number n can be configured or all multiplexing channels of pin number n are traversed. After completion, enter state S2; if there is no untested multiplexing channel for pin number n, enter state S7.

[0038] Among them, the test program numbers the pins and pin multiplexing functions: If the total number of pins is N, the range of the pin number n is (1 to N); if the maximum multiplexing function of the pin is M, the range of the pin multiplexing function number m is (1 to M), and the multiplexing function m of pin n is denoted as a multiplexing channel (n, m).

[0039] The test program differentiates the channel status: If the input signal of the multiplexing channel (n, m) originates from the test output unit, and at the same time the signal output by this multiplexing channel is output to the signal detection unit for detection (multiplexer configuration), the status of this multiplexing channel is denoted as the multiplexing channel test status, otherwise this channel is in a non-test state.

[0040] In the initialization stage of the test program, the pin number n is configured to be 1, and the initial pin function number m is 1 (i.e., the first multiplexing function of the first pin).

[0041] Step 3: In state S2, the test program configures the multiplexing channel (n, m) to be enabled, configures the multiplexer unit, and selects and docks the current multiplexing channel (n, m) to be tested to the corresponding test detection unit and test output unit. After the configuration is completed, it enters state S3.

[0042] Step 4: In state S3, the test program configures the test signal and the multiplexing path (n, m) to form a test item (n, m, i), where i represents the type of the test signal. The test item (n, m, i) is tested, the test detection unit and the result output unit are enabled, and after the channel test is started, it enters state S4.

[0043] Among them, the test program numbers the test signal types. For example, if there are I types of test signals in total, the range of the test type number i is (1 to I). The test item (n, m, i) indicates that the multiplexing channel m of the current pin n is tested using the test signal type i.

[0044] Step 5: In state S4, the test program waits for the test circuit to complete the test of the current test item (n, m, i), records and outputs the i detection result of the current test item (n, m, i), and enters state S5.

[0045] Among them, in this embodiment, the test program can configure the test circuit to use one or more of the test signals such as the level type, flip type, and coding type to test the channel to be measured (n, m) according to the test requirements.

[0046] Step 6: In state S5, the test program checks whether all the multiple test signal types i configured for the multiplexing channel (n, m) have passed the test. If all are completed, it enters state S6. If not, it modifies the i value to switch to the next untested test signal type, and then enters state S4. In this embodiment, the test program needs to clear the historical test result register after recording the test results.

[0047] Step 7: In state S6, the test program determines whether all the multiplexing functions m of the pin number n have been traversed and tested. If completed, it enters state S7; if not, the pin multiplexing function number m is incremented by 1 and then enters state S1.

[0048] Step 8: In state S7, the test program determines whether all pins have been traversed and tested. If the traversal test is completed, it enters state S8; if not, the pin number n is incremented by 1, the pin multiplexing function number m is set to 1, and then it enters state S1;

[0049] Step 9, the state S8 is the end state. In the state S8, after the test program records the test results, it configures the multiplexing channel to the non-test state and closes the test circuit.

[0050] A test circuit and a test method for the pin multiplexing function of an SoC chip provided by the present invention have the following beneficial effects compared with the prior art:

[0051] (1) The present invention proposes a test circuit for the pin multiplexing function of an SoC chip, which can directly test the pin multiplexing function inside the chip. Compared with the existing solutions, it does not require a complex external test circuit, simplifying the test environment.

[0052] (2) The present invention proposes a test circuit for the pin multiplexing function of an SoC chip, which can use various test signals such as program-controlled level types, flip types, and coding types to test the multiplexing channel. Compared with the existing solutions, it can perform a more comprehensive test on the pin multiplexing channel;

[0053] (2) The present invention proposes a test method for the pin multiplexing function of an SoC chip, which can achieve the test of the pin multiplexing function only by relying on the test program running on the chip under test. Compared with the existing solutions, using this test method does not require developing a test program other than the chip test program, improving the test feasibility and shortening the test program development cycle;

[0054] (3) The present invention proposes a test method for the pin multiplexing function of an SoC chip. This test method uses a simplified test environment, and the test is not interfered by external circuits, improving the test reliability.

[0055] It should be noted that in the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0056] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0057] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded computers, or other programmable data processing devices to generate a machine, such that the instructions executed by the processors of the computer or other programmable data processing devices produce means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0058] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0059] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0060] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0061] Obviously, those skilled in the art can make various changes and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A test circuit for the pin multiplexing function of a SoC chip, characterized in that, The test circuit is built into the SoC chip, and the test circuit includes a test output unit, a multiplexer unit, a test detection unit and a result output unit; The test output unit is used to generate multiple different types of test signals and import the generated different types of test signals into the pin multiplexing module of the SoC chip through register configuration based on the test program; The multiplexer unit is used to select the corresponding test detection unit and result output unit according to the configured multiplexing channel (n, m), where n represents the pin number and m represents the pin multiplexing function number; The test detection unit is used to test the corresponding multiplexing channel under each type of test signal, and traverse the test of all multiplexing channels to obtain the test result of each multiplexing channel under each type of test signal; The result output unit is used to output the test result.

2. The SoC chip pin multiplexing function test circuit according to claim 1, wherein The multiple different types of test signals include at least level type test signals, flip type test signals and coding type test signals. The level type test signal refers to a high and low level signal, the flip type test signal refers to a flip signal with double-edge jumps, and the coding type test signal refers to a coding signal with a configurable clock period during encoding.

3. The SoC chip pin multiplexing function test circuit according to claim 2, characterized in that, The test detection unit is used to test the corresponding multiplexing channel under each type of test signal, including: The test detection unit detects the level signal, flip signal and coding signal under the corresponding multiplexing channel, wherein the high and low levels of the level signal are detected; the single / double edge of the flip signal is detected and the edges are counted; and the decoding of the coding signal is verified and detected.

4. A test method for the pin multiplexing function of an SoC chip, which is applied to the test circuit for the pin multiplexing function of the SoC chip described in claim 1, and is characterized in that, The test method includes: Step 1: Enter the power-on initialization state S0, load the test program, initialize the test program to start the test pin multiplexing function test circuit, and enter state S1 after completion. State S1 is the test state; Step 2: In state S1, record the pin number n to be tested and the pin multiplexing function number m to be tested. In state S1, the test program determines whether the current multiplexing channel (n, m) exists. If the multiplexing function m corresponding to pin n does not exist, the pin multiplexing function number m is incremented by 1 until the pin multiplexing function number m corresponding to pin number n can be configured or all multiplexing channels of pin number n are traversed. After completion, enter state S2; if there is no untested multiplexing channel for pin number n, enter state S7; Step 3: In state S2, the test program configures the multiplexing channel (n, m) to be enabled, configures the multiplexer unit, selects and connects the current multiplexing channel (n, m) to be tested to the corresponding test detection unit and test output unit, and enters state S3 after the configuration is completed; Step 4: In state S3, the test program configures the test signal and the multiplexed path (n, m) to form a test item (n, m, i), where i represents the type of the test signal. The test item (n, m, i) is tested, the test detection unit and the result output unit are turned on, and the channel test is turned on before entering state S4. Step 5. In state S4, the test program waits for the test circuit to complete the test on the current test item (n, m, i), records and outputs the i test result of the current test item (n, m, i), and enters state S5; Step 6. In state S5, the test program checks whether all the multiple test signal types i configured for the multiplexing channel (n, m) have passed the test. If all are completed, it enters state S6. If not, it modifies the value of i to switch to the next untested test signal type, and then enters state S4; Step 7. In state S6, the test program determines whether all the multiplexing functions m of the pin number n have been traversed and tested. If completed, it enters state S7; if not, it increases the pin multiplexing function number m by 1 and then enters state S1; Step 8. In state S7, the test program determines whether all pins have been traversed and tested. If traversed and tested, it enters state S8; if not, it increases the pin number n by 1, sets the pin multiplexing function number m to 1, and then enters state S1; Step 9. State S8 is the end state. In state S8, the test program records the test results, configures the multiplexing channel to the non-test state, and turns off the test circuit.

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