FPGA (Field Programmable Gate Array)-based queue driving array radar signal processing implementation method

Abstract

The invention relates to the technical field of array radar signal processing, in particular to an FPGA (Field Programmable Gate Array)-based queue driving array radar signal processing implementation method, which comprises the following steps of: dividing a queue data cache region into a data cache region, a parameter cache region and a data state region; parameters are judged and read through the state of the data state area, and then data are read according to the parameters; performing queue circular storage on the data after DDC according to a transmission pulse period, reading according to a storage sequence and corresponding parameters, and performing DBF operation; carrying out queue circulation storage on the data after the DBF operation according to a transmission pulse period, reading according to a storage sequence and corresponding parameters, and carrying out PC (Personal Computer) operation; and performing queue circular storage on the data after PC operation according to an accumulation period, and performing data reading and MTD operation according to a storage sequence and corresponding parameters. According to the method, processing time sequence coupling between the modules is isolated, and mode parameter switching and program transplantation are facilitated.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of array radar signal processing, and particularly to a method for implementing array radar signal processing based on FPGA with queue driving. Background Art

[0002] With the wide application of digital array radars, the requirements for data throughput and processing capabilities of radar signal processing are getting higher and higher. An array radar often consists of hundreds or thousands, or even tens of thousands of independent receiving array elements, and all array element data needs to be aggregated to achieve beamforming. Moreover, the most significant advantage of digital array radars is their multi-beam capability. Therefore, technicians often need to form multiple beams to cover the airspace of interest, which greatly increases the data processing pressure. The rise of broadband array radars has put forward even higher requirements for signal processing capabilities.

[0003] FPGA has the characteristics of strong data throughput and processing capabilities. For example, the Virtex-7-690T developed by Xilinx has 84 high-speed transceiver ports, and the processing rate of each transceiver port is as high as 11.3 Gbps. At the same time, this development board has 3,600 multipliers and can perform multiplication operations simultaneously. Therefore, FPGA has become an indispensable processor in array radar signal processing. Different from the serial processing based on traditional CPU processors, FPGA is a parallel pipelined processing under a certain clock. In FPGA, all processing is based on timing, and the operation needs to be accurate to one clock cycle. This leads to a very large possible change in the program when parameters change, and sometimes it may even require re-design. When the operation changes with parameter switching, it often takes a lot of effort to adjust the timing, increasing the workload and also raising the difficulty of design and debugging. In addition, when the mode switches quickly, if the time period changes greatly, modules such as frequency domain pulse compression and MTD use the ping-pong form for caching, and the timing arrangement and data caching will be extremely complex. That is to say, although FPGA can effectively achieve high data throughput and complete large data volume calculations, the FPGA program has the disadvantages of inflexible parameter switching, poor program portability, and low program modification efficiency. The flexibility of FPGA urgently needs to be improved. Summary of the Invention

[0004] In view of this, embodiments of the present application propose a method for implementing array radar signal processing based on FPGA with queue driving, which uses a data caching method based on queue driving to isolate the processing timing coupling between modules, ensures the independence of module operations, is conducive to the switching of mode parameters, as well as the transplantation, writing, and debugging of programs.

[0005] To achieve the above object, an embodiment of the present application proposes a method for implementing FPGA-based queue-driven array radar signal processing. The method includes the following steps: Divide the queue data buffer into three parts: a data buffer, a parameter buffer, and a data status area. When performing a read operation, determine the read parameters through the status of the data status area, and then read the data according to the parameters; Store the data after DDC (Digital Down Converter) in a queue in a cyclic manner according to the transmit pulse period, read the data according to the corresponding parameters in the order of storage, and perform DBF (Digital BeamForming) operations; Store the data after DBF operations in a queue in a cyclic manner according to the transmit pulse period, read the data according to the corresponding parameters in the order of storage, and perform PC (Pulse Compression) operations; Store the data after PC operations in a queue in a cyclic manner according to the accumulation period, read the data according to the corresponding parameters in the order of storage, and perform MTD (Moving Target Detection) operations.

[0006] To achieve the above object, an embodiment of the present application also proposes a system for implementing FPGA-based queue-driven array radar signal processing. The system includes: a cache partitioning module, a DBF operation module, a PC operation module, and an MTD operation module; The cache partitioning module is used to divide the queue data buffer into three parts: a data buffer, a parameter buffer, and a data status area, and is used to determine the read parameters through the status of the data status area when performing a read operation, and then read the data according to the parameters; The DBF operation module is used to store the data after DDC in a queue in a cyclic manner according to the transmit pulse period, read the data according to the corresponding parameters in the order of storage, and perform DBF operations; The PC operation module is used to store the data after DBF operations in a queue in a cyclic manner according to the transmit pulse period, read the data according to the corresponding parameters in the order of storage, and perform PC operations; The MTD operation module is used to store the data after PC operations in a queue in a cyclic manner according to the accumulation period, read the data according to the corresponding parameters in the order of storage, and perform MTD operations.

[0007] To achieve the above object, an embodiment of the present application also proposes an electronic device. The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a method for implementing FPGA-based queue-driven array radar signal processing as described above.

[0008] To achieve the above object, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which when executed by a processor, can implement a method for implementing FPGA-based queue-driven array radar signal processing as described above.

[0009] A method for implementing FPGA-based queue-driven array radar signal processing proposed in the present application circularly stores the data after DDC in a queue according to the transmit pulse period, reads the data according to the storage sequence and corresponding parameters, and performs DBF operations. The data after DBF operations is circularly stored in a queue according to the transmit pulse period, read according to the storage sequence and corresponding parameters, and PC operations are performed. The data after PC operations is circularly stored in a queue according to the accumulation period, and the data is read according to the storage sequence and corresponding parameters, and MTD operations are performed. That is to say, in the present application, after DDC, after DBF operations, and after PC operations, data caching in the form of a queue is performed, which realizes isolation between modules and fast switching of parameter timings, avoids using global timings, reduces timing coupling between modules, and ensures the independence of module operations. To implement data caching in the form of a queue, the present application divides the queue data buffer into three parts: a data buffer, a parameter buffer, and a data status area. When performing a read operation, the read parameters are determined through the status of the data status area, and then the data is read according to the parameters. Such a design is conducive to parameter switching, as well as program transplantation, writing, and debugging.

[0010] Optionally, the number of both the data buffer and the parameter buffer is N, and the data buffer corresponds to the parameter buffer one by one; where N is an integer greater than 1.

[0011] Optionally, the data buffer is used to store relevant data during the signal processing process, and the write address and read address are used to implement the write operation and read operation of the data according to the required rules; the parameter buffer is used to place relevant processing parameters corresponding to the data, which are written synchronously with the data. When performing a data read operation, the parameters are read first, and then the number of data read and relevant read rules are determined according to the parameters; the data status area is used to represent the data status of each data buffer. The data status is the unwritten status or the status of waiting after writing. After the data in the data buffer corresponding to the current loop address is read, it is judged whether the data status of the data buffer corresponding to the next loop address is the status of waiting after writing. If so, the data is read. If not, continue to wait until its data status becomes the status of waiting after writing, and then read the data. Such data writing and data storage operations are scientific and reasonable, and no data contamination will occur.

[0012] Optionally, the data after DDC is stored in a queue in a cyclic manner according to the emission pulse period, read according to the corresponding parameters in the order of storage, and then subjected to DBF operation, including: the data after DDC of each pulse is cyclically stored into N data buffer areas in the order of distance first and then channel, and then, based on a preset data rate, the data is read according to the order of storage, the read time of the data is determined according to the situation of the read data and the data rate, and the DBF operation is performed on the read data. The determined read time of the data keeps the rate unchanged after output for DBF operation without changing the structure of the DBF operation.

[0013] Optionally, the data after DBF operation is stored in a queue in a cyclic manner according to the emission pulse period, read according to the corresponding parameters in the order of storage, and then subjected to PC operation, including: the data after DBF operation of each pulse is cyclically stored into N data buffer areas in the order of distance first and then beam, and then, in the order of beam first and then distance, the data of each beam is read out in turn, and the PC operation is performed on the read data.

[0014] Optionally, the data after PC operation is stored in a queue in a cyclic manner according to the accumulation period, read according to the corresponding parameters in the order of storage, and then subjected to MTD operation, including: the data after PC operation of each pulse is cyclically stored into N data buffer areas in the order of beam first, then distance, and then pulse, and then, in the order of distance first, then pulse, and then beam, the data is read, and the MTD operation is performed on the read data.

[0015] Optionally, after the data after PC operation is stored in a queue in a cyclic manner according to the accumulation period, read according to the corresponding parameters in the order of storage, and then subjected to MTD operation, the method further includes: performing constant false alarm detection based on the data after MTD operation. Description of the Drawings

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or the related art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 is a flowchart of a method for implementing queue-driven array radar signal processing based on FPGA provided in an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a queue data buffer area provided in an embodiment of the present application;

[0019] Figure 3 It is a schematic diagram of data flow during data processing provided in an embodiment of the present application;

[0020] Figure 4 It is a schematic diagram of caching the data after DBF operation provided in an embodiment of the present application;

[0021] Figure 5 It is a schematic diagram of caching the data after PC operation provided in an embodiment of the present application;

[0022] Figure 6 It is a schematic structural diagram of a queue-driven array radar signal processing implementation system based on FPGA provided in another embodiment of the present application;

[0023] Figure 7 It is a schematic structural diagram of an electronic device provided in another embodiment of the present application. Detailed implementation manners

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will elaborate on each embodiment of the present application in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided for readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation to the specific implementation manner of the present application. Each embodiment can be combined and cross-referenced with each other on the premise of not being contradictory.

[0025] To solve the problem of insufficient flexibility of FPGA, an embodiment of the present application proposes a method for implementing queue-driven array radar signal processing based on FPGA, which is applied to FPGA. The following will specifically describe the implementation details of the method for implementing queue-driven array radar signal processing based on FPGA proposed in this embodiment. The following content is only the implementation details provided for convenient understanding and is not necessary for implementing this solution.

[0026] The specific process of the method for implementing queue-driven array radar signal processing based on FPGA proposed in this embodiment can be as Figure 1 shown and includes:

[0027] Step 101, divide the queue data buffer into three parts: a data buffer, a parameter buffer, and a data status area. When performing a read operation, determine the read parameter through the status of the data status area, and then read the data according to the parameter.

[0028] In a specific implementation, the data storage involved in this application uses circular queue storage. To avoid using global timing and reduce the timing coupling between modules, the queue data buffer in the FPGA is pre-divided into three parts: a data buffer, a parameter buffer, and a data status area. When performing a read operation, the read parameters are determined through the status in the data status area, and then the data is read according to the parameters. Such data writing and data storage operations are more scientific and reasonable, and there will be no data contamination situation.

[0029] In one example, the number of both the data buffer and the parameter buffer is N, and the data buffer corresponds to the parameter buffer one by one, where N is an integer greater than 1.

[0030] In one example, the partitioning of the queue data buffer is as Figure 2 shown, and the data buffer and the parameter buffer with the same label correspond to each other.

[0031] In one example, all N data buffers are used to store relevant data in the signal processing process, and the write address and read address are used to implement the write operation and the read operation of the data according to the required rules.

[0032] In one example, all N parameter buffers are used to place relevant processing parameters corresponding to the data. The parameters are written synchronously with the data. When performing a data read operation, the parameters are read first, and then the number of data read out and the relevant read rules are determined according to the parameters.

[0033] In one example, the data status area is used to represent the data status of each data buffer. The data status is the unwritten status or the written and waiting status. After the data in the data buffer corresponding to the current loop address is read, it is judged whether the data status of the data buffer corresponding to the next loop address is the written and waiting status. If so, the data is read. If not, continue to wait until its data status becomes the written and waiting status, and then read the data.

[0034] Step 102: Circularly store the data after DDC in a queue according to the transmit pulse period, and read and perform DBF operations according to the corresponding parameters in the storage order.

[0035] In a specific implementation, the FPGA obtains the data after DDC in real time, and then circularly stores the obtained data after DDC in a queue according to the transmit pulse period, reads and performs DBF operations according to the corresponding parameters in the storage order, so as to obtain the data after DBF operation.

[0036] In one example, the data flow situation in the data processing process is as Figure 3 shown.

[0037] In one example, after the FPGA obtains the data after DDC, it is necessary to cyclically store the data after DDC of each pulse into N data buffer areas in the order of distance first and then channel. Then, based on a preset data rate, data is read according to the storage order, and the read time of the data is determined according to the situation of the read data and the data rate, and the DBF operation is performed on the read data. The determined read time of the data can keep the rate of the DBF operation after output unchanged. Such a design does not need to change the structure of the DBF operation.

[0038] It should be noted that the preset data rate can be set by those skilled in the art according to actual needs, and the present application does not make specific limitations on this.

[0039] Step 103: Cyclically store the data after the DBF operation in a queue according to the transmit pulse period, and read and perform the PC operation according to the corresponding parameters in the storage order.

[0040] In a specific implementation, after the FPGA completes the DBF operation and obtains the data after the DBF operation, it is necessary to cyclically store the data after the DBF operation in a queue according to the transmit pulse period, read and perform the PC operation according to the corresponding parameters in the storage order to obtain the data after the PC operation.

[0041] In one example, the FPGA needs to cyclically store the data after the DBF operation of each pulse into N data buffer areas in the order of distance first and then beam. Then, in the order of beam first and then distance, read the data of each beam in turn and perform the PC operation on the read data.

[0042] In one example, the process of caching the data after the DBF operation is as Figure 4 shown.

[0043] Step 104: Cyclically store the data after the PC operation in a queue according to the accumulation period, and read the data and perform the MTD operation according to the corresponding parameters in the storage order.

[0044] In a specific implementation, after the FPGA completes the PC operation and obtains the data after the PC operation, it is necessary to cyclically store the data after the PC operation in a queue according to the accumulation period, read the data and perform the MTD operation according to the corresponding parameters in the storage order to obtain the data after the MTD operation, that is, the MTD detection result.

[0045] In one example, the FPGA needs to store the data obtained from the PC operation for each pulse into N data buffer areas in sequence in a cycle in the order of beam first, range second, and pulse last. Then, the data is read out in the order of range first, pulse second, and beam last, and the MTD operation is performed on the read data.

[0046] In one example, the process of caching the data after the PC operation is as Figure 5 shown.

[0047] In one example, as Figure 3 shown, after the FPGA performs the MTD operation on the read data to obtain the data after the MTD operation, it is also necessary to perform constant false alarm detection based on the data after the MTD operation, so as to determine whether the target signal exists.

[0048] An implementation method for queue-driven array radar signal processing based on FPGA proposed in this embodiment stores the data after DDC in a queue cycle according to the transmit pulse period, reads the data according to the corresponding parameters in the order of storage, and performs the DBF operation. The data after the DBF operation is stored in a queue cycle according to the transmit pulse period, read according to the corresponding parameters in the order of storage, and the PC operation is performed. The data after the PC operation is stored in a queue cycle according to the accumulation period, the data is read according to the corresponding parameters in the order of storage, and the MTD operation is performed. That is to say, in this embodiment, data caching in the form of a queue is performed after DDC, after the DBF operation, and after the PC operation, which realizes isolation between modules and fast switching of parameter timings, avoids using global timings, reduces the timing coupling between modules, and ensures the independence of module operations. To implement data caching in the form of a queue, this application divides the queue data buffer into three parts: a data buffer area, a parameter buffer area, and a data status area. When performing a read operation, the read parameters are determined through the status of the data status area, and then the data is read according to the parameters. Such a design is beneficial to parameter switching, as well as the transplantation, writing, and debugging of the program.

[0049] The step divisions of the above various methods are only for clear description. When implemented, they can be combined into one step, or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this application; adding insignificant modifications to the algorithm or process or introducing insignificant designs, but not changing the core design of its algorithm and process, are all within the protection scope of this application.

[0050] Correspondingly, another embodiment of the present application proposes a system for implementing queue-driven array radar signal processing based on FPGA. The details of the system for implementing queue-driven array radar signal processing based on FPGA proposed in this embodiment will be specifically described below. The following content is only implementation details provided for convenient understanding and is not necessary for implementing this example. Figure 6 It is a schematic structural diagram of a system for implementing queue-driven array radar signal processing based on FPGA proposed in this embodiment, including: a cache partition module 201, a DBF operation module 202, a PC operation module 203, and an MTD operation module 204.

[0051] The cache partition module 201 is used to divide the queue data buffer into three parts: a data buffer, a parameter buffer, and a data status area, and to determine the read parameters through the status of the data status area during the read operation, and then read the data according to the parameters.

[0052] The DBF operation module 202 is used to cyclically store the data after DDC in a queue according to the transmit pulse period, read the data according to the corresponding parameters in the order of storage, and perform DBF operations.

[0053] The PC operation module 203 is used to cyclically store the data after DBF operation in a queue according to the transmit pulse period, read the data according to the corresponding parameters in the order of storage, and perform PC operations.

[0054] The MTD operation module 204 is used to cyclically store the data after PC operation in a queue according to the accumulation period, read the data according to the corresponding parameters in the order of storage, and perform MTD operations.

[0055] It is not difficult to find that this embodiment is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in cooperation with the above method embodiment. The relevant technical details and technical effects mentioned in the above method embodiment are still valid in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above method embodiment.

[0056] It is worth mentioning that each module involved in this embodiment is a logic module. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovative part of the present application, units that are not closely related to solving the technical problems proposed in the present application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0057] Another embodiment of the present application proposes an electronic device, and its specific structure can be as Figure 7As shown in the figure, it includes: at least one processor 301; and a memory 302 communicatively connected to the at least one processor 301; wherein, the memory 302 stores instructions executable by the at least one processor 301, and the instructions are executed by the at least one processor 301 to enable the at least one processor 301 to execute a method for implementing FPGA-based queue-driven array radar signal processing as described in each of the above method embodiments.

[0058] Among them, the memory and the processor are connected in a bus manner. The bus can include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art, so they will not be further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be an element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on the transmission medium. The data processed by the processor is transmitted over the wireless medium through the antenna. Further, the antenna also receives data and transmits the data to the processor.

[0059] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. The memory can be used to store data used by the processor when executing operations.

[0060] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A method for implementing queue-driven array radar signal processing based on FPGA, characterized in that, Including: The queue data buffer is divided into three parts: a data buffer, a parameter buffer, and a data status area. When performing a read operation, the read parameters are determined through the status in the data status area, and then the data is read according to the parameters. The data after DDC is stored in a queue in a cyclic manner according to the transmit pulse period, and read according to the corresponding parameters in the order of storage and then subjected to DBF operation. The data after DBF operation is stored in a queue in a cyclic manner according to the transmit pulse period, and read according to the corresponding parameters in the order of storage and then subjected to PC operation. The data after PC operation is stored in a queue in a cyclic manner according to the accumulation period, and the data is read according to the corresponding parameters in the order of storage and then subjected to MTD operation.

2. The implementation method of a queue-driven array radar signal processing based on FPGA according to claim 1, characterized in that The number of data buffers and parameter buffers is N, and the data buffers and parameter buffers correspond one by one; where N is an integer greater than 1.

3. The method for implementing queue-driven array radar signal processing based on FPGA according to claim 2, wherein The data buffer is used to store the relevant data in the signal processing process, and the write operation and read operation of the data are realized according to the required rules through the write address and read address. The parameter buffer is used to place the relevant processing parameters corresponding to the data, which are written synchronously with the data. When performing a data read operation, the parameters are read first, and then the number of data read out and the relevant read rules are determined according to the parameters. The data status area is used to represent the data status of each data buffer. The data status is the unwritten state or the waiting state after writing. After the data in the data buffer corresponding to the current loop address is read, it is judged whether the data status of the data buffer corresponding to the next loop address is the waiting state after writing. If so, the data is read. If not, continue to wait until its data status becomes the waiting state after writing, and then read the data.

4. The method for implementing queue-driven array radar signal processing based on FPGA according to claim 3, wherein, The data after DDC is stored in a queue in a cyclic manner according to the transmit pulse period, and read according to the corresponding parameters in the order of storage and then subjected to DBF operation, including: The data after DDC of each pulse is cyclically stored in N data buffers in the order of distance first and then channel. Then, based on a preset data rate, the data is read in the order of storage, and the time to read the data is determined according to the read data situation and the data rate, and the time to read the data is determined so that the rate of the output after DBF operation remains unchanged without changing the structure of the DBF operation.

5. The implementation method of a queue-driven array radar signal processing based on FPGA according to claim 3, characterized in that, The data after DBF operation is stored in a queue in a cyclic manner according to the transmit pulse period, and read according to the corresponding parameters in the order of storage and then subjected to PC operation, including: The data after DBF operation of each pulse is cyclically stored in N data buffers in the order of distance first and then beam. Then, the data of each beam is read out in the order of beam first and then distance, and the read data is subjected to PC operation.

6. The method for implementing queue-driven array radar signal processing based on FPGA according to claim 3, wherein, The data after PC operation is stored in a queue in a cyclic manner according to the accumulation period, and the data is read according to the corresponding parameters in the order of storage and then subjected to MTD operation, including: The data obtained from the PC operation for each pulse is cyclically stored in N data buffer areas in sequence in the order of beam first, range second, and pulse last. Then, the data is read in the order of range first, pulse second, and beam last, and the MTD operation is performed on the read data.

7. A method for implementing queue-driven array radar signal processing based on FPGA according to any one of claims 1 to 6, characterized in that After cyclically storing the data obtained from the PC operation in a queue according to the accumulation period, reading the data according to the corresponding parameters in the order of storage, and performing the MTD operation, the method further includes: Performing a constant false alarm rate detection based on the data after the MTD operation.

8. An FPGA-based implementation system for queue-driven array radar signal processing, characterized in that, It includes: A cache partition module, which is used to divide the queue data buffer into three parts: a data buffer area, a parameter buffer area, and a data status area, and is used to determine the reading parameters through the status of the data status area during the reading operation, and then read the data according to the parameters; A DBF operation module, which is used to cyclically store the data after DDC in a queue according to the transmit pulse period, read the data according to the corresponding parameters in the order of storage, and perform the DBF operation; A PC operation module, which is used to cyclically store the data after the DBF operation in a queue according to the transmit pulse period, read the data according to the corresponding parameters in the order of storage, and perform the PC operation; An MTD operation module, which is used to cyclically store the data after the PC operation in a queue according to the accumulation period, read the data according to the corresponding parameters in the order of storage, and perform the MTD operation.

9. An electronic device, characterized in that, It includes: At least one processor; And a memory communicatively connected to the at least one processor; Wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a method for implementing an FPGA-based queue-driven array radar signal processing as described in any one of claims 1 to 7.

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