Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a substrate, a driving circuit layer, a shading layer, a first common electrode layer, a pixel electrode layer, a second common electrode layer and a block-up structure. The driving circuit layer is located on the substrate and comprises a signal line located in the display area. The shading layer is located on the side, away from the substrate, of the driving circuit layer and comprises a plurality of shading lines. The shading line is overlapped with at least part of the signal line and comprises a metal shading layer located in the display area. In the display area, the first common electrode layer overlaps the light shielding layer and is in direct contact with the metal light shielding layer. At least part of the pixel electrode layer is located on the side, away from the substrate, of the first common electrode layer and the light shielding layer and is electrically insulated from the first common electrode layer. The second common electrode layer is located on the side, away from the substrate, of the pixel electrode layer and is electrically insulated from the pixel electrode layer. The heightening structure is located in the display area and located on the side, away from the substrate, of the second common electrode layer. The spacer is located in the display area and located on the heightening structure.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] With the development of 5G communication technology and the improvement of virtual reality (VR) content and hardware, etc., virtual reality technology is in a period of rapid development, and virtual reality technology has very high requirements for the resolution of the screen (>1000).

[0003] For virtual reality devices manufactured with liquid crystal display panels, due to the structural design characteristics of high resolution, the aperture ratio of the liquid crystal display panel is lower than that of conventional products. In order to increase the aperture ratio of the liquid crystal display panel, light-shielding metal lines are provided corresponding to signal lines such as data lines. While reducing the size of the organic light-shielding matrix and thus increasing the aperture ratio by setting the light-shielding metal lines, the reflectivity of the light-shielding metal lines is reduced. However, the introduction of the light-shielding metal lines may cause problems of abnormal display in the display panel. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a display panel and a display device to reduce the risk of abnormal display caused by the light-shielding layer in the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel. The display panel includes a substrate, a driving circuit layer, a light-shielding layer, a first common electrode layer, a pixel electrode layer, a second common electrode layer, and a padding structure. The driving circuit layer is located on the substrate and includes signal lines located in the display area. The light-shielding layer is located on a side of the driving circuit layer away from the substrate and includes a plurality of light-shielding lines. The light-shielding lines overlap with at least some of the signal lines and include a metal light-shielding layer located in the display area. In the display area, the first common electrode layer is stacked with the light-shielding layer and is in direct contact with the metal light-shielding layer. At least part of the pixel electrode layer is located on a side of the first common electrode layer and the light-shielding layer away from the substrate and is electrically insulated from the first common electrode layer. The second common electrode layer is located on a side of the pixel electrode layer away from the substrate and is electrically insulated from the pixel electrode layer. The padding structure is located in the display area and on a side of the second common electrode layer away from the substrate. A spacer is located in the display area and on the padding structure.

[0006] In a second aspect, an embodiment of the present application further provides a display device, and the display device includes the above-mentioned display panel.

[0007] In the display panel and display device of some embodiments of the present application, the shading line overlaps with at least a portion of the signal line to shield at least a portion of the signal line, which is beneficial to reducing the size of the organic shading matrix that also shields the signal line, thereby improving the aperture ratio of the display panel. In addition, the first common electrode layer is superimposed on the shading layer in the display area and is in direct contact with the metal shading layer. The metal shading layer can be connected to the voltage through the first common electrode layer, thereby improving the problem of electrostatic damage and coupling that causes signal crosstalk when the metal shading layer is in a floating state. Furthermore, the direct contact between the first common electrode layer and the metal shading layer can also simplify the connection process between the two and simplify the process of the display panel.

[0008] Furthermore, the spacers are located on the raised structure, which elevates them and reduces the risk of them sliding and damaging other layers. Furthermore, the raised structure is located in the display area, on the side of the second common electrode layer facing away from the substrate, reducing the risk of damage to other insulating layers caused by the raised structure beneath the second common electrode layer. This, in turn, reduces the risk of short circuits between different conductive layers caused by insulation layer damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic cross-sectional structure diagram of a display panel provided in some embodiments of the present application;

[0010] Figure 2 A schematic diagram of a partial planar layout of signal lines and shielding lines provided in some embodiments of the present application;

[0011] Figure 3 A schematic cross-sectional structure diagram of a first common electrode layer in direct contact with a light shielding layer provided in some embodiments of the present application;

[0012] Figure 4 A schematic diagram of a partial layout of an organic insulating layer, a light shielding layer, a first common electrode layer, and a second passivation layer in a display panel provided in some embodiments of the present application;

[0013] Figure 5 A schematic diagram of a partial layout of a pixel electrode layer provided for some embodiments of the present application;

[0014] Figure 6 A schematic structural diagram of a display device provided in some embodiments of the present application.

[0015] Description of reference numerals:

[0016] 200. Display device; 300. Backlight module;

[0017] 100, display panel; 100A, display area; 100B, non-display area;

[0018] 110 、 array substrate;

[0019] 111 、 substrate;

[0020] 120. driving circuit layer;

[0021] 121, signal line; 1211, data line;

[0022] 122, pixel driving circuit; 1221, metal oxide transistor; 1222, top gate; 1223, bottom gate;

[0023] 123. Gate drive circuit; 1231. Low-temperature polysilicon transistor; 1232. Gate;

[0024] 1241, a first semiconductor layer; 1242, a second semiconductor layer;

[0025] 1251, first conductive layer; 1252, second conductive layer; 1253, third conductive layer;

[0026] 1261, a first gate insulating layer; 1262, a second gate insulating layer; 1263, a third gate insulating layer;

[0027] 1271, a first interlayer dielectric layer; 1272, a second interlayer dielectric layer; 1273, a third interlayer dielectric layer;

[0028] 130, light-shielding layer; 131, light-shielding line; 132, metal light-shielding layer; 133, insulating dielectric layer; 131A, first side surface; 131B, first top surface; 131C, first bottom surface;

[0029] 140. First common electrode layer; 141. First common electrode line;

[0030] 150, pixel electrode layer; 151, first light-transmitting conductive layer; 152, second light-transmitting conductive layer; 153, first pixel electrode; 154, second pixel electrode;

[0031] 160. Organic insulating layer; 161. Through groove; 162. Through hole;

[0032] 170. First passivation layer; 171. Second passivation layer; 172. Third passivation layer;

[0033] 180. Light-transmitting conductive structure; 181. Signal transmission structure; 182. Filling material;

[0034] 191, padding structure; 191A, second bottom surface; 191B, second top surface; 191C, second side surface; 192, spacer;

[0035] 193. The second common electrode layer;

[0036] 20. The counter substrate;

[0037] 21. The organic light-shielding matrix;

[0038] H1. The first connection hole; H2. The second connection hole; H3. The third connection hole; H4. The fourth connection hole. Specific embodiments

[0039] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0040] Figure 1 It is a schematic cross-sectional structure diagram of a display panel provided for some embodiments of the present application. Figure 2 It is a schematic partial planar layout diagram of signal lines and light-shielding lines provided for some embodiments of the present application.

[0041] As Figure 1 shown, the display panel 100 has a display area 100A and a non-display area 100B. The non-display area 100B is located on the periphery of the display area 100A. The display panel 100 includes an array substrate 110, a counter substrate 20, and a liquid crystal layer (not shown in the figure). The liquid crystal layer is located between the array substrate 110 and the counter substrate 20.

[0042] The array substrate 110 includes a substrate 111, a driving circuit layer 120, a light-shielding layer 130, and a first common electrode layer 140.

[0043] As Figure 1 and Figure 2 shown, the driving circuit layer 120 is located on the substrate 111 and includes signal lines 121 located in the display area 100A. The signal lines 121 may include data lines 1211 and scanning lines (not shown in the figure). A plurality of data lines 1211 are insulated from and intersect with a plurality of scanning lines.

[0044] As Figure 1 shown, the driving circuit layer 120 further includes pixel driving circuits 122, and the pixel driving circuits 122 may be located in the display area 100A. In some embodiments, as Figure 1As shown, the pixel driving circuit 122 may include a metal oxide transistor 1221, and the metal oxide transistor 1221 is located in the display area 100A. Since the metal oxide active layer of the metal oxide transistor 1221 has light transmissivity, the aperture ratio of the display panel 100 can be increased.

[0045] In addition to including a metal oxide active layer, the metal oxide transistor 1221 may further include one or two gates, and one or two gates overlap with the metal oxide active layer. In some embodiments, as Figure 1 shown, the metal oxide transistor 1221 includes a top gate 1222 and a bottom gate 1223. The metal oxide active layer is located between the top gate 1222 and the bottom gate 1223, and the top gate 1222 and the bottom gate 1223 are connected. In this way, the on-state current of the metal oxide transistor 1221 is increased, and its off-state leakage current is reduced.

[0046] In some embodiments, the pixel driving circuit 122 may further include a low-temperature polysilicon transistor. The low-temperature polysilicon transistor may be located in the display area 100A. Since the low-temperature polysilicon transistor has a high mobility, it has a faster switching speed and a higher driving ability, which is beneficial for the display panel 100 to achieve a high refresh rate.

[0047] As Figure 1 shown, the driving circuit layer 120 may further include a gate driving circuit 123, and the gate driving circuit 123 may be located in the non-display area 100B. In some embodiments, the gate driving circuit 123 may include a low-temperature polysilicon transistor 1231, and the low-temperature polysilicon transistor 1231 is located in the non-display area 100B. Since the low-temperature polysilicon transistor 1231 has a high mobility, it has a faster switching speed and a higher driving ability, which is beneficial for the display panel 100 to achieve a high refresh rate.

[0048] In some embodiments, as Figure 1 shown, the low-temperature polysilicon transistor 1231 includes a low-temperature polysilicon active layer and a gate 1232.

[0049] In some other embodiments, the gate driving circuit 123 may also include a metal oxide transistor.

[0050] It should be noted that in the case where the pixel driving circuit 122 includes the metal oxide transistor 1221 and the gate driving circuit 123 includes the low-temperature polysilicon transistor 1231, the display panel 100 adopts low-temperature polycrystalline oxide (LTPO) to utilize the advantages of the metal oxide transistor 1221 and the low-temperature polysilicon transistor 1231 to improve the display performance and energy efficiency of the display panel 100.

[0051] In an exemplary embodiment, as Figure 1 shown, the driving circuit layer 120 includes a first semiconductor layer 1241, a second semiconductor layer 1242, a first conductive layer 1251, a second conductive layer 1252, and a third conductive layer 1253.

[0052] The first semiconductor layer 1241 may include the low-temperature polysilicon active layer of the low-temperature polysilicon transistor 1231.

[0053] The second semiconductor layer 1242 is located on the side of the first semiconductor layer 1241 away from the substrate 111. The second semiconductor layer 1242 may include the metal oxide active layer of the metal oxide transistor 1221.

[0054] The first conductive layer 1251 may be disposed between the first semiconductor layer 1241 and the second semiconductor layer 1242. The first conductive layer 1251 may include the gate 1232 of the low-temperature polysilicon transistor 1231. The first conductive layer 1251 may further include the bottom gate 1223 of the metal oxide transistor 1221. A first gate insulating layer 1261 may be disposed between the first conductive layer 1251 and the first semiconductor layer 1241. A second gate insulating layer 1262 may be disposed between the first conductive layer 1251 and the second semiconductor layer 1242.

[0055] The second conductive layer 1252 is located on the side of the second semiconductor layer 1242 away from the substrate 111. As Figure 1 shown, the second conductive layer 1252 may include the top gate 1222 of the metal oxide transistor 1221. A third gate insulating layer 1263 may be disposed between the second conductive layer 1252 and the second semiconductor layer 1242.

[0056] The third conductive layer 1253 is located on the side of the second conductive layer 1252 away from the substrate 111. The third conductive layer 1253 may include the source and drain of the low-temperature polysilicon transistor 1231. The third conductive layer 1253 may include a connection electrode, and the connection electrode is connected to the metal oxide active layer. A first interlayer dielectric layer 1271 may be disposed between the third conductive layer 1253 and the second conductive layer 1252.

[0057] The driving circuit layer 120 may further include a second interlayer dielectric layer 1272. The second interlayer dielectric layer 1272 is located on the side of the first interlayer dielectric layer 1271 away from the substrate 111 and covers the third conductive layer 1253 to protect the third conductive layer 1253.

[0058] In some embodiments, any one of the first gate insulating layer 1261 to the third gate insulating layer 1263 and the first interlayer dielectric layer 1271 to the second interlayer dielectric layer 1272 may include an inorganic insulating material.

[0059] Figure 3 Schematic diagram of the partial layout of the organic insulating layer, light-shielding layer, first common electrode layer, and second passivation layer in the display panel provided for some embodiments of the present application. Figure 4 Schematic cross-sectional structure diagram of the direct contact between the first common electrode layer and the light-shielding layer provided for some embodiments of the present application.

[0060] In some embodiments, as Figure 1 and Figure 2 shown, the light-shielding layer 130 is located on the side of the driving circuit layer 120 away from the substrate 111, and includes a plurality of light-shielding lines 131. The plurality of light-shielding lines 131 overlap with at least part of the signal lines 121. In this way, the plurality of light-shielding lines 131 shield at least part of the signal lines 121, which is beneficial to reducing the size of the organic light-shielding matrix 21 that also shields the signal lines 121, and thus improving the aperture ratio of the display panel 100.

[0061] In some embodiments, as Figure 1 and Figure 2 shown, the plurality of light-shielding lines 131 respectively overlap with the plurality of data lines 1211 to ensure that the plurality of light-shielding lines 131 shield the plurality of data lines 1211. In some embodiments, the width of the light-shielding line 131 can be greater than or equal to the width of the data line 1211.

[0062] In some embodiments, the extending direction of the plurality of light-shielding lines 131 can be parallel to the extending direction of the plurality of data lines 1211.

[0063] In other embodiments, the plurality of light-shielding lines 131 can also overlap with the plurality of scan lines to ensure that the plurality of light-shielding lines stop the plurality of scan lines.

[0064] As Figure 4 shown, each light-shielding line 131 includes a metal light-shielding layer 132 located in the display area 100A to improve the light-shielding effect of the light-shielding layer 130. In some embodiments, as Figure 4 shown, each light-shielding line 131 includes two metal light-shielding layers 132 and an insulating dielectric layer 133. The insulating dielectric layer 133 is located between the two metal light-shielding layers 132 to improve the light-shielding effect of the light-shielding line 131 and reduce the light reflectivity of the light-shielding line 131. In other embodiments, each light-shielding line 131 can also include a stacked metal light-shielding layer 132 and an insulating dielectric layer 133.

[0065] In some embodiments, the thickness of the light-shielding layer 130 can be 0.1 micrometer to 0.3 micrometers, ensuring the light-shielding performance of the light-shielding layer 130 while reducing the reflectivity of the light-shielding layer 130.

[0066] In some embodiments, the metal light shielding layer 132 may include at least one of molybdenum, aluminum, titanium, copper, and silver. In some embodiments, the metal light shielding layer 132 may include a stacked metal material such as Mo-Al-Mo, Ti-Al-Ti, Mo-Cu-Mo, Ti-Cu-Ti, Al-Mo, Al-Ti, Cu-Mo, and Cu-Ti.

[0067] In some embodiments, the insulating dielectric layer 133 may include an inorganic insulating material, including but not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0068] In some embodiments, as Figure 4 As shown, each light-shielding line 131 has two opposing first side surfaces 131A, a first top surface 131B, and a first bottom surface 131C. The first top surface 131B is located on the side of the first bottom surface 131C facing away from the substrate 111. Both first side surfaces 131A are connected between the first top surface 131B and the first bottom surface 131C. The first common electrode layer 140 extends from the driving circuit layer 120 through at least one of the first side surfaces 131A to the first top surface 131B of the light-shielding line 131. Thus, a portion of the light-shielding layer 130 is located below the first common electrode layer 140, allowing direct contact between the first common electrode layer 140 and the at least one first side surface 131A and the first top surface 131B of the light-shielding line 131. This facilitates direct contact between the first common electrode layer 140 and the metal light-shielding layer 132, thereby alleviating the problems of electrostatic damage and signal crosstalk caused by the metal light-shielding layer 132 being in a floating state.

[0069] It should be noted that in related art, an insulating layer is provided between the first common electrode layer and the metal light shielding layer, and the two are connected via vias in the insulating layer. Compared to related art, the insulating layer between the first common electrode layer 140 and the metal light shielding layer 132 is removed in the embodiment of the present application. This allows the first common electrode layer 140 to directly contact at least one first side surface 131A and the first top surface 131B of the light shielding line 131, simplifying the manufacturing process of the display panel 100.

[0070] In some embodiments, the angle between the first side surface 131A and the first bottom surface 131C can be greater than or equal to 30 degrees and less than or equal to 70 degrees. This ensures that the inclination of the first side surface 131A is within an appropriate range, reduces the risk of the first common electrode layer 140 breaking when extending along the first side surface 131A, and alleviates the problem of the first side surface 131A having a too small inclination resulting in a high reflectivity of the light shielding layer 130. Alternatively, the angle between the first side surface 131A and the first bottom surface 131C can be greater than or equal to 35 degrees and less than or equal to 65 degrees.

[0071] The first common electrode layer 140 is used to transmit a common voltage. In some embodiments, as Figure 1 and Figure 2 shown, the first common electrode layer 140 includes a plurality of first common electrode lines 141, and the plurality of first common electrode lines 141 are arranged at intervals. The plurality of first common electrode lines 141 can be connected through a conductive connection structure in the non-display area 100B.

[0072] In some embodiments, in the extending direction of the first common electrode line 141, one first common electrode line 141 intersects at least two light-shielding lines 131, that is, the extending direction of the first common electrode line 141 intersects with the extending direction of the light-shielding line 131. And the first common electrode line 141 is in direct contact with the first top surface 131B and the two first side surfaces 131A of each of the at least two light-shielding lines 131. Thus, one first common electrode line 141 can be in contact with the metal light-shielding layer 132 of at least two light-shielding lines 131, simplifying the connection process between the first common electrode line 141 and the at least two light-shielding lines 131.

[0073] In the case where each light-shielding line 131 includes two metal light-shielding layers 132 and an insulating dielectric layer 133, the first common electrode layer 140 can be in direct contact with the two metal light-shielding layers 132 through the first side surface 131A.

[0074] In some embodiments, the first common electrode layer 140 can include a transparent conductive material such as indium tin oxide.

[0075] In some embodiments, as Figure 1 shown, the display panel 100 further includes a pixel electrode layer 150. At least a part of the pixel electrode layer 150 is located on the side of the first common electrode layer 140 and the light-shielding layer 130 away from the substrate 111, and is electrically insulated from the first common electrode layer 140. The pixel electrode layer 150 is connected to the pixel driving circuit 122. The pixel electrode layer 150 overlaps at least a part of the first common electrode layer 140 to form a first storage capacitor.

[0076] In some embodiments, as Figure 1 and Figure 3 shown, the display panel 100 may further include an organic insulating layer 160, and the organic insulating layer 160 is located between the light-shielding layer 130 and the driving circuit layer 120. The organic insulating layer 160 plays a flattening role for the driving circuit layer 120. The organic insulating layer 160 includes a through groove 161, and the through groove 161 is located in the display area 100A and penetrates the organic insulating layer 160. At least a part of the pixel electrode layer 150 is located in the through groove 161, so as to facilitate the connection between the pixel electrode layer 150 and the pixel driving circuit 122 in the driving circuit layer 120, and is also beneficial to the display panel 100 to achieve high-resolution display.

[0077] In the related art, limited by the manufacturing process, the minimum size of the vias formed on the organic insulating layer is in the micron range, resulting in a relatively large layout space occupied by the vias, which is not conducive to the display panel achieving high-resolution display. In the embodiments of the present application, the through groove 161 is adopted, and its formation process is simpler and the size is not limited by the manufacturing process, and it can also ensure the connection between the pixel electrode layer 150 and the pixel driving circuit 122.

[0078] In some embodiments, as Figure 3 shown, the through groove 161 does not overlap with the plurality of light shielding lines 131, reducing the risk of short circuit between the pixel electrode layer 150 in the through groove 161 and the first common electrode layer 140 caused by the contact between the plurality of light shielding lines 131 and the pixel electrode layer 150 in the through groove 161, resulting in a black screen.

[0079] In some embodiments, the extending direction of the through groove 161 is parallel to the extending direction of the first common electrode line 141. The orthographic projection of the through groove 161 on the substrate 111 is located between two adjacent first common electrode lines 141. The gap between two adjacent light shielding lines 131 overlapped by a data line 1211 overlaps with the through groove 161, so that the light shielding lines 131 and the through groove 161 are staggered.

[0080] In some embodiments, the thickness of the organic insulating layer 160 is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0081] In some embodiments, as Figure 1 shown, the display panel 100 further includes a light-transmissive conductive structure 180. The light-transmissive conductive structure 180 connects the pixel electrode layer 150 in the through groove 161 and the pixel driving circuit 122. Since the light-transmissive conductive structure 180 has light-transmissivity, the aperture ratio of the display panel 100 is further improved. When the pixel driving circuit 122 includes a metal oxide transistor 1221, the light-transmissive conductive structure 180 connects the metal oxide transistor 1221 and the pixel electrode layer 150 in the through groove 161.

[0082] In some embodiments, the light-transmissive conductive structure 180 may include a transparent conductive material such as indium tin oxide.

[0083] In some embodiments, as Figure 1 shown, the pixel electrode layer 150 includes a first light-transmissive conductive layer 151 and a second light-transmissive conductive layer 152. At least a part of the first light-transmissive conductive layer 151 is located in the through groove 161. The second light-transmissive conductive layer 152 is located on the side of the first light-transmissive conductive layer 151 away from the substrate. In this way, the risk of connection failure between the pixel electrode layer 150 and the pixel driving circuit 122 is reduced, and it is also beneficial to ensure that the distance between the second light-transmissive conductive layer 152 and the second common electrode layer 193 below is relatively close, ensuring that the electric field generated by the voltage difference between the two can better drive the rotation of the liquid crystal molecules in the liquid crystal layer.

[0084] Figure 5 Schematic diagram of a partial layout of a pixel electrode layer provided for some embodiments of the present application.

[0085] As Figure 5 shown, the first light-transmissive conductive layer 151 may include a plurality of first pixel electrodes 153, and the second light-transmissive conductive layer 152 may include a plurality of second pixel electrodes 154. The plurality of first pixel electrodes 153 may be located in the through-grooves 161. The plurality of first pixel electrodes 153 are respectively stacked and connected to the plurality of second pixel electrodes 154 in a one-to-one manner.

[0086] In some embodiments, the orthographic projection of the first pixel electrode 153 on the substrate 111 is located within the orthographic projection of the second pixel electrode 154 on the substrate 111. Thus, the size of the second pixel electrode 154 is larger than that of the first pixel electrode 153. The second pixel electrode 154 cooperates with the first common electrode layer 140 and the second common electrode layer 193 described below, and can better drive the rotation of liquid crystal molecules in the liquid crystal layer.

[0087] In some embodiments, both the first light-transmissive conductive layer 151 and the second light-transmissive conductive layer 152 include transparent conductive materials such as indium tin oxide.

[0088] In some embodiments, the display panel 100 further includes a filling material 182. The filling material 182 fills the through-grooves 161, and a part of the filling material 182 is located between the first light-transmissive conductive layer 151 and the second light-transmissive conductive layer 152. The filling material plays a planarizing role for the through-grooves 161, and ensures the flatness of structures such as the second light-transmissive conductive layer 152 around the through-grooves 161.

[0089] In some embodiments, the filling material 182 may include a light-transmissive organic insulating material to ensure that the filling material can better fill the through-grooves 161.

[0090] In some embodiments, as Figure 1 shown, the display panel 100 further includes a second common electrode layer 193. The second common electrode layer 193 is used to transmit a common voltage. The second common electrode layer 193 is located on the side of the pixel electrode layer 150 away from the substrate 111 and is electrically insulated from the pixel electrode layer 150. At least a part of the second common electrode layer 193 overlaps with the pixel electrode layer 150 to form a second storage capacitor. The first storage capacitor and the second storage capacitor cooperate to improve the flicker and signal crosstalk problems of the display panel 100.

[0091] In some embodiments, the second common electrode layer 193 may include transparent conductive materials such as indium tin oxide. The second common electrode layer 193 may include a plurality of openings.

[0092] In some embodiments, as Figure 1 shown, the display panel 100 further includes a first passivation layer 170, a second passivation layer 171, and a third passivation layer 172. The first passivation layer 170 to the third passivation layer 172 may all include an inorganic insulating material.

[0093] The organic insulating layer 160 is located between the first passivation layer 170 and the driving circuit layer 120. The first passivation layer 170 is located between the driving circuit layer 120 and the light-shielding layer 130 and between the driving circuit layer 120 and the first common electrode layer 140, and is in direct contact with the first common electrode layer 140 and the light-shielding layer 130.

[0094] The second passivation layer 171 is located between the first common electrode layer 140 and a part of the pixel electrode layer 150 and between the light-shielding layer 130 and a part of the pixel electrode layer 150, and is in direct contact with the light-shielding layer 130 and the first common electrode layer 140.

[0095] The third passivation layer 172 is located between the pixel electrode layer 150 and the second common electrode layer 193.

[0096] In some embodiments, as Figure 1 shown, the driving circuit layer 120 further includes a signal transmission structure 181. The signal transmission structure 181 is located in the non-display area 100B. The signal transmission structure 181 is used to transmit a common voltage. The signal transmission structure 181 may include at least one of a pad and a common electrode trace. In an exemplary embodiment, the third conductive layer 1253 includes the signal transmission structure 181.

[0097] In some embodiments, the organic insulating layer 160 further includes a through hole 162. The through hole 162 is located in the non-display area 100B and penetrates the organic insulating layer 160. The through hole 162 and the through groove 161 can be formed using the same photomask, reducing the manufacturing cost of the display panel 100.

[0098] In some embodiments, as Figure 1 shown, the display panel 100 further includes a first connection hole H1. The first connection hole H1 is located in the through hole 162. The first connection hole H1 penetrates the first passivation layer 170 and the second passivation layer 171 formed in the through hole 162 and extends into the driving circuit layer 120. Thus, the first connection hole H1 is sleeved in the through hole 162, and the first connection hole H1 and the through hole 162 can be formed step by step to reduce the manufacturing difficulty of the display panel 100.

[0099] In an exemplary embodiment, the driving circuit layer 120 may further include a third interlayer dielectric layer 1273. The third interlayer dielectric layer 1273 is located between the organic insulating layer 160 and the second interlayer dielectric layer 1272. The first connection hole H1 penetrates through the first passivation layer 170 and the second passivation layer 171 in the via hole 162 and extends into the third interlayer dielectric layer 1273.

[0100] The display panel 100 further includes a second connection hole H2. The second connection hole H2 is in communication with the first connection hole H1. The second connection hole H2 penetrates through the third passivation layer 172 in the first connection hole H1 and extends into the driving circuit layer 120 to expose the signal transmission structure 181. The second common electrode layer 193 is located in the first connection hole H1 and the second connection hole H2 and is in contact with the signal transmission structure 181. In this way, the second common electrode layer 193 is connected to the signal transmission structure 181 through the first connection hole H1 and the second connection hole H2. Moreover, the first connection hole H1 and the second connection hole H2 can be formed step by step, simplifying the manufacturing process of the display panel 100.

[0101] In an exemplary embodiment, the second connection hole H2 penetrates through the third passivation layer 172 in the first connection hole H1 and extends into the second interlayer dielectric layer 1272.

[0102] In some embodiments, the display panel 100 further includes a third connection hole H3. The third connection hole H3 is located in the through groove 161, penetrates through the first passivation layer 170 and the second passivation layer 171 formed in the through groove 161, and extends into the driving circuit layer 120. A part of the pixel electrode layer 150 is located in the third connection hole H3. In this way, the pixel electrode layer 150 can be connected to the light-transmissive conductive structure 180 in the driving circuit layer 120 through the third connection hole H3. Moreover, the third connection hole H3 is sleeved in the through groove 161, and the third connection hole H3 and the through groove 161 are formed step by step, reducing the manufacturing difficulty of the display panel 100. Furthermore, since both the third connection hole H3 and the first connection hole H1 penetrate through the first passivation layer 170 and the second passivation layer 171 and extend into the driving circuit layer 120, the two can be prepared using the same photomask, reducing the manufacturing cost of the display panel 100.

[0103] In an exemplary embodiment, both the first connection hole H1 and the third connection hole H3 penetrate through the first passivation layer 170 and the second passivation layer 171 and extend into the third interlayer dielectric layer 1273 to facilitate the two to penetrate through the same film layer.

[0104] In some embodiments, the display panel 100 further includes a fourth connection hole H4. The fourth connection hole H4 is located in the non-display area 100B, penetrates through the third passivation layer 172 and the second passivation layer 171, and exposes the first common electrode layer 140. The second common electrode layer 193 is also located in the fourth connection hole H4 and contacts the first common electrode layer 140. In this way, the second common electrode layer 193 bridges the first common electrode layer 140 and the signal transmission structure 181 to transmit the common voltage transmitted by the signal transmission structure 181 to the second common electrode layer 193. Moreover, since both the fourth connection hole H4 and the second connection hole H2 penetrate through the third passivation layer 172, they can be fabricated using the same photomask, reducing the manufacturing cost of the display panel 100.

[0105] Combining the above content, it can be seen that for the through hole 162, the first connection hole H1, and the second connection hole H2, the three can be fabricated through a common photomask, thereby reducing the manufacturing cost of the display panel 100.

[0106] In some embodiments, as Figure 1 shown, the display panel 100 further includes a heightening structure 191 and a spacer 192. The heightening structure 191 is located in the display area 100A and on the side of the second common electrode layer 193 facing away from the substrate 111. The spacer 192 is located in the display area 100A and on the heightening structure 191. In this way, the heightening structure 191 raises the spacer 192, reducing the risk of the spacer 192 sliding and damaging other film layers. Moreover, the heightening structure 191 is located above the second common electrode layer 193, the pixel electrode layer 150, and the first common electrode layer 140, reducing the risk of the heightening structure 191 being located below the second common electrode layer 193 causing damage to other insulating film layers, and further reducing the risk of short circuit between different conductive layers due to damage to the insulating layer. Furthermore, the heightening structure 191 is located above the second common electrode layer 193, enabling the heightening structure 191 to be set thicker and larger to ensure better support performance for the spacer 192.

[0107] In some embodiments, the thickness of the heightening structure 191 is greater than the thickness of the light-shielding layer 130 to ensure that the heightening structure 191 has a greater thickness and better raises the spacer 192, further reducing the risk of the spacer 192 sliding and damaging other film layers.

[0108] In some embodiments, the ratio of the thickness of the heightening structure 191 to the thickness of the light-shielding layer 130 can be greater than 3 and less than or equal to 7. In this way, the thickness of the heightening structure 191 is ensured to be within a suitable range, ensuring the raising effect of the heightening structure 191 while reducing its manufacturing difficulty. Optionally, the ratio of the thickness of the heightening structure 191 to the thickness of the light-shielding layer 130 can be greater than 4 and less than or equal to 6.

[0109] In some embodiments, the elevation structure 191 includes an organic support block to ensure that the elevation structure 191 has sufficient thickness and certain cushioning performance, thereby improving its anti-deformation force. In some embodiments, the elevation structure 191 may further include an inorganic insulating layer.

[0110] In some embodiments, as Figure 1 shown, the elevation structure 191 includes a second bottom surface 191A, a second top surface 191B, and a second side surface 191C. The second top surface 191B is located on the side of the second bottom surface 191A away from the substrate 111. The second side surface 191C is connected between the second bottom surface 191A and the second top surface 191B. The angle between the second side surface 191C and the second bottom surface 191A is greater than or equal to 30 degrees and less than or equal to 90 degrees. In this way, it is ensured that the second side surface 191C has a proper slope, and while ensuring that the second top surface 191B provides a large enough support area for the spacer 192, the problem that the second bottom surface 191A occupies too much space and is not conducive to improving the aperture ratio is improved.

[0111] In some embodiments, the angle between the second side surface 191C and the second bottom surface 191A may be greater than or equal to the angle between the first side surface 131A and the second bottom surface, making the second side surface 191C of the elevation structure 191 steeper and improving the problem that the second bottom surface 191A occupies too much space and is not conducive to improving the aperture ratio.

[0112] In some embodiments, as Figure 1 shown, the display panel 100 further includes an organic light-shielding matrix 21. The organic light-shielding matrix 21 overlaps with the light-shielding lines 131 and the signal lines 121 to shield the signal lines 121. In some embodiments, the organic light-shielding matrix 21 also covers the gaps between adjacent light-shielding lines 131 that overlap with the data lines 1211.

[0113] In some embodiments, the organic light-shielding matrix 21 may be located on the substrate 111 and on the side of the light-shielding layer 130 away from the substrate 111. In other embodiments, as Figure 1 shown, the organic light-shielding matrix 21 may also be located on the counter substrate 20.

[0114] Figure 6 The structural schematic diagram of the display device provided by some embodiments of the present application. As Figure 6 shown, the display device 200 includes the above-mentioned display panel 100 and a backlight module 300. The display panel 100 is located on the light-emitting side of the backlight module 300.

[0115] The description of the above embodiments is only used to help understand the technical solutions and their core ideas of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, The display panel has a display area and includes: a substrate; a driving circuit layer located on the substrate and including signal lines located in the display area; a light-shielding layer located on a side of the driving circuit layer facing away from the substrate and including a plurality of light-shielding lines, the plurality of light-shielding lines overlapping at least a part of the signal lines, and each light-shielding line including a metal light-shielding layer located in the display area; a first common electrode layer stacked with the light-shielding layer in the display area and in direct contact with the metal light-shielding layer; a pixel electrode layer, at least a part of the pixel electrode layer being located on a side of the first common electrode layer and the light-shielding layer facing away from the substrate and being electrically insulated from the first common electrode layer; a second common electrode layer located on a side of the pixel electrode layer facing away from the substrate and being electrically insulated from the pixel electrode layer; a heightening structure located in the display area and on a side of the second common electrode layer facing away from the substrate; and a spacer located in the display area and on the heightening structure.

2. The display panel according to claim 1, wherein The light-shielding line has two opposite first side surfaces, a first top surface, and a first bottom surface, the first top surface being located on a side of the first bottom surface facing away from the substrate, and both of the two first side surfaces being connected between the first top surface and the first bottom surface; wherein, the first common electrode layer extends from the driving circuit layer to the first top surface of the light-shielding line via at least one of the first side surfaces.

3. The display panel according to claim 2, characterized in that, The heightening structure includes a second bottom surface, a second top surface, and a second side surface, the second top surface being located on a side of the second bottom surface facing away from the substrate, and the second side surface being connected between the second bottom surface and the second top surface; wherein, an angle between the second side surface and the second bottom surface is greater than or equal to an angle between the first bottom surface and the first side surface.

4. The display panel according to claim 3, wherein, The angle between the second side surface and the second bottom surface is greater than or equal to 30 degrees and less than or equal to 90 degrees.

5. The display panel according to claim 2, wherein The first common electrode layer includes a plurality of first common electrode lines, and in an extending direction of the first common electrode lines, one first common electrode line intersects at least two of the light-shielding lines and is in direct contact with the first top surface and the two first side surfaces of each of at least two of the light-shielding lines.

6. The display panel according to claim 1, wherein It further includes: an organic insulating layer located between the light-shielding layer and the driving circuit layer and including a through groove located in the display area and penetrating through the organic insulating layer; at least a part of the pixel electrode layer is located in the through groove, and the through groove does not overlap with the plurality of light-shielding lines.

7. The display panel according to claim 1, characterized in that, It further includes: a first passivation layer located between the driving circuit layer and the light-shielding layer and between the driving circuit layer and the first common electrode layer and being in direct contact with the first common electrode layer and the light-shielding layer; a second passivation layer located between the first common electrode layer and a part of the pixel electrode layer and between the light-shielding layer and a part of the pixel electrode layer and being in direct contact with the light-shielding layer and the first common electrode layer; a third passivation layer located between the pixel electrode layer and the second common electrode layer.

8. The display panel according to claim 7, wherein The display panel further has a non-display area and further includes: a signal transmission structure, located in the driving circuit layer of the non-display area; an organic insulating layer, located between the first passivation layer and the driving circuit layer, and comprising a through hole, wherein the through hole is located in the non-display area and penetrates the organic insulating layer; a first connecting hole, located in the through hole, penetrating the first passivation layer and the second passivation layer in the through hole and extending into the driving circuit layer; a second connection hole, communicating with the first connection hole, penetrating the third passivation layer in the first connection hole and extending into the driving circuit layer to expose the signal transmission structure; The second common electrode layer is located in the first connection hole and the second connection hole and is in contact with the signal transmission structure.

9. The display panel according to claim 8, wherein The organic insulating layer further includes a through groove, wherein the through groove is located in the display area and penetrates the organic insulating layer; The display panel also includes a third connection hole, which is located in the through groove and penetrates the first passivation layer and the second passivation layer in the through groove and extends into the driving circuit layer. Part of the pixel electrode layer is located in the third connection hole.

10. The display panel according to claim 8, wherein Also includes: a fourth connection hole, located in the non-display area, penetrating the third passivation layer and the second passivation layer and exposing the first common electrode layer; Wherein, the second common electrode layer is also located in the fourth connection hole and contacts the first common electrode layer.

11. The display panel according to claim 1, wherein, The thickness of the raised structure is greater than the thickness of the light shielding layer.

12. The display panel according to claim 1, wherein, The raising structure includes an organic support block.

13. The display panel according to any one of claims 1 to 12, characterized in that, The light-shielding line includes two metal light-shielding layers and an insulating dielectric layer, and the insulating dielectric layer is located between the two metal light-shielding layers.

14. The display panel according to any one of claims 1 to 12, characterized in that, Also includes: An organic light-shielding matrix overlaps the light-shielding lines and the signal lines.

15. The display panel according to any one of claims 1 to 12, characterized in that, The display panel further has a non-display area, and the driving circuit layer further includes a low-temperature polysilicon transistor, which is located in the non-display area.

16. A display device, characterized in that, The display device comprises the display panel according to any one of claims 1 to 15.

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