Measurement method of overlay error

Abstract

The invention relates to the technical field of semiconductors, provides an overlay error measuring method, and is used for solving the technical problem of how to efficiently and accurately measure an overlay error between a current layer and a previous layer. The measuring method comprises the following steps: acquiring a first scanning image of a first conductive pattern and a second conductive pattern in a semiconductor structure; determining a first overlay error between the second conductive pattern and the first conductive pattern according to the first scanning image; acquiring a second scanning image of the third conductive pattern and the first conductive pattern in the semiconductor structure; determining a second overlay error between the third conductive pattern and the first conductive pattern according to the second scanning image; and determining a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error. Thus, the overlay error between the current layer of pattern and the previous layer of pattern can be accurately and efficiently obtained, product defects caused by the overlay error are reduced, and the quality and yield of products can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a method for measuring overlay error. Background Art

[0002] In the process of semiconductor manufacturing, multiple photolithography processes are usually required to transfer circuit patterns of different layers onto a wafer. By measuring the position deviation between the current layer pattern and the previous layer pattern on the wafer, the overlay error (OVL) between these two layers of patterns can be obtained. The overlay error is a key parameter for measuring the alignment accuracy of different layer patterns and directly affects the yield and performance of the chip.

[0003] Therefore, how to efficiently and accurately measure the overlay error between the current layer pattern and the previous layer pattern has become a technical problem to be solved urgently. Summary of the Invention

[0004] Embodiments of the present disclosure provide a method for measuring overlay error, including: obtaining a first scanned image of a first conductive pattern and a second conductive pattern in a semiconductor structure, where the second conductive pattern is located above the first conductive pattern; determining a first overlay error between the second conductive pattern and the first conductive pattern according to the first scanned image; obtaining a second scanned image of a third conductive pattern and the first conductive pattern in the semiconductor structure, where the third conductive pattern is located above the second conductive pattern; determining a second overlay error between the third conductive pattern and the first conductive pattern according to the second scanned image; and determining a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error.

[0005] In some embodiments, the determining the third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error includes: calculating a difference between the second overlay error and the first overlay error to obtain the third overlay error.

[0006] In some embodiments, the obtaining the first scanned image of the first conductive pattern and the second conductive pattern in the semiconductor structure includes: performing a first measurement on the semiconductor structure formed with the second conductive pattern at a first process station to generate the first scanned image.

[0007] In some embodiments, the obtaining the second scanned image of the third conductive pattern and the first conductive pattern in the semiconductor structure includes: performing a second measurement on the semiconductor structure formed with the third conductive pattern at a second process station after the first process station to generate the second scanned image.

[0008] In some embodiments, the first measurement and the second measurement include high-voltage electron scanning electron microscopy measurement.

[0009] In some embodiments, the measurement method further includes: generating a first measurement result according to that the third overlay error is less than or equal to a preset overlay error, where the first measurement result is used to indicate that the semiconductor structure is allowed to enter the next process site.

[0010] In some embodiments, the measurement method further includes: generating a second measurement result according to that the third overlay error is greater than the preset overlay error, where the second measurement result is used to indicate that the semiconductor structure is prohibited from entering the next process site.

[0011] In some embodiments, the preset overlay error is less than 14.5 nanometers.

[0012] In some embodiments, the first conductive pattern includes a first contact structure, the second conductive pattern includes a metal layer, and the third conductive pattern includes a second contact structure, where the second contact structure, the metal layer, and the first contact structure are connected in sequence from top to bottom, and the first contact structure is connected to the peripheral circuit in the semiconductor structure.

[0013] In some embodiments, the materials of the second conductive pattern and the first conductive pattern are different; the materials of the third conductive pattern and the first conductive pattern are different.

[0014] In the embodiments of the present disclosure, by respectively obtaining a first scan image and a second scan image, the first overlay error between the second conductive pattern and the first conductive pattern and the second overlay error between the third conductive pattern and the first conductive pattern can be measured step by step, and thus the third overlay error between the third conductive pattern and the second conductive pattern can be obtained. In this way, on the one hand, the overlay error between the current layer pattern (i.e., the third conductive pattern) and the previous layer pattern (i.e., the second conductive pattern) can be accurately and efficiently obtained, reducing product defects caused by the overlay error, which is beneficial to improving the product quality and yield; on the other hand, the technical problem that the overlay error between the current layer pattern and the previous layer pattern cannot be directly measured at the current station in some processes is effectively solved, providing an effective measurement means for measuring the overlay error in the semiconductor manufacturing process; on the third hand, it is compatible with the current measurement process and can be realized without adding additional measurement processes, which is beneficial to controlling the production cost; on the fourth hand, the alignment accuracy between each layer can be effectively evaluated, providing detailed and accurate data support for production process optimization. Description of the Drawings

[0015] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in accordance with the present application and should not be regarded as limiting the scope of the present application.

[0016] Figure 1A is a schematic diagram of a semiconductor structure provided by an embodiment; Figure 1B is a scanned image of a semiconductor structure provided by an embodiment; Figure 2 is a flowchart of a method for measuring overlay error provided by an embodiment of the present disclosure; Figure 3A is a schematic diagram of a semiconductor structure formed with a second conductive pattern provided by an embodiment of the present disclosure; Figure 3B is a schematic diagram of a first scanned image provided by an embodiment of the present disclosure; Figure 4A is a schematic diagram of a semiconductor structure formed with a third conductive pattern provided by an embodiment of the present disclosure; Figure 4B is a schematic diagram of a second scanned image provided by an embodiment of the present disclosure; Figure 5 is the measurement result of overlay error and the physical failure analysis result provided by an embodiment of the present disclosure; Figure 6 is the fitting function of the measurement data and the physical failure analysis data provided by an embodiment of the present disclosure. Detailed Description of the Embodiments

[0017] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0018] In the following paragraphs, the present disclosure will be described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will be clearer according to the following description. It should be noted that the drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present disclosure.

[0019] It is to be understood that the meanings of "on", "above", and "over" in this disclosure should be interpreted in the broadest manner, such that "on" not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

[0020] In the embodiments of this disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0021] In the embodiments of this disclosure, the term "layer" refers to a portion of material including a region having a thickness. The layer may extend over the entirety of a lower or upper structure, or may have a scope smaller than the scope of the lower or upper structure. Additionally, the layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of a continuous structure, or the layer may be between any horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along an inclined surface. The layer may include a plurality of sub-layers.

[0022] It should be noted that, without conflict, the technical solutions described in the embodiments of this disclosure can be combined arbitrarily.

[0023] The overlay error after lithography and development is usually measured in the current process (also known as the current process site, abbreviated as the current station). However, in certain specific processes, due to the size and thickness limitations of some patterns, it is impossible to obtain the overlay error between the patterns of the current layer and the previous layer after measurement at the current station, resulting in a lack of effective overlay error detection means in the production line (inline), which affects the quality and yield of the product. The following will be described in conjunction with Figure 1A and Figure 1B for exemplary illustration.

[0024] Figure 1A is a schematic diagram of a semiconductor structure provided by an embodiment, Figure 1B is a scanned image of a semiconductor structure provided by an embodiment.

[0025] Referring to Figure 1A as shown, the semiconductor structure includes a first contact structure 102, a metal layer 104, and a second contact structure 106. The first contact structure 102, the metal layer 104, and the second contact structure 106 may be sequentially formed at different process sites.

[0026] Typically, in the process site where the second contact structure 106 is formed, metrology is required to obtain the overlay error between the second contact structure 106 and the metal layer 104. However, due to the size and thickness limitations of the metal layer 104, for example, the thickness of the metal layer 104 is relatively thin and does not form an image under the scanning lens, resulting in the inability to obtain the overlay error between the second contact structure 106 and the metal layer 104 in the process site where the second contact structure 106 is formed. Furthermore, there is a lack of effective overlay error detection means on the production line, which affects the quality and yield of the product. Here, Figure 1B Only the second contact structure 106 and the first contact structure 102 can be seen in the shown scanning image.

[0027] Based on one or more of the above technical problems, embodiments of the present disclosure provide a method for measuring overlay error.

[0028] Figure 2 It is a flowchart of a method for measuring overlay error provided by embodiments of the present disclosure. Refer to Figure 2 As shown, the measurement method includes: Step S210: Obtain a first scanning image of a first conductive pattern and a second conductive pattern in a semiconductor structure, where the second conductive pattern is located above the first conductive pattern; Step S220: Determine a first overlay error between the second conductive pattern and the first conductive pattern according to the first scanning image; Step S230: Obtain a second scanning image of a third conductive pattern and the first conductive pattern in the semiconductor structure, where the third conductive pattern is located above the second conductive pattern; Step S240: Determine a second overlay error between the third conductive pattern and the first conductive pattern according to the second scanning image; Step S250: Determine a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error.

[0029] In the embodiments of the present disclosure, by separately obtaining a first scanned image and a second scanned image, the first overlay error between the second conductive pattern and the first conductive pattern and the second overlay error between the third conductive pattern and the first conductive pattern can be measured step by step, and thus the third overlay error between the third conductive pattern and the second conductive pattern can be obtained. In this way, on the one hand, the overlay error between the current layer pattern (i.e., the third conductive pattern) and the previous layer pattern (i.e., the second conductive pattern) can be accurately and efficiently obtained, reducing product defects caused by overlay errors, which is beneficial to improving the quality and yield of products; on the other hand, the technical problem that the overlay error between the current layer pattern and the previous layer pattern cannot be directly measured at a certain station in some processes is effectively solved, providing an effective measurement means for measuring the overlay error in the semiconductor manufacturing process; on the third hand, it is compatible with the current measurement process and can be realized without adding additional measurement processes, which is beneficial to controlling production costs; on the fourth hand, the alignment accuracy between each layer can be effectively evaluated, providing detailed and accurate data support for production process optimization.

[0030] Figure 3A FIG. is a schematic diagram of a semiconductor structure formed with a second conductive pattern provided by an embodiment of the present disclosure, Figure 3B FIG. is a schematic diagram of a first scanned image provided by an embodiment of the present disclosure, Figure 4A FIG. is a schematic diagram of a semiconductor structure formed with a third conductive pattern provided by an embodiment of the present disclosure, Figure 4B FIG. is a schematic diagram of a second scanned image provided by an embodiment of the present disclosure. The measurement method of the overlay error provided by the embodiments of the present disclosure will be exemplarily described below in conjunction with Figure 2 , Figure 3A , Figure 3B , Figure 4A and Figure 4B .

[0031] In step S210, as shown in reference to Figure 2 , a first scanned image of the first conductive pattern and the second conductive pattern in the semiconductor structure is obtained, where the second conductive pattern is located above the first conductive pattern.

[0032] A semiconductor structure generally refers to a structure formed on a semiconductor substrate (such as silicon, germanium, etc.) through various semiconductor manufacturing processes. The semiconductor structure can be an intermediate structure at any stage during the manufacturing process.

[0033] In some embodiments, the semiconductor structure may include a single-layer structure. For example, the substrate 300, more specifically, a silicon (Si) substrate, a germanium (Ge) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, a silicon carbide (SiC) substrate, or a gallium nitride (GaN) substrate.

[0034] In some other embodiments, the semiconductor structure may include a multi-layer structure. For example, the semiconductor structure may include a substrate 300, a first conductive pattern, and a second conductive pattern located above the substrate. The present disclosure does not impose any specific limitations on the specific structure and materials of the semiconductor structure. Any structure formed through semiconductor manufacturing processes can be referred to as a semiconductor structure.

[0035] In practical applications, a substrate 300 can be provided, and patterns with specific shapes and sizes can be formed on the substrate through semiconductor manufacturing processes such as ion doping, thin film deposition, lithography, and etching. These patterns can constitute various parts of the semiconductor structure, such as transistors, memory arrays, interconnect lines, etc.

[0036] In some embodiments, referring to Figure 3A as shown, the first conductive pattern includes a first contact structure 302, and the second conductive pattern includes a metal layer 304.

[0037] Referring to Figure 3A as shown, the first contact structure 302 and the metal layer 304 can be sequentially formed on the substrate. The first contact structure 302 is connected to the active region in the substrate, and the metal layer 304 is connected to the first contact structure 302. Here, the active region (e.g., the source or the drain) can be electrically led out through the first contact structure 302 and the metal layer 304.

[0038] It should be noted that the first conductive pattern and the second conductive pattern can be conductive patterns located at different levels in the semiconductor structure. The conductive pattern can be, for example, a contact structure / contact plug (Contact) for connecting a metal layer and an active region, a metal layer / interconnect layer (Metal), an interconnect contact (Via) for connecting two metal layers, and a pad (Pad), etc. The present disclosure does not impose any specific limitations on the types and positions of the first conductive pattern and the second conductive pattern. Any pattern with conductive characteristics in a semiconductor structure can be referred to as a conductive pattern. For the sake of easy understanding, in the following, the first conductive pattern is taken as the first contact structure 302 and the second conductive pattern is taken as the metal layer 304 as an example for illustration.

[0039] The first scanned image refers to an image obtained by using an imaging device such as a scanning electron microscope (SEM), an optical microscope, or other imaging devices. By obtaining the first scanned image, the relative positions of the first conductive pattern and the second conductive pattern, as well as the respective contour shapes of the first conductive pattern and the second conductive pattern, can be displayed.

[0040] In some embodiments, the above step S210 includes: in a first process station, performing a first measurement on the semiconductor structure formed with the second conductive pattern to generate a first scanned image. Here, the first process station can be the current process station where the second conductive pattern is formed, and the first measurement includes high-voltage electron scanning electron microscope measurement.

[0041] Referring to Figure 3A as shown, after forming the metal layer 304, in the current process site where the metal layer 304 is formed, the Figure 3A shown structure can be measured by High Voltage Scanning Electron Microscopy (HV-SEM) to generate a first scanned image 402 as Figure 3B shown. Figure 3B Two first contact structures are shown, namely the first contact structure 302A and the first contact structure 302B; and two corresponding metal layers, namely the metal layer 304A and the metal layer 304B. However, the number of the first contact structures 302 and the number of the metal layers 304 are not limited to Figure 3A and Figure 3B shown.

[0042] It should be noted that the first measurement can also be other measurement techniques capable of obtaining the imaging of the first conductive pattern and the second conductive pattern. Among them, due to the difference in the absorption of secondary electrons and backscattered electrons by different materials, the high-voltage scanning electron microscopy measurement results in different image contrasts and is often used for the measurement of the overlay error (OVL) of different materials.

[0043] In some embodiments, the materials of the second conductive pattern and the first conductive pattern are different. For example, the material of the first conductive pattern includes polysilicon or doped polysilicon, and the material of the second conductive pattern includes tungsten, etc.

[0044] In step S220, referring to Figure 2 as shown, according to the first scanned image, determine the first overlay error between the second conductive pattern and the first conductive pattern. For example, through the relative positions or respective contour shapes of the first conductive pattern and the second conductive pattern in the first scanned image, the first overlay error between the second conductive pattern and the first conductive pattern can be calculated.

[0045] Specifically, the center position of the first conductive pattern can be determined through the imaging of the first conductive pattern in the first scanned image; the center position of the second conductive pattern can be determined through the imaging of the second conductive pattern in the first scanned image; by calculating the position deviation between the center position of the second conductive pattern and the center position of the first conductive pattern, the first overlay error can be obtained.

[0046] Of course, in other embodiments, reference points corresponding to the respective contour shapes of the first conductive pattern and the second conductive pattern in the first scanned image can also be selected to calculate the first overlay error.

[0047] Referring to Figure 3BAs shown, the center positions of the first contact structure 302A, the center position of the first contact structure 302B, the center position of the metal layer 304A, and the center position of the metal layer 304B can be determined respectively; calculate the first position deviation between the center position of the metal layer 304A and the center position of the first contact structure 302A, and calculate the second position deviation between the center position of the metal layer 304B and the center position of the first contact structure 302B; calculate the average value of the first position deviation and the second position deviation, and use the average value of the first position deviation and the second position deviation as the first overlay error between the metal layer 304 and the first contact structure 302.

[0048] Here, when the number of the first contact structures 302 and the metal layers 304 is multiple, the position deviation between each metal layer 304 and the corresponding first contact structure 302 can be calculated to obtain multiple position deviations, and the first overlay error can be obtained by taking the average value of the multiple position deviations.

[0049] In practical applications, the overlay error between two conductive patterns can be determined by scanning the imaging of the two conductive patterns in the image. The overlay error usually includes deviations in two directions, horizontal (e.g., X-axis) and vertical (e.g., Y-axis). The process of determining the overlay error usually involves image processing and analysis, and can include techniques such as edge detection, feature matching, geometric measurement, etc. to ensure the accuracy of the measurement.

[0050] In step S230, refer to Figure 2 As shown, obtain the second scanned image of the third conductive pattern and the first conductive pattern in the semiconductor structure, where the third conductive pattern is located above the second conductive pattern.

[0051] In some embodiments, refer to Figure 4A As shown, the third conductive pattern includes the second contact structure 306.

[0052] Refer to Figure 4A As shown, the second contact structure 306 can be formed on the metal layer 304, and the second contact structure 306 is connected to the metal layer 304. Here, the second contact structure 306, the metal layer 304, and the first contact structure 302 are connected in sequence from top to bottom, and the first contact structure 302 can be connected to the peripheral circuit in the semiconductor structure. For example, the first contact structure 302 is connected to the active region of the transistor in the peripheral circuit.

[0053] Refer to Figure 4A As shown, the semiconductor structure can include a memory array and a peripheral circuit, where the memory array is located in the array region and the peripheral circuit is located in the peripheral region. Here, the first contact structure 302, the metal layer 304, and the second contact structure 306 are all located in the peripheral region.

[0054] It should be noted that the first conductive pattern, the second conductive pattern, and the third conductive pattern may be conductive patterns located at different levels in the semiconductor structure. For example, the first conductive pattern may be a contact structure for connecting the metal layer and the peripheral circuit (abbreviated as the peripheral contact structure (Peripheral Contact, PC)), the second conductive pattern may be the first-level interconnect metal layer (M0), and the third conductive pattern may be a contact structure for connecting the metal layer and the pad (abbreviated as the interconnect contact structure (Contact, CT)). The present disclosure places no special limitations on the types and positions of the first conductive pattern, the second conductive pattern, and the third conductive pattern. For the conductive pattern, reference may be made to the relevant descriptions above.

[0055] The second scanned image refers to an image obtained by using an imaging device such as a scanning electron microscope (SEM), an optical microscope, or others. By obtaining the second scanned image, the relative positions of the first conductive pattern and the third conductive pattern and the respective contour shapes of the first conductive pattern and the third conductive pattern can be displayed. It should be noted that due to the thickness limitation of the second conductive pattern, the second conductive pattern does not form an image under the scanning lens, that is, the second conductive pattern cannot be seen in the second scanned image.

[0056] In some embodiments, the above step S230 includes: in a second process site after the first process site, performing a second measurement on the semiconductor structure formed with the third conductive pattern to generate a second scanned image. Here, the second process site may be the current process site where the third conductive pattern is formed, and the second measurement includes high-voltage electron scanning electron microscope measurement.

[0057] Refer to Figure 4A As shown, after forming the second contact structure 306, in the current process site where the second contact structure 306 is formed, perform Figure 4A high-voltage electron scanning electron microscope measurement on the structure shown in Figure 4B to generate the second scanned image 404 as shown in Figure 4B shows two first contact structures, namely the first contact structure 302A and the first contact structure 302B; and the corresponding two second contact structures, namely the second contact structure 306A and the second contact structure 306B. However, the number of the first contact structures 302 and the number of the second contact structures 306 are not limited to Figure 4A and Figure 4B shown.

[0058] It should be noted that the second measurement may also be other measurement techniques capable of obtaining images of the first conductive pattern and the third conductive pattern. Among them, high-voltage electron scanning electron microscope measurement is often used for measuring the overlay error (OVL) of different materials due to the different absorption of secondary electrons and backscattered electrons by different materials, resulting in different image contrasts.

[0059] In some embodiments, the materials of the third conductive pattern and the first conductive pattern are different. For example, the material of the first conductive pattern includes polysilicon or doped polysilicon, and the material of the third conductive pattern includes tungsten, etc.

[0060] In step S240, with reference to Figure 2 as shown, according to the second scan image, determine the second overlay error between the third conductive pattern and the first conductive pattern. For example, the second overlay error between the third conductive pattern and the first conductive pattern can be calculated through the relative positions or respective contour shapes of the first conductive pattern and the third conductive pattern in the second scan image.

[0061] Specifically, the center position of the first conductive pattern can be determined through the imaging of the first conductive pattern in the second scan image; the center position of the third conductive pattern can be determined through the imaging of the third conductive pattern in the second scan image; by calculating the position deviation between the center position of the third conductive pattern and the center position of the first conductive pattern, the second overlay error can be obtained.

[0062] Of course, in other embodiments, reference points corresponding to the respective contour shapes of the first conductive pattern and the third conductive pattern in the second scan image can also be selected to calculate the second overlay error.

[0063] With reference to Figure 4B as shown, the center positions of the first contact structure 302A, the first contact structure 302B, the second contact structure 306A, and the second contact structure 306B can be determined respectively; calculate the third position deviation between the center position of the second contact structure 306A and the center position of the first contact structure 302A, and calculate the fourth position deviation between the center position of the second contact structure 306B and the center position of the first contact structure 302B; calculate the average value of the third position deviation and the fourth position deviation, and use the average value of the third position deviation and the fourth position deviation as the second overlay error between the second contact structure 306 and the first contact structure 302.

[0064] Here, when the numbers of the first contact structure 302 and the second contact structure 306 are both multiple, the position deviations between each second contact structure 306 and the corresponding first contact structure 302 can be calculated to obtain multiple position deviations, and the second overlay error can be obtained by taking the average value of the multiple position deviations.

[0065] In step S250, a third overlay error between the third conductive pattern and the second conductive pattern is determined based on the second overlay error and the first overlay error. Here, through the second overlay error and the first overlay error, the third overlay error between the third conductive pattern and the second conductive pattern can be indirectly measured, thereby achieving accurate and efficient measurement of the overlay error between the third conductive pattern and the second conductive pattern.

[0066] In some embodiments, the above step S250 includes: calculating the difference between the second overlay error and the first overlay error to obtain the third overlay error.

[0067] In this embodiment, the total positional deviation of the third conductive pattern relative to the first conductive pattern can be the accumulation of the positional deviation of the second conductive pattern relative to the first conductive pattern and the positional deviation of the third conductive pattern relative to the second conductive pattern. By calculating the difference between the second overlay error and the first overlay error, the third overlay error between the third conductive pattern and the second conductive pattern can be accurately obtained. In addition, the measurement of both the first overlay error and the second overlay error is based on the first conductive pattern, that is, the same reference is used, which is beneficial to improving the accuracy of the third overlay error.

[0068] In some embodiments, the above measurement method further includes: generating a first measurement result according to the third overlay error being less than or equal to a preset overlay error, where the first measurement result is used to indicate that the semiconductor structure is allowed to enter the next process station; generating a second measurement result according to the third overlay error being greater than the preset overlay error, where the second measurement result is used to indicate that the semiconductor structure is prohibited from entering the next process station.

[0069] In this embodiment, a corresponding measurement result is generated according to the comparison result between the third overlay error and the preset overlay error. Specifically, when the measured third overlay error is less than or equal to the preset overlay error, this indicates that the alignment accuracy of the current semiconductor structure meets the process requirements. Therefore, a first measurement result is generated, and the current semiconductor structure can enter the next process station for subsequent manufacturing processes. On the contrary, when the measured third overlay error is greater than the preset overlay error, this indicates that the alignment accuracy of the current semiconductor structure does not meet the process requirements. Therefore, a second measurement result is generated, and the current semiconductor structure needs to be reworked or even scrapped in serious cases. The current semiconductor structure should be prohibited from entering the next process station to avoid waste of processes and raw materials.

[0070] It should be noted that the preset overlay error can be a predefined maximum allowable deviation value, which is used to evaluate whether the alignment accuracy in the manufacturing process is within the acceptable range. In this embodiment, the preset overlay error is less than 14.2 nanometers. In practical applications, the preset overlay error can be reasonably set according to design requirements to ensure that the alignment accuracy between each layer of patterns is within the acceptable range. The present disclosure has no special restrictions on this.

[0071] In the semiconductor manufacturing process, it is crucial to ensure the precise alignment between each layer of patterns, as this directly affects the performance and reliability of the final product. In this embodiment, by comparing the magnitude of the third overlay error with the preset overlay error and generating corresponding measurement results, it can be ensured that only semiconductor structures meeting the alignment accuracy requirements can enter the next process station, thereby reducing defects caused by poor alignment and facilitating the improvement of the overall production yield. In addition, when the third overlay error exceeds the preset overlay error, generating the second measurement result in a timely manner and preventing the semiconductor structure from entering the next station can avoid subsequent process steps being carried out on the wrong basis, reducing resource waste and time delays.

[0072] To verify the effectiveness of the measurement method provided in the above embodiment, physical failure analysis (PFA) can be used for verification, which will be further described in conjunction with Figure 5 and Figure 6 as follows.

[0073] Figure 5 FIG. is a schematic diagram of the measurement result of an overlay error and the physical failure analysis result provided by an embodiment of the present disclosure, Figure 6 FIG. is a fitting function of the measurement data and the physical failure analysis data provided by an embodiment of the present disclosure. Among them, Figure 5 in CT_PC_Y in FIG. indicates that the measurement object is the interconnection contact structure CT and the peripheral contact structure PC, SEM represents the HV-SEM scanning images of CT and PC, PFA IMG represents the PFA slice images of CT and PC, PV2E represents the measurement data of the overlay error between CT and PC obtained from the SEM scanning images, and PFA represents the physical failure analysis data of the overlay error between CT and PC obtained from the PFA slice images. In addition, to verify the effectiveness of the measurement method provided in the above embodiment, multiple positions can be selected. For example, Figure 5 FIG. provides 5 positions, and the 5 positions are numbered from (1) to (5).

[0074] Referring to Figure 5 as shown, according to the SEM at positions (1) to (5), the measurement data of the overlay error between the corresponding CT and PC are -11.517 nm, -9.293 nm, 9.672 nm, 10.632 nm, and 0.509 nm respectively; according to the PFA IMG at positions (1) to (5), the physical failure analysis data of the overlay error between the corresponding CT and PC are -16.4 nm, -17.37 nm, 6.4 nm, 13.25 nm, and 0.6 nm respectively.

[0075] Using the above measurement data as the abscissa (i.e., the x-axis) and the physical failure analysis data as the ordinate (i.e., the y-axis), establish the coordinate axes as shown in Figure 6 . According to the measurement data and physical failure analysis data at the above positions (1) to (5), five coordinate points as shown in Figure 6 can be obtained (i.e., the black solid dots in Figure 6 ). Fitting the five coordinate points, a fitting function as shown in Figure 6 can be obtained: y = 1.2995x - 2.7048, where the slope is 1.2995 and the R-squared (R 2 ) is 0.9576.

[0076] Here, the value range of R 2 is from 0 to 1. The closer R 2 is to 1, the higher the degree of coincidence. Therefore, it can be seen from Figure 6 that by comparing the measurement results with the physical failure analysis results, the measurement data and the physical failure analysis data are highly coincident, that is, the measurement method provided in the above embodiment can effectively measure the overlay error between the current layer pattern and the previous layer pattern.

[0077] It should be noted that the overlay error between the interconnection contact structure CT and the first layer of interconnect metal layer M0 is mainly contributed by the overlay error of CT_PC in the CT Etch (CTEH) station. Therefore, Figure 5 the measurement object in

[0078] can be the interconnection contact structure CT and the peripheral contact structure PC. As described above, only the specific embodiments of the present disclosure are provided, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure.

Claims

1. A method for measuring overlay error, characterized in that Including: Obtaining a first scanned image of a first conductive pattern and a second conductive pattern in a semiconductor structure, wherein the second conductive pattern is located above the first conductive pattern; Determining a first overlay error between the second conductive pattern and the first conductive pattern according to the first scanned image; Obtaining a second scanned image of a third conductive pattern and the first conductive pattern in the semiconductor structure, wherein the third conductive pattern is located above the second conductive pattern; Determining a second overlay error between the third conductive pattern and the first conductive pattern according to the second scanned image; Determining a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error.

2. The measurement method of overlay error according to claim 1, characterized in that The determining a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error includes: Calculating a difference between the second overlay error and the first overlay error to obtain the third overlay error.

3. The measurement method of overlay error according to claim 1, characterized in that The obtaining a first scanned image of a first conductive pattern and a second conductive pattern in a semiconductor structure includes: At a first process station, performing a first measurement on the semiconductor structure formed with the second conductive pattern to generate the first scanned image.

4. The measurement method of overlay error according to claim 3, wherein The obtaining a second scanned image of a third conductive pattern and the first conductive pattern in the semiconductor structure includes: At a second process station after the first process station, performing a second measurement on the semiconductor structure formed with the third conductive pattern to generate the second scanned image.

5. The method for measuring overlay error according to claim 4, characterized in that, The first measurement and the second measurement include high-voltage electron scanning electron microscopy measurement.

6. The measurement method of overlay error according to any one of claims 1 to 5, characterized in that, The measurement method further includes: Generating a first measurement result according to the third overlay error being less than or equal to a preset overlay error, wherein the first measurement result is used to indicate that the semiconductor structure is allowed to enter the next process station.

7. The method for measuring overlay error according to claim 6, wherein The measurement method further includes: Generating a second measurement result according to the third overlay error being greater than the preset overlay error, wherein the second measurement result is used to indicate that the semiconductor structure is prohibited from entering the next process station.

8. The measurement method of overlay error according to claim 6, characterized in that, The preset overlay error is less than 14.5 nanometers.

9. The measurement method of overlay error according to claim 1, characterized in that, The first conductive pattern includes a first contact structure, the second conductive pattern includes a metal layer, and the third conductive pattern includes a second contact structure, wherein the second contact structure, the metal layer, and the first contact structure are connected in sequence from top to bottom, and the first contact structure is connected to an external circuit in the semiconductor structure.

10. The method for measuring overlay error according to claim 1, wherein The materials of the second conductive pattern and the first conductive pattern are different; the materials of the third conductive pattern and the first conductive pattern are different.

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