Data processing method, device and equipment of central controller, medium and program product

Abstract

The invention discloses a data processing method, device and equipment of a central controller, a medium and a program product, and relates to the technical field of computers. The method comprises the following steps: firstly, based on communication connection of a first main control chip and a second main control chip, performing data synchronization of the first main control chip and the second main control chip; and performing configuration in advance under the condition of predicting that the first main control chip may have a hardware fault according to the current data and the temperature data of the first main control chip. Therefore, when it is determined that the first main control chip breaks down according to the heartbeat information, all operation tasks of the first main control chip can be rapidly taken over and processed according to the synchronized chip data and the initialized configuration in the second main control chip. Therefore, the normal operation of the system can be ensured, and the operation stability of the system is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a data processing method, apparatus, device, medium, and program product for a central controller. Background Art

[0002] In some systems where multiple devices cooperate and are controlled by a central controller, the central controller serves as the core computing platform in a small-scale deployment environment and is used to handle various control, communication, and data management tasks. For example, in a smart home system, the central controller in the home host is mainly used to coordinate various smart home devices, such as lighting control, ambient temperature adjustment, and security monitoring. This can ensure the efficient and intelligent operation of the smart home system.

[0003] However, as the number of smart devices in the system increases day by day, users' requirements for the stability and reliability of the system also gradually increase. When the central controller works under high intensity for a long time, the probability of hardware failures increases, and system downtime occurs when a hardware failure occurs, reducing the operating security of the system. Summary of the Invention

[0004] In view of the technical problem that in the current system, when the central controller works under high intensity for a long time, the probability of hardware failures increases, reducing the operating security of the system, the present invention is proposed to provide a data processing method, apparatus, device, medium, and program product for a central controller that can overcome or at least partially solve the above problems.

[0005] Based on the first aspect of the present invention, a data processing method for a central controller is provided. The central controller includes a first main control chip and a second main control chip, and the method includes:

[0006] Based on the communication connection between the first main control chip and the second main control chip, data synchronization between the first main control chip and the second main control chip is performed;

[0007] Temperature data and current data at key detection positions of the first main control chip are obtained;

[0008] When it is determined, based on the temperature data and the current data, that the first main control chip meets the status warning condition, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip;

[0009] If the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, the second main control chip takes over the operation tasks of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first main control chip.

[0010] An optional invention content, determining that the first main control chip meets the status warning condition based on the temperature data and current data, includes:

[0011] Input the temperature data and current data into a fault prediction model for identification to determine the fault probability value of the first main control chip;

[0012] When the fault probability value exceeds the set fault threshold, determine that the current operating state of the first main control chip meets the status warning condition.

[0013] An optional invention content, the method further includes a training step of the fault prediction model, and the training step includes:

[0014] Input the current sample features and temperature sample features associated with multiple sample data into a fault prediction model for identification to obtain the fault probability value of the sample main control chip. Among them, the current sample features are obtained by preprocessing the current data at the key detection positions of the sample main control chip, and the temperature sample features are obtained by preprocessing the temperature data at the key detection positions of the sample main control chip;

[0015] Determine the loss function value of the fault prediction model according to the fault probability value and labeled data of each sample data;

[0016] Adjust the model parameters of the fault prediction model according to the loss function value to determine the trained fault prediction model.

[0017] An optional invention content, executing the chip reset strategy of the first main control chip, includes:

[0018] The second main control chip generates a chip reset instruction and sends it to the first main control chip, so that the first main control chip performs chip reset in response to the chip reset instruction;

[0019] If the second main control chip receives the heartbeat information sent by the first main control chip again, determine that the first main control chip reset is successful, and the first main control chip enters the standby state;

[0020] If the second main control chip still does not receive the heartbeat information sent by the first main control chip after timing out, determine that the first main control chip reset fails, and generate a chip fault record of the first main control chip.

[0021] An optional invention content, the method further includes:

[0022] Generate an alarm message based on the chip fault record and upload it to the server, so that the server sends the alarm message to the operation and maintenance mobile terminal for display.

[0023] An optional invention content, wherein the heartbeat information at least includes: a heartbeat flag, chip status information, resource occupancy, task synchronization information, a heartbeat timestamp, and error diagnosis information.

[0024] An optional invention content, whether the second master chip times out without receiving the heartbeat information sent by the first master chip, includes:

[0025] When the second master chip receives the last heartbeat information sent by the first master chip, extract the last heartbeat timestamp of the last heartbeat information;

[0026] If, starting from the last heartbeat timestamp, the second master chip receives the heartbeat information sent by the first master chip within a preset time interval, it is determined that the second master chip has timely received the heartbeat information sent by the first master chip;

[0027] If, starting from the last heartbeat timestamp, the second master chip does not receive the heartbeat information sent by the first master chip within a preset time interval, it is determined that the second master chip times out without receiving the heartbeat information sent by the first master chip.

[0028] An optional invention content, performing data synchronization between the first master chip and the second master chip, includes:

[0029] Screen the chip data in the first master chip to determine the key chip data and non-key chip data other than the key chip data;

[0030] Perform real-time synchronization of the key chip data in the second master chip and perform timed synchronization of the non-key chip data in the second master chip.

[0031] Based on the second aspect of the present invention, there is also provided a data processing device for a central controller. The central controller includes a first master chip and a second master chip. The device includes:

[0032] A data synchronization module for performing data synchronization between the first master chip and the second master chip based on the communication connection between the first master chip and the second master chip;

[0033] A data acquisition module for acquiring temperature data and current data at key detection positions of the first master chip;

[0034] An early warning determination module for, when it is determined that the first master chip meets the status early warning condition based on the temperature data and the current data, the second master chip performs configuration initialization according to the master configuration information of the first master chip;

[0035] A fault response module, which is configured to, if the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, the second main control chip takes over the operation tasks of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first main control chip.

[0036] Based on the third aspect of the present invention, there is also provided an electronic device, including:

[0037] One or more processors;

[0038] A memory;

[0039] One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs are configured to execute any of the methods described in the above invention content.

[0040] Based on the fourth aspect of the present invention, there is also provided a computer-readable storage medium storing a computer program for use in conjunction with an electronic device, wherein the computer program is executable by a processor to complete any of the methods described in the above invention content.

[0041] Based on the fifth aspect of the present invention, there is also provided a computer program product including a computer program / computer-executable instructions, wherein the computer program / computer-executable instructions, when executed by a processor in an electronic device, implement any of the methods described in the above invention content.

[0042] Compared with the prior art, the present invention includes first synchronizing the data of the first main control chip and the second main control chip based on the communication connection between the first main control chip and the second main control chip. Then, the temperature data and current data of the key detection positions of the first main control chip are acquired. And when it is determined that the first main control chip meets the status warning condition according to the temperature data and current data, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip. Finally, if the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, the second main control chip takes over the operation tasks of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first main control chip. Thus, configuration can be pre-performed when it is predicted that the first main control chip may have a hardware failure. Therefore, when it is determined that the first main control chip has failed according to the heartbeat information, all the operation tasks of the first main control chip can be quickly taken over and processed according to the chip data and initialization configuration synchronized in the second main control chip. Thus, the normal operation of the system can be ensured, and the operation stability of the system is greatly improved.

[0043] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are given below. Brief Description of the Drawings

[0044] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components.

[0045] In the drawings:

[0046] Figure 1 is a schematic flow chart of the steps of a data processing method of a central controller provided by an embodiment of the present invention;

[0047] Figure 2 is a schematic flow chart of the steps of another data processing method of a central controller provided by an embodiment of the present invention;

[0048] Figure 3 is a schematic flow chart of the training steps of a fault prediction model provided by an embodiment of the present invention;

[0049] Figure 4 is a schematic structural diagram of a data processing device of a central controller provided by an embodiment of the present invention. Detailed Description of the Embodiments

[0050] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be fully conveyed to those skilled in the art.

[0051] In some systems where multiple devices cooperate and work under the control of a central controller, the central controller, as the core computing platform in a small-scale deployment environment, is used to handle various control, communication, and data management tasks. For example, in a smart home system, the central controller in the home host is mainly used to coordinate various smart home devices, such as lighting control, ambient temperature adjustment, and security monitoring. Thus, it can ensure that the smart home system operates efficiently and intelligently.

[0052] However, as the number of smart devices in the system increases day by day, users' requirements for the stability and reliability of the system also gradually increase. When the central controller works under high intensity for a long time, the probability of hardware failures increases, and when a hardware failure occurs, it will cause the system to shut down, reducing the operating safety of the system.

[0053] Based on the above technical problems, the embodiments of the present invention are proposed. The embodiments of the present invention can first perform data synchronization between the first main control chip and the second main control chip based on the communication connection between the first main control chip and the second main control chip. Then, temperature data and current data at the key detection positions of the first main control chip are obtained. And when it is determined, based on the temperature data and the current data, that the first main control chip meets the status warning condition, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip. Finally, if the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, the second main control chip takes over the running tasks of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first main control chip. Thus, pre-configuration can be performed when it is predicted that the first main control chip may have a hardware failure. Therefore, when it is determined that the first main control chip has failed based on the heartbeat information, all the running tasks of the first main control chip can be quickly taken over and processed according to the chip data and the initialization configuration synchronized in the second main control chip. Thus, the normal operation of the system can be ensured, and the operating stability of the system is greatly improved.

[0054] In an embodiment of the present invention, the central controller can be applied to an integrated system that requires intelligent control of multiple devices. For example, it can be applied to integrated systems in the fields of smart home, industrial automation, medical care, communication technology, etc. For example, the central controller can be a home host in a smart home system for centralized control of multiple smart home devices. For another example, the central controller can be the main controller in an industrial automation control system for collaborative control of multiple industrial devices or multiple industrial robots. For yet another example, the central controller can be the main controller in a smart medical system for centralized control of multiple medical devices (such as monitors, ventilators, etc.).

[0055] Referring to Figure 1 , a data processing method of a central controller provided by an embodiment of the present invention is shown, and the method may include:

[0056] S101. Based on the communication connection between the first main control chip and the second main control chip, perform data synchronization between the first main control chip and the second main control chip.

[0057] In an embodiment of the present invention, the central controller can be understood as a controller for centrally managing and coordinating the operation of multiple subsystems or devices. At least two main control chips are provided in the central controller, namely a first main control chip and a second main control chip. The first main control chip is mainly responsible for processing all current task processes of the system. The second main control chip is mainly used to perform data synchronization on the chip data in the first main control chip. For example, the data synchronization method can be mirror backup (that is, making a complete and accurate copy of the chip data).

[0058] In some embodiments, a communication connection can be established between the first main control chip and the second main control chip through a dedicated hardware channel and / or through an advanced data synchronization protocol. Among them, the dedicated hardware channel can be understood as directly performing data transmission and synchronization between the first main control chip and the second main control chip through a dedicated physical connection. The dedicated physical connection can include but is not limited to high-speed serial interface lines and dedicated buses, etc. The dedicated hardware channel can provide characteristics of high bandwidth and low latency, and can ensure the data transmission efficiency.

[0059] In some other embodiments, the advanced data synchronization protocol refers to a series of rules and agreements used to ensure real-time, accurate, and efficient transmission and update of data between different systems, devices, or application programs in a network environment. It can include but is not limited to the high-level data link control protocol, synchronous optical network / synchronous digital hierarchy protocol, etc. The communication connection established between the first main control chip and the second main control chip through the advanced data synchronization protocol can ensure the consistency of data synchronization through a handshake and confirmation mechanism, and has good fault tolerance.

[0060] In some preferred embodiments, a communication connection can be jointly established between the first main control chip and the second main control chip through a dedicated hardware channel and an advanced data synchronization protocol, so that while ensuring the consistency and reliability of data synchronization, the data transmission efficiency can be greatly improved.

[0061] In the above embodiments, step S101 can be executed by the first main control chip or by the second main control, and no further limitation is made here.

[0062] S102. Obtain the temperature data and current data of the key detection positions of the first main control chip.

[0063] In the embodiments of the present invention, the key detection positions can be understood as the positions where the first main control chip is likely to generate relatively high heat during operation. For example, the key detection positions can include, but are not limited to, a central processing unit (CPU), a power management module, a cache area, an input / output interface, a voltage regulator, and a storage unit, etc. For example, the central processing unit generates relatively high heat during operation. Those skilled in the art can determine the key detection positions according to the positions where the specific first main control chip is likely to generate heat, and no specific limitation is made on the key detection positions here. The temperature data is detected by a temperature sensor installed at the key detection position, and the current data is detected by a current sensor installed at the key detection position.

[0064] In the above embodiments, step S102 can be executed by the first main control chip or by the second main control, and no further limitation is made here.

[0065] S103. When it is determined according to the temperature data and current data that the first main control chip meets the status warning conditions, the second main control chip executes configuration initialization according to the main control configuration information of the first main control chip.

[0066] In the embodiments of the present invention, the temperature data and current data at different key detection positions can be used to characterize the operating state of the first main control chip. For example, it can be determined whether the first main control chip is overheated through the temperature data. For another example, it can be determined whether the second main control chip is overloaded through the current data.

[0067] The status warning conditions refer to the relevant conditions for determining that the first main control chip is likely to fail if it continues to operate according to the current operating state. For example, the status warning conditions can be comprehensively determined based on the temperature data and current data.

[0068] When it is determined that the first master chip meets the status warning conditions and it is determined that the first master chip will probably have a hardware failure when continuing to operate according to the current operating status. The master configuration information can be understood as the configuration information of the first master chip as the control chip of the system when it is not actually processing tasks. Thus, the second master chip performs configuration initialization according to the master configuration information of the first master chip, so that the driver program and the configuration of relevant parameters can be loaded. For example, the configuration initialization may include initializing variables and data structures, allocating memory space, loading configuration files and resources, etc. Thus, the task running environment of the second master chip can be made consistent with the task running environment of the first master chip in the idle state. After the second master chip performs configuration initialization, it remains in the idle state and does not process any tasks.

[0069] In step S103 of the above embodiment, the method steps for determining whether the first master chip meets the status warning conditions may be executed by the first master chip or by the second master, which is not limited here.

[0070] S104. If the second master chip does not receive the heartbeat information sent by the first master chip within the timeout period, the second master chip takes over the running tasks of the first master chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first master chip.

[0071] In the embodiment of the present invention, between the first master chip and the second master chip, the current operating status of each other can be detected by periodically sending heartbeat information. For example, if the second master chip does not receive the heartbeat information sent by the first master chip within the timeout period, it is determined that the first master chip has failed and the operating status is abnormal.

[0072] Thus, when the second master chip does not receive the heartbeat information sent by the first master chip within the timeout period, it is determined that the first master chip has failed. The last heartbeat information refers to the heartbeat information finally received by the second master chip, which may include the relevant status information before the first master chip fails.

[0073] At this time, the second master chip can quickly take over the running tasks that the first master chip was processing before the failure according to the synchronized chip data and the last heartbeat information, so that the unfinished running tasks can be processed by the second master chip on behalf of. And the chip reset strategy of the first master chip can be executed to eliminate the failure of the first master chip. Thus, the normal operation of the system can be ensured, and the operation stability of the system is greatly improved.

[0074] Reference Figure 2 , which shows another data processing method of a central controller provided by an embodiment of the present invention. The method may include:

[0075] S201. Based on the communication connection between the first main control chip and the second main control chip, perform data synchronization between the first main control chip and the second main control chip.

[0076] In the embodiment of the present invention, the description content of step S201 refers to the description content of the above step S101. The difference from the above embodiment of the invention is that when performing data synchronization between the first main control chip and the second main control chip, the chip data in the first main control chip can also be screened to determine key chip data and non-key chip data other than the key chip data. Among them, the key chip data can be understood as the necessary data required for the first main control chip to process and run tasks. For example, user setting data, system status data, etc. The non-key chip data can be understood as data that is not necessary for the first main control chip to process and run tasks. For example, log records and temporary files, etc.

[0077] Therefore, different synchronization priorities can be set according to the importance degree of the chip data affecting the chip operation. In some embodiments, real-time synchronization of the key chip data is performed in the second main control chip, and timed synchronization of the non-key chip data is performed in the second main control chip. The real-time synchronization of the key chip data can ensure that the second main control chip can quickly and without exception continue to process the unfinished running tasks when the first main control chip fails. The timed synchronization of the non-key chip data can ensure the consistency of the chip data in the second main control chip and the chip data in the first main control chip, and on the basis of facilitating the user to query or call the non-key chip data after the first main control chip fails, at the same time, the resource occupation of the two main control chips can be reduced through timed synchronization, and the system overhead can be reduced.

[0078] S202. Obtain the temperature data and current data at the key detection positions of the first main control chip.

[0079] In the embodiments of the present invention, the key detection position can be understood as the position where the first main control chip is likely to generate relatively high heat during operation. For example, the key detection position may include, but is not limited to, a central processing unit, a power management module, a cache area, an input / output interface, a voltage regulator, and a storage unit, etc. For example, the central processing unit generates relatively high heat during operation. Those skilled in the art can determine the key detection position according to the positions where the specific first main control chip is likely to generate heat, and no specific limitation is imposed on the key detection position herein. The temperature data is detected by a temperature sensor installed at the key detection position, and the current data is detected by a current sensor installed at the key detection position.

[0080] S203. Input the temperature data and the current data into a fault prediction model for identification to determine the fault probability value of the first main control chip.

[0081] In the embodiments of the present invention, the fault prediction type refers to the probability of predicting a hardware fault of the first main control chip. It can be a Convolutional Neural Network (CNN). Inputting the temperature data and the current data into the fault prediction model for identification can obtain the fault probability value of the first main control chip.

[0082] In some embodiments, the obtained temperature data and current data can be preprocessed, and the preprocessed temperature data and current data are then input into the fault prediction model, thereby improving the identification accuracy of the fault prediction model. The preprocessing may include data screening, normalization processing, data formatting, etc.

[0083] In some optional embodiments of the present invention, the method further includes a training step of the fault prediction model, and the training step includes:

[0084] SZ31. Input the current sample features and temperature sample features associated with multiple sample data into a fault prediction model for identification to obtain the fault probability value of the sample main control chip, where the current sample features are obtained by preprocessing the current data at the key detection positions of the sample main control chip, and the temperature sample features are obtained by preprocessing the temperature data at the key detection positions of the sample main control chip.

[0085] In an embodiment of the present invention, multiple pieces of sample data, including all hardware fault types for a sample main control chip, can be pre-collected. The sample main control chip has the same structure as the first main control chip. For example, hardware fault types may include, but are not limited to, overheating, current anomalies, hardware aging, transient faults, and overload faults. For example, an overheating fault manifests as a rapid increase in the temperature of a key detection location within a short period of time or exceeding a critical temperature value. Overheating may cause performance degradation or even permanent damage to the first main control chip.

[0086] For another example, the current anomaly is manifested as a rapid increase or decrease in the rate of change of the current at the key detection position in a short period of time, which is used to characterize the presence of a short circuit, open circuit or other electrical fault in the detection circuit. For another example, hardware aging is manifested as the current at the key detection position gradually decreasing over a long period of time (the resistance value gradually increases), or the temperature gradually increasing, etc. Hardware aging will cause the performance of the first main control chip to gradually decline. For another example, a transient fault is manifested as a transient fluctuation in temperature and / or current at the key detection position, such as a transient voltage spike and electromagnetic interference, etc. Transient faults may cause the first main control chip to temporarily fail to function. For another example, an overload fault is manifested as an excessively high temperature or current at the key detection position. An overload fault indicates that the first main control chip is bearing a workload that exceeds its design specifications, which can easily cause damage to the first main control chip.

[0087] Thus, the fault prediction model can be trained based on the multiple sample data items of different hardware faults. For example, the multiple sample data items of different hardware faults can be pre-divided into training set samples and test set samples. For example, the number of sample data items in the training set samples accounts for 70% of the total number of sample items, and the number of sample data items in the test set samples accounts for 30% of the total number of sample items.

[0088] Each piece of sample data is preprocessed. For example, preprocessing may include data screening, normalization, and data formatting. For example, outliers, missing values, and noise data can be removed from the temperature and current data. Normalization can convert the temperature and current data to the same dimension to facilitate identification of the fault prediction model. For example, methods such as minimum-maximum normalization and Z-score normalization can be used for normalization. Data that can be used to determine chip hardware faults is also screened out, such as the temperature and current change rates, the maximum and minimum temperature and current values, and the temperature and current standard deviations.

[0089] Perform data conversion on the preprocessed sample data. For example, convert the preprocessed current data and temperature data with time series into a feature format suitable for input to the fault prediction model. For example, each current sample feature may include normalized current values at N time points, and each temperature sample feature may include normalized temperature values at N time points. Thus, the sample data input into the fault prediction model can be an N*2 matrix. For example, N can be 80, 100, or 120.

[0090] Thus, input the current sample feature and temperature sample feature associated with each sample data into the fault prediction model for identification to obtain the fault probability value of the sample main control chip.

[0091] SZ32. Determine the loss function value of the fault prediction model based on the fault probability values and labeled data of each sample data.

[0092] SZ33. Adjust the model parameters of the fault prediction model according to the loss function value to determine the trained fault prediction model.

[0093] In the embodiment of the present invention, the labeled data can be the operation result labeled by the user based on the actual hardware fault occurrence situation of the chip corresponding to each sample data. Thus, the loss function value of the fault prediction model can be determined according to the fault probability value and labeled data of the sample data.

[0094] Then, adjust the model parameters of the fault prediction model according to the loss function value. After adjusting the model parameters, repeat the above steps, input the second sample data into the fault prediction model after parameter adjustment to obtain the corresponding fault probability value, and continue to adjust the parameters. Until after 70% of the sample data in the training sample set and 30% of the sample data in the test sample set are identified, the decrease in the loss function value is very small, for example, within 1‰, it can be determined that the loss function value is constrained to the minimum value, and thus stop the model training of the commodity detection model to obtain the trained commodity detection model.

[0095] S204. Determine whether the fault probability value exceeds the set fault threshold.

[0096] In an embodiment of the present invention, the failure probability value is a value ranging from 0 to 1, which is used to characterize the likelihood of a hardware failure occurring in the chip. In other words, the larger the failure probability value, the closer the current chip is determined to be to the failure state. Thus, a set failure threshold can be preset. For example, the set failure threshold can be set to values such as 0.7, 0.8, or 0.9. The set failure threshold is used to characterize the critical value at which the first main control chip is likely to have a hardware failure in a future time period. If the failure probability value is greater than the set failure threshold, the following step S205 is executed. If the failure probability value is less than the set failure threshold, it is determined that the current and temperature of the key detection position of the first main control chip are within the normal range and no hardware failure will occur, and thus the above step S202 can be executed.

[0097] S205. Determine that the current operating state of the first main control chip meets the state warning condition, and the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip.

[0098] In an embodiment of the present invention, the state warning condition refers to the relevant conditions for determining that the first main control chip is likely to have a failure if it continues to operate according to the current operating state. It may at least include: the failure probability value determined based on the current data and temperature data exceeds the set failure threshold.

[0099] The main control configuration information can be understood as the configuration information of the first main control chip as the control chip of the system when it is not actually processing tasks. Thus, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip, so as to load the driver program and the configuration of relevant parameters. For example, the configuration initialization may include initializing variables and data structures, allocating memory space, loading configuration files and resources, etc. Thus, the task operating environment of the second main control chip can be made consistent with the task operating environment of the first main control chip in the idle state. After the second main control chip performs configuration initialization, it remains in the idle state and does not process any tasks.

[0100] S206. Whether the second main control chip has not received the heartbeat information sent by the first main control chip after a timeout.

[0101] In the embodiments of the present invention, between the first main control chip and the second main control chip, the current operating state of each other can be detected by regularly sending heartbeat information. For example, if the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, it is determined that the first main control chip has failed and the operating state is abnormal, and the following step S207 is executed. If the second main control chip timely receives the heartbeat information sent by the first main control chip, it is determined that the first main control chip is operating normally, and the steps of S206 are repeated regularly.

[0102] In some embodiments, the heartbeat information at least includes: a heartbeat flag, chip status information, resource occupancy, task synchronization information, a heartbeat timestamp, and error diagnosis information. On the one hand, the heartbeat information can be used to detect whether the first main control chip is operating normally. On the other hand, the relevant status information of the first main control chip can also be transmitted to the second main control chip through the heartbeat information, so as to help the second main control chip take over and process the running tasks interrupted by the failure of the first main control chip more quickly and accurately.

[0103] The heartbeat flag is a flag bit used to indicate that the first main control chip is operating normally. The chip status information may include a task queue, task execution status, and cache content included in the first main control chip, and is used to characterize the basic status information of the first main control chip. The resource occupancy may include the memory currently used by the first main control chip, the utilization rate of the central processing unit, the input / output port status, etc. The task synchronization information includes the list of tasks being executed and the task progress in the first main control chip. For example, it may include task identifiers, task priorities, task dependencies, etc. The heartbeat timestamp refers to the moment when the first main control chip sends the heartbeat information, and the second main control chip can determine the timeliness of the heartbeat timestamp through the heartbeat timestamp to avoid receiving expired heartbeat information. The error diagnosis information refers to the error code or diagnosis information detected by the first main control chip.

[0104] In an alternative embodiment of the invention, whether the second main control chip times out without receiving the heartbeat information sent by the first main control chip includes:

[0105] When the second main control chip receives the last heartbeat information sent by the first main control chip, the last heartbeat timestamp of the last heartbeat information is extracted.

[0106] If the second main control chip receives the heartbeat information sent by the first main control chip within a preset time interval starting from the last heartbeat timestamp, it is determined that the second main control chip timely receives the heartbeat information sent by the first main control chip.

[0107] If, starting from the last heartbeat timestamp, the second master chip does not receive the heartbeat information sent by the first master chip within a preset duration, it is determined that the second master chip has timed out and not received the heartbeat information sent by the first master chip.

[0108] In an embodiment of the present invention, the last heartbeat information refers to the heartbeat information last received by the second master chip, which includes relevant status information before the first master chip fails.

[0109] After the second master chip receives the heartbeat information each time, it extracts the heartbeat timestamp in the heartbeat information. For example, after extracting the last heartbeat timestamp, starting from the sending time / receiving time of the last heartbeat timestamp, if the second master chip receives new heartbeat information within a preset duration, it is determined that the second master chip has timely received the heartbeat information sent by the first master chip, and it is determined that the first master chip is currently operating normally.

[0110] Starting from the sending time / receiving time of the last heartbeat timestamp, if the second master chip does not receive new heartbeat information within a preset duration, it is determined that the second master chip has timed out and not received the heartbeat information sent by the first master chip, and it is determined that the first master chip has failed. The preset duration can be determined by those skilled in the art according to the normal reception time interval of the two heartbeat information. For example, if the heartbeat information is sent every 3S, the corresponding preset duration can be 10S, etc., and no more limitations are made here.

[0111] S207. The second master chip takes over the operation task of the first master chip and executes the chip reset policy of the first master chip according to the synchronized chip data and the last heartbeat information.

[0112] In the embodiment of the present invention, when it is determined that the first main control chip fails, the second main control chip can quickly take over the running tasks being processed by the first main control chip before the failure according to the synchronized chip data and the last heartbeat information, so that the uncompleted running tasks can be processed by the second main control chip on behalf of the first main control chip. For example, files or data can be called more quickly through the synchronized chip data. The hardware resources in the second main control chip can be quickly allocated according to the resource occupancy in the last heartbeat information. For example, the second main control chip can also understand the current task status of the first main control chip according to the chip status information in the last heartbeat information, which helps the second main control chip seamlessly take over the running tasks interrupted by the failure of the first main control chip. The error diagnosis information in the last heartbeat information can also help the second main control chip to more quickly determine the fault problem in the first main control chip and can timely match the associated relief measures. And the chip reset strategy of the first main control chip can be executed to eliminate the faults of the first main control chip.

[0113] Moreover, by analyzing the temperature data and current data, potential hardware faults of the first main control chip can be found, and multi-layer preventive measures such as data synchronization through the second main control chip, pre-configuring the operating environment, and timely synchronizing the chip status through heartbeat information can be taken to reduce task processing interruptions or delays that may occur during the chip switching process. When the first main control chip fails, quickly and accurately take over the running tasks interrupted by the first main control chip. Thus, the normal operation of the system can be ensured, and the operation stability of the system is greatly improved.

[0114] The chip reset strategy refers to the relevant strategy for eliminating the first main control chip. Executing the chip reset strategy of the first main control chip includes: the second main control chip generates a chip reset instruction and sends it to the first main control chip, so that the reset mechanism of the first main control chip can be triggered by the chip reset instruction. Thus, the first main control chip responds to the chip reset instruction to perform chip reset. If the second main control chip receives the heartbeat information sent by the first main control chip again within a preset time period after sending the chip reset instruction, it is determined that the chip reset of the first main control chip is successful, and the first main control chip enters the standby state. The first main control chip entering the standby state can also be understood as a functional conversion between the two main control chips. The first main control chip in the standby state serves as the updated second main control chip and plays a role in data backup. The second main control chip that is processing the running tasks serves as the updated first main control chip and is responsible for processing all the current task processes of the system.

[0115] The second main control chip has the same structure as the first main control chip, and a temperature sensor and a current sensor are respectively arranged at the key detection positions of the second main control chip.

[0116] If the second main control chip still fails to receive the heartbeat information sent by the first main control chip after a timeout, it is determined that the first main control chip still fails to be reset through software reset. The second main control chip generates a chip fault record of the first main control chip.

[0117] In an optional embodiment of the invention, the method may further include generating an alarm message according to the chip fault record and uploading it to the server, so that the server can send the alarm message to the operation and maintenance mobile terminal for display. For example, the server calls the SMS (Short Message Service Gateway Service) gateway service through the API (Application Programming Interface) to send a text message to the operation and maintenance mobile terminal of the operation and maintenance personnel for display, reminding the operation and maintenance personnel that the main control chip has a fault.

[0118] In an optional embodiment of the invention, the first main control chip may also regularly upload key data to the cloud server for backup, so as to ensure the security and recoverability of the data when both main control chips in the central controller fail at the same time. When backing up the data to the cloud server, the cloud server can compress the backup data to reduce the storage space occupied by the cloud server. The main control chip can encrypt the backup data in an encrypted manner and then upload it to ensure the security of data transmission and storage. When the cloud server detects that both main control chips have failed, it can automatically download the backup data from the cloud server to the main control chip to restore the data and ensure the rapid recovery of the system.

[0119] In summary, the embodiments of the present invention disclose a data processing method for a central controller. The method may include first performing data synchronization between the first main control chip and the second main control chip based on the communication connection between the first main control chip and the second main control chip. Then, temperature data and current data of key detection positions of the first main control chip are acquired. And when it is determined that the first main control chip meets the status warning condition according to the temperature data and the current data, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip. Finally, if the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, the second main control chip takes over the operation tasks of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset policy of the first main control chip. Thus, configuration can be pre-performed when it is predicted that the first main control chip may have a hardware failure. Therefore, when it is determined that the first main control chip fails according to the heartbeat information, all the operation tasks of the first main control chip can be quickly taken over and processed according to the chip data and the initialization configuration synchronized in the second main control chip. Thus, the normal operation of the system can be ensured, the operation stability of the system can be greatly improved, and the user experience can be greatly improved.

[0120] For example, when one of the main control chips fails, the system integrated in the central controller can still operate normally, thereby reducing the downtime of the system due to failures. The automatic switching and reset functions of the two main control chips can reduce the maintenance requirements of the operation and maintenance personnel, and reduce the maintenance cost and maintenance time of the system.

[0121] It should be noted that, for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present application are not limited by the described action sequence, because according to the embodiments of the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present application.

[0122] Referring to Figure 4 , a data processing device for a central controller provided by an embodiment of the present invention is shown. The central controller includes a first main control chip and a second main control chip. The device includes:

[0123] A data synchronization module 401, configured to perform data synchronization between the first main control chip and the second main control chip based on the communication connection between the first main control chip and the second main control chip.

[0124] The data acquisition module 402 is configured to acquire the temperature data and current data of the key detection positions of the first main control chip.

[0125] The warning determination module 403 is configured to, when it is determined that the first main control chip meets the status warning condition based on the temperature data and the current data, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip.

[0126] The fault response module 404 is configured to, if the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, the second main control chip takes over the operation task of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first main control chip.

[0127] In an optional inventive embodiment, the warning determination module 403 includes:

[0128] The fault value determination sub-module is configured to input the temperature data and the current data into a fault prediction model for identification, and determine the fault probability value of the first main control chip.

[0129] The warning determination sub-module is configured to determine that the current operating state of the first main control chip meets the status warning condition when the fault probability value exceeds the set fault threshold.

[0130] In an optional inventive embodiment, the device may further include a training module for the fault prediction model, and the training module may be configured to:

[0131] Input the current sample features and temperature sample features associated with multiple sample data into the fault prediction model for identification respectively, to obtain the fault probability value of the sample main control chip, where the current sample features are obtained by preprocessing the current data of the key detection positions of the sample main control chip, and the temperature sample features are obtained by preprocessing the temperature data of the key detection positions of the sample main control chip.

[0132] Determine the loss function value of the fault prediction model according to the fault probability value and the labeled data of each sample data.

[0133] Adjust the parameters of the fault prediction model according to the loss function value, and determine the trained fault prediction model.

[0134] In an optional inventive embodiment, the fault response module 404 may include:

[0135] A reset instruction generation sub-module is used to generate a chip reset instruction for the second master chip and send it to the first master chip, so that the first master chip performs chip reset in response to the chip reset instruction.

[0136] A heartbeat information receiving sub-module is used to determine that the first master chip has been reset successfully and the first master chip enters the standby state if the second master chip receives the heartbeat information sent by the first master chip again.

[0137] The heartbeat information receiving sub-module is further used to determine that the first master chip reset fails and generate a chip fault record of the first master chip if the second master chip still has not received the heartbeat information sent by the first master chip after a timeout.

[0138] In an optional embodiment of the invention, the device may further include a fault record module, and the fault record module is used for:

[0139] Generating an alarm message based on the chip fault record and uploading it to the server, so that the server distributes the alarm message to the operation and maintenance mobile terminal for display.

[0140] In an optional embodiment of the invention, the heartbeat information at least includes: a heartbeat flag, chip status information, resource occupancy, task synchronization information, a heartbeat timestamp, and error diagnosis information.

[0141] In an optional embodiment of the invention, the fault response module 404 may further include:

[0142] A time extraction sub-module is used to extract the last heartbeat timestamp of the last heartbeat information when the second master chip receives the last heartbeat information sent by the first master chip.

[0143] The heartbeat information receiving sub-module is further used to determine that the second master chip has received the heartbeat information sent by the first master chip in a timely manner if the second master chip receives the heartbeat information sent by the first master chip within a preset time interval starting from the last heartbeat timestamp.

[0144] The heartbeat information receiving sub-module is further used to determine that the second master chip has not received the heartbeat information sent by the first master chip in a timely manner if the second master chip has not received the heartbeat information sent by the first master chip within a preset time interval starting from the last heartbeat timestamp.

[0145] In an optional embodiment of the invention, the data synchronization module 401 may further include:

[0146] A data screening sub-module, configured to screen the chip data in the first main control chip to determine key chip data and non-key chip data other than the key chip data.

[0147] A data synchronization sub-module, configured to perform real-time synchronization of the key chip data in the second main control chip and perform timed synchronization of the non-key chip data in the second main control chip.

[0148] In summary, the embodiment of the present invention discloses a data processing device for a central controller. The device may first perform data synchronization between the first main control chip and the second main control chip based on the communication connection between the first main control chip and the second main control chip. Then, temperature data and current data at key detection positions of the first main control chip are acquired. And when it is determined, based on the temperature data and the current data, that the first main control chip meets the status warning condition, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip. Finally, if the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, the second main control chip takes over the running tasks of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first main control chip. Thus, pre-configuration can be performed when it is predicted that the first main control chip may have a hardware failure. Therefore, when it is determined that the first main control chip fails according to the heartbeat information, all running tasks of the first main control chip can be quickly taken over and processed according to the chip data and the initialization configuration already synchronized in the second main control chip. Thereby, the normal operation of the system can be ensured, and the operation stability of the system is greatly improved.

[0149] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0150] It is easy for those skilled in the art to think that any combination application of the above-mentioned embodiments is feasible. Therefore, any combination of the above-mentioned embodiments is an implementation scheme of the present invention. However, due to space limitations, this specification does not elaborate on each of them here.

[0151] In the specification provided here, a large number of specific details are described. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0152] Similarly, it should be understood that, in order to streamline the present invention and assist in understanding one or more of the various inventive aspects, in the foregoing description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected by the claims, the inventive aspects lie in less than all of the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description hereby expressly incorporate the detailed description, where each claim itself serves as a separate embodiment of the present invention.

[0153] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and disposed in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0154] An electronic device, comprising:

[0155] One or more processors;

[0156] A memory;

[0157] One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to execute the method described in the foregoing embodiments.

[0158] A computer-readable storage medium storing a computer program for use in conjunction with an electronic device, the computer program being executable by a processor to complete the method described in the foregoing embodiments.

[0159] A computer program product comprising a computer program / computer-executable instructions, which when executed by a processor in an electronic device implement the method described in any one of the foregoing inventive embodiments.

[0160] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, an apparatus, or a computer program product. Therefore, the embodiments of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0161] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks or combinations of blocks.

[0162] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1 one or more of the flows Figure 1 or blocks or combinations of blocks.

[0163] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, such that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks or combinations of blocks.

[0164] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0165] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising said element.

[0166] The above has introduced in detail a data processing method and a data processing device of a central controller provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A data processing method for a central controller, characterized in that The central controller includes a first main control chip and a second main control chip, and the method includes: Based on the communication connection between the first main control chip and the second main control chip, perform data synchronization between the first main control chip and the second main control chip; Obtain the temperature data and current data of the key detection positions of the first main control chip; When it is determined that the first main control chip meets the status warning condition according to the temperature data and current data, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip; If the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period, the second main control chip takes over the operation task of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first main control chip.

2. The data processing method of the central controller according to claim 1, wherein The determining that the first main control chip meets the status warning condition according to the temperature data and current data includes: Input the temperature data and current data into a fault prediction model for identification to determine the fault probability value of the first main control chip; When the fault probability value exceeds the set fault threshold, it is determined that the current operating state of the first main control chip meets the status warning condition.

3. The data processing method of the central controller according to claim 2, wherein The method further includes a training step of the fault prediction model, and the training step includes: Input the current sample features and temperature sample features associated with multiple sample data into the fault prediction model for identification to obtain the fault probability value of the sample main control chip. Among them, the current sample features are obtained by preprocessing the current data of the key detection positions of the sample main control chip, and the temperature sample features are obtained by preprocessing the temperature data of the key detection positions of the sample main control chip; Determine the loss function value of the fault prediction model according to the fault probability value and the labeled data of each sample data; Adjust the parameters of the fault prediction model according to the loss function value to determine the trained fault prediction model.

4. The data processing method of the central controller according to claim 1, wherein The executing the chip reset strategy of the first main control chip includes: The second main control chip generates a chip reset instruction and sends it to the first main control chip, so that the first main control chip performs chip reset in response to the chip reset instruction; If the second main control chip receives the heartbeat information sent by the first main control chip again, it is determined that the first main control chip reset is successful, and the first main control chip enters the standby state; If the second main control chip still does not receive the heartbeat information sent by the first main control chip within the timeout period, it is determined that the first main control chip reset fails, and a chip fault record of the first main control chip is generated.

5. The data processing method of the central controller according to claim 4, characterized in that, The method further includes: Generate an alarm information according to the chip fault record and upload it to the server, so that the server issues the alarm information to the operation and maintenance mobile terminal for display.

6. The data processing method of the central controller according to claim 1, wherein The heartbeat information at least includes: heartbeat flag, chip status information, resource occupancy, task synchronization information, heartbeat timestamp, and error diagnosis information.

7. The data processing method of the central controller according to claim 6, characterized in that, Whether the second main control chip does not receive the heartbeat information sent by the first main control chip within the timeout period includes: When the second main control chip receives the last heartbeat information sent by the first main control chip, it extracts the last heartbeat timestamp of the last heartbeat information; If the second main control chip receives the heartbeat information sent by the first main control chip within a preset time interval starting from the last heartbeat timestamp, it is determined that the second main control chip has received the heartbeat information sent by the first main control chip in a timely manner; If the second main control chip does not receive the heartbeat information sent by the first main control chip within a preset time interval starting from the last heartbeat timestamp, it is determined that the second main control chip has timed out and not received the heartbeat information sent by the first main control chip.

8. The data processing method of the central controller according to claim 1, characterized in that Performing data synchronization between the first main control chip and the second main control chip includes: Screening the chip data in the first main control chip to determine the key chip data and the non-key chip data other than the key chip data; Performing real-time synchronization of the key chip data in the second main control chip and performing timed synchronization of the non-key chip data in the second main control chip.

9. A data processing device for a central controller, characterized in that, The central controller includes a first main control chip and a second main control chip, and the device includes: A data synchronization module for performing data synchronization between the first main control chip and the second main control chip based on the communication connection between the first main control chip and the second main control chip; A data acquisition module for acquiring temperature data and current data at the key detection positions of the first main control chip; An early warning determination module for, when it is determined that the first main control chip meets the status early warning condition based on the temperature data and the current data, the second main control chip performs configuration initialization according to the main control configuration information of the first main control chip; A fault response module for, if the second main control chip times out and does not receive the heartbeat information sent by the first main control chip, the second main control chip takes over the operation task of the first main control chip according to the synchronized chip data and the last heartbeat information, and executes the chip reset strategy of the first main control chip.

10. An electronic device, characterized in that, Includes: One or more processors; A memory; One or more programs, where the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs are configured to execute the method according to any one of claims 1-8.

11. A computer-readable storage medium storing a computer program for use in conjunction with an electronic device, characterized in that, The computer program can be executed by a processor to complete the method according to any one of claims 1-8.

12. A computer program product comprising a computer program / computer-executable instructions, characterized in that, The computer program / computer executable instruction, when executed by a processor in an electronic device, implements the method according to any one of claims 1-8.

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