Time sequence control device

Abstract

The embodiment of the invention provides a time sequence control device. In one specific embodiment, the module comprises a DSP processor, a driving chip, at least one CAN transceiver chip and a plurality of optocoupler substrates. According to the embodiment, the DSP processor, the driving chip, the CAN transceiver chip and the optocoupler substrate are integrated on the same substrate through the preset packaging structure, so that the integration level is high; the chips are directly connected, higher-density mounting is supported, and the size of the time sequence control module is smaller; and the chips are directly connected without additionally arranging a peripheral circuit, so that the material cost is reduced. The method is suitable for space-limited scenes such as aircrafts. Complex peripheral circuits do not need to be arranged among discrete components such as the DSP, the driving chip, the CAN transceiver chip and the optocoupler substrate, the circuit structure is simple, the design cost is reduced, and the automatic production efficiency is improved. Signal processing, communication and control functions are integrated in the package, redundant wiring among discrete components is eliminated, a signal transmission path is shortened, and signal delay and power consumption are reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of timing control, and more specifically, to a timing control device. Background Art

[0002] Currently, timing control devices are used in aircraft for timing control, receiving input trigger signals and outputting timing control signals. Existing timing control devices often use discrete circuit designs, relying on a large number of complex peripheral components (such as resistors, capacitors, and discrete logic gates) for signal processing and logic control. This results in poor integration and bulky design. Furthermore, the input terminals of existing timing control devices lack isolation, making them susceptible to damage and interference from external signals. Summary of the Invention

[0003] The purpose of the present disclosure is to provide a timing control device with high integration, small size and optoelectronic isolation at the input end, so as to solve at least one of the problems existing in the prior art.

[0004] To achieve the above objectives, the present disclosure adopts the following technical solutions:

[0005] A first aspect of the present disclosure provides a timing control device, comprising:

[0006] DSP processor, driver chip, at least one CAN transceiver chip and multiple optocoupler substrates;

[0007] The optical coupling substrate is used to output the first trigger signal input from the outside to the DSP processor through optical coupling isolation;

[0008] The CAN transceiver chip is used to receive a second trigger signal input from the outside and output it to the DSP processor;

[0009] The DSP processor is configured to output a driving control signal to the driver chip based on a preset configuration according to the first trigger signal from the optocoupler substrate or the second trigger signal from the CAN transceiver chip, so that the driver chip outputs a timing control signal according to the driving control signal;

[0010] The DSP processor, the driver chip, the CAN transceiver chips and the optocoupler substrates are configured to be packaged on the same substrate in a preset packaging structure.

[0011] Furthermore, the timing control module also includes a power management component, which is used to convert external input power into multiple voltages to respectively power the DSP processor, the driver chip, each CAN transceiver chip and each optocoupler substrate.

[0012] Further, the power management component includes a first power management chip, a second power management chip, a third power management chip, a first capacitor, a second capacitor, and a third capacitor;

[0013] One end of the first capacitor is respectively connected to the main power input pin and the control circuit power pin of the first power management chip, and the other end is grounded;

[0014] One end of the second capacitor is respectively connected to the main power input pin and the control circuit power pin of the second power management chip, and the other end is grounded;

[0015] One end of the third capacitor is respectively connected to the main power input pin and the control circuit power pin of the third power management chip, and the other end is grounded;

[0016] The power supply terminal of the first power management chip is respectively connected to the first power supply terminal of the DSP processor, the first power supply terminal of the driver chip, the power supply terminals of each CAN transceiver chip, and the power supply terminals of each optocoupler substrate;

[0017] The power supply terminal of the second power management chip is connected to the second power supply terminal of the driver chip;

[0018] The power supply terminal of the third power management chip is connected to the second power supply terminal of the DSP processor;

[0019] The DSP processor, the driver chip, each CAN transceiver chip, each optocoupler substrate, the first power management chip, the second power management chip, the third power management chip, the first capacitor, the second capacitor, and the third capacitor are configured to be encapsulated on the same substrate in a preset packaging structure.

[0020] Further, the input voltage ranges of the first power management chip, the second power management chip, and the third power management chip are 5V - 12V respectively.

[0021] Further, the bus terminal of the CAN transceiver chip is connected to an external terminal so that the external terminal can read the operating parameters of the DSP processor through the CAN transceiver chip.

[0022] Further, the DSP processor is configured to include a general-purpose input / output interface, an analog-to-digital conversion interface, and a digital-to-analog conversion interface.

[0023] Further, the timing control module includes at least two CAN transceiver chips.

[0024] Further, the driver chip includes at least 16 drive output interfaces.

[0025] Further, the timing control module includes at least six optocoupler substrates.

[0026] Further, the preset packaging structure is a ceramic column grid array 388.

[0027] The beneficial effects of the present disclosure are as follows:

[0028] The present disclosure integrates a DSP processor, a driver chip, a CAN transceiver chip, and an optocoupler substrate in a preset packaging structure on the same substrate. The DSP processor, the driver chip, the CAN transceiver chip, and the optocoupler substrate are all in chip structure, with high integration. The chips are directly connected to each other, supporting higher-density mounting, and the volume of the timing control module will be smaller. In addition, since there is no need to additionally set up peripheral circuits such as resistors and capacitors due to the direct connection, the material cost is reduced. It is very suitable for scenarios with limited space such as aircraft.

[0029] There is no need to set up complex peripheral circuits between discrete components such as a DSP processor, a driver chip, a CAN transceiver chip, and an optocoupler substrate, and the chips are directly connected to each other. The circuit structure is simple, reducing the design cost and improving the automated production efficiency.

[0030] The signal processing, communication, and control functions are integrated within the package, eliminating redundant wiring between discrete components, shortening the signal transmission path, and reducing signal delay and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The following further describes in detail the specific embodiments of the present disclosure with reference to the drawings.

[0032] Figure 1 A schematic diagram of a timing control module provided by an embodiment of the present disclosure is shown.

[0033] Figure 2 A schematic diagram showing a first power management chip, a second power management chip, and a third power management chip supplying power to other chips provided by an embodiment of the present disclosure is shown.

[0034] Figure 3 A circuit diagram of a timing control module provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] To more clearly illustrate the present disclosure, the following further describes the present disclosure with reference to the embodiments and the drawings. Similar components in the drawings are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the protection scope of the present disclosure.

[0036] As Figure 1 shown, the present invention provides a timing control device, including:

[0037] A digital signal processor (Digital Signal Processor, DSP processor 01), a driver chip 04, at least one Controller Area Network Transceiver (CAN transceiver) chip, and multiple optocoupler substrates 02;

[0038] The output end of the optocoupler substrate 02 is connected to the first communication end of the DSP processor 01 to isolate and output the externally input first trigger signal to the DSP processor 01 through the optocoupler 02;

[0039] The controller end of the CAN transceiver chip 03 is connected to the second communication end of the DSP processor 01 to receive the externally input second trigger signal and output it to the DSP processor 01;

[0040] The control end of the DSP processor 01 is connected to the driver chip 04, and is used to output a drive control signal to the driver chip 04 based on a preset configuration according to the first trigger signal from the optocoupler substrate 02 or according to the second trigger signal from the CAN transceiver chip 03, so that the driver chip 04 outputs a timing control signal according to the drive control signal output by the DSP processor 01;

[0041] The DSP processor 01, the driver chip 04, each CAN transceiver chip 03, and each optocoupler substrate 02 are configured to be encapsulated on the same substrate in a preset encapsulation structure.

[0042] In a specific example, the preset configuration includes the following content:

[0043] Signal input detection configuration: The DSP processor 01 is configured to detect the rising edge or falling edge of the first trigger signal output by the optocoupler substrate 02 through the first communication end, and trigger an interrupt service; wherein, the first trigger signal is a 200ms pulse signal, and the first communication end is a general-purpose input / output interface, namely GPIO. For example, when the pulse rising edge arrives, start a timer to measure the pulse width. Start the timer in the interrupt. If it is detected that the high-level duration is 195ms to 205ms, it is determined as a valid trigger signal, otherwise it is regarded as noise interference. On the other hand, the DSP processor 01 is configured to generate a 200ms pulse through the second trigger signal, and the DSP processor 01 outputs a drive control signal according to the 200ms pulse.

[0044] It should be noted that the present disclosure is not limited to using pulse signals only. Different types of signals can be set according to specific requirements during use. The present disclosure does not limit the signal type;

[0045] It should be noted that, according to requirements, the present disclosure can configure different second trigger signals to enable the DSP processor 01 to generate pulses of different frequencies; similarly, the first trigger signal can also be a pulse signal of different frequencies. The present disclosure does not make any restrictions in this regard.

[0046] Priority configuration: The DSP processor 01 is configured such that if the second trigger signal of the CAN transceiver chip 03 and the first trigger signal of the optocoupler substrate 02 arrive simultaneously, the priorities of the first trigger signal and the second trigger signal are set to a master-slave mode through interrupt nesting or software flag bits, that is, the first trigger signal is set to a high priority and the second trigger signal is set to a low priority. The trigger source selection bit is configured through an internal register to dynamically switch the signal channel.

[0047] Output interface configuration: The control terminal of the DSP processor 01 is configured to preset timing parameters according to the requirements of the driver chip 04. For example, the control terminal of the DSP processor 01 is configured to the SPI mode. At this time, the drive control signal is a 16-bit control word. !]]

[0048] It should be noted that in the present disclosure, the driver chip 04 adopts an input / output (IO) driver chip 04, and this drive circuit can directly drive a relay.

[0049] The present disclosure integrates the DSP processor 01, the driver chip 04, the CAN transceiver chip 03, and the optocoupler substrate 02 into the same substrate in a preset packaging structure. The DSP processor 01, the driver chip 04, the CAN transceiver chip 03, and the optocoupler substrate 02 are all in chip structures, with high integration; the chips are directly connected to each other, supporting higher-density mounting, and the volume of the timing control module will be smaller; in addition, since there is no need to additionally set peripheral circuits such as resistors and capacitors due to the direct connection, the material cost is reduced. It is very suitable for scenarios with limited space such as aircraft.

[0050] There is no need to set complex peripheral circuits between discrete components such as the DSP processor 01, the driver chip 04, the CAN transceiver chip 03, and the optocoupler substrate 02, and the chips are directly connected to each other, with a simple circuit structure, reducing the design cost and improving the automated production efficiency.

[0051] The signal processing, communication, and control functions are integrated within the package, eliminating redundant wiring between discrete components, shortening the signal transmission path, and reducing signal delay and power consumption.

[0052] In a possible implementation, as Figure 2 shown, the timing control module further includes a power management component, and the power management component is used to convert the externally input power into multiple voltages to supply power to the DSP processor 01, the driver chip 04, each CAN transceiver chip 03, and each optocoupler substrate 02 respectively.

[0053] Specifically, the power management component includes a first power management chip 061, a second power management chip 062, a third power management chip 063, a first capacitor C70, a second capacitor C71, and a third capacitor C73;

[0054] One end of the first capacitor C70 is connected to the main power input pin ( Figure 3 Vcc of D1 in the middle) and the control circuit power pin ( Figure 3 Connect the VIN of D1 in the middle and the other end to ground;

[0055] One end of the second capacitor C71 is connected to the main power input pin ( Figure 3 Vcc of D2) and the control circuit power pin ( Figure 3 Connect the VIN of D2 in the middle and the other end to ground;

[0056] One end of the third capacitor C73 is connected to the main power input pin ( Figure 3 Vcc of D3 in the middle) and the control circuit power pin ( Figure 3 Connect the VIN of D3 in the middle and the other end to ground;

[0057] The power supply end of the first power management chip 061 is respectively connected to the first power supply end of the DSP processor 01, the first power supply end of the driver chip 04, the power supply end of each CAN transceiver chip 03, and the power supply end of each optocoupler substrate 02;

[0058] The power supply terminal of the second power management chip 062 is connected to the second power supply terminal of the driver chip 04;

[0059] The power supply terminal of the third power management chip 063 is connected to the second power supply terminal of the DSP processor 01;

[0060] The DSP processor 01, the driver chip 04, the CAN transceiver chips 03, the optocoupler substrates 02, the first power management chip 061, the second power management chip 062, the third power management chip 063, the first capacitor C70, the second capacitor C71, and the third capacitor C73 are configured to be packaged on the same substrate in a preset package.

[0061] In the circuit disclosed herein, the core functions of the capacitor at the power input of the power management chip and the power pin of the control circuit are high-frequency noise filtering, energy storage buffering, and transient response enhancement.

[0062] Among them, the present disclosure integrates a DSP processor 01, a driver chip 04, each CAN transceiver chip 03, each optocoupler substrate 02, a first power management chip 061, a second power management chip 062, a third power management chip 063, a first capacitor C70, a second capacitor C71, and a third capacitor C73, which are configured to be encapsulated on the same substrate in a preset package. There is no additional peripheral circuit except for the three capacitors, with high integration; it also supports higher-density mounting, and the timing control module has a smaller volume.

[0063] In a possible implementation, the input voltage range of the first power management chip 061, the second power management chip 062, and the third power management chip 063 is 5V - 12V. The wide voltage input range enables the present disclosure to be applicable to a variety of external power supply sources.

[0064] In a possible implementation, the bus terminal of the CAN transceiver chip 03 is connected to an external terminal 05 so that the external terminal 05 can read the operating parameters of the DSP processor 01 through the CAN transceiver chip 03. It should be noted that the operating parameters include but are not limited to the power supply situation, operating voltage, input situation, and output situation of the DSP processor 01.

[0065] In the present disclosure, the external terminal 05 can be a terminal device on an aircraft.

[0066] In a possible implementation, the DSP processor 01 is configured to include a general-purpose input / output interface, an analog-to-digital conversion interface, and a digital-to-analog conversion interface.

[0067] In a possible implementation, the timing control module includes at least two CAN transceiver chips 03.

[0068] The redundant design using two or more CAN transceiver chips 03 can significantly improve the reliability and fault tolerance of the system. After one CAN transceiver fails, another CAN transceiver can automatically take over the communication task.

[0069] In a possible implementation, the driver chip 04 includes at least 16 drive output interfaces.

[0070] In a possible implementation, the timing control module includes at least 6 optocoupler substrates 02.

[0071] In a possible implementation, the preset package structure is a ceramic column grid array 388.

[0072] Among them, the ceramic column grid array 388 substrate uses alumina, aluminum nitride, or beryllium oxide ceramics, which have excellent thermal conductivity and low dielectric constant, and are suitable for high-temperature, high-humidity, or radiation environments.

[0073] Solder column: It is made of high-lead solder with 90% lead - 10% tin or 80% lead - 20% tin, and its melting point is about 300°C, which is much higher than 183°C of ordinary solder, ensuring welding stability.

[0074] Compared with traditional ceramic ball grid arrays, CCGA uses cylindrical solder columns with a height of about 2 mm and a diameter of about 0.5 mm, and the pitch is about 1 mm. The solder columns buffer the thermal expansion difference between the ceramic substrate and the PCB through their own deformation, reducing the solder joint stress and improving reliability. There are a total of 388 solder columns in the ceramic column grid array in this disclosure.

[0075] In a specific example, such as Figure 2 and Figure 3 shown, in this disclosure, the input voltage range of the first power management chip 061, the second power management chip 062, and the third power management chip 063 is 5V - 12V. Among them, the first power management chip 061 is configured to convert the input external voltage of 5V - 12V into a voltage of 3.3V, and supply power to the power supply terminal of the DSP processor 01, the first power supply terminal of the driver chip 04, the power supply terminals of each CAN transceiver chip 03, and the power supply terminals of each optocoupler substrate 02 respectively. That is, except for each power management chip, the pins marked with 3.3V on each chip in the figure are all powered by the VO1 port of the first power management chip 061; the second power management chip 062 is configured to convert the input external voltage of 5V - 12V into a voltage of 5V and supply power to the driver chip 04. For example, the pin marked with 5V on the driver chip 04 is powered by the VO2 port of the second power management chip 062. The third power management chip 063 is configured to convert the input external voltage of 5V - 12V into a voltage of 1.2V and supply power to the DSP processor 01. For example, the pin marked with 1.2V on the DSP processor 01 is powered by the VO3 port of the third power management chip 063, that is; among them, the driver chip 04 is preferably an SM164245 chip, that is Figure 3 D9 in Figure 3 ; in a specific example, the first power management chip 061, the second power management chip 062, and the third power management chip 063 respectively adopt TPS5432 chips; among them, the first power management chip 061 is Figure 3 D1 in Figure 3 ; the second power management chip 062 is Figure 3 D2 in

[0076] Specifically, referring to Figure 1 and Figure 3 , the working principle of the timing control module is:

[0077] The optocoupler substrate 02 receives an external first trigger signal and transmits the signal to the first communication end of the DSP processor 01 through the optocoupler 02 isolation technology.

[0078] The CAN transceiver chip 03 receives an external second trigger signal (through the CAN bus) and transmits the signal to the second communication end of the DSP processor 01, supporting reliable communication between multiple devices.

[0079] The DSP processor 01 generates a drive control signal according to the received trigger signal (from the optocoupler 02 or the CAN transceiver) according to a preset rule. The DSP processor 01 also supports a general-purpose input / output interface GPIO, an analog-to-digital conversion interface ADC, and a digital-to-analog conversion interface DAC; multiple types of interfaces can be used to expand data acquisition and output functions. And the redundant design of multiple CAN transceivers ensures communication fault tolerance.

[0080] The drive chip 04 receives the drive control signal from the DSP and outputs at least 16 channels of timing control signals to directly drive external devices such as relays.

[0081] In terms of power supply, stable power supply is achieved through three power management chips (such as TPS5432) and filter capacitors to reduce noise interference.

[0082] Ceramic column grid array (CCGA388) package: Integrate all components (DSP, drive chip 04, CAN transceiver, optocoupler 02, power chip, etc.) on the same substrate, reduce redundant wiring, shorten the signal path, and reduce delay and power consumption.

[0083] The external terminal 05 reads the operating parameters of the DSP processor 01 such as the power supply status and logic signals through the CAN bus to achieve real-time monitoring and debugging.

[0084] Optocoupler 02 isolation and redundant design ensure the stable operation of the system in a complex environment.

[0085] The timing control module integrates 6 optocoupler substrates 02, 1 DSP processor 01, three power management chips, three capacitors, 1 driver chip 04, 2 CAN transceiver chips 03, etc., a total of 13 chips and 3 capacitors. It can achieve 6-channel isolated input, 16-channel drive output, 3-channel secondary power conversion, and 2-channel CAN bus communication. The DSP processor 01 reserves general-purpose input / output interfaces GPIO, analog-to-digital conversion interfaces ADC, and digital-to-analog conversion interfaces DAC. It has the characteristics of multi-function, high density, high reliability, simple peripheral circuit, modularization, etc. The module power consumption is less than 2W, powered by 5-12V, with a packaging form of Ceramic Column Grid Array 388 (CCGA388), a size of 28×28×6.51mm (including column implantation), and a weight of 15g.

[0086] Heterogeneous and heterogeneous integration of 7 bare chips such as the DSP processor 01, power supply, driver chip 04, and CAN transceiver, and 6 optocoupler substrates 02 is achieved. The hybrid integration of optoelectronic devices, digital devices, and analog devices is realized, and system-level functions such as high-voltage isolated signal acquisition, digital communication, and control processing are achieved. The weight and volume of the product components are reduced to less than 40% of the traditional design.

[0087] In this disclosure, multiple electrical functions are highly integrated, and functions such as control, optoelectronic isolation, power supply, level conversion, and drive are highly integrated into a single chip. It has a wide input voltage range, supports an input voltage of 5-12V, and meets the application requirements under different power supply voltage scenarios. It includes a high-performance embedded processor and rich processor peripheral interfaces, with strong scalability.

[0088] In the description of this disclosure, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of this disclosure. Unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0089] It should also be noted that in the description of the present disclosure, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent in such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0090] Obviously, the above-mentioned embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, rather than limitations on the implementation manners of the present disclosure. For those of ordinary skill in the art, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to enumerate all implementation manners here. Any obvious changes or modifications derived from the technical solutions of the present disclosure still fall within the protection scope of the present disclosure.

Claims

1. A timing control device, characterized in that, Comprising: A DSP processor, a driver chip, at least one CAN transceiver chip, and multiple optocoupler substrates; The optocoupler substrate is used to isolate and output the externally input first trigger signal to the DSP processor through optocoupling; The CAN transceiver chip is used to receive the externally input second trigger signal and output it to the DSP processor; The DSP processor is used to output a drive control signal to the driver chip based on the first trigger signal from the optocoupler substrate or the second trigger signal from the CAN transceiver chip according to a preset configuration, so that the driver chip outputs a timing control signal according to the drive control signal; Wherein, the DSP processor, the driver chip, each CAN transceiver chip, and each optocoupler substrate are configured to be packaged on the same substrate in a preset packaging structure.

2. The timing control device according to claim 1, wherein The timing control device further includes a power management component, and the power management component is used to convert the externally input power into multiple voltages to supply power to the DSP processor, the driver chip, each CAN transceiver chip, and each optocoupler substrate respectively.

3. The timing control device according to claim 2, wherein The power management component includes a first power management chip, a second power management chip, a third power management chip, a first capacitor, a second capacitor, and a third capacitor; One end of the first capacitor is respectively connected to the main power input pin and the control circuit power pin of the first power management chip, and the other end is grounded; One end of the second capacitor is respectively connected to the main power input pin and the control circuit power pin of the second power management chip, and the other end is grounded; One end of the third capacitor is respectively connected to the main power input pin and the control circuit power pin of the third power management chip, and the other end is grounded; The power supply end of the first power management chip is respectively connected to the first power supply end of the DSP processor, the first power supply end of the driver chip, the power supply ends of each CAN transceiver chip, and the power supply ends of each optocoupler substrate; The power supply end of the second power management chip is connected to the second power supply end of the driver chip; The power supply end of the third power management chip is connected to the second power supply end of the DSP processor; The DSP processor, the driver chip, each CAN transceiver chip, each optocoupler substrate, the first power management chip, the second power management chip, the third power management chip, the first capacitor, the second capacitor, and the third capacitor are configured to be packaged on the same substrate in a preset packaging structure.

4. The timing control device according to claim 3, wherein The ranges of the input voltages of the first power management chip, the second power management chip, and the third power management chip are respectively 5V - 12V.

5. The timing control device according to claim 1, wherein The bus end of the CAN transceiver chip is connected to an external terminal so that the external terminal can read the operating parameters of the DSP processor through the CAN transceiver chip.

6. The timing control device according to claim 1, wherein The DSP processor is configured to include a general-purpose input / output interface, an analog-to-digital conversion interface, and a digital-to-analog conversion interface.

7. The timing control device according to claim 1, wherein the timing control device includes at least two CAN transceiver chips.

8. The timing control device according to claim 1, wherein the driver chip includes at least 16 drive output interfaces.

9. The timing control device according to claim 1, wherein the timing control device includes at least 6 optocoupler substrates.

10. The timing control device according to claim 1, wherein the preset packaging structure is a ceramic column grid array 388.

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