Low-power-consumption and high-power-supply-rejection-ratio method with load current sampling technology
Through sampling load current feedback and new bias current distribution circuits, the bandwidth and gain of the error amplifier are dynamically increased, and the problem of insufficient mid-to-high-band power rejection ratio of low-dropout linear regulators under low-power consumption design is solved, and the high-band power rejection ratio is improved and the low-band power rejection ratio is maintained.
Patent Information
- Application Number
- CN202510426177.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-19
- Publication Date
- 2025-08-01
AI Technical Summary
Existing low-dropout linear regulators are difficult to achieve high power rejection ratios in the medium and high frequency bands under low power consumption designs. Conventional design methods lead to reduced bandwidth and reduced power rejection ratios in the low frequency band.
The low-power high-power rejection ratio LDO circuit with sampled load current technology is used to feed back the bias circuit of the error amplifier through the sampling load current, and combined with the new bias current distribution circuit, the bandwidth and gain of the error amplifier are dynamically increased to maintain low cost.
Improve the power supply rejection ratio in the medium and high frequency bands, while keeping the power supply rejection ratio in the low frequency band not lowered, achieving a balance between ultra-low power consumption and high power supply rejection ratio.
Smart Images
Figure CN120406636A_ABST
Abstract
Description
[0001] This application is a divisional application of the following application: application date: September 19, 2022, application number: 202211137078.9, invention title: Low-power high-power supply rejection ratio LDO circuit and algorithm with sampling load current technology.
[0002] The present invention belongs to the technical field of voltage regulators, and particularly relates to a low-power high-power supply rejection ratio LDO circuit with sampling load current technology. Background Art
[0003] Low-dropout linear regulators have the advantages of small output noise, simple circuit structure, small chip area occupation, and small voltage ripple, and have become an important type of circuit in power management chips. Especially in mobile devices, the ultra-low static power consumption of low-dropout linear regulators is more prominent. The ultra-low static power consumption can extend the battery usage time and life, etc. Therefore, low-power design has also become a key indicator in the design of low-dropout linear regulators. However, a low static current will affect other parameter indicators of the low-dropout linear regulator, such as: load transient response, power supply rejection ratio (PSRR), output noise, etc.
[0004] Among them, low static power consumption and power supply rejection ratio (PSRR) are key performance indicators of linear regulators. And the power supply rejection ratio often depends on the accuracy of the bandgap reference and the open-loop gain of the error amplifier loop of the linear regulator. Usually, in order to obtain a higher power supply rejection ratio, a linear regulator uses a larger open-loop gain of the error amplifier, or increases the coupling capacitor at the output end. Using a larger open-loop gain of the error amplifier, such as a multi-stage operational amplifier, will not only increase the power consumption and area of the chip, but also bring greater challenges to circuit design. And the method of increasing the coupling capacitor at the output end will increase the chip area and production cost. At the same time, such a practice will lead to a reduction in the bandwidth of the linear regulator, so a high power supply rejection ratio cannot be obtained in the medium and high frequency bands.
[0005] With the improvement of users' requirements for power supply ripple suppression ability, low-power, high-power supply rejection ratio linear regulators are required to still have a good power supply rejection ratio of 60 dB at 100 kHz. This is also a challenge for low-power circuit design, because if the static current of the circuit is low, the bandwidth of the entire system will be reduced, and thus the power supply rejection ratio in the high frequency band will also be limited.
[0006] Under the requirements of low power consumption and low cost, the power supply rejection ratio curve of an LDO using a conventional error amplifier is as shown in Figure 3 Curve 1, which decreases at a rate of 20 dB / 10dec at relatively low frequency points, and the power supply rejection ratio of the LDO circuit under the restriction of the pair of contradictory points of open-loop gain and bandwidth is not ideal in the high frequency band.
[0007] According to relevant theories, the bandwidth of the error amplifier is proportional to the gm value of the input pair transistors. The gm increases as the current flowing through the input pair transistors increases. By using the load current sampling and feedback technique, a dynamic bias current can be injected into the error amplifier without increasing the static power consumption, dynamically increasing the gm of the input pair transistors when the LDO is loaded. However, the current design method directly injects the sampled bias current into the bias circuit of the error amplifier. This way of injecting the dynamic current, although increasing the bias current of the input pair transistors and thus partially increasing the gm of the differential input pair transistors and broadening the bandwidth of the error amplifier, also increases the bias current flowing through the load circuit and correspondingly significantly reduces the output resistance of the error amplifier. According to the gain formula of the error amplifier Av = gm * Rout, the gain of the error amplifier also decreases accordingly, resulting in a decrease in the power supply rejection ratio of the LDO at low frequencies, as Figure 3 shown by curve two in Figure 3 Comparison with curve one reveals that although the power supply rejection ratio in the high-frequency band is improved due to the increased bandwidth, the power supply rejection ratio in the mid- and low-frequencies also decreases significantly due to the decrease in the DC gain. This design method does not have a prominent effect on improving the power supply rejection ratio. SUMMARY OF THE INVENTION
[0008] To meet the requirements of low power consumption and high power supply rejection ratio for low-dropout linear regulators, the object of the present invention is to provide a low-power and high-power supply rejection ratio LDO circuit with a load current sampling technique that samples the load current and feeds it back to the bias circuit in the error amplifier, and uses a new type of bias current distribution circuit to increase the gain of the error amplifier in the mid- and high-frequencies while also increasing the bandwidth of the error amplifier. Another object of the present invention is to provide a low-power and high-power supply rejection ratio LDO circuit with a load current sampling technique that samples the output current, feeds the sampled current back to the error amplifier, and superimposes the sampled current on the fixed bias current of the error amplifier using a new type of bias current distribution circuit to increase the bandwidth of the error amplifier, improve the gain of the error amplifier in the high-frequency band, and achieve a high power supply rejection ratio in the high-frequency band while maintaining low cost. Yet another object of the present invention is to provide a low-power and high-power supply rejection ratio LDO circuit with a load current sampling technique that efficiently dynamically biases the error amplifier by sampling the output current, improves the power supply rejection ratio in the high-frequency band, and maintains ultra-low power consumption under no-load conditions, realizing an ultra-low static power consumption and high power supply rejection ratio low-dropout linear regulator.
[0009] The technical solution of the present invention is the low-power consumption and high power supply rejection ratio LDO circuit with sampling load current technology, which is special in that it includes: an error amplifier with dynamic current bias, an adjustment tube MP, a resistor feedback circuit, a reference circuit, and an output current sampling circuit: the output current sampling circuit is connected to the dynamic bias input terminal of the error amplifier; the inverting input of the error amplifier is connected to the reference voltage source VREF, the output terminal of the error amplifier is connected to the control terminal of the adjustment tube MP and the sampling tube MS, and the adjustment tube MP is connected to the non-inverting input terminal of the error amplifier through the resistor feedback circuit; the input terminal of the adjustment tube is connected to the power supply, and the common terminal of the adjustment tube MP and the resistor feedback circuit serves as the output terminal of the low voltage difference linear regulator circuit; the error amplifier converts the feedback voltage V output by the resistor feedback circuit into a voltage V. FB With the reference voltage V REF An error signal is generated by comparison, and the adjustment tube MP is adjusted by amplifying the error signal; the bias current in the error amplifier is fed back by sampling the load current, and the bias current distribution circuit is used to increase the gain of the medium and high frequency error amplifier while also increasing the bandwidth of the error amplifier.
[0010] Preferably, the output current sampling circuit includes a first transistor M1, a second transistor M2, and an eighteenth transistor MS; the input end of the eighteenth transistor MS is connected to the power supply, the output end of the eighteenth transistor MS is connected to the output end of the first transistor M1 and the control ends of the first transistor M1 and the second transistor M2, the output end of the second transistor M2 is connected to the dynamic bias input end of the error amplifier, and the input ends of the first transistor M1 and the second transistor M2 are connected to the ground end.
[0011] Preferably, the error amplifier includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M 10 , the eleventh transistor M 11 , the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 and the seventeenth transistor M 17 The input terminal of the fifth transistor M5 is connected to the power supply, and the control terminal of the fifth transistor M5 is connected to the fourth bias voltage V b4, the output terminal of the fifth transistor M5 is respectively connected to the input terminal of the sixth transistor M6 and the input terminal of the seventh transistor M7; the control terminal of the sixth transistor M6 serves as the non-inverting input terminal of the error amplifier and is connected to the feedback circuit, and the control terminal of the seventh transistor M7 serves as the inverting input terminal of the error amplifier and is connected to the reference voltage source VREF; the input terminal of the sixteenth transistor M 16 and the input terminal of the seventeenth transistor M 17 are both connected to the power supply; the output terminal, the control terminal of the sixteenth transistor M 16 and the control terminal of the seventeenth transistor M 17 are connected; the input terminal of the fourteenth transistor M 14 is connected to the output terminal of the sixteenth transistor M 16 , the control terminal of the fourteenth transistor M 14 is connected to the control terminal of the fifteenth transistor M 15 , and the common terminal of the two control terminals is connected to the first bias voltage V b1 , the input terminal of the fifteenth transistor M 15 is connected to the output terminal of the seventeenth transistor M 17 ; the input terminal of the twelfth transistor M 12 is connected to the output terminal of the fourteenth transistor M 14 , the control terminal of the twelfth transistor M 12 is connected to the control terminal of the thirteenth transistor M 13 , and the common terminal of the two control terminals is connected to the second bias voltage V b2 , the input terminal of the thirteenth transistor M 13 is connected to the output terminal of the fifteenth transistor M 15 , wherein, the common terminal of the thirteenth transistor M 13 and the fifteenth transistor M 15 serves as the output terminal of the error amplifier; the input terminal of the tenth transistor M 10 is connected to the output terminal of the twelfth transistor M 12 , and the input terminal of the tenth transistor M 10 is connected to the output terminal of the sixth transistor M6, the output terminal of the tenth transistor M 10 is connected to the ground terminal, the control terminal of the tenth transistor M 10 is connected to the control terminal of the eleventh transistor M 11 , and the common terminal of the two control terminals is connected to the third bias voltage V b3 , the input terminal of the eleventh transistor M 11 is connected to the output terminal of the thirteenth transistor M 13 , and the output terminal of the thirteenth transistor M 13The input terminal of 13 is connected to the output terminal of the seventh transistor M7, and the output terminal of the thirteenth transistor M 12 is connected to the ground terminal; the input terminals of the third transistor M3 and the fourth transistor M4 are both connected to the power supply, the output terminal of the third transistor M3 is connected to the output terminal of the second transistor M2, the control terminal of the third transistor M3 is connected to the control terminal of the fourth transistor M4 and the common terminal of the two control terminals is connected to the output terminal of the second transistor M2, and the output terminal of the fourth transistor M4 is respectively connected to the input terminal of the sixth transistor M6 and the input terminal of the seventh transistor M7; the input terminals of the eighth transistor M8 and the ninth transistor M9 are both connected to the ground terminal, the control terminal of the eighth transistor M8 is connected to the control terminal of the ninth transistor M9 and the common terminal of the two control terminals is connected to the output terminal of the eighteenth transistor MS, the input terminal of the eighth transistor M8 is connected to the output terminal of the twelfth transistor M 12 ; the input terminal of the ninth transistor M9 is connected to the output terminal of the thirteenth transistor M 13 .
[0012] Preferably: the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 and the thirteenth transistor M 13 are PMOS transistors; the eighth transistor M8, the ninth transistor M9, the tenth transistor M 10 and the eleventh transistor M 11 are NMOS transistors.
[0013] Preferably: the resistor feedback circuit includes: a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the output terminal of the regulating transistor MP, the other end of the first resistor R1 is connected to the ground terminal through the second resistor R2, and the common terminal of the first resistor R1 and the second resistor R2 is used as the output terminal of the feedback resistor and is connected to the non-inverting input terminal of the error amplifier.
[0014] Another technical solution of the present invention is the algorithm with low power consumption and high power supply rejection ratio of the sampling load current technology, which is characterized by including:
[0015] Increasing the loop gain of the LDO to improve the power supply noise suppression characteristic of the LDO:
[0016]
[0017] Wherein, A EA is the gain of the error amplifier, β is the feedback coefficient of the feedback circuit, A POW is the gain of the power stage, PSR EA and PSR POW are the power supply rejection ratios of the error amplifier and the power stage respectively when they exist alone. It can be seen from this formula that increasing the gain of the error amplifier can improve the power supply noise suppression characteristic of the LDO;
[0018] To improve the power supply noise suppression characteristic of the LDO at medium and high frequencies, it is achieved by increasing the gain of the error amplifier in the medium and high frequency bands. For the error amplifier:
[0019] A EA = g m * = R out (2)
[0020]
[0021] R OUT ≈ g m15 r m15 r m17 || g m13 r m13 (r m7 || r m11 ) (5)
[0022]
[0023] Wherein, g m represents the transconductance of the input transistor of the error amplifier, r m15 , r m17 , r m13 , r m7 , r m11 are the output resistances of the fifteenth transistor M 15 , the seventeenth transistor M 17 , the thirteenth transistor M 13 , the seventh transistor M7, the eleventh transistor M 11 in the telescopic structure of the error amplifier respectively, g m15 , g m13 are the transconductances of the thirteenth transistor M 13 and the fifteenth transistor M 15 respectively, R out represents the output resistance of the error amplifier, GBW EA is the gain bandwidth product of the error amplifier, C POW is the load capacitance of the output stage of the error amplifier, I D is the drain-source current flowing through the input transistor;
[0024] As can be seen from the above formula: the bandwidth of the error amplifier is proportional to the gm value of the input pair transistors, and gm increases as the current I flowing through the input pair increases. For the dynamic current biasing circuit using the load current sampling feedback technique, the sampled biasing current is directly injected into the biasing circuit of the error amplifier, and the dynamic current is distributed to the differential input pair transistors and the cascode structure according to the fixed biasing current distribution ratio designed for the original error amplifier: m value is proportional to, and gm m increases as the current I flowing through the input pair increases. For the dynamic current biasing circuit using the load current sampling feedback technique, the sampled biasing current is directly injected into the biasing circuit of the error amplifier, and the dynamic current is distributed to the differential input pair transistors and the cascode structure according to the fixed biasing current distribution ratio designed for the original error amplifier: D increases as the current I flowing through the input pair increases. For the dynamic current biasing circuit using the load current sampling feedback technique, the sampled biasing current is directly injected into the biasing circuit of the error amplifier, and the dynamic current is distributed to the differential input pair transistors and the cascode structure according to the fixed biasing current distribution ratio designed for the original error amplifier:
[0025] Among them, the case where no dynamic biasing current is injected:
[0026] The case where dynamic biasing current is injected:
[0027]
[0028] As is injected, the biasing current I D flowing through the differential input pair transistors increases, increasing the gm of the differential input pair transistors, and correspondingly broadening the bandwidth of the error amplifier. However, as I′2 is injected, the output resistance r o of each transistor in the cascode structure also decreases significantly, and the output resistance R OUT of the error amplifier also decreases accordingly. According to formula (2), the gain of the error amplifier also decreases accordingly, resulting in a decrease in the power supply rejection ratio of the LDO at low frequencies.
[0029] Preferably: To further improve the power supply rejection ratio of the LDO, M4 provides the dynamic biasing current I B1 for the amplifier input pair transistors, and M7 and M8 provide the dynamic biasing currents I B2 and I B3 for the cascode circuit, where the dynamic biasing currents are:
[0030] The case where no dynamic biasing current is injected:
[0031]
[0032] The case where dynamic biasing current is injected:
[0033]
[0034] Design then I′2 = 0
[0035] Since the values of I′1 and I′2 are zero, the current flowing through the twelfth transistor M 12 、the thirteenth transistor M 13, the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 , the seventeenth transistor M 17 The current of is the same as that without adding the dynamic bias current. According to formula (4) and formula (6), g m15 , g m13 , r m15 , r m17 , r m13 The values of are also the same as those before injecting the dynamic bias current. According to formula (5), the output resistance of the error amplifier will not be significantly reduced due to the addition of the dynamic bias current, and all the injected dynamic bias current is injected into the differential input pair transistors, significantly improving the gm of the input pair transistors. According to formula (2) and formula (3), this injection method improves the open-loop gain and broadens the bandwidth of the error amplifier. Similarly, as the gain A EA of the error amplifier increases, according to formula (1), the power supply rejection ratio of the LDO is significantly improved
[0036] Compared with the prior art, the beneficial effects of the present invention are:
[0037] ⑴ The present invention utilizes the load current sampling feedback technology, and through the novel dynamic bias circuit modulation module, it specifically increases the bias current of some key modules of the error amplifier. While significantly improving the transconductance Gm of the error amplifier, it slows down the change in the resistance value of the output resistance of the error amplifier, improves the gain in the medium and high frequencies, and further increases the loop bandwidth, so that the power supply rejection ratio of the LDO loop is still large at high frequencies, and the power supply rejection ratio in the medium and low frequencies is not affected by the newly added dynamic current and still remains at a relatively high level. As can be seen from the above: The low-power and high-power supply rejection ratio LDO circuit of the present invention realizes a high power supply rejection ratio in the high-frequency band while maintaining a low cost.
[0038] ⑵ The present invention performs high-efficiency dynamic current biasing on the error amplifier by sampling the output current, maintaining the high-gain characteristic of the error amplifier while broadening the bandwidth of the error amplifier, thereby improving the power supply rejection ratio of the LDO in the high-frequency band and maintaining ultra-low power consumption under no-load conditions.
[0039] ⑶ The present invention samples the output current, feeds back the sampled current to the error amplifier, and superimposes the sampled current on the fixed bias current of the error amplifier by using the novel bias current distribution circuit, increasing the bandwidth of the error amplifier and improving the power supply rejection ratio in the high-frequency band of the error amplifier.
[0040] ⑷ The power supply rejection ratio of the LDO using the sampling circuit and dynamic bias of the present invention to adjust the error amplifier is as shown by the dotted line in Curve 2. Compared with Figure 4 Figure 4 By comparing Curve 1 (the power supply rejection ratio curve of the LDO with an error amplifier without dynamic bias adjustment), it can be found that the power supply rejection ratio in the medium and high frequency bands has a relatively large improvement, while the power supply rejection ratio in the medium and low frequencies also remains at a relatively high level. Description of the Drawings
[0041] Figure 1 is the block diagram of the low-dropout linear regulator with low power consumption and high power supply rejection ratio of the present invention;
[0042] Figure 2 is the block diagram of the error amplifier with a dynamic sampling current bias circuit of the present invention;
[0043] Figure 3 is the comparison chart of the power supply rejection ratio of the LDO with a conventional dynamic bias error amplifier and the LDO with a conventional error amplifier;
[0044] Figure 4 is the comparison chart of the power supply rejection ratio of the LDO with a novel dynamic bias error amplifier and the LDO with a conventional error amplifier of the present invention. Detailed Description of the Invention
[0045] The present invention will be further described in detail below with reference to the accompanying drawings:
[0046] Please refer to Figure 1 As shown, the low-dropout linear regulator circuit of the present invention includes: a reference circuit, an error amplifier with a dynamic current bias, an adjustment transistor MP, an output current sampling circuit, and a feedback circuit. Among them:
[0047] The inverting input terminal of the error amplifier is connected to the reference voltage source VREF, the output terminal of the error amplifier is connected to the control terminal of the adjustment transistor Mp, the output terminal of the adjustment transistor MP is connected to the non-inverting input terminal of the error amplifier through the feedback circuit, the input terminal of the output current sampling circuit is connected to the output terminal of the error amplifier, and the output terminal of the output current sampling circuit is connected to the dynamic current input terminal of the error amplifier;
[0048] Since the function of the error amplifier is to compare the feedback voltage with the reference voltage Vref to generate an error signal, and adjust the adjustment transistor Mp by amplifying the error signal, so as to finally stabilize the output voltage of the entire circuit. Therefore, the performance of the error amplifier directly affects various performance parameters of the entire circuit, such as power supply rejection ratio, load regulation rate, linear regulation rate, etc. To achieve a high power supply rejection ratio in a relatively wide frequency band, it is usually required that the error amplifier has a high gain in a relatively wide frequency band. Therefore, the error amplifier generally adopts a folded cascode amplifier or a two-stage operational amplifier structure. Since the two-stage operational amplifier will generate two poles, it is necessary to design an additional compensation circuit to generate a zero point to cancel one pole, which undoubtedly increases the design difficulty of the compensation network of the entire circuit. While the folded cascode amplifier is a single-stage operational amplifier that can reduce the compensation difficulty, and the folded cascode amplifier can also provide a large gain and a large loop bandwidth. Therefore, the present invention adopts a dynamic current-biased error amplifier based on a folded cascode amplifier.
[0049] Please refer to Figure 2 As shown, the dynamic current-biased error amplifier provided by the embodiment of the present invention includes: a third switch transistor M3, a fourth switch transistor M4, a fifth switch transistor M5, a sixth switch transistor M6, a seventh switch transistor M7, an eighth switch transistor M8, a ninth switch transistor M9, a tenth switch transistor M 10 , an eleventh switch transistor M 11 , a twelfth switch transistor M 12 , a thirteenth switch transistor M 13 , a fourteenth switch transistor M 14 , a fifteenth switch transistor M 15 , a sixteenth switch transistor M 16 and a seventeenth switch transistor M 17 ;
[0050] Wherein: the input end of the fifth transistor M5 is connected to the power supply VDD, the control end of the fifth transistor M5 is connected to the fourth bias voltage M4, and the output end of the fifth transistor M5 is respectively connected to the input ends of the sixth transistor M6 and the seventh transistor M7;
[0051] The control end of the sixth transistor M6 is used as the non-inverting input end of the error amplifier and is connected to the feedback circuit (feedback power supply V FB ), and the control end of the seventh transistor M7 is used as the inverting input end of the error amplifier and is connected to the reference voltage source V REF ;
[0052] The input ends of the sixteenth transistor M 16 and the seventeenth transistor M 17 are both connected to the power supply V DD , and the sixteenth transistor M16 The output terminal, control terminal and the seventeenth transistor M 17 The control terminal is connected;
[0053] The fourteenth transistor M 14 The input terminal is connected to the output terminal of the sixteenth transistor M 16 The control terminal of the fourteenth transistor M 14 Is connected to the control terminal of the fifteenth transistor M 15 And the common terminal of the two control terminals is connected to the first bias voltage. The input terminal of the fifteenth transistor M 15 Is connected to the output terminal of the seventeenth transistor M 17 ;
[0054] The input terminal of the twelfth transistor M 12 Is connected to the output terminal of the fourteenth transistor M 14 The control terminal of the twelfth transistor M 12 Is connected to the control terminal of the thirteenth transistor M 13 And the common terminal of the two control terminals is connected to the second bias voltage. The input terminal of the thirteenth transistor M 13 Is connected to the output terminal of the fifteenth transistor M 15 Wherein, the common terminal of the thirteenth transistor M 13 And the fifteenth transistor M 15 Is used as the output terminal of the error amplifier;
[0055] The input terminal of the tenth transistor M 10 Is connected to the output terminal of the twelfth transistor M 12 And the input terminal of the tenth transistor M 10 Is connected to the output terminal of the sixth transistor M6. The output terminal of the tenth transistor M 10 Is connected to the ground terminal GND. The control terminal of the tenth transistor M 10 Is connected to the control terminal of the eleventh transistor M 11 And the common terminal of the two control terminals is connected to the third bias voltage. The input terminal of the eleventh transistor M 11 Is connected to the output terminal of the thirteenth transistor M 13 And the input terminal of the thirteenth transistor M 13 Is connected to the output terminal of the seventh transistor M7. The output terminal of the thirteenth transistor M 13 Is connected to the ground terminal GND;
[0056] The input terminals of the third transistor M3 and the fourth transistor M4 are both connected to the power supply V DD, the output terminal of the third transistor M3 is connected to the output terminal of the second transistor M2, the control terminal of the third transistor M3 is connected to the control terminal of the fourth transistor M4, and the common terminal of the two control terminals is connected to the output terminal of the second transistor M2. The output terminal of the fourth transistor M4 is respectively connected to the input terminal of the sixth transistor M6 and the input terminal of the seventh transistor M7;
[0057] The input terminals of the eighth transistor M8 and the ninth transistor M9 are both connected to the ground terminal. The control terminal of the eighth transistor M8 is connected to the control terminal of the ninth transistor M9, and the common terminal of the two control terminals is connected to the output terminal of the eighteenth transistor MS. The input terminal of the eighth transistor M8 is connected to the output terminal of the twelfth transistor M 12 , and the input terminal of the ninth transistor M9 is connected to the output terminal of the thirteenth transistor M 13 ;
[0058] It should be noted that in the error amplifier, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 and the thirteenth transistor M 13 are PMOS transistors;
[0059] The eighth transistor M8, the ninth transistor M9, the tenth transistor M 10 and the eleventh transistor M 11 are NMOS transistors.
[0060] It can be seen from the figure that the input differential pair of the error amplifier is a PMOS transistor, so that the error amplifier can still work normally when the input voltage is low. There are three bias voltages in the cascode structure to provide a DC bias point for the operational amplifier.
[0061] To further illustrate that the low-dropout linear regulator circuit provided by the present invention can significantly improve the power supply rejection ratio, the error amplifier with dynamic current bias is analyzed and calculated below. According to relevant theories, increasing the loop gain of the LDO is beneficial to improving the power supply noise suppression characteristic of the LDO:
[0062]
[0063] Among them, A EA is the gain of the error amplifier, β is the feedback coefficient of the feedback circuit, and A POWis the gain of the power stage, PSR EA and PSR POW are the power supply rejection ratios of the error amplifier and the power stage when they exist separately. It can be seen from the above formula that increasing the gain of the error amplifier can improve the power supply noise suppression characteristic of the LDO.
[0064] It can also be known from this that to improve the power supply noise suppression characteristic of the LDO at medium and high frequencies, it can be achieved by increasing the gain of the error amplifier in the medium and high frequency bands. For the error amplifier:
[0065] A EA = g m *R out (2)
[0066]
[0067] R OUT ≈ g m15 r m15 r m17 || g m13 r m13 (r m7 || r m11 ) (5)
[0068]
[0069] In the formula, g m represents the transconductance of the input transistor of the error amplifier, r m15 , r m17 , r m13 , r m7 , r m11 are the output resistances of the fifteenth transistor M 15 , the seventeenth transistor M 17 , the thirteenth transistor M 13 , the seventh transistor M7, the eleventh transistor M 11 in the telescopic structure of the error amplifier respectively, g m15 , g m13 are the transconductances of the thirteenth transistor M 13 and the fifteenth transistor M 15 respectively, R out represents the output resistance of the error amplifier, GBW EA is the gain-bandwidth product of the error amplifier, C POW is the load capacitance of the output stage of the error amplifier, I D is the drain-source current flowing through the input transistor;
[0070] It can be known from the above formula that: the bandwidth of the error amplifier is proportional to the g m value of the input pair transistors, and g mAs the current I flowing through the input pair D increases, if a dynamic current biasing circuit using load current sampling feedback technology directly injects the sampled biasing current into the biasing circuit of the error amplifier, the dynamic current is respectively allocated to the differential input pair transistors and the cascode structure according to the distribution ratio of the fixed biasing current designed for the original error amplifier:
[0071] The situation where no dynamic biasing current is injected:
[0072] The situation where dynamic biasing current is injected:
[0073]
[0074] As the injection increases, the biasing current I D flowing through the differential input pair transistors increases, which improves the gm of the differential input pair transistors and correspondingly broadens the bandwidth of the error amplifier. However, with the injection of I′2, the output resistance r o of each transistor in the cascode structure also decreases significantly, and the output resistance R OUT of the error amplifier also decreases accordingly. According to Equation 2, the gain of the error amplifier also decreases accordingly, resulting in a decrease in the power supply rejection ratio of the LDO at low frequencies. As Figure 3 shown, Curve 1 is the power supply rejection ratio curve of the LDO without the dynamic biasing circuit, and Curve 2 is the power supply rejection ratio curve of the LDO with the dynamic biasing circuit. By comparison, it can be found that although the power supply rejection ratio of the LDO in the high-frequency band increases due to the increase in g m with the increase in the biasing current, the R OUT of the error amplifier decreases with the increase in the biasing circuit, and A EA also decreases accordingly, resulting in a significant decrease in the power supply rejection ratio in the mid-low frequency range, which does not meet our design goal.
[0075] In order to more reasonably broaden the bandwidth of the error amplifier, improve the open-loop gain of the error amplifier in the mid-high frequency range, and further improve the power supply rejection ratio of the LDO, the present invention adopts a novel dynamic sampling current biasing circuit module in the error amplifier, as Figure 2 shown. Where Isense is the sampling current, M1 and M2, M3 and M4 respectively form current mirrors, M4 provides the dynamic biasing current I B1 for the amplifier input pair transistors, and M7 and M8 provide the dynamic biasing currents I B2 and I B3 for the cascode circuit. The dynamic biasing current is:
[0076] The situation where no dynamic biasing current is injected:
[0077]
[0078] Injecting dynamic bias current:
[0079]
[0080] design Then I′2=0
[0081] Since the values of I′1 and I′2 are zero, the current flowing through the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 , the seventeenth transistor M 17 The current is the same as that without adding dynamic bias current. According to formula 4 and formula 6, g m15 、g m13 、r m15 、r m17 、r m13 The values of are the same as before the dynamic bias current is injected. According to formula 5, the output resistance of the error amplifier will not be significantly reduced due to the addition of the dynamic bias current. The dynamic bias current is injected into the differential input pair tube, which can more significantly improve the gm of the input pair tube. According to formulas 2 and 3, this injection method will greatly improve the open-loop gain and widen the bandwidth of the error amplifier. Similarly, as the gain A of the error amplifier increases EA According to formula (1), this method can significantly improve the power supply rejection ratio of the LDO. The power supply rejection ratio of the LDO using the sampling circuit and the dynamic bias adjustment error amplifier in the embodiment of the present invention is as follows: Figure 4 The dotted line of curve 2 is shown. Figure 4 Comparing Curve 1 (the LDO power supply rejection ratio curve using an error amplifier without dynamic bias adjustment), it can be found that the power supply rejection ratio in the mid-to-high frequency band has been greatly improved, while the power supply rejection ratio in the mid-to-low frequency band has also remained at a relatively high level.
[0082] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention shall fall within the scope of the claims of the present invention.
Claims
1. A method with a sampling load current technology for low power consumption and high power supply rejection ratio, characterized in that, Including: Increasing the loop gain of the LDO to improve the power supply noise suppression characteristic of the LDO: Wherein, A EA is the gain of the error amplifier, β is the feedback coefficient of the feedback circuit, A POW is the gain of the power stage, PSR EA and PSR POW are the power supply rejection ratios of the error amplifier and the power stage when they exist alone respectively. It can be seen from formula (1) that increasing the gain of the error amplifier can improve the power supply noise suppression characteristic of the LDO; To improve the power supply noise suppression characteristic of the LDO at medium and high frequencies, it is achieved by increasing the gain of the error amplifier in the medium and high frequency bands. For the error amplifier: A EA = g m * R out (2) R OUT ≈g m15 r m15 r m17 ||g m13 r m13 (r m7 ||r m11 ) (5) where g m represents the transconductance of the input transistor of the error amplifier, and r m15 , r m17 , r m13 , r m7 , r m11 are the output resistances of the fifteenth transistor M 15 , the seventeenth transistor M 17 , the thirteenth transistor M 13 , the seventh transistor M7, and the eleventh transistor M 11 in the telescopic structure of the error amplifier, respectively. g m15 , g m13 are the transconductances of the thirteenth transistor M 13 and the fifteenth transistor M 15 respectively. R out represents the output resistance of the error amplifier, GBW EA is the gain-bandwidth product of the error amplifier, C POW is the load capacitance of the output stage of the error amplifier, and I D is the drain-source current flowing through the input transistor; As can be seen from the above formula: the bandwidth of the error amplifier is proportional to the g of the input pair transistors, and g m increases as the current I flowing through the input pair increases. The dynamic current biasing circuit using the load current sampling feedback technology directly injects the sampled biasing current into the biasing circuit of the error amplifier. The dynamic current is respectively distributed to the differential input pair transistors and the cascode structure according to the fixed biasing current distribution ratio designed for the original error amplifier: m As the current I flowing through the input pair increases, and g D increases as the current I flowing through the input pair increases. The dynamic current biasing circuit using the load current sampling feedback technology directly injects the sampled biasing current into the biasing circuit of the error amplifier. The dynamic current is respectively distributed to the differential input pair transistors and the cascode structure according to the fixed biasing current distribution ratio designed for the original error amplifier: The case where no dynamic bias current is injected: Case of injecting dynamic bias current: With injection, the bias current I D flowing through the differential input pair transistors increases, improving the g m of the differential input pair transistors. Correspondingly, the bandwidth of the error amplifier is widened. However, with the injection of I′2, the output resistances r o of the transistors in the cascode structure are significantly reduced accordingly, and the output resistance R OUT of the error amplifier is also reduced accordingly. According to formula (2), the gain of the error amplifier is reduced accordingly, resulting in a decrease in the power supply rejection ratio of the LDO at low frequencies.
2. The method of low power consumption and high power supply rejection ratio with sampling load current technology according to claim 1, characterized in that, To further improve the power supply rejection ratio of the LDO, M4 provides the dynamic bias current I for the input pair of the amplifier B1 , M7 and M8 provide the dynamic bias currents I B2 and I B3 , where the dynamic bias current is: The case where no dynamic bias current is injected: The case where dynamic bias current is injected: Design Then I'2 = 0 Since the values of I′1 and I′2 are zero, the current flowing through the twelfth transistor M 12 、the thirteenth transistor M 13 、the fourteenth transistor M 14 、the fifteenth transistor M 15 、the sixteenth transistor M 16 、the seventeenth transistor M 17 is the same as that without the dynamic bias current. According to formulas ⑷ and ⑹, g m15 、g m13 、r m15 、r m17 、r m13 are also the same as those before the injection of the dynamic bias current. According to formula ⑸, the output resistance of the error amplifier will not be significantly reduced due to the addition of the dynamic bias current, and all the injected dynamic bias current is injected into the differential input pair transistors, significantly increasing the g m of the input pair transistors. According to formulas ⑵ and ⑶, this injection method will increase the open-loop gain and broaden the bandwidth of the error amplifier. Similarly, as the gain A EA of the error amplifier increases, according to formula ⑴, the power supply rejection ratio of the LDO is significantly improved.