Accelerated computing system and computing system

Abstract

The invention discloses an accelerated computing system and a computing system, and relates to the technical field of computers.In the accelerated computing system, a first board card and a second board card are correspondingly connected with a third board card through cables respectively, the first board card is connected with the second board card, and the second board card is provided with a signal relay device; compared with the prior art that the acceleration cards are installed in a server case and limited by a mainboard in a host, the number of the acceleration cards cannot be increased, and space conflicts with devices such as a power source in the case are caused by the fact that the acceleration cards are installed on one board card, and the like, the method has the advantages that the signal relay function is provided for the data channels between the host node and the acceleration cards; according to the invention, flexible layout in the case can be realized through the connection relationship between the board cards, and sufficient space is provided for modules such as a power supply occupying a relatively large space in the case, so that the deployment density of the acceleration cards can be effectively improved, and more acceleration cards can be deployed in a limited space to realize a larger-scale computing power cluster.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to an accelerated computing system and a computing system. Background Art

[0002] With the development of artificial intelligence technology, the demand for computing power has increased significantly. Related technologies have proposed solutions such as deploying acceleration cards inside servers and interconnecting multiple servers to form a multi-machine multi-card cluster, resulting in a shortage of space in the data center. It is necessary to deploy servers with high density to make full use of the cabinet space and chassis space.

[0003] How to increase the number of deployed acceleration cards in a limited space is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The present invention provides an accelerated computing system and a computing system to at least solve the problem of limited number of acceleration cards deployed in the server chassis in related technologies.

[0005] The present invention provides an accelerated computing system, including: a first board, a second board, and a third board; The third board corresponding to the first board is connected to the first board through a cable, and the third board corresponding to the second board is connected to the second board through a cable; The first board is connected to the second board; Both the first board and the third board are provided with first slots for installing acceleration cards; The second board is provided with a signal relay device. The first end of the signal relay device is connected to the host node, and the second end of the signal relay device is correspondingly connected to the first slot on the first board and the first slot on the third board.

[0006] The present invention also provides a computing system, including: a host node and an accelerated computing system; The accelerated computing system includes: a first board, a second board, and a third board; The third board corresponding to the first board is connected to the first board through a cable, and the third board corresponding to the second board is connected to the second board through a cable; The first board is connected to the second board; Both the first board and the third board are provided with first slots for installing acceleration cards; The second board is provided with a signal relay device. The first end of the signal relay device is connected to the host node, and the second end of the signal relay device is correspondingly connected to the first slot on the first board and the first slot on the third board.

[0007] According to the present invention, an accelerated computing system with only acceleration cards deployed is provided. The accelerated computing system includes a first board, a second board, and a third board. The first board is connected to the corresponding third board through a cable, the second board is connected to the corresponding third board through a cable, the first board is connected to the second board. Both the first board and the third board are provided with first slots for installing acceleration cards, and the second board is provided with a signal relay device. The first end of the signal relay device is connected to the host node to provide a signal relay function for the data channel between the host node and each acceleration card. Compared with the related art where the installation of acceleration cards in the server chassis is limited by components such as the motherboard in the host and the number cannot be expanded, and where the acceleration cards are installed on an entire acceleration card board and there is a space conflict with devices such as the power supply in the chassis, through the cable connection relationship between the first board and the third board and between the second board and the third board in the present invention, the layout of each board in the chassis where the accelerated computing system is located can be flexibly adjusted, providing sufficient space for modules such as the power supply that occupy a large amount of space in the chassis. Therefore, the deployment density of the acceleration cards can be effectively increased, and more acceleration cards can be deployed in a limited space to achieve a larger-scale computing power cluster. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0009] Figure 1 Schematic diagram of the structure of an accelerated computing system provided by an embodiment of the present invention; Figure 2 Schematic diagram of the structure of a first board provided by an embodiment of the present invention; Figure 3 Schematic diagram of the structure of a second board provided by an embodiment of the present invention; Figure 4 Schematic diagram of the structure of a power supply board provided by an embodiment of the present invention; Figure 5 Schematic diagram of the installation structure of an accelerated computing system provided by an embodiment of the present invention; Figure 6 Circuit diagram of a second board provided by an embodiment of the present invention; Figure 7 Circuit diagram of the power-on and power-off control circuit of an acceleration card provided by an embodiment of the present invention; Among them, 100 is an acceleration computing system, 101 is a first board, 102 is a second board, 103 is a third board, 104 is a signal relay device, 105 is a first slot, 106 is a status management controller, 107 is a first power-on controller, 108 is a power-on / off signal input device, 109 is a first connector, 110 is a second connector, 111 is a third connector, 112 is a gold finger, 113 is a gold finger slot, 114 is a power supply board, 115 is a power supply module, 116 is a chassis, 117 is a chassis housing structure, and 200 is a host node. Specific embodiments

[0010] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0011] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0012] In order to enable those skilled in the art of the present technology to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0013] Here, some key terms used in the embodiments of the present invention will be explained first.

[0014] With the development of cloud computing applications, informatization has gradually covered all fields of society. People's daily work increasingly communicates through the network, and the network data volume has also grown explosively. As the core device for processing and storing data, the server has higher and higher requirements for performance and configuration. In order to meet the complex and diverse application scenarios of different users in various fields, the configuration of the server also needs to be flexible and variable.

[0015] The server is mainly composed of electronic devices such as circuit boards, central processing units, memories, and chip sets. It has a high computing rate, a long running time, and a large data throughput. The performance of only the central processing unit (CPU) cannot meet the requirements, so an acceleration card needs to be used as an extended computing resource.

[0016] An acceleration card is a hardware device used to improve the performance of a computing device and accelerate the data transfer rate. It is usually installed on the Peripheral Component Interconnect Express (PCIe) slot of the computing device and connected to the motherboard of the computing device. The acceleration card includes a circuit structure for implementing relevant data operations, which can be specifically presented as: Graphics Processing Unit (GPU), Field-Programmable Gate Array (FPGA), etc. The acceleration card reduces the machine's dependence on the CPU and performs some of the original CPU work.

[0017] With the wide application of acceleration cards in the fields of artificial intelligence, scientific computing, graphics rendering, etc., the performance of a single acceleration card is gradually difficult to meet the requirements of large-scale and complex tasks. It is necessary to combine multiple acceleration cards, and even multiple servers to build a cluster for collaborative work, and data transfer and interaction are required between acceleration cards and between acceleration cards and the CPU.

[0018] During the process of building a cluster, the space of the chassis in the data center poses a limitation. Currently, in the chassis of a server, it is necessary to deploy a motherboard, a backplane, an expansion board, a power supply board, a management card, a cooling system, etc. In addition to considering the size of the board cards, the installation distance limit between board cards also needs to be considered, which greatly limits the number of acceleration cards that can be expanded in a single server. In addition, acceleration cards are usually large in size. For example, the dual-width GPU widely used in high-performance computing and artificial intelligence tasks occupies the width of two PCIe expansion slots and requires a larger fan and heat sink, posing higher requirements for the chassis space and motherboard layout.

[0019] Currently, in a 4U chassis, usually only 4 to 8 acceleration cards can be deployed. "U" is the unit of the server chassis, and 1U is equal to 4.445 centimeters (1.75 inches). In the data center, servers with 4U chassis are widely used. The height of a 4U chassis is 4U, that is, 4 × 4.445 centimeters = 17.78 centimeters (about 17.8 centimeters). The width and depth of this chassis also have certain standards. Generally, the width is 19 inches (about 48.26 centimeters), and the depth varies depending on the specific model and use. The common depth is about 70 - 100 centimeters.

[0020] Although more acceleration cards can be accommodated by replacing the chassis with a larger size, this requires a large-scale replacement of the chassis in the data center and an expansion of the data center space, which will bring huge costs.

[0021] To solve the problem that the limited number of acceleration cards in the chassis cannot meet the high-demand scenarios, the embodiments of the present invention provide an acceleration computing system and a computing system, wherein the acceleration computing system is only used for deploying acceleration cards. The acceleration computing system includes a first board, a second board, and a third board. The first board is connected to the corresponding third board through a cable, the second board is connected to the corresponding third board through a cable, the first board is connected to the second board, and both the first board and the third board are provided with first slots for installing acceleration cards. The second board is provided with a signal relay device, and the first end of the signal relay device is connected to the host node to provide a signal relay function for the data channel between the host node and each acceleration card. Compared with the related art, where installing acceleration cards in the server chassis is restricted by components such as the motherboard in the host and cannot expand the quantity, and installing acceleration cards on an entire acceleration card board conflicts with the space of components such as the power supply in the chassis, through the cable connection relationship between the first board and the third board and between the second board and the third board, the present invention can flexibly adjust the layout of each board in the chassis where the acceleration computing system is located, providing sufficient space for modules such as the power supply that occupy a large amount of space in the chassis. Therefore, it can effectively increase the deployment density of acceleration cards, deploy more acceleration cards in a limited space to achieve a larger-scale computing power cluster.

[0022] The "status management controller" or "management controller" in the embodiments of the present invention may refer to an out-of-band management controller board, which, in addition to the out-of-band monitoring master controller, further includes various bus controllers, logic programmable units, memories, and other components. The "out-of-band management controller" in the embodiments of the present invention may also refer to the out-of-band monitoring master controller on the baseboard management controller board, which may be a single-core processor or a multi-core processor. In the embodiments of the present invention, the out-of-band management controller or the out-of-band monitoring master controller on the out-of-band management controller board may adopt an ARM processor, on which the operating system of the out-of-band management controller runs.

[0023] In devices such as servers, a baseboard management controller (BMC) provides out-of-band management and monitoring capabilities. Typically installed on a motherboard or the mainboard of the monitored device, the BMC uses, but is not limited to, the Intelligent Platform Management Interface (IPMI) protocol to monitor the status of server hardware by monitoring sensors within the server system. The BMC can communicate with internal server modules such as the southbridge (Platform Controller Hub, PCH), memory (such as dual-inline memory modules (DIMMs)), and power supplies using an integrated circuit bus (such as the two-wire serial bus (Inter-Integrated Circuit, I2C)) or the Intelligent Platform Management Bus (IPMB). The baseboard management controller can also be connected to sensors in the server through an integrated circuit bus or an intelligent platform management bus, and use the sensors to monitor the status of the hardware in the server, such as temperature, humidity, power supply voltage, fan speed, communication parameters and operating system (OS) functions, etc., and take action when any of these variables exceeds a specified range. The processing methods may include but are not limited to: recording logs, triggering reset of abnormal components and other abnormal solutions, sending remote alarm information to the remote alarm terminal to notify operation and maintenance personnel to handle the abnormality, etc.

[0024] Figure 1 A schematic diagram of the structure of an accelerated computing system provided by an embodiment of the present invention; Figure 2 A schematic structural diagram of a first board provided in an embodiment of the present invention; Figure 3 A schematic structural diagram of a second board provided in an embodiment of the present invention; Figure 4 A schematic structural diagram of a power supply board provided in an embodiment of the present invention; Figure 5 A schematic diagram of the installation structure of an accelerated computing system provided by an embodiment of the present invention.

[0025] like Figure 1As shown in the figure, the acceleration computing system 100 provided by an embodiment of the present invention may include: a first board 101, a second board 102, and a third board 103; the first board 101 is connected to the third board 103 corresponding to the first board 101 through a cable, and the second board 102 is connected to the third board 103 corresponding to the second board 102 through a cable; the first board 101 is connected to the second board 102; both the first board 101 and the third board 103 are provided with a first slot 105 for installing an acceleration card; the second board 102 is provided with a signal relay device 104, a first end of the signal relay device 104 is connected to the host node 200, and a second end of the signal relay device 104 is correspondingly connected to the first slot 105 on the first board 101 and the first slot 105 on the third board 103.

[0026] In an embodiment of the present invention, the acceleration card may be a Graphics Processing Unit (GPU), a Field-Programmable Gate Array (FPGA), or other types of acceleration cards.

[0027] The first slot 105 is a slot for installing an acceleration card, and the first slot 105 may be a Peripheral Component Interconnect Express (PCIe) slot.

[0028] In an embodiment of the present invention, a first board 101 may be provided with a plurality of first slots 105 for installing a plurality of acceleration cards. A third board 103 may be provided with one or more first slots 105.

[0029] In some optional implementation manners of an embodiment of the present invention, the third board may adopt a small board (Paddle card) provided with a first slot 105, so as to be flexibly arranged in the chassis 116.

[0030] In an embodiment of the present invention, the signal relay device 104 may adopt a retimer, for example, a Physical Layer retimer (PHY retimer) may be adopted.

[0031] In an embodiment of the present invention, the retimer may adopt a retimer chip, and one retimer chip may be used to provide one or more communication channels, which may be respectively used for signal relaying of high-speed data signals, clock signals, etc.

[0032] In an embodiment of the present invention, a second board 102 may be provided with one or more signal relay devices 104. In some alternative embodiments of the embodiment of the present invention, a second board 102 may be provided with four retimer chips for four accelerator cards.

[0033] In some alternative embodiments of the embodiment of the present invention, a third board 103 is provided with a first slot 105; a first board 101 is provided with three first slots 105 and a first connector 109 for connecting to the third board 103 through a cable; a second board 102 is provided with two second connectors 110 for connecting to the third board 103; a first board 101 is connected to two second boards 102; the signal relay devices 104 on a second board 102 altogether provide four data channels.

[0034] In an embodiment of the present invention, the connection between the first board 101 and the second board 102 may include: the gold fingers 112 of the second board 102 are connected to the second slot of the first board 101.

[0035] As Figure 1 shown, Figure 1 only one second board 102 is shown. The second board 102 is provided with four signal relay devices 104. The first ends of the respective signal relay devices 104 are respectively connected to the host node 200 through the third connectors 111 on the second board 102. Two signal relay devices 104 are connected to the first board 101 through the gold fingers 112 between the first board 101 and the second board 102. The other two signal relay devices 104 are respectively connected to the first slots 105 on the third board 103 through the second connectors 110 on the second board 102 and cables in one-to-one correspondence.

[0036] As Figure 3 shown, the first end of the second board 102 is the third connector 111, and the third connector 111 is connected to the host node 200 through a cable. The other end of the second board 102 is the gold fingers 112 for plugging into the gold finger slot 113 of the first board 101. The second board 102 is provided with four signal relay devices 104 (the on-board traces are not shown) for four accelerator cards. The second board 102 is further provided with two second connectors 110 respectively for connecting to the third board 103 through cables.

[0037] As Figure 2 shown, a first board 101 may be provided with three first slots 105 and is connected to the first slot 105 on a third board 103 through the first connector 109 on the first board 101 and a cable. The first board 101 may be provided with two gold finger slots 113 for plugging two second boards 102 as Figure 1 shown.

[0038] Integrated Figure 1 、 Figure 2 、 Figure 3 In some alternative embodiments of the embodiments of the present invention, a first board 101 can directly mount three acceleration cards, and mount one acceleration card through a third board 103 connected by a first connector 109 of the first board 101. After plugging two second boards 102 on the first board 101, each second board 102 is respectively connected to two third boards 103 for mounting two acceleration cards. Thus, in the system formed by one first board 101, two second boards 102 and five third boards 103, a total of eight acceleration cards can be installed, and signal relay on the high-speed link between the acceleration cards and the host node 200 is provided by a total of eight signal relay devices 104 on the two second boards 102.

[0039] In the embodiments of the present invention, the first slot 105 can adopt a PCIe x16 Slot slot, and can support a full-height double-width PCIe card. If a GPU is adopted, it can be compatible with PCIe Gen3, PCIe Gen4 and PCIe Gen5 designs.

[0040] Using the system structure of the three boards introduced above Figure 1 、 Figure 2 、 Figure 3 In an acceleration computing system 100, two such systems can be included, that is, two first boards 101, four second boards 102 and ten third boards 103 are set, and a total of 16 PCIe x16 Slots can be designed, which can support 16 double-width GPUs.

[0041] As Figure 4 shown, the acceleration computing system 100 provided by the embodiments of the present invention may further include a power supply board 114; the power supply board 114 is provided with a power management unit, and the power module 115 of the acceleration computing system 100 is connected to the power management unit through a connection row. The connection row can adopt a multi-layer composite structure connection row (Busbar).

[0042] As Figure 5 shown, the power supply board 114 can be installed in the middle of the chassis 116. If the acceleration computing system 100 for installing 16 GPUs is adopted above, the power supply board 114 can be provided with a power supply unit (Power Supply Unit, PSU) connector to connect with four common redundant power supplies (Common Redundant Power Supply, CRPS), and at the same time, through two unit supply units on a vertical power supply board 114, it is connected to the power supply board 114 through a multi-layer composite structure connection row to provide 3+3 redundant power supply for the acceleration computing system 100.

[0043] As Figure 1 shown, an embodiment of the present invention may further include a state management controller 106 for managing the states of components of the acceleration computing system 100. The state management controller 106 may employ a baseboard management controller (BMC) for managing the states of acceleration cards installed in the acceleration computing system 100, monitoring the temperatures of components of the acceleration computing system 100, implementing a fan control strategy, detecting liquid leakage, etc. An embodiment of the present invention may further include a first power-on controller 107 for controlling the power-on and power-off timing of the acceleration computing system 100. The first power-on controller 107 may employ a complex programmable logic device (CPLD).

[0044] As Figure 5 shown, the state management controller 106 and the first power-on controller 107 may be installed on the power supply board 114. In addition, the first power-on controller 107 may further be used to implement other on-board logic expansions on the power supply board 114, such as reset logic, clock enabling, GPU power-on status LED driving, etc.

[0045] In an embodiment of the present invention, the first connector 109 and the second connector 110 may employ multi-channel input / output connectors (Multi-Channel I / O, MCIO).

[0046] The third connector 111 may employ a compact 400G form-factor pluggable connector (Compact 400G Form-factor Pluggable, CDFP).

[0047] In some alternative embodiments of the embodiment of the present invention, 16 groups of x16 CDFP connectors may directly extend from the rear side of the chassis 116 of the acceleration computing system 100. Each group of x16 CDFP connectors is connected to the x16 CDFP connectors on a first switching board (PCIe switch) through an external CDFP cable (CDFP Cable) to lead out PCIe x16 signals. One end is distributed to the corresponding first slot 105, and the other end is connected to the host node 200 to establish a high-speed link between the CPU of the host node 200 and the acceleration cards installed in the acceleration computing system 100.

[0048] In an embodiment of the present invention, the acceleration computing system 100 may include two first boards 101, four second boards 102, and ten third boards 103, and further includes a power supply board 114, a fan board, etc., providing a total of 16 first slots 105 for x16 PCIe, which can support 16 double-width GPUs.

[0049] As shown Figure 5 in the figure, installed in the chassis 116, the acceleration computing system 100 may include two first boards 101. Each first board 101 has three first slots 105 (PCIE x16 SLOT) for directly installing acceleration cards, and two gold finger slots 113 (PCIE x32 CEM SLOT) for plugging into the second board 102. There is also a first connector 109 (x16 MCIO) on the first board 101 to transmit a group of x16 PCIe signals to the third board 103 through a cable.

[0050] Each second board 102 has 4 second connectors 110 on each side, and the signal relay device 104 is used to extend the transmission distance of the interface and improve the signal quality. The second board 102 is equipped with an x32 gold finger 112 that can be vertically inserted into the gold finger slot 113 on the first board 101 to transmit two groups of x16 PCIe signals to the first board 101. The second board 102 also has 2 x16 second connectors 110 (x16 MCIO) to transmit two groups of x16 PCIe signals to the third board 103 through a cable.

[0051] A total of 8 second connectors 110 (x16 MCIO) are provided by 4 second boards 102. Coupled with one first connector 109 (x16 MCIO) on each of the two first boards 101, there are a total of 10 x16 MCIO connectors, which can be connected to 10 third boards 103 and fixed to the chassis 116 with screws for installing 10 acceleration cards.

[0052] As shown Figure 5 in the figure, through the chassis outer shell structure 117 on the left side of the figure, the third board 103 fixed to the chassis 116 can be seen. The third board 103 is connected to the first connector 109 on the first board 101 or the second connector 110 on the second board 102 on the right side of the figure through a cable, and is also connected to the power connector on the power board 114. The third board 103 is a long strip-shaped printed circuit board (Printed Circuit Board, PCB), and the board is provided with first slots 105. Through the deployment of the third board 103, the space inside the chassis 116 can be fully utilized.

[0053] The acceleration computing system 100 provided by an embodiment of the present invention includes a first board 101, a second board 102, and a third board 103. The first board 101 is connected to the corresponding third board 103 through a cable. The second board 102 is connected to the corresponding third board 103 through a cable. The first board 101 is connected to the second board 102. Both the first board 101 and the third board 103 are provided with a first slot 105 for installing acceleration cards. The second board 102 is provided with a signal relay device 104. The first end of the signal relay device 104 is connected to the host node 200 to provide a signal relay function for the data channel between the host node 200 and each acceleration card. Compared with the related art, in which the acceleration cards are installed in the server chassis 116 and the number cannot be expanded due to limitations such as the motherboard in the host, and the acceleration cards are installed on an entire acceleration card board, resulting in a space conflict with devices such as the power supply in the chassis 116, the present invention can flexibly adjust the layout of each board in the chassis 116 of the acceleration computing system 100 through the cable connection relationship between the first board 101 and the third board 103, and between the second board 102 and the third board 103, providing sufficient space for modules such as the power supply that occupy a large amount of space in the chassis 116. Therefore, the deployment density of the acceleration cards can be effectively increased, and more acceleration cards can be deployed in a limited space to achieve a larger-scale computing power cluster.

[0054] In a traditional server, various components are integrated into a single chassis, and a power supply and heat dissipation system, as well as sensors for detecting the firmware status, are configured inside the chassis. Only acceleration cards are installed in the chassis 116 of the acceleration computing system 100 provided by an embodiment of the present invention. At this time, in order to manage the status of the chassis 116 of the acceleration computing system 100, the acceleration computing system 100 needs to be provided with an independent status management controller 106. After connecting the acceleration computing system 100 to the host node 200, the status management controller 106 of the acceleration computing system 100 needs to be interconnected with the management controller of the host node 200 so that the management controller of the host node 200 can obtain the network address (IP address) and some monitoring data of the dynamic management controller of the acceleration computing system 100, realizing the monitoring and management of the acceleration computing system 100 by the host node 200.

[0055] Then, the acceleration computing system 100 provided by an embodiment of the present invention may further include a status management controller 106 respectively connected to the status signal pins of the signal relay device 104 and the status signal pins of the first slot 105.

[0056] To realize the monitoring and management of the acceleration computing system 100 by the host node 200, the status signal pins of the status management controller 106 are also connected to the management controller of the host node 200.

[0057] In an embodiment of the present invention, the status management controller 106 can be used to upload the identification information of the acceleration cards installed in the acceleration computing system 100 to the host node 200, so that the host node 200 can call the acceleration cards based on the identification information of the acceleration cards.

[0058] Thus, through the connection between the host node 200 and the acceleration cards, and the interconnection between the acceleration cards, the host node 200 can call the acceleration cards as needed to achieve resource pooling. With the pooling ability, artificial intelligence applications can call any number of acceleration cards according to the load requirements, or even aggregate the acceleration cards of multiple acceleration computing systems 100; when the artificial intelligence application stops, the acceleration card resources are released back to the resource pool to facilitate the efficient flow of resources and make full use of them.

[0059] The acceleration computing system 100 provided by the embodiment of the present invention may further include an acceleration card controller (mCPU) respectively connected to the first slot 105. The status signal pin of the acceleration card controller can be connected to the management controller of the host node 200.

[0060] Figure 6 It is a circuit diagram of a second board card provided by an embodiment of the present invention.

[0061] As Figure 6 shown, taking an implementation manner of a second board card 102 provided by an embodiment of the present invention as an example, the second board card 102 is provided with four signal relay devices 104 (signal relay device 1040, signal relay device 1041, signal relay device 1042, signal relay device 1043), and four third connectors 111 (i.e., Figure 6 the third connectors 0, 1, 2, and 3 shown). Each third connector 111 introduces two groups of integrated circuit bus signals from the host node 200, one group for BMC I2C for CDFP ID address recognition, and the other group mCPU I2C for managing the connected acceleration cards through the acceleration card controller (mCPU).

[0062] In Figure 6 it, x = 0, 1, 2, 3.

[0063] The signal relay device may also be provided with debugging pins connected to a debugger, and the debugging pins can be 3-pin headers. Each third connector 111 can separately input a reset signal (PERST_CDFP0, PERST_CDFP1, PERST_CDFP2, PERST_CDFP3) and a power-on enable signal PWR_EN, which are used to control the individual power-on and reset (reset) of each acceleration card by the host node 200.

[0064] As Figure 6As shown, the signal relay device reset (PERSTx) can be controlled by the reset signal (PERSTx_CDFP) output by the host node 200 and the reset signal (PERSTx_CPLD) output by the first power-on controller 107.

[0065] Each third connector 111 can be provided with a group of indicator lights. A red light can be used to indicate a constant on when there is a data transmission failure, which is controlled by the status management controller 106. A green light can be used to indicate a flash when there is data transmission and a constant on when there is no data transmission, which is controlled by the GPIO of the signal relay device 104.

[0066] Each signal relay device 104 can be equipped with a configuration memory for storing the configuration information of the signal relay device 104, such as Figure 6 the configuration memories 0, 1, 2, and 3 shown. The configuration memory can use an electrically erasable programmable read-only memory (EEPROM).

[0067] In the acceleration computing system 100 provided by the embodiment of the present invention, the second board 102 can also be provided with a first bus arbiter; the input ends of the first bus arbiter are respectively connected to the status management controller 106 and the acceleration card controller of the acceleration computing system 100, and the output end of the first bus arbiter is connected to the status signal pin of the signal relay device 104.

[0068] As Figure 6 shown, the first bus arbiter can use PCA9641 to access the integrated circuit bus signal (Retimerx_SMBUS) of the status management controller 106 and the integrated circuit bus signal (mCPU_SMBUSx) of the acceleration card controller to the signal relay device 104.

[0069] In the acceleration computing system 100 provided by the embodiment of the present invention, the second board 102 can also be provided with a second bus arbiter; the input end of the second bus arbiter is connected to the status signal pin of the status management controller 106, and the output end of the second bus arbiter is respectively connected to the status signal pins of multiple signal relay devices 104.

[0070] As Figure 6 shown, Retimer0_SMBUS, Retimer1_SMBUS, Retimer2_SMBUS, Retimer3_SMBUS, the second bus arbiter can use PCA9548 to monitor the status of each signal relay device 104 by the status management controller 106.

[0071] In the acceleration computing system 100 provided by the embodiments of the present invention, the second board 102 may further be provided with a third bus arbiter; the input end of the third bus arbiter is connected to the status signal pin of the status management controller 106, and the output end of the third bus arbiter is respectively connected to the signal status pins of the configuration memories of the signal relay device 104.

[0072] As Figure 6 shown in the EEPROM0_SMBUS, EEPROM1_SMBUS, EEPROM2_SMBUS, EEPROM3_SMBUS, the third bus arbiter may adopt PCA9546 for the status management controller 106 to monitor the status of each configuration memory.

[0073] As Figure 6 shown, on one second board 102, two signal relay devices 104 are connected to the third board 103 through two second connectors 110 (such as Figure 6 the second connector 0 and the second connector 1 shown) and cables. The signal relay device 0 and the signal relay device 1 transmit high-speed data signals x16 PCIe in, x16 PCIe out, as well as status signals (SMBUS0, SMBUS1) and clock signals (GPU0_CLK, GPU1_CLK) between the second connector 0 and the second connector 1 respectively.

[0074] The signal relay device 2 and the signal relay device 3 are connected to the acceleration card installed on the first board 101 through the gold fingers 112 of the second board 102. The signal relay device 2 and the signal relay device 3 transmit high-speed data signals x16 PCIe in, x16 PCIe out, as well as status signals (SMBUS2, SMBUS2) and clock signals (GPU2_CLK, GPU3_CLK) to and from the acceleration card installed on the first board 101.

[0075] In the embodiments of the present invention, the status management controller 106 may be provided on the power supply board 114 of the acceleration computing system 100.

[0076] The acceleration computing system 100 provided by the embodiments of the present invention may further include a first power-on controller 107 connected to the status management controller 106; the first enable pin of the first power-on controller 107 is connected to the host node 200, the second enable pin of the first power-on controller 107 is connected to the status management controller 106, and the third enable pin of the first power-on controller 107 is connected to the power-on / off signal input device 108 of the acceleration computing system 100; the output end of the first power-on controller 107 is respectively connected to the power-on enable pins of the signal relay device 104 and the first slot 105.

[0077] The power-on / off signal input device 108 (PWR Button) can be disposed on the input / output board (IO board) of the chassis 116 of the acceleration computing system 100.

[0078] In an embodiment of the present invention, the status management controller 106 can also be configured to, when the power-on enable signal of the host node 200 is invalid, if a power-on / off signal input from the management interface is received, control the first power-on controller 107 to perform a power-on / off operation.

[0079] Figure 7 It is a circuit diagram of a power-on / off control circuit for an acceleration card provided by an embodiment of the present invention.

[0080] As Figure 7 shown, in an embodiment of the present invention, each acceleration card is independently powered, and the power-on / off of different acceleration cards does not interfere with each other. When the host node 200 establishes an interconnection relationship with the acceleration computing system 100, the power-on / off of the corresponding acceleration card is controlled by the enable signal of the host node 200. When the host node 200 issues a power-on enable (PWR enable) signal for a certain acceleration card, the first power-on controller 107 issues a 12V acceleration card power enable signal (P12V_PWR_EN), a 3.3V acceleration card standby power enable signal (P3V3_STBY_PWR_EN), and a 3.3V acceleration card power enable signal (P3V3_PWR_EN) to supply power to the acceleration card. When the enable signal of any host node 200 is valid, the key operation of the power-on / off signal input device 108 (PWR Button) of the acceleration computing system 100 will be ignored by the first power-on controller 107; meanwhile, the power-on enable switch (PWR_EN Button) of the corresponding acceleration card of the host node 200 on the management interface (BMC WEB) of the status management controller 106 will be in a prohibited operation state. Both the first power-on controller 107 and the status management controller 106 will receive the acceleration card reset (GPU_PRSNT) signal from the first slot 105. When the GPU_PRSNT of a certain first slot 105 is pulled high, it indicates that an acceleration card has been inserted into the first slot 105, and the enable signal from the host node 200 will be valid. Otherwise, the status management controller 106 will save the fault data and notify the first power-on controller 107 to ignore the enable signal from the host node 200.

[0081] When the enable signal of the host node 200 is invalid, the power-on and power-off operations of the corresponding acceleration cards can be implemented through the BMC WEB interface, or the power-on and power-off control of all acceleration cards can be achieved by pressing the button of the power-on and power-off signal input device 108 on the rear IO board. When the PWRBTN button on the BMC WEB interface is pressed, the status management controller 106 will send a control signal (BMC_GPUx_WEB_BTN) to the first power-on controller 107, telling the first power-on controller 107 which acceleration card needs to be powered on. The first power-on controller 107 will then supply the required 12V, 3V3_STBY, and 3V3 power for the acceleration card. When the button of the power-on and power-off signal input device 108 on the rear IO board is pressed, the power-on and power-off signal input device 108 will send a signal to the first power-on controller 107. If some acceleration cards are in the powered-on state, pressing the button can achieve power-off; if all acceleration cards are in the powered-off state, pressing the button can achieve power-on for all acceleration cards.

[0082] The first power-on controller 107 receives the GPU power supply enable signals from the PWR Button on the rear IO board, the Host side, and the BMC respectively. At the same time, the BMC will receive the GPU_PRSNT signal. When the first power-on controller 107 receives the EN signal but does not receive the PRSNT signal of this slot, the first power-on controller 107 will not issue PWR_EN, and the status management controller 106 will record the event.

[0083] The status management controller 106 receives the power-on and power-off enable signals of the acceleration cards from the host node 200 on the one hand, and also receives the power-on and power-off enable signals of the acceleration cards output by the first power-on controller 107 and the VR output P3V3_GPUx_PWRGD GPU power-on status signal. Through the internal logic judgment of the status management controller 106, the power supply status of the acceleration cards is displayed on the BMC WEB interface.

[0084] In addition, the CDFP_EN signal of the host node 200 is also connected to the first board 101 through the gold finger 112, and then connected to the status management controller 106 / first power-on controller 107 of the power supply board 114 through a cable. The signals do not affect each other, realizing the independent power-on and power-off control of the acceleration cards.

[0085] The first board 101 is connected to the power supply board 114 through a 2X6 power connector to obtain 12V, 12V_GPUx (x = 0, 1, 2, the same below), and 3V3_STBY power. Three power (VR) chips are placed on each first board 101 to generate 3V3_GPUx. 3V3_STBY_GPUx is also branched out by the switch chip on the first board 101. Each 3V3_GPUx and 3V3_STBY_GPUx has its own enable signal, which is connected to the first power-on controller 107 of the power supply board 114 through an x8 MCIO connector. The first power-on controller 107 controls the individual power-on and power-off of each accelerator card.

[0086] As Figure 6 shown, three I2C signals come from the status management controller 106 on the power supply board 114, which are respectively used for the ID recognition and clock management of the accelerator card, as well as for managing the signal relay device 104, connecting sensors and field replaceable units (FRUs). A temperature detector is provided on the first board 101. The temperature detector can use TMP75. Five temperature detectors can be provided on the first board 101 to monitor the temperature, and the board configuration information is obtained through 1 field replaceable unit.

[0087] The acceleration computing system 100 provided by the embodiment of the present invention may further include a first clock generator; the output ends of the first clock generator are respectively connected to the clock pin of the signal relay device 104 and the clock pin of the first slot 105.

[0088] A first clock generator may also be provided on the first board 101. The first clock generator can use CK440 to provide an asynchronous clock for the entire system. CK440 emits 8 groups of clock signals, which are connected to the gold finger 112 and are designed for compatibility (Colay) with the synchronous clock sent from the host node 200 on the second board 102.

[0089] As Figure 6 shown, the 100M CLK output by each group of third connectors 111 has unreliable signal quality due to too long wiring, and a reserved design is made. The clock is provided by CK440 on the first board 101.

[0090] As Figure 6 shown, the clock signal (CLK) output by the third connector 111 passes through a clock buffer to provide clock signals Retimerx_CLK and GPUx_CLK for the signal relay device 104 and the accelerator card.

[0091] Using the acceleration computing system 100 provided by the embodiments of the present invention, resource pooling of 16 GPUs can be achieved within a 4U chassis 116. The power-on and power-off of each GPU do not interfere with each other and are managed separately. Data exchange is performed with the interconnection module through CDFP cables. In the case of insufficient GPU resources, GPU tasks can be queued and the queue priorities can be set. When resource contention occurs among multiple GPU tasks, resource guarantee can be provided for high-priority tasks.

[0092] An embodiment of the present invention further provides a computing system, which may include: a host node 200 and an acceleration computing system 100.

[0093] Among them, the acceleration computing system 100 may include: a first board 101, a second board 102, and a third board 103; the first board 101 is connected to the third board 103 corresponding to the first board 101 through a cable, and the second board 102 is connected to the third board 103 corresponding to the second board 102 through a cable; the first board 101 is connected to the second board 102; the first board 101 and the third board 103 are both provided with a first slot 105 for installing an acceleration card; the second board 102 is provided with a signal relay device 104, a first end of the signal relay device 104 is connected to the host node 200, and a second end of the signal relay device 104 is correspondingly connected to the first slot 105 on the first board 101 and the first slot 105 on the third board 103.

[0094] The computing system provided by the embodiments of the present invention may further include a first switching board; a first end of the first switching board is connected to the host node 200, and a second end of the first switching board is connected to a first end of the signal relay device 104.

[0095] In the computing system provided by the embodiments of the present invention, multiple acceleration cards are interconnected; the acceleration computing system 100 may further include a status management controller 106, and the status management controller 106 is used to upload the identification information of the acceleration cards installed in the acceleration computing system 100 to the host node 200, so that the host node 200 can call the acceleration cards based on the identification information of the acceleration cards.

[0096] In the computing system provided by the embodiments of the present invention, it may include one or more host nodes 200, and may also include one or more acceleration computing systems 100. The host node 200 and the acceleration computing system 100 may form a one-to-one correspondence, a one-to-many correspondence, or a many-to-one correspondence. After establishing the connection between the host node 200 and the acceleration computing system 100 through the bus and the first switching board, through the connection between the host node 200 and the acceleration card, and the interconnection between the acceleration cards, the host node 200 can call the acceleration cards as needed to achieve resource pooling. With the pooling ability, the artificial intelligence application can call any number of acceleration cards according to the load demand, and even aggregate the acceleration cards of multiple acceleration computing systems 100; when the artificial intelligence application stops, the acceleration card resources are released back to the resource pool to facilitate the efficient flow of resources and make full use of them.

[0097] The acceleration computing system 100 may further include an acceleration card controller (mCPU) respectively connected to the acceleration cards.

[0098] For the specific implementation manners of the computing system provided by the embodiments of the present invention, reference may be made to the introduction of the embodiments of the acceleration computing system 100 above, and details will not be elaborated herein.

[0099] The computing system provided by the embodiments of the present invention includes a host node and an acceleration computing system 100. The acceleration computing system 100 includes a first board 101, a second board 102, and a third board 103. The third board 103 corresponding to the first board 101 is connected to the first board 101 through a cable, and the third board 103 corresponding to the second board 102 is connected to the second board 102 through a cable. The first board 101 is connected to the second board 102. Both the first board 101 and the third board 103 are provided with first slots 105 for installing acceleration cards. The second board 102 is provided with a signal relay device 104. The first end of the signal relay device 104 is connected to the host node 200 to provide a signal relay function for the data channel between the host node 200 and each acceleration card. Compared with the related art, in which the acceleration cards are installed in the server chassis 116 and the number cannot be expanded due to the limitations of the motherboard in the host, and the acceleration cards are installed on an entire acceleration card board, resulting in a space conflict with devices such as the power supply in the chassis 116, in the embodiments of the present invention, through the cable connection relationship between the first board 101 and the third board 103, and between the second board 102 and the third board 103, the layout of each board in the chassis 116 where the acceleration computing system 100 is located can be flexibly adjusted, providing sufficient space for modules such as the power supply that occupy a large space in the chassis 116. Based on this, the computing system provided by the embodiments of the present invention may include one or more host nodes and one or more acceleration computing systems 100. The host node can more flexibly call the computing resources of the acceleration cards, and more acceleration cards can be deployed in a limited space to achieve a larger-scale computing power cluster.

[0100] Those skilled in the art may further realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the above description. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0101] The above has introduced in detail an acceleration computing system and a computing system provided by the present invention. Specific examples are used herein to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. An accelerated computing system, characterized in that, Including: The first board, the second board and the third board; The first board is connected to the corresponding third board by a cable, and the second board is connected to the corresponding third board by a cable; The first board is connected to the second board; Both the first board and the third board are provided with a first slot for installing an acceleration card; The second board is provided with a signal relay device. The first end of the signal relay device is connected to the host node, and the second end of the signal relay device is correspondingly connected to the first slot on the first board and the first slot on the third board.

2. The acceleration computing system according to claim 1, wherein One of the first boards is provided with a plurality of the first slots; One of the third boards is provided with one or more of the first slots.

3. The acceleration computing system according to claim 2, wherein One of the third boards is provided with one of the first slots; One of the first boards is provided with three of the first slots and a first connector for connecting the third board by a cable; One of the second boards is provided with two second connectors for connecting the third board; One of the first boards is connected to two of the second boards; The signal relay device on one of the second boards provides a total of four data channels.

4. The acceleration computing system according to claim 1, wherein It further includes a status management controller respectively connected to the status signal pin of the signal relay device and the status signal pin of the first slot.

5. The acceleration computing system according to claim 4, wherein The status signal pin of the status management controller is connected to the management controller of the host node.

6. The acceleration computing system according to claim 4, wherein The status management controller is used to upload the identification information of the acceleration card installed in the acceleration computing system to the host node, so that the host node can call the acceleration card based on the identification information of the acceleration card.

7. The acceleration computing system according to claim 4, wherein The second board is further provided with a first bus arbiter; The input ends of the first bus arbiter are respectively connected to the status management controller and the acceleration card controller of the acceleration computing system, and the output end of the first bus arbiter is connected to the status signal pin of the signal relay device.

8. The acceleration computing system according to claim 4, wherein The second board is further provided with a second bus arbiter; The input end of the second bus arbiter is connected to the status signal pin of the status management controller, and the output end of the second bus arbiter is respectively connected to the status signal pins of a plurality of the signal relay devices.

9. The acceleration computing system according to claim 4, wherein The second board is further provided with a third bus arbiter; The input end of the third bus arbiter is connected to the status signal pin of the status management controller, and the output end of the third bus arbiter is respectively connected to the signal status pins of the configuration memory of the signal relay device.

10. The accelerated computing system according to claim 4, wherein The status management controller is arranged on the power supply board of the acceleration computing system.

11. The acceleration computing system according to claim 4, wherein It further includes a first power-on controller connected to the status management controller; The first enable pin of the first power-on controller is connected to the host node, the second enable pin of the first power-on controller is connected to the status management controller, and the third enable pin of the first power-on controller is connected to the power-on and power-off signal input device of the acceleration computing system; the output end of the first power-on controller is respectively connected to the power-on enable pin of the signal relay device and the power-on enable pin of the first slot.

12. The acceleration computing system according to claim 11, wherein The state management controller is used to control the first power-on controller to perform power-on and power-off operations when the power-on enable signal of the host node is invalid and a power-on and power-off signal input by the management interface is received.

13. The acceleration computing system according to claim 4, wherein The signal relay device is further provided with debugging pins for connecting a debugger.

14. The acceleration computing system according to claim 1, wherein It further includes an acceleration card controller respectively connected to the first slot.

15. The acceleration computing system according to claim 14, wherein The status signal pin of the acceleration card controller is connected to the management controller of the host node.

16. The accelerated computing system according to claim 1, wherein It further includes a first clock generator; The output end of the first clock generator is respectively connected to the clock pin of the signal relay device and the clock pin of the first slot.

17. The acceleration computing system according to claim 1, wherein It further includes a power supply board; The power supply board is provided with a power management unit, and the power module of the acceleration computing system is connected to the power management unit through a connection row.

18. The acceleration computing system according to claim 1, wherein The first board is connected to the second board, including: The gold finger of the second board is connected to the second slot of the first board.

19. The acceleration computing system according to claim 3, wherein Both the first connector and the second connector are multi-channel input / output connectors.

20. The acceleration computing system according to claim 1, wherein The signal relay device is a retimer.

21. A computing system, characterized in that, Including: A host node and an acceleration computing system; The acceleration computing system includes: a first board, a second board, and a third board; The first board is connected to the corresponding third board of the first board through a cable, and the second board is connected to the corresponding third board of the second board through a cable; The first board is connected to the second board; Both the first board and the third board are provided with first slots for installing acceleration cards; The second board is provided with a signal relay device, the first end of the signal relay device is connected to the host node, and the second end of the signal relay device is correspondingly connected to the first slot on the first board and the first slot on the third board.

22. The computing system according to claim 21, wherein It further includes a first switching board; The first end of the first switching board is connected to the host node, and the second end of the first switching board is connected to the first end of the signal relay device.

23. The computing system according to claim 21, wherein Multiple acceleration cards are interconnected; The acceleration computing system further includes a state management controller, and the state management controller is used to upload the identification information of the acceleration cards installed in the acceleration computing system to the host node so that the host node can call the acceleration cards based on the identification information of the acceleration cards.

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