Memory, acceleration unit and electronic device

Abstract

The embodiment of the invention provides a memory, an acceleration unit and electronic equipment, the memory comprises a logic chip, a compensation unit and a plurality of memory chips; the logic chip, the compensation unit and the plurality of storage chips are vertically stacked, and the plurality of storage chips are located between the compensation unit and the logic chip; the logic chip is electrically connected with the attached storage chips, the attached storage chips are electrically connected, and the compensation unit is electrically connected with the attached storage chips; the compensation unit comprises a capacitive element, and the capacitive element is electrically connected in a connecting circuit of the compensation unit and the storage chip; and the logic chip is used for receiving a read-write request and reading and writing the storage chip according to the read-write request. The signal integrity of the power supply signal and the read-write signal received by the storage chip far away from the logic chip is high.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of chip technology, and in particular, to a memory, an acceleration unit, and an electronic device. Background Art

[0002] With the rapid development of fields such as big data, artificial intelligence, and cloud computing, the demand for memory by hosts and servers is increasing day by day. Currently, by stacking multiple memory chips, a memory with a relatively small occupied space and a large capacity is formed to meet the memory requirements of hosts and servers.

[0003] However, due to reasons such as line loss and external interference, the signal integrity of the power supply signal and the read / write signal received by the memory chips stacked on the upper layer is poor, resulting in poor read / write performance of the memory chips stacked on the upper layer. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory, an acceleration unit, and an electronic device to at least solve or alleviate the above problems.

[0005] According to a first aspect of the embodiments of the present disclosure, there is provided a memory, including: a logic chip, a compensation unit, and a plurality of memory chips; the logic chip, the compensation unit, and the plurality of memory chips are vertically stacked, and the plurality of memory chips are located between the compensation unit and the logic chip; the logic chip is electrically connected to the adjacent memory chip, the adjacent memory chips are electrically connected to each other, and the compensation unit is electrically connected to the adjacent memory chips; the compensation unit includes a capacitive element, and the capacitive element is electrically connected in the connection circuit between the compensation unit and the memory chip; the logic chip is configured to receive a read / write request and perform read / write operations on the memory chip according to the read / write request.

[0006] According to a second aspect of the embodiments of the present disclosure, there is provided an acceleration unit, including: a substrate, a processing unit, and at least one memory as described in the first aspect above; the processing unit is electrically connected to the substrate, the logic chip in the memory is electrically connected to the substrate, and the processing unit and the memory are located on the same side of the substrate; the processing unit is configured to send a read / write request to the logic chip, so that the logic chip performs read / write operations on the memory chips in the memory according to the read / write request.

[0007] According to a third aspect of the embodiments of the present disclosure, there is provided an electronic device, including: an acceleration unit as described in the second aspect above.

[0008] As can be seen from the above technical solutions, the memory includes a logic chip, a compensation unit, and multiple memory chips. The compensation unit includes capacitive elements, and the capacitive elements are electrically connected in the connection circuit between the compensation unit and the memory chips. The multiple memory chips are located between the compensation unit and the logic chip. Thus, capacitive compensation can be provided for the memory through the capacitive elements in the compensation unit, increasing the total capacitance value of the circuits in the memory. Moreover, the capacitive elements can perform high-frequency filtering on the signals transmitted in the memory circuits, reducing signal interference, so that the power supply signals and read / write signals received by the memory chips farther from the logic chip have higher signal integrity, and the power supply quality and read / write performance of the memory chips farther from the logic chip can be improved. And because there is a compensation unit, the capacitive elements in the compensation unit can provide capacitance values. Therefore, fewer capacitive compensation structures can be arranged in the memory chips, which can reduce the design and production difficulty of the memory chips and the cost of the memory chips. Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0010] Figure 1 is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0011] Figure 2 is a schematic diagram of an equivalent circuit of a memory according to an embodiment of the present disclosure;

[0012] Figure 3 is a schematic diagram of a memory including N memory chips according to an embodiment of the present disclosure;

[0013] Figure 4 is a schematic diagram of a memory including N memory chips according to another embodiment of the present disclosure;

[0014] Figure 5 is a schematic diagram of a memory including multiple auxiliary chips according to an embodiment of the present disclosure;

[0015] Figure 6 is a schematic diagram of an equivalent circuit of a memory according to another embodiment of the present disclosure;

[0016] Figure 7 is a schematic diagram of an acceleration unit according to an embodiment of the present disclosure;

[0017] Figure 8 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Embodiments

[0018] The present disclosure will be described based on embodiments, but the present disclosure is not limited to these embodiments. In the following detailed description of the present disclosure, some specific details are described in detail. Those skilled in the art can fully understand the present disclosure without the description of these details. In order to avoid obscuring the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. Additionally, the accompanying drawings are not necessarily drawn to scale.

[0019] First, some nouns or terms that appear in the process of describing the embodiments of the present disclosure are applicable to the following explanations.

[0020] Acceleration unit: In view of the low efficiency of traditional processors in some special-purpose fields (such as data reading, etc.), a processing unit designed to improve the data processing speed in these special-purpose fields. In the embodiments of the present disclosure, it is mainly a special processing unit designed to improve the speed of accessing DDR.

[0021] Memory: Memory is a hardware device in a computer system used to temporarily store data and instructions and is an important part of the operation of a computer. The main function of memory is to provide a data storage space for quick access for a processor (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU), an artificial intelligence (AI) processor, etc., so as to efficiently execute programs and process tasks.

[0022] Dynamic random access memory: Dynamic Random Access Memory (DRAM) is a commonly used computer memory. Usually, a transistor and a capacitor are used to represent a bit, and the stored data will be lost after the power is cut off.

[0023] Memory

[0024] Figure 1 The schematic diagram of a memory according to an embodiment of the present disclosure is shown. As Figure 1As shown, the memory 100 includes a logic chip 101, a compensation unit 103, and multiple memory chips 102. The logic chip 101, the compensation unit 103, and the multiple memory chips 102 are vertically stacked, and the multiple memory chips 102 are located between the compensation unit 103 and the logic chip 101. The logic chip 101 is electrically connected to the adjacent memory chip 102, the adjacent memory chips 102 are electrically connected to each other, and the compensation unit 103 is electrically connected to the adjacent memory chip 102. The compensation unit 103 includes capacitive elements, and the capacitive elements are electrically connected in the connection circuit between the compensation unit 103 and the memory chip 102. The logic chip 101 can receive read / write requests and perform read / write operations on the memory chip 102 according to the read / write requests.

[0025] The memory 100 includes a logic chip 101, a compensation unit 103, and multiple memory chips 102. As an example, Figure 1 Fig. shows a memory 100 including 5 memory chips 102. The multiple memory chips 102 are stacked on one side of the logic chip 101, and the multiple memory chips 102 are located between the compensation unit 103 and the logic chip 101, so as to Figure 1 As an example, the compensation unit 103 and the logic chip 101 are respectively arranged on both sides of the stacked multiple memory chips 102.

[0026] The compensation unit 103 includes capacitive elements. The logic chip 101 is electrically connected to the adjacent memory chip 102, the adjacent memory chips 102 are electrically connected to each other, and the compensation unit 103 is electrically connected to the adjacent memory chip 102, so that the capacitive elements are electrically connected in the connection circuit between the compensation unit 103 and the memory chip 102. The capacitive elements can act as capacitors in the circuit. When the capacitive elements are electrically connected in the connection circuit between the compensation unit 103 and the memory chip 102, they can provide capacitive compensation for the memory 100 circuit. In one example, Figure 2 is a schematic diagram of the equivalent circuit of a memory according to an embodiment of the present disclosure. As Figure 2 shown, the logic chip 101 can be equivalent to a first capacitor C1 and a first resistor R1, the electrical connection line can be equivalent to a second resistor R2, each memory chip 102 can be equivalent to a second capacitor C2 and a third resistor R3, and the compensation unit 103 can be equivalent to a third capacitor C3 and a fourth resistor R4. It should be understood that the capacitive elements in the compensation unit 103 can be equivalent to the third capacitor C3, and the compensation unit 103 has a certain resistance value and can be equivalent to the fourth resistor R4. The adjacent memory chips 102 among the multiple memory chips 102 are electrically connected to each other, so that the multiple memory chips 102 and the logic chip 101 are equivalent to a parallel connection, and the third capacitor C3 equivalent to the compensation unit 103 is connected in parallel with the memory chip 102 and the logic chip 101. As Figure 2In the equivalent circuit shown, the capacitive element in the compensation unit 103 provides capacitive compensation for the circuit, increasing the total capacitance in the circuit. Moreover, the compensation unit 103 can perform high-frequency filtering on the signal, enabling the power signal and read / write signal received by the memory chip 102 that is relatively far from the logic chip 101 to have high signal integrity.

[0027] The logic chip 101 is electrically connected to each memory chip 102 respectively. After receiving a read / write request, the logic chip 101 analyzes the read / write request to determine the read / write address of the memory chip 102 requested to be read / written in the read / write request, and performs read / write operations on the memory chip 102 corresponding to the read / write address according to the read / write request. Optionally, the logic chip 101 can send a power signal to the memory chip 102 through a first line, and can send a read / write signal to the memory chip 102 through a second line to achieve power supply and read / write of the memory chip 102.

[0028] Optionally, since the capacitive element in the compensation unit 103 can provide capacitive compensation for the memory 100, only a partial capacitive compensation structure can be provided in the memory chip 102, or no capacitive compensation structure can be provided in the memory chip 102, which can reduce the design difficulty and production difficulty of the memory chip 102 and reduce the cost of the memory chip 102.

[0029] In an embodiment of the present disclosure, the memory 100 includes a logic chip 101, a compensation unit 103, and a plurality of memory chips 102. The compensation unit 103 includes a capacitive element, and the capacitive element is electrically connected in the connection circuit between the compensation unit 103 and the memory chip 102. The plurality of memory chips 102 are located between the compensation unit 103 and the logic chip 101. Thus, the capacitive element in the compensation unit 103 can provide capacitive compensation for the memory 100, increasing the total capacitance of the circuit in the memory 100. Moreover, the capacitive element can perform high-frequency filtering on the signal transmitted in the memory 100 circuit, reducing signal interference, enabling the power signal and read / write signal received by the memory chip 102 that is relatively far from the logic chip 101 to have high signal integrity, and improving the power quality and read / write performance of the memory chip 102 that is relatively far from the logic chip 101. And because there is a compensation unit 103, the capacitive element in the compensation unit 103 can provide a capacitance value, so fewer capacitive compensation structures can be provided in the memory chip 102, which can reduce the design and production difficulty of the memory chip 102 and reduce the cost of the memory chip 102.

[0030] Figure 3 is a schematic diagram of a memory including N memory chips according to an embodiment of the present disclosure. As Figure 3As shown in the figure, the memory 100 includes N memory chips 102, where N is an integer greater than 2; the first surface of the first memory chip 102 among the N memory chips 102 is attached to the first surface of the logic chip 101, the first surface of the nth memory chip 102 among the N memory chips 102 is attached to the second surface of the (n - 1)th memory chip 102, the nth memory chip 102 is electrically connected to the logic chip 101 through the first to (n - 1)th memory chips 102, the compensation unit 103 is attached to the second surface of the Nth memory chip 102 among the N memory chips 102, and the compensation unit 103 is electrically connected to the logic chip 101 through the N memory chips 102, where n is an integer greater than or equal to 2 and less than or equal to N.

[0031] The memory 100 includes N memory chips 102. The N memory chips 102 are stacked in sequence on one side of the logic chip 101. The compensation unit 103 is attached to the Nth memory chip 102, such that the N memory chips 102 are located between the compensation unit 103 and the logic chip 101.

[0032] The following is an illustration with N = 5. When N = 5, n can be 2, 3, 4, and 5.

[0033] The first surface of the first memory chip 102 among the 5 memory chips 102 is attached to the first surface of the logic chip 101, the first surface of the second memory chip 102 is attached to the second surface of the first memory chip 102, the first surface of the third memory chip 102 is attached to the second surface of the second memory chip 102, the first surface of the fourth memory chip 102 is attached to the second surface of the third memory chip 102, the first surface of the fifth memory chip 102 is attached to the second surface of the fourth memory chip 102, and the first surface of the compensation unit 103 is attached to the second surface of the fifth memory chip 102. The first memory chip 102 is electrically connected to the logic chip 101, the second memory chip 102 is electrically connected to the logic chip 101 through the first memory chip 102, the third memory chip 102 is electrically connected to the logic chip 101 through the first memory chip 102 and the second memory chip 102, the fourth memory chip 102 is electrically connected to the logic chip 101 through the first to third memory chips 102, the fifth memory chip 102 is electrically connected to the logic chip 101 through the first to fourth memory chips 102, and the compensation unit 103 is electrically connected to the logic chip 101 through the first to fifth memory units, such that the capacitive element in the compensation unit 103 is electrically connected in the connection circuit between the compensation unit 103 and the memory chip 102.

[0034] In an embodiment of the present disclosure, a plurality of memory chips 102 are sequentially stacked on one side of the logic chip 101, realizing the stacked arrangement of the memory chips 102, and the plurality of memory chips 102 are respectively electrically connected to the logic chip 101, enabling the logic chip 101 to read and write any one of the memory chips 102 electrically connected to the logic chip 101 according to read and write requests, meeting the read and write requirements. The capacitive element of the compensation unit 103 is electrically connected in the circuit, which can provide capacitive compensation for the circuit of the memory 100, increase the total capacitance of the circuit in the memory 100, and can perform high-frequency filtering on the signals transmitted in the circuit of the memory 100 through the capacitive element, reducing signal interference, so that the power supply signal and the read and write signal received by the memory chip 102 farther from the logic chip 101 have higher signal integrity, and can improve the power supply quality and read and write performance of the memory chip 102 farther from the logic chip 101.

[0035] Figure 4 FIG. is a schematic diagram of a memory including N memory chips according to another embodiment of the present disclosure. As Figure 4 shown, the compensation unit 103 is electrically connected to the Nth memory chip 102 through micro-bumps, the nth memory chip 102 is electrically connected to the (n - 1)th memory chip 102 through micro-bumps, and the logic chip 101 is electrically connected to the first memory chip 102 through micro-bumps.

[0036] The first memory chip 102 is electrically connected to the logic chip 101 through micro-bumps, the compensation unit 103 is electrically connected to the Nth memory chip 102 through micro-bumps, and adjacent memory chips 102 are electrically connected through micro-bumps. In one example, the memory chip 102 may adopt the through-silicon via technology, and the nth memory chip 102 is electrically connected to the logic chip 101 through the first to (n - 1)th memory chips 102 by a metal layer formed in the through-hole, and the compensation unit 103 is electrically connected to the logic chip 101 through the first to Nth memory chips 102. For example, the fourth memory chip 102 is electrically connected to the logic chip 101 through the first to third memory chips 102, the fifth memory chip 102 is electrically connected to the logic chip 101 through the first to fourth memory chips 102. When N = 5, the compensation unit 103 is electrically connected to the logic chip 101 through the first to fifth memory chips 102.

[0037] In an embodiment of the present disclosure, the compensation unit 103 is electrically connected to the Nth memory chip 102 through microbumps. The nth memory chip 102 is electrically connected to the (n - 1)th memory chip 102 through microbumps. The logic chip 101 is electrically connected to the first memory chip 102 through microbumps, realizing electrical connection between the chips. Through the microbumps, the compensation unit 103, multiple memory chips 102, and the logic chip 101 can be stacked, and the vertical connection through the microbumps shortens the distance between the chips, reducing the resistance and parasitic capacitance in signal transmission and reducing signal delay.

[0038] In a possible implementation, the compensation unit 103 includes at least one auxiliary chip, and the auxiliary chip includes capacitive elements.

[0039] The compensation unit 103 may include at least one auxiliary chip, and the auxiliary chip includes capacitive elements. In one example, the auxiliary chip may be a failed memory chip 102, for example, a memory chip 102 damaged during the production process.

[0040] In an embodiment of the present disclosure, the compensation unit 103 includes at least one auxiliary chip, and the auxiliary chip includes capacitive elements. Capacitive compensation can be provided for the memory 100 through the auxiliary chip, increasing the total capacitance value in the circuit. Moreover, the capacitive elements in the auxiliary chip can perform high-frequency filtering on the signal, enabling the memory chip 102 farther from the logic chip 101 to receive power signals and read / write signals with higher signal integrity.

[0041] Figure 5 It is a schematic diagram of a memory including multiple auxiliary chips according to an embodiment of the present disclosure. As Figure 5 shown, the compensation unit 103 includes multiple auxiliary chips 1031. The multiple auxiliary chips 1031 are vertically stacked and electrically connected between the adjacent auxiliary chips 1031. Moreover, the capacitive elements included in the auxiliary chips 1031 are electrically connected in the connection circuit between the auxiliary chips 1031. The bottom auxiliary chip 1031 is electrically connected to the adjacent memory chip 102, and the capacitive elements included in the bottom auxiliary chip 1031 are electrically connected in the connection circuit between the bottom auxiliary chip 1031 and the adjacent memory chip 102.

[0042] When the compensation unit 103 includes multiple auxiliary chips 1031, the multiple auxiliary chips 1031 are stacked, and the adjacent auxiliary chips 1031 are electrically connected. In one example, as Figure 5As shown, the auxiliary chips 1031 in contact with each other can be electrically connected through microbumps. In another example, the auxiliary chips 1031 can adopt the through-silicon via technology, and the plurality of auxiliary chips 1031 are respectively electrically connected to the memory chip 102 and the logic chip 101 through the metal layer formed in the through holes. That is, the capacitive elements included in the auxiliary chips 1031 are electrically connected in the connection circuit between the auxiliary chips 1031, and the capacitive elements included in the bottom auxiliary chips 1031 are electrically connected in the connection circuit between the bottom auxiliary chips 1031 and the memory chip 102 in contact therewith.

[0043] Figure 6 FIG. shows a schematic diagram of an equivalent circuit of a memory according to another embodiment of the present disclosure. As Figure 6 shown, the logic chip 101 can be equivalent to a first capacitor C1 and a first resistor R1, the electrical connection line can be equivalent to a second resistor R2, each memory chip 102 can be equivalent to a second capacitor C2 and a third resistor R3, and each auxiliary chip 1031 can be equivalent to a third capacitor C3 and a fourth resistor R4. As Figure 6 shown, the auxiliary chips 1031 in contact with each other are electrically connected, and the third capacitor C3 equivalent to the capacitive element included in the auxiliary chip 1031 is electrically connected in the connection circuit between the auxiliary chips 1031, and the third capacitor C3 equivalent to the capacitive element included in the bottom auxiliary chip 1031 close to the memory chip 102 is electrically connected in the connection circuit between the bottom auxiliary chip 1031 and the memory chip 102 in contact therewith. It should be understood that the capacitive element in the auxiliary chip 1031 can be equivalent to the third capacitor C3, and the auxiliary chip 1031 has a certain resistance and can be equivalent to the fourth resistor R4.

[0044] In the embodiment of the present disclosure, the compensation unit 103 includes a plurality of auxiliary chips 1031, and the plurality of auxiliary chips 1031 are vertically stacked. The capacitive elements in the plurality of stacked auxiliary chips 1031 can provide capacitive compensation for the memory 100, increase the total capacitance value of the circuit in the memory 100, and can perform high-frequency filtering on the signals transmitted in the memory 100 circuit through the capacitive elements, reduce signal interference, so that the power supply signal and read / write signal received by the memory chip 102 far from the logic chip 101 have high signal integrity, can improve the power supply quality and read / write performance of the memory chip 102 far from the logic chip 101, and because a plurality of auxiliary chips 1031 are provided, a relatively high capacitive compensation can be provided, so that the memory chip 102 does not need to be provided with a capacitive compensation structure, which can reduce the design and production difficulty of the memory chip 102 and reduce the cost of the memory chip 102.

[0045] In a possible implementation manner, the circuit structures of the auxiliary chip 1031 and the memory chip 102 are the same.

[0046] Optionally, the auxiliary chip 1031 can be used as a spare storage chip 102. When all the storage chips 102 are valid, for example, all the storage chips 102 are good products during the production of the memory 100, the auxiliary chip 1031 is only set as a capacitive element in the memory 100 and does not participate in storing data. When there are failed storage chips 102 among the storage chips 102, for example, there are defective storage chips 102 in the memory 100 during the production process, the auxiliary chip 1031 can be used to replace the failed storage chips 102 to store data. Specifically, the logic chip 101 can receive a configuration instruction, and according to the received configuration instruction, determine the target storage chip 102 and the target auxiliary chip 1031. The target storage chip 102 is the failed storage chip 102, and the target auxiliary chip 1031 is the auxiliary chip 1031 that replaces the target storage chip 102 to store data. Determine the mapping relationship between the read / write address of the target storage chip 102 and the read / write address of the target auxiliary chip 1031, and after receiving a read / write request for reading and writing to the target storage chip 102, read and write to the target auxiliary chip 1031 according to the read / write request and the mapping relationship.

[0047] Optionally, the auxiliary chip 1031 can also be a defective storage chip 102 during production. It should be understood that when the auxiliary chip 1031 is a defective storage chip 102 during production, the auxiliary chip 1031 needs to include complete capacitive elements, and the capacitive elements included in the auxiliary chip 1031 can be electrically connected in the connection circuit between the compensation unit 103 and the storage chip 102.

[0048] In the embodiment of the present disclosure, the circuit structures of the auxiliary chip 1031 and the storage chip 102 are the same. Thus, the auxiliary chip 1031 can be used as a spare storage chip 102. When the storage chip 102 fails, the auxiliary chip 1031 can be used to replace the storage chip 102 to store data, so that the failure of some storage chips 102 in the memory 100 will not affect the working performance of the memory 100, the yield rate of the memory 100 during the production process can be improved, and the production cost can be reduced. The failed storage chips 102 during the production process can also be used as the auxiliary chip 1031. Thus, the failed storage chips 102 can be utilized without the need to additionally produce the auxiliary chip 1031, and the production cost can be reduced.

[0049] In a possible implementation manner, the capacitive element includes a deep trench capacitor.

[0050] In an embodiment of the present disclosure, the capacitive element of the compensation unit 103 includes a deep trench capacitor, which can achieve a higher capacitance value under the same planar area, provide higher capacitive compensation for the memory 100 circuit, enable fewer capacitive compensation structures to be designed or no capacitive compensation structure to be designed in the storage chip 102, reduce the design and production difficulty of the storage chip 102, and reduce the cost of the storage chip 102.

[0051] In a possible implementation, the storage chip 102 includes a dynamic random access memory.

[0052] In an embodiment of the present disclosure, the storage chip 102 includes a DRAM, which enables the storage chip 102 to have high read and write performance, and enables the memory 100 to be used as the memory of a host or a server.

[0053] Acceleration Unit

[0054] Figure 7 The schematic diagram of an acceleration unit according to an embodiment of the present disclosure is shown. As Figure 7 shown, the acceleration unit 200 includes a substrate 201, a processing unit 202, and at least one memory 100. The processing unit 202 is electrically connected to the substrate 201, the logic chip 101 in the memory 100 is electrically connected to the substrate 201, and the processing unit 202 and the memory 100 are located on the same side of the substrate 201. The processing unit 202 is configured to send read / write requests to the logic chip 101, so that the logic chip 101 reads and writes the storage chip 102 in the memory 100 according to the read / write requests.

[0055] The acceleration unit 200 may be provided with multiple memories 100, and the multiple memories 100 and the processing unit 202 are all located on the same side of the substrate 201. For example, the acceleration unit 200 includes 3 memories 100, each memory 100 includes 9 storage chips 102, so that the acceleration unit 200 includes 27 storage chips 102. The processing unit 202 in the acceleration unit 200 may be a chip with processing capabilities such as a CPU or a GPU. When a program running on the processing unit 202 needs to read and write the memory 100, the processing unit 202 may send read / write requests to the logic chip 101 in the memory 100, so that the logic chip 101 in the memory 100 executes read / write tasks based on the read / write requests. The memory 100 in the present disclosure may be the memory 100 in any of the above embodiments, and the structure of the memory 100 and the interaction logic between the chips can be seen in the description of any of the above embodiments.

[0056] In one example, the substrate 201 and the processing unit 202, and the substrate 201 and the logic chip 101 can be electrically connected through microbumps. In some other examples, the substrate 201 and the processing unit 202, and the substrate 201 and the logic chip 101 can also be electrically connected in other ways. The processing unit 202 and the logic chip 101 can transmit signals through the substrate 201. For example, the processing unit 202 can transmit read / write requests to the logic chip 101 through the substrate 201, and the logic chip 101 can transmit the read data to the processing unit 202 through the substrate 201.

[0057] In the embodiment of the present disclosure, the acceleration unit 200 includes a substrate 201, a processing unit 202, and at least one memory 100. The processing unit 202 can send read / write requests to the logic chip 101 in the memory 100. The logic chip 101 can read and write the storage chip 102 according to the read / write requests. Since a compensation unit 103 is provided in the memory 100, the compensation unit 103 includes capacitive elements, and the capacitive elements are electrically connected in the connection circuit between the compensation unit 103 and the storage chip 102. A plurality of storage chips 102 are located between the compensation unit 103 and the logic chip 101. Thus, capacitive compensation can be provided to the memory 100 through the capacitive elements in the compensation unit 103, increasing the total capacitance value of the circuit in the memory 100, and high-frequency filtering can be performed on the signals transmitted in the circuit through the capacitive elements, reducing signal interference. The signal integrity of the power supply signal and the read / write signal received by the storage chip 102 farther from the logic chip 101 is relatively high, which can improve the power quality and read / write performance of the memory 100. And since the compensation unit 103 is provided, the capacitive elements in the compensation unit 103 can provide capacitance values. Therefore, fewer capacitive compensation structures can be provided in the storage chip 102, which can reduce the design and production difficulty of the storage chip 102 and reduce the production cost of the storage chip 102.

[0058] Electronic Device

[0059] Figure 8 The schematic diagram of an electronic device according to an example of the present disclosure is shown, as Figure 8 shown, the electronic device 300 includes the acceleration unit 200 in any of the foregoing embodiments.

[0060] It should be noted that the electronic device 300 in this embodiment and the embodiment of the foregoing acceleration unit 200 are based on the same inventive concept and have the same beneficial effects as the embodiment of the foregoing acceleration unit 200, and will not be elaborated herein.

[0061] It should be noted that the information related to users (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present disclosure are all information and data authorized by the users or fully authorized by all parties. Moreover, the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for users to choose to authorize or reject.

[0062] It should be understood that the embodiments in this specification are all described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key points of each embodiment are to illustrate the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the device and system embodiments, the description is relatively simple, and the relevant parts can refer to the partial descriptions of other embodiments.

[0063] It should be understood that the specific embodiments of this specification have been described above. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be executed in a different order from that in the embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0064] It should be understood that an element described in the singular form in this text or shown as only one in the drawings does not represent limiting the quantity of the element to one. In addition, the modules or elements described or shown as separate in this text can be combined into a single module or element, and the module or element described or shown as a single one in this text can be split into multiple modules or elements.

[0065] It should also be understood that the terms and expressions used in this text are only for description, and one or more embodiments of this specification should not be limited to these terms and expressions. Using these terms and expressions does not mean excluding any equivalent features of the illustration and description (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Correspondingly, the claims should be regarded as covering all such equivalents.

Claims

1. A memory device, comprising: Logic chip, compensation unit and multiple memory chips; The logic chip, the compensation unit and the multiple memory chips are vertically stacked, and the multiple memory chips are located between the compensation unit and the logic chip; The logic chip is electrically connected to the adjacent memory chip, the adjacent memory chips are electrically connected to each other, and the compensation unit is electrically connected to the adjacent memory chip; The compensation unit includes a capacitive element, and the capacitive element is electrically connected in the connection circuit between the compensation unit and the memory chip; The logic chip is configured to receive read / write requests and perform read / write operations on the memory chips according to the read / write requests.

2. The memory according to claim 1, wherein The memory includes N memory chips, where N is an integer greater than 2; the first surface of the first memory chip among the N memory chips is attached to the first surface of the logic chip, the first surface of the nth memory chip among the N memory chips is attached to the second surface of the (n - 1)th memory chip, the nth memory chip is electrically connected to the logic chip through the first to (n - 1)th memory chips, the compensation unit is attached to the second surface of the Nth memory chip among the N memory chips, and the compensation unit is electrically connected to the logic chip 101 through the N memory chips, where n is an integer greater than or equal to 2 and less than or equal to N.

3. The memory according to claim 2, wherein, The compensation unit is electrically connected to the Nth memory chip through micro-bumps, the nth memory chip is electrically connected to the (n - 1)th memory chip through micro-bumps, and the logic chip is electrically connected to the first memory chip through micro-bumps.

4. The memory according to claim 1, wherein, The compensation unit includes at least one auxiliary chip, and the auxiliary chip includes the capacitive element.

5. The memory according to claim 4, wherein, The compensation unit includes multiple auxiliary chips, and the multiple auxiliary chips are vertically stacked; The adjacent auxiliary chips are electrically connected to each other, and the capacitive element included in the auxiliary chip is electrically connected in the connection circuit between the auxiliary chips; The bottom auxiliary chip is electrically connected to the adjacent memory chip, and the capacitive element included in the bottom auxiliary chip is electrically connected in the connection circuit between the bottom auxiliary chip and the adjacent memory chip.

6. The memory according to claim 4 or 5, wherein, The circuit structure of the auxiliary chip is the same as that of the memory chip.

7. The memory according to claim 4 or 5, wherein, The capacitive element includes a deep trench capacitor.

8. The memory according to any one of claims 1-5, wherein, The memory chip includes a dynamic random access memory.

9. An acceleration unit, comprising: A substrate, a processing unit and at least one memory as claimed in any one of claims 1 - 8; The processing unit is electrically connected to the substrate, the logic chip in the memory is electrically connected to the substrate, and the processing unit and the memory are located on the same side of the substrate; The processing unit is configured to send read / write requests to the logic chip, so that the logic chip performs read / write operations on the memory chips in the memory according to the read / write requests.

10. An electronic device, comprising an acceleration unit as claimed in claim 9.

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