Read-write switching method and device for command sending of memory controller and memory controller

Abstract

The invention provides a read-write switching method and device for a command sent by a memory controller and the memory controller. The method comprises the following steps: acquiring a preparation queue of a plurality of commands, read-write states of a plurality of storage blocks and a current read-write state of a memory; and dynamically changing the read-write state of the memory, and determining the optimal read-write switching moment. According to the method, the opportunity for switching the read-write commands can be optimized, and the time consumed for switching the read-write commands can be reduced, so that the data channel utilization rate of the DDR is improved, and the time delay of the commands is reduced.

Description

Technical Field

[0001] This application relates to the field of chip design, and particularly to a read-write switching method, apparatus, and memory controller for a memory controller to send commands. Background Art

[0002] With the rapid development of memory technology, the 5th generation of low power double data rate 5 (LPDDR5) synchronous dynamic random access memory (SDRAM) has emerged as the times require. Compared with the previous generations of DDR, LPDDR5 has lower power consumption and a smaller volume.

[0003] Currently, when switching between read operation commands and write operation commands in LPDDR5, read-write switching is usually performed at regular intervals, but this switching method may lead to improper switching timing. For example, within the set timing time, the read command for the target row of a certain memory block has not been completely sent before switching to the write command, resulting in the closure of the target row. After that, when the write state corresponding to the write command switches back to the read state corresponding to the read command, the target row needs to be reactivated to continue sending the read command. This not only reduces the utilization rate of the DDR data channel but also increases the delay of the command. Summary of the Invention

[0004] This application provides a read-write switching method, apparatus, and memory controller for a memory controller to send commands, which can improve the utilization rate of the DDR data channel and reduce the delay of the command.

[0005] In a first aspect, this application provides a read-write switching method for a memory controller to send commands. The method includes: obtaining a plurality of operation commands in a preparation queue and a first state of a memory. The plurality of operation commands include read operation commands and write operation commands. When the memory executes a read operation command, the first state is a read state, and when the memory executes a write operation command, the first state is a write state; when a first operation command among the plurality of operation commands meets a preset condition, determining the sending moment of a second operation command corresponding to the first state and being the last one in the preparation queue as the state switching moment of the memory, where the state switching moment is the moment when the memory switches from the first state to a second state corresponding to the first operation command.

[0006] In some possible implementation manners, the preset condition includes: the priority of the first operation command is higher than the priority of the second operation command; before determining the sending moment of the second operation command corresponding to the first state and being the last one in the preparation queue as the state switching moment of the memory, the method further includes: setting the priority of the first operation command to be higher than the priority of the second operation command.

[0007] In some possible embodiments, the preset conditions include: the number of first operation commands is greater than a preset number; before determining the state transition moment of the memory by using the transmission moment of the last second operation command corresponding to the first state in the preparation queue, the method further includes: determining the number of first operation commands.

[0008] In some possible embodiments, the method further includes: when it is determined to transition from the first state to the second state, sending an activation command before sending the last second operation command, where the activation command is used to activate a target row of a target storage block in the memory, so as to operate on the target row through the second operation command.

[0009] In some possible embodiments, obtaining a plurality of operation commands in the preparation queue includes: determining the operation state and the corresponding operation command of each storage block in the next clock cycle according to the operation state of each storage block among a plurality of storage blocks of the memory and the preparation queue of the operation commands for each storage block, where the operation state includes a read state or a write state.

[0010] In some possible embodiments, determining the operation state and the corresponding operation command of each storage block in the next clock cycle according to the operation state of each storage block among a plurality of storage blocks of the memory and the preparation queue of the operation commands for each storage block includes: when the operation state of each storage block is the first state, obtaining the priority of the first operation command and the priority of the second operation command; when the priority of the first operation command is higher than the priority of the second operation command, determining that the operation state of each storage block in the next clock cycle is the second state, and determining the first operation command with a row hit in the preparation queue of the operation commands for each storage block as the operation command corresponding to the second state.

[0011] In some possible embodiments, the method further includes: obtaining the operation state of the memory; when the operation state of the memory is the first state and there are second operation commands with row misses in the preparation queue of the operation commands for each storage block, determining that the operation state of each storage block in the next clock cycle is the first state, and determining the second operation commands with row misses in the preparation queue of the operation commands for each storage block as the operation commands corresponding to the first state.

[0012] In some possible embodiments, the method further includes: when the operation state of the memory is the first state and there is no second operation command with a row miss in the preparation queue of operation commands for each storage block, determining whether there is a first operation command with a row miss in the preparation queue of operation commands for each storage block; when there is a first operation command with a row miss in the preparation queue of operation commands for each storage block and it meets the condition that no second operation command is executed for each storage block within a preset time period, determining that the operation state of each storage block in the next clock cycle is the second state, and determining the first operation command with a row miss in the preparation queue of operation commands for each storage block as the operation command corresponding to the second state; when there is no first operation command with a row miss in the preparation queue of operation commands for each storage block, or when it does not meet the condition that no second operation command is executed for each storage block within a preset time period, determining that the operation state of each storage block in the next clock cycle is the first state, and determining the second operation command in the preparation queue of operation commands for each storage block as the operation command corresponding to the first state.

[0013] In some possible embodiments, the read operation commands include read commands and read commands with auto-precharge, and the write operation commands include write commands and write commands with auto-precharge.

[0014] In a second aspect, the present application provides a read-write switching device for a memory controller to send commands. The device includes: an acquisition module, configured to acquire a plurality of operation commands in a preparation queue and a first state of a memory, where the plurality of operation commands include read operation commands and write operation commands. When the memory executes a read operation command, the first state is a read state, and when the memory executes a write operation command, the first state is a write state; a determination module, configured to, when a first operation command among the plurality of operation commands meets a preset condition, determine the sending moment of the last second operation command corresponding to the first state in the preparation queue as the state switching moment of the memory, where the state switching moment is the moment when the memory switches from the first state to the second state corresponding to the first operation command.

[0015] In a third aspect, the present application provides a memory controller, and the memory controller is configured to implement the steps in the method described in the first aspect.

[0016] The beneficial effects of the technical solution provided by the present application compared with the prior art are:

[0017] In an embodiment of the present application, the memory controller determines the state transition moment of the memory by obtaining multiple operation states in the preparation queue and the first state of the memory, and when the first operation command among multiple operations meets a preset condition, determining the sending moment of the last second operation command corresponding to the first state in the preparation queue as the state transition moment of the memory. Therefore, in the embodiment of the present application, when the first operation command meets the preset condition, the time when the second operation command is sent is determined as the moment of memory state transition, so that more operation commands in the same direction can be issued, reducing the number of switches. Moreover, in the embodiment of the present application, the operation state of the memory can be dynamically switched to determine the optimal read / write switching time, which can improve the data channel utilization rate of DDR and reduce the latency of commands.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0020] Figure 1 It is a schematic flowchart of an implementation of the read / write switching method for the memory controller to send commands provided by an embodiment of the present application;

[0021] Figure 2 It is a schematic flowchart of an implementation of determining the operation state of each storage block provided by an embodiment of the present application;

[0022] Figure 3 It is a schematic flowchart of an implementation of determining the operation state of the memory provided by an embodiment of the present application;

[0023] Figure 4 It is a schematic timing diagram of sending commands when the read state is switched to the write state provided by an embodiment of the present application;

[0024] Figure 5 It is another schematic timing diagram of sending commands when the read state is switched to the write state provided by an embodiment of the present application;

[0025] Figure 6 It is a schematic timing diagram of sending commands when the write state is switched to the read state provided by an embodiment of the present application;

[0026] Figure 7 It is another schematic timing diagram of sending commands when the write state is switched to the read state provided by an embodiment of the present application;

[0027] Figure 8It is a schematic diagram of test data under the original global mode switching logic provided by the embodiments of the present application;

[0028] Figure 9 It is a schematic diagram of test results under the original global mode switching logic provided by the embodiments of the present application;

[0029] Figure 10 It is a schematic diagram of test data only under the optimized global mode switching logic provided by the embodiments of the present application;

[0030] Figure 11 It is a schematic diagram of test results only under the optimized global mode switching logic provided by the embodiments of the present application;

[0031] Figure 12 It is a schematic diagram of test data under the optimized global mode switching logic and perbank mode switching logic provided by the embodiments of the present application;

[0032] Figure 13 It is a schematic diagram of test results under the optimized global mode switching logic and perbank mode switching logic provided by the embodiments of the present application;

[0033] Figure 14 It is a schematic diagram of the composition structure of a read / write switching device for a memory controller to send commands provided by the embodiments of the present application. Detailed implementation manners

[0034] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are only examples consistent with some aspects of the present application as detailed in the appended claims.

[0035] Before explaining in detail the read / write switching method for a memory controller to send commands provided by the embodiments of the present application, the application scenarios of the embodiments of the present application will be introduced first.

[0036] LPDDR5 is a memory technology based on low-power double data rate (LPDDR), and it is one of the memory (storage) standards with relatively high performance in mobile devices. It is an upgraded version of LPDDR4X and has significant improvements in data rate, power consumption, and memory capacity.

[0037] The main advantage of LPDDR5 lies in its high-speed data transmission ability. By adopting higher prefetch values and higher frequencies, the memory transfer speed of LPDDR5 has been greatly improved. Moreover, LPDDR5 also has significant optimization in terms of power consumption. It uses low voltage and less power consumption to save energy and effectively reduce power consumption. At the same time, LPDDR5 also adopts a more intelligent proxy selection and queuing mechanism to manage memory access more efficiently, further improving the energy use efficiency. In terms of memory capacity, LPDDR5 has also made a breakthrough. It can support a maximum capacity of 16GB, which is a significant improvement compared to 8GB of LPDDR4X. This means that users can run more applications simultaneously, process larger files, or run more complex games.

[0038] Currently, LPDDR5 implements the JEDEC STANDARD JESD209-5 standard. In this standard, when LPDDR5 switches between read operation commands and write operation commands, there will be a relatively large delay. To address this issue, related technologies propose a timing switching scheme, that is, a clock cycle is preset. When the time for the memory to execute a certain command reaches this preset clock cycle, the state of the memory executing the current command is switched to the state corresponding to another command. However, this will result in improper switching timing. For example, the read command for the target row of a certain memory block is not completely sent before switching to the write command, causing the target row to be precharged. After that, when the write state corresponding to the write command switches back to the read state corresponding to the read command, the target row needs to be reactivated to continue sending the read command. This not only reduces the utilization rate of the DDR data channel but also increases the command delay.

[0039] In addition, during the process of the memory executing read operation commands and write operation commands, the memory controller also needs to execute an activate (ACT) command to activate a certain row of a certain memory block in order to perform corresponding operations on this row through the converted operation command. It can be understood that LPDDR5 splits an ACT command into two sub-commands (ACT1 and ACT2). The timing switching method will also delay the sending of ACT1 and ACT2, resulting in the problem of low data channel utilization, thus affecting the performance of DDR.

[0040] Based on the above problems, the embodiments of this application provide a read-write switching method for a memory controller to send commands. This method can dynamically switch the read-write state of the memory to determine the optimal read-write switching time, effectively improving the utilization rate of the DDR data channel and reducing the command delay.

[0041] Figure 1It is a schematic flowchart of an implementation process of a read / write switching method for a memory controller to send commands provided by an embodiment of the present application. Exemplarily, this method can be executed by the memory controller. As Figure 1 shown, this method includes steps S110 to S120.

[0042] Step S110: Obtain multiple operation commands in the preparation queue and the first state of the memory.

[0043] In some embodiments, the multiple operation commands include read operation commands and write operation commands, and the first state is the current state of the memory. When the memory executes a read operation command, the first state is the read state, and when the memory executes a write operation command, the first state is the write state.

[0044] In some embodiments, the read operation commands include read (RD) commands and read with auto - precharge (RDA) commands, and the write operation commands include write (WR) commands and write with auto - precharge (WRA) commands.

[0045] It can be understood that the storage units inside the memory are matrix units composed of banks, rows, and columns. When accessing the memory body selected by rows and columns in a certain bank, an ACT command must be sent first to activate the corresponding row of the bank, and then a read / write command can be sent along with the column to be accessed. After meeting the corresponding time parameters, the corresponding data is sent to the data queue (DQ). When the storage block accessed by the latter command is the same as that accessed by the previous command but the rows in the storage block are different, the row accessed by the previous command must be closed with a precharge command first, and then the row accessed by the latter command is activated with an activation command before a read command or a write command can be sent. A read command or a write command with auto - precharge can perform auto - precharge automatically after the corresponding read / write operation, that is, after the data is read or written, the currently accessed row is automatically closed and prepared for the next access, which reduces the latency of subsequent accesses because there is no need to explicitly issue a precharge command.

[0046] In some embodiments, the implementation process of step S110 can be: Determine the operation state and the corresponding operation command of each storage block in the next clock cycle according to the operation state of each storage block among the multiple storage blocks of the memory and the preparation queue of the operation commands for each storage block. The operation state includes the read state and the write state.

[0047] It can be understood that the memory includes multiple memory blocks, and each memory block can determine the operation state in the next clock cycle and several operation commands to be sent according to its own current operation state and the command preparation queue.

[0048] In some embodiments, when the current state is the first state corresponding to the second operation command and there is an unissued first operation command in the preparation queue, the priority of the first operation command is set higher than that of the second operation command. That is, when the current state continuously remains the state corresponding to a certain operation command and there is always another operation command in the preparation queue that has not been issued, the priority of the other operation command is set higher than that of the operation command corresponding to the current state.

[0049] In some embodiments, after the state is switched, the memory can send the operation command after the switch. When a preset number of operation commands after the switch are sent, the priority of this operation command is adjusted to the initial value.

[0050] Exemplarily, within the preset time period (rd2wr_scheduler_priority_time) when the read state transitions to the write state, the memory / memory block continuously stays in the read direction (read state), and there is always an operation command in the write direction that has not been sent (pending). That is, there is an unissued write operation command, so the priority of the write direction (the write operation command corresponding to the write state) is increased to scheduler_priority_1; within the preset time period (wr2rd_scheduler_priority_time) when the write state transitions to the read state, the memory / memory block continuously stays in the write direction (write state), and there is always an operation command in the read direction pending, so the priority of the read direction (the read operation command corresponding to the read state) is increased to scheduler_priority_1; if when a preset number of operation commands in the direction of scheduler_priority_1 are sent or the operation commands in this direction are all sent, the priority of this direction can be adjusted back to scheduler_priority_0. Exemplarily, rd2wr_scheduler_priority_time and wr2rd_scheduler_priority_time can take the default value of 128 clock cycles.

[0051] In some embodiments, when the operation state of each storage block is in the first state, obtain the priority of the first operation command and the priority of the second operation command; when the priority of the first operation command is higher than the priority of the second operation command, determine that the operation state of each storage block in the next clock cycle is the second state, and determine the first operation command with a row hit in the preparation queue of the operation commands for each storage block as the operation command corresponding to the second state.

[0052] In some embodiments, when the priority of the first operation command is lower than the priority of the second operation command, determine that the operation state of each storage block in the next clock cycle remains the first state, and determine the second operation command in the preparation queue of the operation commands for each storage block as the operation command corresponding to the first state.

[0053] It can be understood that after each storage block obtains the current operation state, it can first obtain the priority of the read operation command and the priority of the write operation command. If the priority of a certain operation command is higher than the priority of another operation command, then determine that the operation state in the next clock cycle is the operation state corresponding to the operation command with a higher priority, and determine the command with a higher priority as several operation commands to be sent later. Otherwise, each storage block will maintain the previous operation state.

[0054] In some embodiments, after each storage block determines that the priority of the first operation command is higher than the priority of the second operation command, it can also determine whether the first operation command is the operation command with a row hit in the storage block. If the first operation command is the operation command with a row hit in each storage block, then determine the operation command with a row hit as the operation command to be sent. Otherwise, each storage block will also maintain the previous operation state, and use the operation command corresponding to the previous operation state in the preparation queue as the operation command to be sent.

[0055] Exemplarily, each storage block can first judge the priorities of the read operation command and the write operation command. If the priority of the read operation command is higher than the priority of the write operation command, then each storage block can determine whether the read operation command has a row hit. If so, each storage block determines that the operation state in the next clock cycle is the read state, and uses the read operation command with a row hit as the operation command to be sent. Otherwise, each storage block will maintain the previous write state, and use the write operation command in the preparation queue as the operation command to be sent.

[0056] In some embodiments, in the absence of the priority of operation commands, each storage block may further determine whether the second operation command in the ready queue hits a row and whether the first operation command misses a row. In the case where the second operation command hits a row and the first operation command misses a row, it continues to determine whether the current operation state of each storage block is the first state and whether the number of second operation commands in the ready queue meets the command quantity threshold. In the case where the current operation state is the first state and the number of second operation commands meets the command quantity threshold, each storage block determines that the operation state in the next clock cycle is the first state; otherwise, each storage block maintains the previous operation state. Herein, the command quantity threshold is the maximum value of the number of second operation commands to be sent after the operation state is converted to the first state corresponding to the second operation command.

[0057] Exemplarily, in the absence of the priority of operation commands, each storage block determines whether the write operation command hits a row and whether the read operation command misses a row. If so, each storage block may further determine whether the current operation state is the read state and whether the number of write operation commands in the ready queue meets the first quantity threshold. If so, it determines that the operation state in the next clock cycle is the read state and uses the read operation command in the ready queue as the operation command to be sent. Otherwise, it determines that the operation state in the next clock cycle maintains the previous write state and uses the write operation command in the ready queue as the operation command to be sent.

[0058] In some embodiments, each storage block may obtain the operation state of the memory. In the case where the operation state of the memory is the first state and there is a second operation command with a row miss in the ready queue of the operation commands for each storage block, it determines that the operation state of each storage block in the next clock cycle is the first state and determines the second operation command with a row miss in the ready queue of the operation commands for each storage block as the operation command corresponding to the first state.

[0059] It can be understood that in the case where both the read operation command and the write operation command miss a row, the memory may further obtain the current operation state of the memory (the overall memory). If the operation state of the overall memory is the write state, each storage block may determine whether the write operation command misses a row. If so, each storage block determines that the operation state in the next clock cycle is the write state and uses the write operation command as the operation command to be sent. Conversely, if the operation state of the overall memory is the read state, each storage block may determine whether the read operation command misses a row. If so, each storage block determines that the operation state in the next clock cycle is the read state and uses the read operation command as the operation command to be sent.

[0060] In some embodiments, when the operation state of the memory is the first state and there is no second operation command with a row miss in the preparation queue of operation commands for each storage block, each storage block may determine whether there is a first operation command with a row miss in the preparation queue of operation commands for each storage block; when there is a first operation command with a row miss in the preparation queue of operation commands for each storage block and it meets the condition that no second operation command has been executed by each storage block within a preset time period, it is determined that the operation state of each storage block in the next clock cycle is the second state, and the first operation command with a row miss in the preparation queue of operation commands for each storage block is determined as the operation command corresponding to the second state; when there is no first operation command with a row miss in the preparation queue of operation commands for each storage block, or when it does not meet the condition that no second operation command has been executed by each storage block within a preset time period, it is determined that the operation state of each storage block in the next clock cycle is the first state, and the second operation command in the preparation queue of operation commands for each storage block is determined as the operation command corresponding to the first state.

[0061] Exemplarily, if the operation state of the memory is the write state and there is no row miss in the write operation command, each memory may determine whether there is a row miss in the read operation command and whether no write operation command has been sent by each storage block within a preset time period. If so, each storage block determines that the operation state in the next clock cycle is the read state, and the read operation command with a row miss is used as the operation command to be sent. If not, each memory may maintain the previous write state, and the write operation command in the preparation queue is used as the operation command to be sent.

[0062] Figure 2 It is a schematic diagram of an implementation process for determining the operation state of each storage block provided by an embodiment of the present application. As Figure 2 shown, the method includes the following steps S201 to step S213. Figure 2 It can also be called an optimized perbank mode switching logic diagram.

[0063] In step S201, each memory determines whether the priority of the read direction is 1 and the priority of the write direction is 0 (read in scheduler_priority_1 & write in scheduler_priority_0).

[0064] If the priority of the read direction is 1 and the priority of the write direction is 0, the operation of step S202 is executed; otherwise, the operation of step S203 is executed.

[0065] In step S202, each storage block determines whether the read operation command in the preparation queue is row hit.

[0066] If the read operation command line is hit, each memory block determines that the operation state for the next clock cycle is the read state, and uses the read operation command with the row hit as the operation command to be sent. Otherwise, each memory block determines that the operation state for the next clock cycle maintains the previous write state, and uses the write operation command in the preparation queue as the operation command to be sent.

[0067] In step S203, each memory block determines whether the priority of the write direction is 1 and the priority of the read direction is 0 (write in scheduler_priority_1 & read in scheduler_priority_0).

[0068] If the priority of the write direction is 1 and the priority of the read direction is 0, then perform the operation in step S204; otherwise, perform the operation in step S205.

[0069] In step S204, each memory block determines whether the write operation command in the preparation queue has a row hit.

[0070] If the write operation command line is hit, each memory block determines that the operation state for the next clock cycle is the write state, and uses the write operation command with the row hit as the operation command to be sent. Otherwise, each memory block determines that the operation state for the next clock cycle maintains the previous read state, and uses the read operation command in the preparation queue as the operation command to be sent.

[0071] In step S205, each memory block determines whether the write operation command in the preparation queue has a row hit and whether the read operation command has a row miss (write row hit & read row miss).

[0072] If the write operation command line is hit and the read operation command line is not hit, then perform the operation in step S206; otherwise, perform the operation in step S207.

[0073] In step S206, each memory block determines whether the current operation state is the read state and whether the write operation command in the preparation queue meets the first quantity threshold (read mode & meet wr_continue_time), where the first quantity threshold is the maximum value of the number of write operation commands that need to be sent after the operation state is converted to the write state.

[0074] If the current operation state is the read state and the number of write operation commands in the ready queue meets the first quantity threshold, each storage block determines that the operation state for the next clock cycle is the read state and uses the read operation commands in the ready queue as the operation commands to be sent. Otherwise, each storage block determines that the operation state for the next clock cycle maintains the previous write state and uses the write operation commands in the ready queue as the operation commands to be sent.

[0075] In step S207, each storage block determines whether the read operation commands in the ready queue are row hits and whether the write operation commands are row misses (read row hit & write row miss).

[0076] If the read operation commands are row hits and the write operation commands are row misses, perform the operations in step S208. Otherwise, perform the operations in step S209.

[0077] In step S208, each storage block determines whether the current operation state is the write state and whether the read operation commands in the ready queue meet the second quantity threshold (write mode & meet read_continue_time), where the second quantity threshold is the maximum number of read operation commands that need to be sent after the operation state is converted to the read state.

[0078] If the current operation state is the write state and the read operation commands in the ready queue meet the second quantity threshold, each storage block determines that the operation state for the next clock cycle is the write state and uses the write operation commands in the ready queue as the operation commands to be sent. Otherwise, each storage block determines that the operation state for the next clock cycle maintains the previous read state and uses the read operation commands in the ready queue as the operation commands to be sent.

[0079] In step S209, each storage block determines whether the current state of the memory is the write state (global mode == write).

[0080] If the current state of the memory is the write state, perform the operations in step S210. Otherwise, perform the operations in step S211.

[0081] In step S210, each storage block can determine whether the write operation commands in the ready queue are row misses (write row miss). If so, each storage block determines that the operation state for the next clock cycle is the write state and uses the write operation commands in the ready queue as the operation commands to be sent. Otherwise, perform the operations in step S212.

[0082] In step 211, each memory block can determine whether the read operation command in the preparation queue has a read row miss. If so, each memory block determines that the operation state in the next clock cycle is the read state, and uses the read operation command in the preparation queue as the operation command to be sent. Otherwise, the operation in step S213 is executed.

[0083] In step S212, each memory block can determine whether the read operation command in the preparation queue has a read row miss and whether a write operation command has not been sent within a preset time period (read row miss & wr_act_idle_gap is satisfied). If so, each memory block determines that the operation state in the next clock cycle is the read state, and uses the read operation command in the preparation queue as the operation command to be sent. Otherwise, it determines that the operation state in the next clock cycle maintains the previous write state, and uses the write operation command in the preparation queue as the operation command to be sent.

[0084] In step S213, each memory block can determine whether the write operation command in the preparation queue has a write row miss and whether a read operation command has not been sent within a preset time period (write row miss & rd_act_idle_gap is satisfied). If so, each memory block determines that the operation state in the next clock cycle is the write state, and uses the write operation command in the preparation queue as the operation command to be sent. Otherwise, it determines that the operation state in the next clock cycle maintains the previous read state, and uses the read operation command in the preparation queue as the operation command to be sent.

[0085] After obtaining the operation state of each memory block in the next clock cycle and the corresponding operation command, the memory controller can determine the optimal read-write switching moment based on this.

[0086] Step S120: When the first operation command among multiple operation commands meets the preset conditions, determine the sending moment of the last second operation command corresponding to the first state in the preparation queue as the state switching moment of the memory.

[0087] In some embodiments, the state switching moment is the moment when the memory switches from the first state to the second state corresponding to the first operation command.

[0088] In some embodiments, the preset conditions include: the priority of the first operation command is higher than the priority of the second operation command. Before determining the sending moment of the last second operation command corresponding to the first state in the preparation queue as the state switching moment of the memory, the priority of the first operation command can also be set to be higher than the priority of the second operation command.

[0089] As described above, embodiments of the present application can set the priority of operation commands. For example, within a preset time period (rd2wr_scheduler_priority_time) when the read state transitions to the write state, the memory / storage block continues in the read direction (read state), and there are always operation commands in the write direction that are not sent (pending). That is, there are unsent write operation commands, then the priority of the write direction (the write operation command corresponding to the write state) is raised to scheduler_priority_1; within a preset time period (wr2rd_scheduler_priority_time) when the write state transitions to the read state, the memory / storage block continues in the write direction (write state), and there are always operation commands in the read direction that are pending, then the priority of the read direction (the read operation command corresponding to the read state) is raised to scheduler_priority_1; if when a preset number of operation commands are sent in the direction of scheduler_priority_1 or the operation commands in that direction are all sent, the priority of that direction can be adjusted back to scheduler_priority_0.

[0090] In addition, in embodiments of the present application, the priority of a certain operation command can also be set manually, and the priority of the manually set operation command is the highest. By way of example, when there are manually set highest-priority commands and system-level priority commands in the read or write direction, the priority of that direction is scheduler_priority_2.

[0091] Therefore, the memory controller can obtain the priority of the read operation command or the write operation command, and based on the priority of the operation command, determine whether to switch the state of the memory. By way of example, when the current state of the memory is the read state, if the priority of the write operation command is higher than that of the read operation command, and the write operation command line in the ready queue hits, then the memory controller can determine that the state of the memory switches from the read state to the write state. If the priority of the read operation command is higher than that of the read operation command, and the read operation command line in the ready queue hits, then the memory controller can determine that the memory maintains the previous read state.

[0092] In some embodiments, the preset conditions include: the number of first operation commands is greater than a preset number, and the preset number is the maximum value for storing the number of first operation commands. Before determining the transmission time of the last second operation command corresponding to the first state in the ready queue as the state transition time of the memory, the number of first operation commands can also be determined; in the case where the number of first operation commands is greater than the preset number, the memory controller determines that the memory transitions from the first state to the second state.

[0093] In some embodiments, in the absence of priorities, the memory controller may determine whether there is an unsent second operation command corresponding to the first state in the ready queue and the second operation command line hits. When it is determined that there is a second operation command and the second operation command line hits, the memory controller may determine that the memory maintains the previous first state. Otherwise, the memory controller may determine whether there is an unsent first operation command in the ready queue and the first operation command line hits. When it is determined that there is a first operation command and the first operation command line hits, the memory controller may determine that the memory is converted from the first state to the second state corresponding to the first operation command.

[0094] In some embodiments, when all operation commands in the ready queue do not hit, the memory controller may determine whether there is an unsent second operation command corresponding to the first state in the ready queue. When it is determined that there is a second operation command and the second operation command line hits, the memory controller may determine that the memory maintains the previous first state.

[0095] In some embodiments, the memory controller may set a preset idle time interval, which represents the longest time for which the first state of the memory lasts, that is, the longest time for which the second state is idle. The memory controller may determine whether the first state meets the preset idle time interval. If it meets, the memory controller may determine that the memory is converted from the first state to the second state. Otherwise, the memory controller determines that the memory maintains the previous first state.

[0096] Figure 3 It is a schematic diagram of an implementation process for determining the operation state of a memory provided by an embodiment of the present application. As Figure 3 shown, the method includes the following steps S301 to step S319. Figure 3 It can also be called an optimized global mode switching logic diagram.

[0097] In step S301, the memory controller determines whether the global state is a write state. If the global state is not a write state, the operations of steps S302 to step S10 are performed. Otherwise, the operations of steps S311 to step S319 are performed.

[0098] In step S302, the memory controller determines whether the priority of the read direction is 2. If the priority of the read direction is 2, it is determined that the operation state of the memory maintains the previous read state. Otherwise, the operation of step S303 is performed.

[0099] In step S303, the memory controller determines whether the priority of the write direction is 2. If the priority of the write direction is 2, it is determined that the operation state of the memory is converted to a write state. Otherwise, the operation of step S304 is performed.

[0100] In step S304, the memory controller determines whether the number of write operation commands in the preparation queue is greater than a preset number. If the number of write operation commands is greater than the preset number, it is determined that the operation state of the memory is converted to the write state; otherwise, the operation in step S305 is performed.

[0101] In step S305, the memory controller determines whether the priority of the read direction in the preparation queue is 1 and whether the read operation command hits the row. If the priority of the read direction is 1 and the read operation command hits the row, it is determined that the operation state of the memory maintains the previous read state; otherwise, the operation in step S306 is performed.

[0102] In step S306, the memory controller determines whether the priority of the write direction in the preparation queue is 1 and whether the write operation command hits the row. If the priority of the write direction is 1 and the write operation command hits the row, it is determined that the operation state of the memory is converted to the write state; otherwise, the operation in step S307 is performed.

[0103] In step S307, the memory controller determines whether there is an unsent read operation command in the preparation queue and whether the read operation command hits the row. If there is an unsent read operation command and the read operation command hits the row, it is determined that the operation state of the memory maintains the previous read state; otherwise, the operation in step S308 is performed.

[0104] In step S308, the memory controller determines whether there is an unsent write operation command in the preparation queue and whether the write operation command hits the row. If there is an unsent write operation command and the write operation command hits the row, it is determined that the operation state of the memory is converted to the write state; otherwise, the operation in step S309 is performed.

[0105] In step S309, the memory controller determines whether there is an unsent read operation command in the preparation queue. If there is an unsent read operation command, it is determined that the operation state of the memory maintains the previous read state; otherwise, the operation in step S310 is performed.

[0106] In step S310, the memory controller determines whether the write direction meets a preset idle time interval. If so, it is determined that the operation state of the memory is converted to the write state; otherwise, it is determined that the operation state of the memory maintains the previous read state.

[0107] In step S311, the memory controller determines whether the priority of the write direction is 2. If the priority of the write direction is 2, it is determined that the operation state of the memory maintains the previous write state; otherwise, the operation in step S312 is performed.

[0108] In step S312, the memory controller determines whether the priority of the read direction is 2. If the priority of the read direction is 2, it is determined that the operation state of the memory is converted to the read state; otherwise, the operation in step S313 is performed.

[0109] In step S313, the memory controller determines whether the number of write operation commands in the ready queue is greater than a preset number. If the number of write operation commands is greater than the preset number, it is determined that the operation state of the memory maintains the previous write state; otherwise, the operation in step S314 is performed.

[0110] In step S314, the memory controller determines whether the priority of the write direction in the ready queue is 1 and whether the write operation command hits the row. If the priority of the write direction is 1 and the write operation command hits the row, it is determined that the operation state of the memory maintains the previous write state; otherwise, the operation in step S315 is performed.

[0111] In step S315, the memory controller determines whether the priority of the read direction in the ready queue is 1 and whether the read operation command hits the row. If the priority of the read direction is 1 and the read operation command hits the row, it is determined that the operation state of the memory is converted to the read state; otherwise, the operation in step S316 is performed.

[0112] In step S316, the memory controller determines whether there is an unsent write operation command in the ready queue and whether the read operation command hits the row. If there is an unsent write operation command and the write operation command hits the row, it is determined that the operation state of the memory maintains the previous write state; otherwise, the operation in step S317 is performed.

[0113] In step S317, the memory controller determines whether there is an unsent read operation command in the ready queue and whether the read operation command hits the row. If there is an unsent read operation command and the read operation command hits the row, it is determined that the operation state of the memory is converted to the read state; otherwise, the operation in step S318 is performed.

[0114] In step S318, the memory controller determines whether there is an unsent write operation command in the ready queue. If there is an unsent write operation command, it is determined that the operation state of the memory maintains the previous write state; otherwise, the operation in step S319 is performed.

[0115] In step S319, the memory controller determines whether the read direction meets a preset idle time interval. If so, it is determined that the operation state of the memory is converted to the read state; otherwise, it is determined that the operation state of the memory maintains the previous write state.

[0116] It can be understood that when it is determined to switch from the first state to the second state, the memory controller may send an activation command and an operation command corresponding to the second state, where the activation command is used to activate the target row of the target storage block in the memory, so as to perform read / write operations on the target row through the second operation command.

[0117] Figure 4 It is a timing diagram of sending commands when the read state is switched to the write state provided by an embodiment of the present application. In Figure 4 it, the initial operation state of the memory is the read state, RD0 represents a read command for the same row (activated row) in a storage block group bankgroup0, and RD1 represents a read command for the same row (activated row) in another storage block group bankgroup1. That is, there are two bankgroups performing read command operations simultaneously. After the second RD1 is sent, the storage state is converted from the read state to the write state. As Figure 4 shown, after the second RD1 is sent, the first activation command ACT1 and the second activation command ACT2 for activating WR2, and the first activation command ACT1 and the second activation command ACT2 for activating WR3 are sent. After being activated through the activation command line, the memory controller sends WR2 and WR3. There is a row-to-row delay (tRRD) between the first ACT1 and the second ACT1, and there is also a tRRD between the second ACT2 and the second ACT2. tRRD_S is the delay between different bankgroups, tRRD_S = 4tCK. There is a RAS to CAS delay (tRCD) between the first ACT2 and the first read command (the first WR2) of the activated target row, and there is a tRCD between the second ACT2 and the second WR2, tRCD = 15tCK. After the second read command is sent, the read commands on the data channel start to be closely arranged. Therefore, it can be determined that the interval between the last RD1 sent before the state transition and the second WR (the second WR2) closely arranged after the state transition is 21tCK.

[0118] In some embodiments, when it is determined to switch from the first state to the second state, the memory controller may send the activation command before sending the last second operation command, so as to reduce the delay between the activation commands.

[0119] Figure 5 It is another timing diagram of sending commands when the read state is switched to the write state provided by an embodiment of the present application. In Figure 5In [description], after the second RD1 is sent, the storage state is converted from the read state to the write state. However, after the first RD1 is sent, the memory controller starts to send the first activation command ACT1 and the second activation command ACT2 for activating WR2, and the first activation command ACT1 and the second activation command ACT2 for activating WR3 during the gap between the RD commands. Thus, after the last RD1 is sent, there is a read command to write command delay duration (write to read delay, tWRRD) between the RD command and the WR command and the WRD command. tWRRD_S is the delay between different bankgroups, and tWRRD_S = 15tCK. Therefore, it can be determined that the interval duration between the last RD1 sent before the state transition and the second WR (the first WR3) closely arranged after the state transition is 17tCK.

[0120] Therefore, by Figure 4 and Figure 5 it can be seen that sending the activation command before the moment of the read / write state switching of the memory can make the interval between the read command before the switching and the write command after the switching lower, and also make the subsequent write commands more closely arranged during sequential read and write. Through calculation, it can be obtained that the scheme of sending the activation command in advance can save 4 clock cycles compared with the scheme of not sending the activation command in advance.

[0121] Figure 6 is a timing diagram of sending commands when the write state is switched to the read state provided by an embodiment of the present application. In Figure 6 the initial operation state of the memory is the read state. WR0 represents the write command for the same row (activated row) in a storage block group bankgroup0, and WR1 represents the write command for the same row (activated row) in another storage block group bankgroup1. That is, there are two bankgroups performing write command operations simultaneously. After the second WR1 is sent, the storage state is converted from the write state to the read state. As Figure 6 shown, after the second WR1 is sent, the first activation command ACT1 and the second activation command ACT2 for activating RD2, and the first activation command ACT1 and the second activation command ACT2 for activating RD3 are sent. After activation through the activation command line, the memory controller sends RD2 and RD3. Similarly, it can be determined that the interval duration between the last WR1 sent before the state transition and the second RD (the second RD2) closely arranged after the state transition is 21tCK.

[0122] Figure 7 is another timing diagram of sending commands when the read state is switched to the write state provided by an embodiment of the present application. In Figure 7In [the above situation], after the second WR1 is sent, the storage state changes from the read state to the write state. However, the memory controller pre-sends the first activation command ACT1 and the second activation command ACT2 for activating RD2, and the first activation command ACT1 and the second activation command ACT2 for activating RD3 during the gap between WR commands. In this way, after the last WR1 is sent, there is a delay duration (read to write delay, tRDWR) from the write command to the read command between the WR command and the RD command. tRDWR_S is the delay between different bankgroups, and tRDWR_S = 12tCK. Therefore, it can be determined that the interval duration between the last WR1 sent before the state transition and the second RD (the first RD3) closely arranged after the state transition is 14tCK.

[0123] Therefore, by Figure 6 and Figure 7 it can be seen that sending the activation command before the moment of the read-write state switch of the memory can make the interval between the write command before the switch and the read command after the switch lower, and also make the subsequent read commands more closely arranged during sequential read and write. Through calculation, it can be obtained that the scheme of sending the activation command in advance can save 7 clock cycles compared with the scheme of not sending the activation command in advance.

[0124] In some embodiments, the default configuration of LPDDR5 can be adopted for testing, and the commands input are the real traces under a certain working condition.

[0125] Figure 8 It is a schematic diagram of the test data adopting the original global mode switching logic provided by the embodiment of the present application. Figure 9 It is a schematic diagram of the test result adopting the original global mode switching logic provided by the embodiment of the present application. It can be seen that the average delay of the DDR after testing with the read-write switching scheme under the original global mode switching logic is 383015.48 picoseconds (ps), the maximum delay is 2230000 ps, and the minimum delay is 7500 ps.

[0126] Figure 10 It is a schematic diagram of the test data only adopting the optimized global mode switching logic provided by the embodiment of the present application. Figure 11It is a schematic diagram of the test results only under the optimized global mode switching logic provided by the embodiments of the present application. It can be seen that after testing with the read-write switching scheme under the optimized global mode switching logic, the average delay of the DDR is 377454.50 ps, the maximum delay is 4738750 ps, and the minimum delay is 5000 ps. Based on Figure 11 and Figure 9 It can be found that, compared with the original global mode switching logic, the read-write switching scheme under the optimized global mode switching logic adopted in the embodiments of the present application improves the data channel utilization rate of the DDR and reduces the average delay of the command. There are a small number of optimizations.

[0127] Figure 12 It is a schematic diagram of the test data under the optimized global mode switching logic and perbank mode switching logic provided by the embodiments of the present application. Figure 13 It is a schematic diagram of the test results under the optimized global mode switching logic and perbank mode switching logic provided by the embodiments of the present application. It can be seen that after testing with the read-write switching scheme under the optimized global mode switching logic and perbank mode switching logic, the average delay of the DDR is 329593.30 ps, the maximum delay is 2001250 ps, and the minimum delay is 5000 ps. Therefore, for the read-write switching scheme under the optimized global mode switching logic and perbank mode switching logic adopted in the embodiments of the present application, the data channel utilization rate of the DDR is greatly improved, and both the average delay and the maximum delay are significantly reduced, and the overall effect is good. Therefore, the logic of the present application is relatively simple, the implementation area is small, the power consumption increase is small, and it has almost no impact on the clock frequency and hardly affects the overall performance.

[0128] In the embodiments of the present application, the memory controller obtains multiple operation states in the preparation queue and the first state of the memory. When the first operation command among the multiple operations meets the preset conditions, the sending moment of the last second operation command corresponding to the first state in the preparation queue is determined as the state switching moment of the memory. That is to say, the embodiments of the present application can dynamically switch the operation state of the memory to determine the optimal read-write switching time, which can improve the data channel utilization rate of the DDR and reduce the delay of the command.

[0129] Figure 14 It is a schematic diagram of the composition structure of a read-write switching device for a memory controller to send commands provided by the embodiments of the present application. As Figure 14As shown in the figure, the read / write switching device 1400 for the memory controller to send commands includes: an acquisition module 1401 and a determination module 1402. Among them,

[0130] In some embodiments, the acquisition module 1401 is configured to acquire a plurality of operation commands in the preparation queue and the first state of the memory. The plurality of operation commands include read operation commands and write operation commands. When the memory executes a read operation command, the first state is the read state. When the memory executes a write operation command, the first state is the write state. The determination module 1402 is configured to, when a first operation command among the plurality of operation commands meets a preset condition, determine the transmission time of the last second operation command corresponding to the first state in the preparation queue as the state switching time of the memory, where the state switching time is the time when the memory switches from the first state to the second state corresponding to the first operation command.

[0131] In some possible implementation manners, the preset condition includes: the priority of the first operation command is higher than the priority of the second operation command. The determination module 1402 is further configured to: set the priority of the first operation command to be higher than the priority of the second operation command.

[0132] In some possible implementation manners, the preset condition includes: the number of the first operation commands is greater than a preset number. The determination module 1402 is further configured to: determine the number of the first operation commands.

[0133] In some possible implementation manners, the device further includes: a sending module, configured to, when it is determined to switch from the first state to the second state, send an activation command before sending the last second operation command. The activation command is used to activate the target row of the target storage block in the memory, so as to operate on the target row through the second operation command.

[0134] In some possible implementation manners, the acquisition module 1401 is further configured to: determine the operation state and the corresponding operation command of each storage block in the next clock cycle according to the operation state of each storage block among the plurality of storage blocks of the memory and the preparation queue of the operation commands for each storage block. The operation state includes the read state or the write state.

[0135] In some possible implementation manners, the acquisition module 1401 is further configured to: when the operation state of each storage block is the first state, acquire the priority of the first operation command and the priority of the second operation command. When the priority of the first operation command is higher than the priority of the second operation command, determine that the operation state of each storage block in the next clock cycle is the second state, and determine the first operation command with row hit in the preparation queue of the operation commands for each storage block as the operation command corresponding to the second state.

[0136] In some possible implementation manners, the obtaining module 1401 is further configured to: obtain the operation state of the memory; when the operation state of the memory is the first state and there is a second operation command with a row miss in the preparation queue of the operation commands for each storage block, determine that the operation state of each storage block in the next clock cycle is the first state, and determine the second operation command with a row miss in the preparation queue of the operation commands for each storage block as the operation command corresponding to the first state.

[0137] In some possible implementation manners, the obtaining module 1401 is further configured to: when the operation state of the memory is the first state and there is no second operation command with a row miss in the preparation queue of the operation commands for each storage block, determine whether there is a first operation command with a row miss in the preparation queue of the operation commands for each storage block; when there is a first operation command with a row miss in the preparation queue of the operation commands for each storage block and the condition that each storage block has not executed the second operation command within a preset time period is satisfied, determine that the operation state of each storage block in the next clock cycle is the second state, and determine the first operation command with a row miss in the preparation queue of the operation commands for each storage block as the operation command corresponding to the second state; when there is no first operation command with a row miss in the preparation queue of the operation commands for each storage block, or the condition that each storage block has not executed the second operation command within a preset time period is not satisfied, determine that the operation state of each storage block in the next clock cycle is the first state, and determine the second operation command in the preparation queue of the operation commands for each storage block as the operation command corresponding to the first state.

[0138] In some possible implementation manners, the read operation command includes a read command and a read command with automatic precharge, and the write operation command includes a write command and a write command with automatic precharge.

[0139] The description of the above device embodiments is similar to the description of the above method embodiments and has similar beneficial effects to the method embodiments. In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. For the technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0140] The embodiments of the present application provide a memory controller, and the memory controller is used to implement the steps in the above method.

[0141] It should be noted that other embodiments of the present application will be readily contemplated by those skilled in the art after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0142] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A read / write switching method for a memory controller to send commands, characterized in that, The method includes: Obtaining a plurality of operation commands in a preparation queue and a first state of a memory, where the plurality of operation commands include read operation commands and write operation commands. When the memory executes a read operation command, the first state is a read state, and when the memory executes a write operation command, the first state is a write state; When a first operation command among the plurality of operation commands meets a preset condition, determining the sending moment of the last second operation command corresponding to the first state in the preparation queue as the state transition moment of the memory, where the state transition moment is the moment when the memory transitions from the first state to a second state corresponding to the first operation command.

2. The method according to claim 1, wherein The preset condition includes: the priority of the first operation command is higher than the priority of the second operation command; Before determining the sending moment of the last second operation command corresponding to the first state in the preparation queue as the state transition moment of the memory, the method further includes: Setting the priority of the first operation command to be higher than the priority of the second operation command.

3. The method according to claim 1, characterized in that, The preset condition includes: the number of the first operation commands is greater than a preset number; Before determining the sending moment of the last second operation command corresponding to the first state in the preparation queue as the state transition moment of the memory, the method further includes: Determining the number of the first operation commands.

4. The method according to claim 1, characterized in that, The method further includes: When it is determined to transition from the first state to the second state, sending an activation command before sending the last second operation command, where the activation command is used to activate a target row of a target storage block in the memory so as to operate on the target row through the second operation command.

5. The method according to claim 1, wherein The obtaining the plurality of operation commands in the preparation queue includes: Determining the operation state of each storage block in the next clock cycle and the corresponding operation command according to the operation state of each storage block among the plurality of storage blocks of the memory and the preparation queue of the operation commands for each storage block, where the operation state includes a read state or a write state.

6. The method according to claim 5, wherein The determining the operation state of each storage block in the next clock cycle and the corresponding operation command according to the operation state of each storage block among the plurality of storage blocks of the memory and the preparation queue of the operation commands for each storage block includes: When the operation state of each storage block is the first state, obtaining the priority of the first operation command and the priority of the second operation command; When the priority of the first operation command is higher than the priority of the second operation command, determining the operation state of each storage block in the next clock cycle as the second state, and determining the first operation command with a row hit in the preparation queue of the operation commands for each storage block as the operation command corresponding to the second state.

7. The method according to claim 5, characterized in that The method further includes: Obtaining the operation state of the memory; When the operating state of the memory is the first state and there is a second operation command with a row miss in the preparation queue of operation commands for each storage block, determine that the operating state of each storage block in the next clock cycle is the first state, and determine the second operation command with a row miss in the preparation queue of operation commands for each storage block as the operation command corresponding to the first state.

8. The method according to claim 7, wherein The method further includes: When the operating state of the memory is the first state and there is no second operation command with a row miss in the preparation queue of operation commands for each storage block, determine whether there is a first operation command with a row miss in the preparation queue of operation commands for each storage block; When there is a first operation command with a row miss in the preparation queue of operation commands for each storage block and it satisfies the condition that the second operation command has not been executed for each storage block within a preset time period, determine that the operating state of each storage block in the next clock cycle is the second state, and determine the first operation command with a row miss in the preparation queue of operation commands for each storage block as the operation command corresponding to the second state; When there is no first operation command with a row miss in the preparation queue of operation commands for each storage block, or it does not satisfy the condition that the second operation command has not been executed for each storage block within a preset time period, determine that the operating state of each storage block in the next clock cycle is the first state, and determine the second operation command in the preparation queue of operation commands for each storage block as the operation command corresponding to the first state.

9. The method according to any one of claims 1 to 8, characterized in that, The read operation command includes a read command and a read command with auto-precharge, and the write operation command includes a write command and a write command with auto-precharge.

10. A read / write switching device for a memory controller to send commands, characterized in that, The device includes: An acquisition module, configured to acquire a plurality of operation commands in a preparation queue and a first state of a memory, the plurality of operation commands including read operation commands and write operation commands. When the memory executes a read operation command, the first state is a read state, and when the memory executes a write operation command, the first state is a write state; A determination module, configured to determine the transmission moment of the last second operation command corresponding to the first state in the preparation queue as the state transition moment of the memory when the first operation command in the plurality of operation commands meets a preset condition, where the state transition moment is the moment when the memory switches from the first state to the second state corresponding to the first operation command.

11. A memory controller, characterized in that, The memory controller is used to implement the steps in the method according to any one of claims 1 to 9.

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