Method and device for detecting mapping relation of data lines, server and electronic equipment

Abstract

The embodiment of the invention discloses a method and device for detecting the mapping relation of data lines, a server and electronic equipment, relates to the technical field of computers, and can simply and efficiently determine the mapping relation of the data lines at a memory end and a processor end. The method comprises the following steps: training a memory to enable the memory to enter a read-write state; selecting at least one target data line from a memory end, and activating a link-by-link adjustable characteristic corresponding to the target data line on the memory; the link-by-link adjustable characteristic characterization allows for independent adjustment of an electrical parameter for each link of the memory; adjusting step lengths of corresponding electrical parameters based on the link-by-link adjustable characteristics, executing write training on the target data line under each step length, and recording write margin data of the target data line; and determining a mapping relationship between the target data line and a processor end data line according to the write margin data.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a method, an apparatus, a server, and an electronic device for detecting a mapping relationship of data lines. Background Art

[0002] In a computer system, the connection between a memory and a processor is crucial. With the development of technologies, some original equipment manufacturers (OEMs) directly mount the memory chips of the dynamic random access memory (DRAM) manufacturer and register clock drivers (RCDs) on the motherboard to optimize product designs, instead of externally connecting memory modules. This design has extremely high requirements for the correctness of the connection relationship between the data lines of the CPU and each memory chip. Since the Memory Down method requires leading wires from the CPU end to pass through the motherboard and directly connect to the data line points of the memory chips, the connection relationship is complex, and it is very easy to connect the data lines or memory chips wrongly during the wiring process. Moreover, the CRC feature of the memory controller and the DDR physical layer (PHY) training process rely on a clear mapping relationship between the data lines of the CPU and the memory chips. Therefore, accurately detecting the mapping relationship of the data lines has become a key issue for ensuring the stable operation of the system.

[0003] In the related technologies, there are mainly a method based on data patterns (Pattern) and a method based on multi-purpose register (MPR, Multi - Purpose Register) commands. Among them, in the method based on data Patterns, specific Patterns are generated through memory reference code (MRC), and the mapping relationship of the data lines is deduced by combining the left and right movement of the double data rate synchronous dynamic random access memory physical layer receive - end phase - locked loop delay (DDR PHY Rx PLL Delay) during the memory training. For the latter method, based on the read - write commands of the control registers of DDR4, the mapping relationship is obtained by configuring a one - hot code to the MPR register of the DRAM and reading back and parsing. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method, an apparatus, a server, and an electronic device for detecting a mapping relationship of data lines, which can simply and efficiently determine the mapping relationship between the data lines at the memory end and the processor end.

[0005] In a first aspect, an embodiment of the present application provides a method for detecting a mapping relationship of data lines, including: training a memory to enable the memory to enter a readable and writable state; selecting at least one target data line from the memory side and activating a per-link adjustable characteristic corresponding to the target data line on the memory; the per-link adjustable characteristic indicates that electrical parameters can be independently adjusted for each link of the memory; adjusting the step size of the corresponding electrical parameter based on the per-link adjustable characteristic, performing write training on the target data line at each step size, and recording the write margin data of the target data line; determining the mapping relationship between the target data line and the data line on the processor side according to the write margin data.

[0006] According to a specific implementation manner of the embodiment of the present application, the determining the mapping relationship between the target data line and the data line on the processor side according to the write margin data includes: determining the change magnitude of the write margin data of each target data line with the adjustment of the step size; determining the target data line with the largest change in the write margin data as the one having a mapping relationship with the data line on the processor side.

[0007] According to a specific implementation manner of the embodiment of the present application, the electrical parameter corresponding to the per-link adjustable characteristic includes at least one of a data termination equalization parameter and a write reference voltage offset parameter.

[0008] According to a specific implementation manner of the embodiment of the present application, the adjusting the step size of the corresponding electrical parameter based on the per-link adjustable characteristic, performing write training on the target data line at each step size, and recording the write margin data of the target data line includes: adjusting the step size of the corresponding electrical parameter based on the per-link adjustable characteristic; determining whether the current step size reaches a preset maximum step size; if not, performing write training on the target data line at the current step size; recording the write margin data of the target data line at the current step size, and incrementing the step size by a count value; repeating the above steps until the step size reaches the preset maximum step size.

[0009] According to a specific implementation manner of the embodiment of the present application, before determining the target data line with the largest change in the write margin data as the one having a mapping relationship with the data line on the processor side, it further includes: when it is monitored that the write margin data of a certain target data line has a margin mutation extreme point during the step size adjustment, determining that the write margin data of the target data line has the largest change.

[0010] According to a specific implementation manner of an embodiment of the present application, after determining the mapping relationship between the target data line and the data line at the processor end, the method further includes: performing an increment operation on the sequence number identifier of the target data line; wherein, the sequence number identifier is used to identify the number of target data lines; determining whether the sequence number identifier of the target data line reaches the upper limit value of the sequence number identifier; if not, sequentially determining the mapping relationship between all target data lines and the data line at the processor end until the signal identifier of the target data line reaches the upper limit value of the sequence number identifier; integrating all determined mapping relationships to form a complete mapping relationship between all data lines at the memory end and the data line at the processor end.

[0011] In a second aspect, an embodiment of the present application further provides a device for detecting a data line mapping relationship, including: a training module configured to train the memory to make the memory enter a readable and writable state; a characteristic control module configured to select at least one target data line from the memory end and activate the per-link adjustable characteristic corresponding to the target data line on the memory; the per-link adjustable characteristic indicates that the electrical parameters of each link of the memory are allowed to be independently adjusted; a data collection module configured to adjust the step size of the corresponding electrical parameter based on the per-link adjustable characteristic, perform write training on the target data line at each step size, and record the write margin data of the target data line; an analysis module configured to determine the mapping relationship between the target data line and the data line at the processor end according to the write margin data.

[0012] According to a specific implementation manner of an embodiment of the present application, the analysis module includes: an analysis unit configured to determine the change magnitude of the write margin data of each target data line with the adjustment of the step size; a mapping determination unit configured to determine that a target data line with the largest change in write margin data has a mapping relationship with the data line at the processor end.

[0013] According to a specific implementation manner of an embodiment of the present application, the data collection module includes: a step size adjustment unit configured to adjust the step size of the corresponding electrical parameter based on the per-link adjustable characteristic; a step size judgment unit configured to judge whether the current step size reaches the preset maximum step size; a training execution unit configured to perform write training on the target data line when the step size does not reach the preset maximum step size; a data recording unit configured to record the write margin data of the target data line at the current step size and increment the step size by a count value; a loop control unit configured to repeatedly execute the tasks performed by the step size judgment unit, the training execution unit, and the data recording unit until the step size reaches the preset maximum step size.

[0014] According to a specific implementation manner of an embodiment of the present application, the analysis unit is specifically configured to: monitor whether a margin mutation extreme point appears in the write margin data of the target data line during the step size adjustment process; when detecting the margin mutation extreme point, determine that the change in the write margin data of the target data line is the largest.

[0015] According to a specific implementation manner of an embodiment of the present application, it further includes: a serial number management module configured to, after determining the mapping relationship between the target data line and the processor-side data line, perform an increment operation on the serial number identifier of the target data line; a serial number judgment module configured to judge whether the serial number identifier of the target data line reaches the upper limit value of the serial number identifier; a mapping traversal module configured to, when the serial number identifier does not reach the upper limit value, sequentially determine the mapping relationships between all target data lines and the processor-side data lines until the signal identifier of the target data line reaches the upper limit value of the serial number identifier; a mapping integration module integrates all determined mapping relationships to form a complete mapping relationship between all data lines on the memory side and the processor-side data lines.

[0016] In a third aspect, an embodiment of the present application further provides a server, including: a main board; a processor installed on the main board, and a memory controller is integrated inside the processor; a memory installed on the main board and interconnected with the interface of the memory controller; wherein, the memory controller is configured to: train the memory to make the memory enter a readable and writable state; select at least one target data line from the memory side, activate the per-link adjustable characteristic corresponding to the target data line on the memory, and the per-link adjustable characteristic indicates that the electrical parameters of each link of the memory are allowed to be independently adjusted; adjust the step size of the corresponding electrical parameter based on the per-link adjustable characteristic, perform write training on the target data line at each step size; record the write margin data of the target data line; and determine the mapping relationship between the target data line and the processor-side data line according to the write margin data.

[0017] In a fourth aspect, an embodiment of the present application further provides an electronic device, including: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is arranged inside the space surrounded by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to each circuit or device of the above-mentioned electronic device; the memory is used to store executable program codes; the processor runs a program corresponding to the executable program codes by reading the executable program codes stored in the memory, and is used to execute the method for detecting the mapping relationship of the data line provided in any one of the foregoing embodiments. Description of the Drawings

[0018] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic diagram of the data line connection structure between the CPU and the memory particles according to a fixed cross mapping relationship; Figure 2 It is a schematic flowchart of a method for detecting the mapping relationship of data lines provided by an embodiment of the present application; Figure 3 It is a schematic flowchart of a method for detecting the mapping relationship of data lines provided by another embodiment of the present application; Figure 4 It is a schematic flowchart of a method for detecting the mapping relationship of data lines provided by yet another embodiment of the present application; Figure 5 It is a schematic flowchart of a method for detecting the mapping relationship of data lines provided by still another embodiment of the present application; Figure 6 It is a schematic diagram of the structure of a device for detecting the mapping relationship of data lines provided by an embodiment of the present application; Figure 7 It is a schematic block diagram of the structure of a server provided by an embodiment of the present application; Figure 8 It is a schematic block diagram of the structure of an electronic device provided by an embodiment of the present application. Detailed Embodiments

[0020] The following will describe the embodiments of the present application in detail with reference to the drawings.

[0021] It should be clear that the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0022] To enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present application, the following will be described in detail through specific embodiments.

[0023] In the field of computer storage, with the development of technology, some original equipment manufacturers (OEMs) have adopted a design method of directly mounting the original DRAM chips (Memory Down) and RCDs on the motherboard, without externally connecting memory modules. This design makes the connection relationship between the CPU and the data lines of each memory chip complex. Since the connection requires leading wires from the CPU end through the motherboard to directly connect to the data line points corresponding to each memory chip, it is easy to connect the data lines or chips incorrectly during the wiring process. Moreover, the cyclic redundancy check (CRC) feature of the memory controller and the training process of the double data rate synchronous dynamic random access memory (DDR) physical layer (PHY) highly depend on the clear mapping relationship between the CPU and the chips. See Figure 1 , the mapping relationship of standard memory modules is not one-to-one, and the data lines are connected according to a fixed cross-mapping relationship. The mapping relationship can be imported by referring to the documents provided by the memory module manufacturer. However, for the case of directly attaching the chips to the motherboard, the mapping relationship is uncontrollable, and the correctness of the mapping relationship cannot be determined. Therefore, accurately detecting the data line mapping relationship has become an urgent problem to be solved.

[0024] Currently, the mainstream methods for dynamically detecting the data line mapping relationship have many deficiencies. For example, the method based on data Pattern generates specific Patterns through the memory initialization code (MRC) and estimates the data line mapping relationship by combining the left and right movement of the DDR PHY Rx PLL Delay during the memory training. However, this method requires the hardware to support the configurability of the memory training Pattern, and the design difficulty and algorithm complexity of the specific Pattern are high.

[0025] Another method based on the multi-purpose register (MPR) command configures a one-hot code to the MPR register of the DRAM and reads it back for parsing to obtain the mapping relationship based on the read and write commands of the control register of DDR4. However, the MPR command combination rules are different for different types of chips. For example, the MPR command combination rules for X4 / X8 / X16 type chips are different, which has certain limitations in application and is generally only applicable to memory chips that support MPR commands.

[0026] To this end, the embodiments of the present application propose a method for detecting the mapping relationship of data lines with a different technical concept. Based on some analog circuit characteristics of the memory itself, such as the decision feedback equalizer (DFE) and the reference voltage Vref in some memories, and the ability or characteristic of each link to independently adjust electrical parameters, by utilizing the influence of such characteristics on the training results, it is applicable to the detection scenario of the data line mapping relationship between peer devices with per-link adjustable characteristics or functions. Thus, there is no need to design complex algorithms or Patterns, and the mapping relationship of the peer data lines can be dynamically detected simply and efficiently.

[0027] See Figure 2 and Figure 3 , in some embodiments, a method for detecting the mapping relationship of data lines provided by the embodiments of the present application includes: S110. Train the memory to make the memory enter a readable and writable state.

[0028] S120. Select at least one target data line from the memory end, and activate the per-link adjustable characteristic corresponding to the target data line on the memory; the per-link adjustable characteristic indicates that the electrical parameters of each link of the memory are allowed to be independently adjusted.

[0029] S130. Based on the per-link adjustable characteristic, adjust the step size of the corresponding electrical parameter, perform write training on the target data line at each step size, and record the write margin data of the target data line.

[0030] S140. Determine the mapping relationship between the target data line and the data line at the processor end according to the write margin data.

[0031] See Figure 3 , during the execution of a specific example, in step S111, when the processor, specifically the memory controller (DDR controller) integrated in the processor, trains the memory (training), taking the DDR5 particle memory as an example, a series of initialization operations are performed on the memory, including configuring parameters such as the internal clock frequency and voltage of the memory, and specific timing parameters inside it need to be configured according to the DDR5 specification, such as the precharge time, activation to read / write delay time, etc. After the memory training is completed, the controller can read and write the memory, and then the detection process of the mapping relationship can be started.

[0032] The memory and the memory controller at the processor end generally include multiple data lines. Serial number identifiers can be configured for the data lines, and then each data line can be detected one by one. The data lines can be selected for detection in sequence from the memory end. For example Figure 1In step S121, select LaneNum as 0, that is, start detection from the 0th data line.

[0033] In terms of activating the per-link adjustable feature, for DDR5 x4 particles, when selecting a certain target data line, such as DQ0, specific instructions need to be written to its corresponding specific register to activate the corresponding feature. For example, DQ0 - MR113 is used for the decision feedback equalizer (DFE) feature, and DQ0 - MR134 is used for the write reference voltage (Vref) feature. Among them, different DQ lines correspond to different register addresses, and the settings of the registers determine the adjustment method and step (Step) range of the electrical parameters of the corresponding data lines.

[0034] It can be understood that when it is necessary to activate the per-link adjustable feature or function for the corresponding memory, it is necessary to first select the corresponding memory to be detected (S125a), and then enable the per-lane feature or function of the memory (S125b). In the DDR5 particle memory, each data line has a corresponding control register. Through the settings of the corresponding control register, the memory controller can activate per-link (Per-lane) adjustable features such as the decision feedback equalizer or the write reference voltage. This feature allows independent adjustment of the electrical parameters of each link of the memory. See Figure 4 and Figure 5 , corresponding to Figure 3 step S125b in. Specifically, the electrical parameters corresponding to the per-link adjustable feature include at least one of the data termination equalization parameter and the write reference voltage offset parameter. After selecting a certain target data line, by modifying its corresponding control register and enabling the DFE or Vref function, the signal of this data line can be optimized.

[0035] Among them, the data termination equalization parameter is mainly adjusted through the decision feedback equalizer. During high-speed data transmission, the signal will be distorted due to factors such as the loss of the transmission line. The DFE can process the signal, compensate for signal distortion, and improve signal quality. For example, by adjusting parameters such as the gain and delay of the DFE, its processing effect on the signal can be changed, thereby affecting the write margin data of the data line.

[0036] The Write VrefDQ Offset is achieved by adjusting the write reference voltage. When writing data, Vref serves as the reference voltage, determining the logical level judgment standard for data. In DDR5 chips, by adjusting the value of the VrefDQ Offset register, the offset of the write reference voltage is changed, thereby affecting the write margin data. In practical applications, according to the specific characteristics and requirements of the memory, one can choose to adjust the DFE parameters or the Vref parameters, or adjust both simultaneously, and observe the impact on the write training data results to achieve the detection effect of the mapping relationship.

[0037] See Figure 3 and Figure 4 , taking the step size for adjusting the DFE characteristics as an example. During the adjustment process, each time the step size is changed, write training is performed on the target data line at that step size, and the write margin data of the target data line is recorded. Assume that the DFE step size starts from the initial value. For example, the initial value of the DFE step size is 0, and it increases by a fixed value each time. Each time the step size is adjusted, a specific data pattern is written to the target data line, and then the accuracy of data transmission is detected to obtain the write margin data (Margin). The write margin data is used to characterize the reliability of writing data to the data line under the current electrical parameter settings. See Figure 3 step S141 in Figure 4 step 141A in Figure 5 step 141B in . After collecting the Margin of the data line training results, analyze the data to determine which Margin of the target data line corresponding to the data line at the controller end has changed significantly, and then the mapping relationship between the target data line and the data line at the processor end can be determined.

[0038] It can be understood that when the controller adjusts the step size of the electrical parameters of a certain data line, due to the per-link adjustable characteristic, that is, when adjusting the data link, the write margin data of the controller-end data line with a mapping relationship changes more significantly than that of other data lines. Then, observe which data line records a large change in the write margin data at the controller end, and it can be determined that there is a mapping relationship between the data line with a large change at the processor end and the target data line at the memory end, thereby solving the problem of disordered data line mapping relationships and ensuring accurate data transmission between the processor and the memory.

[0039] Therefore, the method for detecting the mapping relationship of the data lines provided in this embodiment adjusts the step size of the electrical parameters on the target data line at the memory end at the controller end by utilizing the inherent per-link adjustable characteristic of the memory, and records the write margin data of the data lines at the controller end at each step size. Since the electrical parameters are adjusted independently for each link of the memory, the write margin data of the data lines at the controller end with a mapping relationship changes more significantly than that of other data lines. By observing at the controller end which data line records a large change in the write margin data, it can be determined that there is a mapping relationship between the data line with a large change at the processor end and the target data line at the memory end, thereby solving the problem of disordered mapping relationship of the data lines and ensuring accurate data transmission between the processor and the memory.

[0040] In some embodiments, determining the mapping relationship between the target data line and the data line at the processor end according to the write margin data includes: determining the change magnitude of the write margin data of each target data line with the adjustment of the step size; and determining the target data line with the largest change in the write margin data as the one having a mapping relationship with the data line at the processor end.

[0041] Specifically, it is necessary to determine the change magnitude of the write margin data of each target data line with the adjustment of the step size. In other words, a comparative analysis of the write margin data recorded at different step sizes at the controller end is required. For example, for each target data line, record the write margin data when the step size is 0, 1, 2,... and other different values, and then observe the change trend of the data. Determine the data line with the largest change in the write margin data recorded at the control end as the one having a mapping relationship with the target data line.

[0042] In actual operation, when the write margin data corresponding to a certain target data line shows obvious fluctuations during the step size adjustment, such as suddenly becoming 0 or a very small value, while the write margin data of other data lines changes relatively little, it can be determined that there is a mapping relationship between the target data line with the largest change in the write margin data and the data line being detected at the processor end.

[0043] See Figures 3 to 5, in some embodiments, the step of adjusting the corresponding electrical parameter based on the per-link adjustable characteristic, and performing write training on the target data line at each step, and recording the write margin data of the target data line includes: S131, adjusting the step of the corresponding electrical parameter based on the per-link adjustable characteristic; S1, determining whether the current step reaches a preset maximum step; S3, if not, performing write training on the target data line at the current step, and recording the write margin data of the target data line at the current step; S5, incrementing the step by a count value; repeating the above steps S1 to S5, recording all the write margin data of the target data line points corresponding to the steps until the step reaches the preset maximum step, and performing step S141.

[0044] See Figure 4 , still taking the DDR5 particle as an example, adjust the DFE register corresponding to the 0th target data line (DQ0), such as the step of MR113, and the step starts from the initial value 0. Determine whether the current step reaches the preset maximum step StepMax, and this maximum step can be set according to specific memory characteristics and detection requirements. For example, in the DFE characteristic scheme, the step range is usually from 0 to 0x40. If the preset maximum step is not reached, continue to perform write training on the target data line at the current step, such as writing a specific data pattern to the target data line and detecting the accuracy of data transmission, and record the write margin data of the target data line at the current step; then increment the step by a count value. Repeat the above steps until the step reaches the preset maximum step to complete the collection of all data. This can avoid problems such as data omission or incomplete detection caused by improper step adjustment.

[0045] In some embodiments, before determining the target data line with the largest change in write margin data as the one having a mapping relationship with the processor-side data line, it further includes: when it is monitored that the write margin data of a certain target data line appears an extreme point of margin mutation during the step adjustment, such as the write margin data suddenly becomes 0 or is at a minimum value, it is determined that the write margin data of the target data line has the largest change.

[0046] See Figure 5, taking the mapping relationship detection based on the Vref characteristics of DDR5 x4 particles as an example, when adjusting the step size Vref Offset corresponding to the Vref characteristics of a certain target data line, after the training result collection of this data line is completed, if it is found that the write margin data of a certain DQ line drops sharply from a large value to 0, while the write margin data of other DQ lines changes little, at this time, it can be determined that the write margin data of this DQ line changes the most, and the data line with the largest change in write margin data is determined to have a mapping relationship with the data line at the processor end. By detecting the mutation extreme point and quantitatively characterizing the change magnitude, the mapping relationship between data lines can be captured more accurately, improving the reliability of the detection result.

[0047] During the mapping relationship detection based on the Vref characteristics of DDR5 x4 particles, in order to make the change of the write training result Margin obvious when adjusting Vref Offset during Write 1D training and it is easy to accurately judge the corresponding mapping relationship, refer to Figure 5 , in some embodiments, after the memory completes training, it further includes: performing Write2D training on the memory to obtain an eye diagram composed of an output phase delay (Delay) and Vref that characterizes the signal quality; selecting a Vref value from the upper boundary of Vref in the eye diagram as the Vref value in the subsequent Write 1D training. In this embodiment, since the selected Vref value is a relatively poor critical value, on this basis, fine-tuning will cause an obvious change in the write training result of the corresponding DQ, so that it is easy to accurately judge the corresponding mapping relationship.

[0048] Refer to Figures 3 to 5 , in some embodiments, after determining the mapping relationship (step S142) between the target data line and the data line at the processor end, the method further includes: S143. Perform an increment operation on the serial number identifier of the target data line and return to step S123; where the serial number identifier is used to identify the number of target data lines; S123. Judge whether the serial number identifier of the target data line reaches the upper limit value of the serial number identifier, that is, judge whether the data line serial number identifier LaneNun is less than the upper limit value N in the figure; if not, that is, if the data line serial number identifier LaneNun is less than the upper limit value N, then determine the mapping relationship between all target data lines and the data line at the processor end in turn until the signal identifier of the target data line reaches the upper limit value of the serial number identifier; specifically, refer to the previous steps S120 to S140, or further refer to the relevant descriptions of S125a~S143, which will not be elaborated here. S150. Integrate all the determined mapping relationships to form a complete mapping relationship between all data lines at the memory end and the data lines at the processor end.

[0049] According to this embodiment, in the detection of DDR5 x4 particles, traversal detection can be sequentially performed on DQ0, DQ1, DQ2, and DQ3 to determine the mapping relationship between each DQ line and the data line at the processor end. Finally, the complete mapping relationship of all data lines is integrated to prevent missing the detection of the mapping relationship of a certain data line and ensure that the complete mapping relationship of all data lines can be obtained.

[0050] To help further understand the technical solutions and technical effects in the embodiments of the present application, now in combination with Figure 5 and Figure 7 , taking the DDR5 x4 particle and the dynamic detection of the data line mapping relationship based on the reference voltage Vref characteristic during write training as an example, it is described in detail as follows: Assume that it is necessary to determine the mapping relationship between the data lines DQ0 - DQ3 on the particle side and the data lines DQ0 - DQ3 on the processor side. The detection process is as follows: S111. After the basic training of the DDR5 particle is completed and initialized, it enters the stable working state. In order to make the result change more obvious after adjusting the step size of the electrical parameters of the corresponding characteristic. After the DDR5 particle training is completed, enter step S112. Perform Write 2D training on the DDR5 particle, and select the Vref at a relatively poor position as the Vref value for the subsequent Write 1D training. Specifically, the upper boundary of Vref in the eye diagram obtained by Write 2D training can be selected as the center point Vref value for Write 1D training, so that the write margin (Margin) is in a critical state. In this way, during the subsequent Write 1D training process, the adjustment of VrefDQ is more likely to cause a Margin mutation.

[0051] S121. Start detecting from the data line with the serial number marked as the 0th data line. The initial detection object is the DQ0 line on the particle side, and the sequence identification number LaneNum = 0.

[0052] S123. If the serial number identification of the data line is less than the upper limit value N, then enter S125a.

[0053] S125a. Use the physical device address PDA ID to locate the DDR5 particle to be detected to ensure that the operation only affects the current target particle.

[0054] S125b3. Enable the Write VrefDQ Offset characteristic or function of DQ0 to make the current link in a separately adjustable state.

[0055] S131b. Activate the write reference voltage offset adjustment function of the DQ0 line through register operations, such as MR134. Adjust the VrefDQ Offset step size and perform training. The step size range is from -3 to +3, and specifically execute Step = -3, -2, -1, 0, 1, 2, 3 in sequence. For each adjustment of the step size, modify the VrefDQ register corresponding to DQ0.

[0056] S1. Before performing write training, first judge the step size value. If the current compensation value is less than the current step size value and the current step size value is less than the step size upper limit value, enter the S2 process to start performing write training.

[0057] S2. Perform Write 1D training (one-dimensional training related to data writing) on the 4 data lines on the die side, namely DQ0 - DQ3, and record the training result Margin value of each data line under the current step size value.

[0058] After recording the write training results under the current step size value, enter process S3. Add 1 to the current value, return to step S1, and continue to judge whether the step size reaches the upper limit StepMax = +3. If it does not reach, continue to iteratively execute steps S2 and S3, and continue to collect the write training results under the current step size value until the current step size value reaches the upper limit, and complete the collection of all write training data for the 0th data line. Enter step S141, and then start to analyze the Margin data to determine the mapping relationship. Of course, for each data line, it can also start to analyze after collecting each data line, or analyze them uniformly.

[0059] Observe at the controller end which data line has a relatively large change in the write training result Margin of the target data line DQ0 at the memory end corresponding to it. For example, when Step = 0, the Margin detected by DQ3 at the controller end is 50%, and the other lines are all 60%. When Step = +1, the Margin detected by DQ3 at the controller end drops suddenly to 0%, and there is no obvious change in the other lines. This indicates that die side DQ0 → processor side DQ3.

[0060] After detecting the mapping relationship between the memory die DQ0 and the data lines at the controller end, increment LaneNum and re - execute the detection process for DQ0. LaneNum increases from 0 to the upper limit value 3 in sequence, and sequentially detect the mapping relationships between the DQ1 - DQ3 lines at the memory die end and the data lines at the controller end: The execution process of the detection is similar to that of DQ0, which can be referred to and will not be elaborated here.

[0061] After collecting the write training results of all data lines and analyzing, it is found that: by adjusting its VrefDQ register MR142, the Margin of the DQ2 line at the controller end mutates, and the mapping relationship DQ1→DQ2 is determined. By adjusting its VrefDQ register MR150, the Margin of the DQ0 line at the controller end mutates, and the mapping relationship DQ2→DQ0 is determined. By adjusting its VrefDQ register MR158, the Margin of the DQ1 line at the controller end mutates, and the mapping relationship DQ3→DQ1 is determined.

[0062] Integrate the complete mapping relationship. The final mapping relationship is: DQ0 on the die side → DQ3 on the processor side; DQ1 on the die side → DQ2 on the processor side; DQ2 on the die side → DQ0 on the processor side; DQ3 on the die side → DQ1 on the processor side.

[0063] It should be noted that the above is an example with DDR5 die, but the method provided in the embodiments of the present application is not limited to DDR5. Any other memory die or device with per-link adjustable characteristics or functions is also applicable when it comes to mapping relationship detection. For example, DDR4, high bandwidth memory (HBM), PCIe controller, serializer / deserializer (SerDes).

[0064] Therefore, in the embodiments of the present application, for a memory with Per-DQ DFE characteristics or Per-DQ WriteVrefDq characteristics, by virtue of the per-path adjustable analog characteristics of each data link, and the influence of adjusting the corresponding characteristics Step on the write margin data result of the data line write direction during the training process, according to the characterization observation of the write margin data result, the data line mapping relationship between each data line of the memory and the controller end can be dynamically detected quickly and accurately.

[0065] It should be noted that the methods provided in the above embodiments of the present application can be solidified in a certain manufactured physical hardware device in the form of software or a program. When the software or program is run, the above method flow can be reproduced.

[0066] See Figure 6 , the embodiments of the present application also provide a device for detecting the data line mapping relationship, including: a training module 210 configured to perform basic training on the memory to make the memory enter a readable and writable state; A characteristic control module 220 configured to select at least one target data line from the memory end and activate the per-link adjustable characteristic corresponding to the target data line on the memory; the per-link adjustable characteristic indicates that the electrical parameters of each link of the memory can be independently adjusted; The data collection module 230 is configured to adjust the step size of the corresponding electrical parameter based on the per-link adjustable characteristic, perform write training on the target data line at each step size, and record the write margin data of the target data line. The analysis module 240 is configured to determine the mapping relationship between the target data line and the data line at the processor end according to the write margin data.

[0067] In some embodiments, the analysis module 240 includes: an analysis unit configured to determine the change magnitude of the write margin data of each target data line with the adjustment of the step size; a mapping determination unit configured to determine that there is a mapping relationship between the processor-end data line and the target data line with the largest change in write margin data.

[0068] In some embodiments, the data collection module 230 includes: a step size adjustment unit configured to adjust the step size of the corresponding electrical parameter based on the per-link adjustable characteristic; a step size judgment unit configured to judge whether the current step size reaches a preset maximum step size; a training execution unit configured to perform write training on the target data line when the step size does not reach the preset maximum step size; a data recording unit configured to record the write margin data of the target data line at the current step size and increment the step size by a count value; a loop control unit configured to repeatedly execute the tasks performed by the step size judgment unit, the training execution unit, and the data recording unit until the step size reaches the preset maximum step size.

[0069] In some embodiments, the analysis unit is specifically configured to: monitor whether there is a margin mutation extreme point in the write margin data of the target data line during the step size adjustment process; when detecting the margin mutation extreme point, determine that the change in the write margin data of the target data line is the largest.

[0070] In some embodiments, it further includes: a serial number management module configured to increment the serial number identifier of the target data line after determining the mapping relationship between the target data line and the data line at the processor end; a serial number judgment module configured to judge whether the serial number identifier of the target data line reaches the serial number identifier upper limit value; a mapping traversal module configured to sequentially determine the mapping relationships between all target data lines and the data line at the processor end when the serial number identifier does not reach the upper limit value until the signal identifier of the target data line reaches the serial number identifier upper limit value; a mapping integration module integrates all determined mapping relationships to form a complete mapping relationship between all data lines at the memory end and the data line at the processor end.

[0071] In some embodiments, the electrical parameter corresponding to the per-link adjustable characteristic includes at least one of a data termination equalization parameter and a write reference voltage offset parameter.

[0072] See Figure 7, an embodiment of the present application also provides a server 300, including: a motherboard; a processor installed on the motherboard, and a memory controller is integrated inside the processor; a memory installed on the motherboard and interconnected with the interface of the memory controller; wherein, the memory controller is configured to: train the memory to make the memory enter a readable and writable state; select at least one target data line from the memory end, and activate the per-link adjustable characteristic corresponding to the target data line on the memory, and the per-link adjustable characteristic indicates that it is allowed to independently adjust the electrical parameters of each link of the memory; based on the per-link adjustable characteristic, adjust the step size of the corresponding electrical parameter, and perform a write training on the target data line at each step size; record the write margin data of the target data line; and determine the mapping relationship between the target data line and the data line at the processor end according to the write margin data.

[0073] Certainly, the memory controller in this embodiment is also configured to perform the method for detecting the data line mapping relationship described in any of the foregoing embodiments. Reference can be made to each other and will not be elaborated here.

[0074] See Figure 8 , an embodiment of the present application also provides an electronic device, including: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55. Among them, the circuit board 54 is arranged inside the space surrounded by the housing 51, and the processor 52 and the memory 53 are arranged on the circuit board 54; the power supply circuit 55 is used to supply power to each circuit or device of the above-mentioned electronic device; the memory 53 is used to store executable program codes; the processor 52 runs a program corresponding to the executable program code by reading the executable program codes stored in the memory 53, and is used to execute the method for detecting the data line mapping relationship provided in any of the foregoing embodiments.

[0075] The specific execution process of the above steps by the processor 52 and the further steps executed by the processor 52 by running the executable program code can be referred to the description of the foregoing embodiments and will not be elaborated here.

[0076] In summary, the method, device, server, and electronic device for detecting the data line mapping relationship provided by the embodiments of the present application utilize the per-link adjustable characteristics, such as characteristics like DFE and VrefDQ, to affect the write training result Margin of the memory data line. And mainstream memories have general DFE and VrefDQ characteristics or functions, providing a new specific technical solution for detecting the data line mapping relationship, which can simply and efficiently complete the detection of the mapping relationship and improve the detection accuracy, so as to facilitate the memory controller to obtain an accurate mapping relationship in scenarios such as Memory Down and solve the problem of disordered data line mapping.

[0077] It should be noted that in this text, the focuses of the solutions described in various embodiments are different, but there is a certain interrelated relationship among the various embodiments. When understanding the solutions of this application, the various embodiments can be referred to each other. Additionally, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or measurement control unit comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or measurement control unit. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or measurement control unit comprising the said element.

[0078] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in this application should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A method for detecting the mapping relationship of a data line, characterized in that Including: Training the memory to put the memory into a readable and writable state; Selecting at least one target data line from the memory side and activating the per-link adjustable characteristic corresponding to the target data line on the memory; the per-link adjustable characteristic characterizes that electrical parameters can be independently adjusted for each link of the memory; Based on the per-link adjustable characteristic, adjusting the step size of the corresponding electrical parameter, and performing write training on the target data line at each step size, and recording the write margin data of the target data line; According to the write margin data, determining the mapping relationship between the target data line and the data line on the processor side.

2. The method according to claim 1, wherein The determining the mapping relationship between the target data line and the data line on the processor side according to the write margin data includes: Determining the change magnitude of the write margin data of each target data line with the adjustment of the step size; Determining that a target data line with the largest change in write margin data has a mapping relationship with the data line on the processor side.

3. The method according to claim 1, characterized in that, The electrical parameter corresponding to the per-link adjustable characteristic includes at least one of a data termination equalization parameter and a write reference voltage offset parameter.

4. The method according to claim 1, wherein The adjusting the step size of the corresponding electrical parameter based on the per-link adjustable characteristic, performing write training on the target data line at each step size, and recording the write margin data of the target data line includes: S1. Adjusting the step size of the corresponding electrical parameter based on the per-link adjustable characteristic; S3. Judging whether the current step size reaches a preset maximum step size; S5. If not, performing write training on the target data line at the current step size; S6. Recording the write margin data of the target data line at the current step size, and incrementing the step size by a count value; Repeating the above steps S3~S6 until the step size reaches the preset maximum step size.

5. The method according to claim 2, wherein Before determining that a target data line with the largest change in write margin data has a mapping relationship with the data line on the processor side, it further includes: When it is monitored that the write margin data of a certain target data line has a margin mutation extreme point during the step size adjustment process, it is determined that the change in the write margin data of the target data line is the largest.

6. The method according to claim 1, wherein After determining the mapping relationship between the target data line and the data line on the processor side, the method further includes: performing an increment operation on the serial number identifier of the target data line; wherein, the serial number identifier is used to identify the number of target data lines; Judging whether the serial number identifier of the target data line reaches the serial number identifier upper limit value; If not, sequentially determining the mapping relationships between all target data lines and the data lines on the processor side until the signal identifier of the target data line reaches the serial number identifier upper limit value; Integrating all determined mapping relationships to form a complete mapping relationship between all data lines on the memory side and the data lines on the processor side.

7. A device for detecting the mapping relationship of a data line, characterized in that, Including: A training module configured to train the memory to put the memory into a readable and writable state; A characteristic control module configured to select at least one target data line from the memory side and activate the per-link adjustable characteristic corresponding to the target data line on the memory; the per-link adjustable characteristic characterizes that electrical parameters can be independently adjusted for each link of the memory; A data collection module, configured to adjust the step size of the corresponding electrical parameter based on the per-link adjustable characteristic, perform write training on the target data line at each step size, and record the write margin data of the target data line; An analysis module, configured to determine the mapping relationship between the target data line and the data line at the processor end according to the write margin data.

8. The device according to claim 7, characterized in that, The analysis module includes: An analysis unit, configured to determine the change magnitude of the write margin data of each target data line with the adjustment of the step size; A mapping determination unit, configured to determine that there is a mapping relationship between the target data line with the largest change in write margin data and the data line at the processor end.

9. The device according to claim 7, characterized in that, The data collection module includes: A step size adjustment unit, configured to adjust the step size of the corresponding electrical parameter based on the per-link adjustable characteristic; A step size judgment unit, configured to judge whether the current step size reaches a preset maximum step size; A training execution unit, configured to perform write training on the target data line when the step size does not reach the preset maximum step size; A data recording unit, configured to record the write margin data of the target data line at the current step size and increment the step size by a count value; A loop control unit, configured to repeatedly execute the tasks performed by the step size judgment unit, the training execution unit, and the data recording unit until the step size reaches the preset maximum step size.

10. The device according to claim 8, characterized in that, The analysis unit is specifically configured to: monitor whether there is a margin mutation extreme point in the write margin data of the target data line during the step size adjustment process; when detecting a margin mutation extreme point, determine that the write margin data of the target data line changes the most.

11. The device according to claim 7, characterized in that, It further includes: A serial number management module, configured to increment the serial number identifier of the target data line after determining the mapping relationship between the target data line and the data line at the processor end; A serial number judgment module, configured to judge whether the serial number identifier of the target data line reaches the upper limit value of the serial number identifier; A mapping traversal module, configured to sequentially determine the mapping relationships between all target data lines and the data line at the processor end when the serial number identifier does not reach the upper limit value until the signal identifier of the target data line reaches the upper limit value of the serial number identifier; A mapping integration module integrates all determined mapping relationships to form a complete mapping relationship between all data lines at the memory end and the data line at the processor end.

12. The device according to claim 7, characterized in that, The electrical parameter corresponding to the per-link adjustable characteristic includes at least one of a data termination equalization parameter and a write reference voltage offset parameter.

13. A server, including: A main board; A processor, installed on the main board, and a memory controller is integrated inside the processor; A memory, installed on the main board, and interconnected with the interface of the memory controller; wherein, The memory controller is configured to: Train the memory to make the memory enter a readable and writable state; Select at least one target data line from the memory end, activate the per-link adjustable characteristic corresponding to the target data line on the memory, and the per-link adjustable characteristic indicates that the electrical parameter of each link of the memory is allowed to be independently adjusted; Adjust the step size of the corresponding electrical parameter based on the per-link adjustable characteristic, and perform write training on the target data line at each step size; Record the write margin data of the target data line; Determine the mapping relationship between the target data line and the data line at the processor end according to the written margin data.

14. The server according to claim 13, wherein The memory controller is further configured to execute the method according to any one of claims 2 to 6.

15. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit. Among them, the circuit board is arranged inside the space surrounded by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to each circuit or device of the above-mentioned electronic device; the memory is used to store executable program codes; the processor runs the program corresponding to the executable program codes by reading the executable program codes stored in the memory, and is used to execute the method according to any one of the foregoing claims 1 to 6.

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