Controller, control method and related device for solid state disk

Abstract

The invention provides a controller, a control method and a related device for a solid state disk. The controller comprises at least one controller channel, each controller channel provides a plurality of groups of data buses and a group of control buses, a plurality of groups of flash memory particles are connected with the group of control buses, the plurality of groups of flash memory particles are connected with the plurality of groups of data buses respectively, and each controller channel comprises a control bus control unit used for generating a corresponding control instruction, transmitting a corresponding control instruction to a plurality of groups of flash memory particles through a group of control buses; the data bus control unit is used for generating a corresponding data instruction; the data bus selection unit is used for generating a selection signal based on a host transmission demand, conducting one group of data buses in the plurality of groups of data buses in a time-sharing manner according to the selection signal, and transmitting a corresponding data instruction to the corresponding flash memory particle through the conducted group of data buses so as to perform data reading and writing on the corresponding flash memory particle; the storage capacity can be expanded, and the production cost is reduced.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of memory, and particularly relates to a controller, a control method and related devices for a solid state drive. Background Art

[0002] A solid state drive (SSD) is a storage hard disk made of solid state electronic storage chips, including a controller and a storage medium. Currently, the most mainstream solid state drives adopt flash memory as the storage medium, for example, a non-volatile memory such as flash memory particles (also called flash memory chips, NAND flash in English). Generally, a controller has multiple controller channels, and multiple flash memory particles can be mounted on each controller channel.

[0003] Figure 1 The structural schematic diagram of a solid state drive in the related art is shown. As Figure 1 shown, the solid state drive 100 includes a controller 110 and a storage medium 120. The controller 110 includes at least one controller channel (such as CH0 to CHn, where n is an integer greater than or equal to 1). The storage medium 120 is, for example, an array of flash memory particles. Multiple flash memory particles are mounted under each controller channel. The driving ability of each controller channel is limited, that is, the number of flash memory particles that can be mounted on each controller channel is limited. A commonly used means to expand the storage capacity of an SSD is to increase the number of channels. However, for a large-capacity SSD that has been designed, due to the bandwidth limitation of other modules (such as the host interface), the number of controller channels of the controller has approached the upper limit. In order to support a larger storage capacity, that is, to control more flash memory particles, continuing to increase the number of channels will not continue to bring performance improvement, but will bring some adverse effects. On the one hand, increasing the number of channels will cause the control circuit and wiring layout of the corresponding channels to be integrated inside the controller chip, thereby significantly increasing the chip area of the controller and increasing the production cost. On the other hand, increasing the number of channels will cause more wiring, interfaces and related components to be set on the printed circuit board (PCB) to support the corresponding channels, thereby significantly increasing the overall area of the PCB, reducing the production cost, reducing the system integration and space utilization rate, and may bring a series of new challenges to aspects such as system heat dissipation and electrical performance. Summary of the Invention

[0004] In view of the above problems, the present disclosure provides a controller, a control method and related devices for a solid state drive, aiming to support large-capacity storage, reduce production costs, and balance performance bandwidth and chip area cost.

[0005] According to a first aspect of the present disclosure, there is provided a controller for a solid-state drive, the solid-state drive including the controller and a storage medium, including:

[0006] At least one controller channel, under each of which are mounted multiple groups of flash memory particles in the storage medium. Each controller channel provides multiple groups of data buses and a group of control buses. The multiple groups of flash memory particles are all connected to the group of control buses, and the multiple groups of flash memory particles are respectively connected to the multiple groups of data buses.

[0007] Each controller channel includes:

[0008] A control bus control unit, connected to the group of control buses, for generating corresponding control instructions and transmitting the corresponding control instructions to the multiple groups of flash memory particles via the group of control buses.

[0009] A data bus control unit, for generating corresponding data instructions.

[0010] A data bus selection unit, connected to the data bus control unit and the multiple groups of data buses, for generating a selection signal based on the host transmission requirement, time-divisionally conducting one of the multiple groups of data buses according to the selection signal, and transmitting the corresponding data instruction to the corresponding flash memory particle via the conducted one of the multiple groups of data buses, so as to perform data reading and writing on the corresponding flash memory particle.

[0011] Optionally, when a group of data buses and a group of flash memory particles are added to the controller channel, the data bus selection unit is connected to the added group of data buses, and the added group of data buses is connected to the added group of flash memory particles.

[0012] The data bus selection unit is further configured to time-divisionally conduct the added group of data buses according to the selection signal, and transmit the corresponding data instruction to the corresponding added flash memory particle via the added group of data buses, so as to perform data reading and writing on the corresponding added flash memory particle.

[0013] Optionally, when a group of data buses and a group of flash memory particles are added to the controller channel, the group of control buses is connected to the added group of flash memory particles, and the control bus control unit is further configured to transmit the corresponding control instruction to the added group of flash memory particles via the group of control buses.

[0014] Optionally, the bandwidth design of the added group of data buses for the controller channel is the same as the bandwidth design of the multiple groups of data buses originally set in the controller channel.

[0015] Optionally, when a set of data buses and a set of flash memory particles are deleted for the controller channel, disconnect the data bus selection unit from the deleted set of data buses.

[0016] Optionally, when a set of data buses and a set of flash memory particles are deleted for the controller channel, disconnect the set of control buses from the deleted set of flash memory particles.

[0017] According to a second aspect of the present disclosure, there is provided a solid state drive, comprising:

[0018] A storage medium;

[0019] A controller, including at least one controller channel, under each of the controller channels, multiple sets of flash memory particles in the storage medium are mounted, each of the controller channels provides multiple sets of data buses and a set of control buses, the multiple sets of flash memory particles are all connected to the set of control buses, and the multiple sets of flash memory particles are respectively connected to the multiple sets of data buses.

[0020] Each of the controller channels includes:

[0021] A control bus control unit, connected to the set of control buses, for generating corresponding control instructions and transmitting the corresponding control instructions to the multiple sets of flash memory particles via the set of control buses;

[0022] A data bus control unit, for generating corresponding data instructions;

[0023] A data bus selection unit, connected to the data bus control unit and the multiple sets of data buses, for generating a selection signal based on the host transmission requirement, time-divisionally conducting one set of data buses among the multiple sets of data buses according to the selection signal, and transmitting the corresponding data instructions to the corresponding flash memory particles via the conducted set of data buses, so as to facilitate data reading and writing of the corresponding flash memory particles.

[0024] According to a third aspect of the present disclosure, there is provided a control method for a controller of a solid state drive, the solid state drive includes the controller and a storage medium, and the controller includes:

[0025] At least one controller channel, under each of the controller channels, multiple sets of flash memory particles in the storage medium are mounted, each of the controller channels provides multiple sets of data buses and a set of control buses, the multiple sets of flash memory particles are all connected to the set of control buses, and the multiple sets of flash memory particles are respectively connected to the multiple sets of data buses. Each of the controller channels includes a control bus control unit connected to the set of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple sets of data buses.

[0026] The control method includes:

[0027] Generating corresponding control instructions by the control bus control unit, and transmitting the corresponding control instructions to the multiple groups of flash memory particles via the group of control buses;

[0028] Generating corresponding data instructions by the data bus control unit;

[0029] Generating a selection signal by the data bus selection unit based on the host transmission requirement, time-divisionally conducting one of the multiple groups of data buses according to the selection signal, and transmitting the corresponding data instructions to the corresponding flash memory particles via the conducted group of data buses, so as to facilitate data reading and writing of the corresponding flash memory particles.

[0030] According to a fourth aspect of the present disclosure, there is provided a control device for a controller of a solid-state drive, the solid-state drive including the controller and a storage medium, the controller including:

[0031] At least one controller channel, multiple groups of flash memory particles in the storage medium being mounted under each controller channel, each controller channel providing multiple groups of data buses and a group of control buses, the multiple groups of flash memory particles being all connected to the group of control buses, the multiple groups of flash memory particles being respectively connected to the multiple groups of data buses, and each controller channel including a control bus control unit connected to the group of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple groups of data buses;

[0032] The control device includes:

[0033] A control instruction transmission unit, configured to generate corresponding control instructions by the control bus control unit, and transmit the corresponding control instructions to the multiple groups of flash memory particles via the group of control buses;

[0034] A data instruction generation unit, configured to generate corresponding data instructions by the data bus control unit;

[0035] A data instruction transmission unit, configured to generate a selection signal by the data bus selection unit based on the host transmission requirement, time-divisionally conduct one of the multiple groups of data buses according to the selection signal, and transmit the corresponding data instructions to the corresponding flash memory particles via the conducted group of data buses, so as to facilitate data reading and writing of the corresponding flash memory particles.

[0036] According to a fifth aspect of the present disclosure, there is provided an electronic device, including: a processor, a memory, and a program stored on the memory and executable on the processor, and when the program is executed by the processor, the steps of the method described above are implemented.

[0037] The present disclosure brings the following beneficial effects:

[0038] The controller for a solid-state drive provided by the present disclosure can support controlling more flash memory particles, achieving storage capacity expansion, by setting two or more sets of data buses in each controller channel without adding control buses, just like increasing the number of controller channels. For a large-capacity SSD that has already been designed, compared with adding controller channels, it can reduce the physical layer for setting control buses, and by adding a data bus selection unit between the physical layer and the protocol layer, there is no need to change the control bus control unit and the data bus control unit, which reduces the design difficulty. There is no need to integrate the control circuit and wiring layout of the corresponding channel inside the controller chip, reducing the chip area and production cost of the controller, and balancing the performance bandwidth and the chip area cost. There is no need to set more wiring, interfaces, and related components on the PCB to support the corresponding channel, reducing the overall area and production cost of the PCB, improving the system integration and space utilization rate, and can improve the performance in aspects such as system heat dissipation and electrical performance.

[0039] Other features and advantages of the present disclosure will be described in the following description, and in part, will become apparent from the description or be understood by implementing the present disclosure. The objectives and other advantages of the present disclosure are achieved and obtained by the structures specifically pointed out in the description and the drawings.

[0040] To make the above objectives, features, and advantages of the present disclosure more obvious and understandable, the following specific preferred embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. Description of the Drawings

[0041] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objectives, features, and advantages of the present disclosure will become clearer. In the drawings:

[0042] Figure 1 Showing a schematic structural diagram of a solid-state drive in the related art;

[0043] Figure 2 Showing a schematic structural diagram of a computer system provided according to an embodiment of the present disclosure;

[0044] Figure 3 Showing a schematic structural diagram of a controller channel and a flash memory particle provided according to an embodiment of the present disclosure;

[0045] Figure 4 Showing a schematic structural diagram of a controller channel provided according to an embodiment of the present disclosure;

[0046] Figure 5 Showing a schematic flowchart of a control method for a memory of a solid-state drive provided according to an embodiment of the present disclosure;

[0047] Figure 6 A schematic diagram showing a control device for a memory of a solid-state drive provided according to an embodiment of the present disclosure;

[0048] Figure 7 A schematic diagram showing the structure of an electronic device provided according to an embodiment of the present disclosure. Detailed implementation manners

[0049] The various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0050] The following terms are used herein:

[0051] A controller channel (Channel) is a set of physical pins in an SSD that connects the controller of the SSD and the storage medium and is responsible for receiving and transmitting data and commands.

[0052] Figure 2 A schematic diagram showing the structure of a computer system provided according to an embodiment of the present disclosure. As Figure 2 shown, the computer system 200 includes a host 210 and a solid-state drive. The solid-state drive includes a controller 220 and a storage medium 230. The controller 220 is connected to the host 210 and is used to exchange data with the host 210. The controller 220 connects the host 210 and the storage medium 230 and stores the write data of the host 210 in the storage medium 230.

[0053] The controller 220 includes a host interface 221, a processor 222, a cache unit 223, a memory controller 224, and at least one controller channel (for example, CH0 to CHn, where n is an integer greater than or equal to 1). The host interface 221 of the controller 220 is connected to the host 210 to transmit data and read / write instructions. The processor 222 is connected to the host interface 221, the cache unit 223, and the memory controller 224. The processor 222 parses and executes read / write operations on the read / write instructions. The cache unit 223 is, for example, an SRAM and is used to store a mapping table. The memory controller 224 controls the transmission and storage of write data. The processor 222 is also used to implement the core software layer of memory control, that is, the FTL (Flash Translation Layer). The FTL consists of several programs. The processor 222 executes the programs so that when a read / write instruction is received, the instruction can be converted to complete the access to the storage medium 230. Therefore, the file system and operating system of the host 210 can access the storage medium as if it were their own memory. This FTL also has features such as supporting bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0054] The storage medium 230 is, for example, an array of flash memory particles. To improve data read / write performance, the memory controller 224 can read from and write to the flash memory particles of the storage medium 230 via the controller channels. In some embodiments, the controller channels can adopt a new flash memory interface protocol (for example, Separate Command Address, abbreviated as SCA). The SCA protocol separates the command / address and data transmissions and places them on two different transmission buses for transmission, that is, the control instructions (which can also be called Command and Address instructions, abbreviated as CA instructions) are transmitted on the control bus (which can also be called the CA bus), and the data instructions (which can also be called DATA instructions, abbreviated as DQ instructions) (that is, the data to be written to or read from the flash memory particles) are transmitted on the data bus (which can also be called the DQ bus). For example, the control instructions include CE, CLE, ALE, and WEn. For example, the data instructions include DQ, DBI, DQS, DQSn, REn, and RE. In some embodiments, multiple groups of flash memory particles are mounted under each controller channel. Each group of flash memory particles includes multiple flash memory particles. Each controller channel provides multiple groups of data buses and a group of control buses, and multiple groups of flash memory particles are all connected to the group of control buses. Multiple groups of flash memory particles are respectively connected to multiple groups of data buses. For example, for a large-capacity storage hard disk scenario, the controller 220 includes 4 controller channels, and the storage capacity of a single flash memory particle is 128 GB. Then, to achieve a storage capacity of 8 TB for the storage medium 230, 16 flash memory particles are mounted under each controller channel. These 16 flash memory particles can be divided into 2 groups, with each group including 4 flash memory particles. These 16 flash memory particles can be connected to a group of control buses, and the two groups of flash memory particles are respectively connected to the corresponding data buses. Figure 3 FIG. shows a schematic structural diagram of a controller channel and flash memory particles provided according to an embodiment of the present disclosure. As Figure 3 shown, 4 groups of flash memory particles are mounted under the controller channel CH0, that is, flash memory particle Group0 to flash memory particle Group3. The controller channel CH0 provides 4 groups of data buses (that is, DQ BUS 0 to DQ BUS 3) and a group of control buses (that is, CA BUS). Flash memory particle Group0 to flash memory particle Group3 are all connected to the group of control buses and share the group of control buses. Flash memory particle Group0 to flash memory particle Group3 correspond to DQ BUS 0 to DQ BUS 3, and each group of flash memory particles is respectively connected to a corresponding group of data buses. In some embodiments, at the working rate required by the product, if the maximum number of flash memory particles that a controller channel can drive is A, and the maximum drivable capacity of a group of data buses is B, then the number of groups of data buses set for a controller channel is the ceiling result of (A / B).

[0055] Figure 4The structural schematic diagram of a controller channel provided according to an embodiment of the present disclosure is shown. As Figure 3 shown, the controller channel 300 communicates with the host interface 221. The controller channel 300 includes a transport layer 350, a protocol layer 360, and a physical layer 340. The protocol layer 360 includes a control bus management unit 310 and a data bus management unit 320. The physical layer 340 includes multiple groups of data buses (e.g., DQ BUS 0 to DQ BUS 3) and a group of control buses (e.g., CA BUS). In some embodiments, the controller channel 300 further includes a data bus selection unit 330. The data bus selection unit 330 is located between the protocol layer 360 and the physical layer 340.

[0056] In some embodiments, the control bus control unit 310 is connected to the group of control buses, and is used to generate corresponding control instructions, and transmit the corresponding control instructions to the multiple groups of flash memory particles via the group of control buses. The data bus control unit 320 generates corresponding data instructions. The data bus selection unit 330 is connected to the data bus control unit 310 and the multiple groups of data buses, and is used to generate a selection signal based on the host transmission requirement, time-divisionally conduct one group of data buses in the multiple groups of data buses according to the selection signal, and transmit the corresponding data instructions to the corresponding flash memory particle via the conducted one group of data buses (e.g., DQ BUS 0), so as to facilitate data reading and writing of the corresponding flash memory particle. It can be understood that by setting two or more groups of data buses in each controller channel without adding control buses, it is possible to support controlling more flash memory particles like increasing the number of controller channels, thereby realizing storage capacity expansion. Selecting the corresponding data bus to conduct according to the selection signal and setting the other data buses to the low-power mode and not working temporarily can reduce power consumption.

[0057] It can be understood that for a large-capacity SSD that has been designed, compared with adding controller channels, the physical layer for setting control buses can be reduced, and by adding a data bus selection unit between the physical layer and the protocol layer, there is no need to change the control bus control unit and the data bus control unit, which reduces the design difficulty. There is no need to integrate the control circuit and wiring layout of the corresponding channel inside the controller chip, which reduces the chip area and production cost of the controller. It effectively simplifies the complex wiring layout of the PCB, enables the PCB that originally required a multi-layer board design due to dense wiring to reduce the number of layers, reduces the design complexity and overall area of the PCB, reduces the raw material cost, processing cost, and potential debugging cost caused by complex design in the production and manufacturing links, improves the system integration and space utilization rate, and can improve the performance in aspects such as system heat dissipation and electrical performance.

[0058] In some embodiments, when adding a set of data buses and a set of flash memory particles for a controller channel, the data bus selection unit 330 is connected to the added set of data buses, the added set of data buses is connected to the added set of flash memory particles, and a set of control buses is connected to the added set of flash memory particles. The data bus selection unit 330 also conducts the added set of data buses in a time-sharing manner according to the selection signal, and transmits the corresponding data instructions to the corresponding added flash memory particles via the added set of data buses, so as to facilitate data reading and writing of the corresponding added flash memory particles. The control bus control unit 310 also transmits the corresponding control instructions to the added set of flash memory particles via a set of control buses. It can be understood that since the I / O rate of the control bus is relatively low, more flash memory particles can be driven, and the flash memory particles mounted under the same controller channel can share the control bus. It can be understood that the flash memory particles originally mounted on one controller channel can be divided into multiple groups, and each data bus is connected to a group of flash memory particles, which can ensure the transmission rate of the data bus, reduce the load of the data bus, effectively disperse the mounting pressure originally concentrated on a single data bus, and greatly reduce the number of flash memory particles connected to each data bus. The reduction of the load on each data bus creates favorable conditions for the improvement of the data bus rate, enabling data transmission to run at a higher speed. In some embodiments, the bandwidth design of the added set of data buses for the controller channel is the same as the bandwidth design of the multiple sets of data buses originally set in the controller channel. It can be understood that without modifying the physical layer and protocol layer of the controller channel, the storage capacity of the solid-state drive can be expanded by adding a set of data buses and a set of flash memory particles to the controller channel, which can reduce the design difficulty. Only by adding data buses instead of adding a complete controller channel, only a small number of PINs need to be added to balance the performance bandwidth and the chip area cost.

[0059] In some embodiments, when deleting a set of data buses and a set of flash memory particles for a controller channel, the data bus selection unit 330 is disconnected from the deleted set of data buses, and a set of control buses is disconnected from the deleted set of flash memory particles. It can be understood that without modifying the physical layer and protocol layer of the controller channel, the storage capacity of the solid-state drive can be changed by deleting a set of data buses and a set of flash memory particles from the controller channel, making the storage capacity design of the solid-state drive more flexible.

[0060] Figure 5The flowchart shows a control method for a memory of a solid-state drive provided according to an embodiment of the present disclosure. The solid-state drive includes the controller and the storage medium. The controller includes: at least one controller channel, under each of which multiple groups of flash memory particles in the storage medium are mounted. Each controller channel provides multiple groups of data buses and a group of control buses. The multiple groups of flash memory particles are all connected to the group of control buses, and the multiple groups of flash memory particles are respectively connected to the multiple groups of data buses. Each controller channel includes a control bus control unit connected to the group of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple groups of data buses. As Figure 5 shown, the control method of the embodiment of the present disclosure may include:

[0061] In step S510, the control bus control unit generates corresponding control instructions and transmits the corresponding control instructions to the multiple groups of flash memory particles via the group of control buses.

[0062] In step S520, the data bus control unit generates corresponding data instructions.

[0063] In step S530, the data bus selection unit generates a selection signal based on the host transmission requirement, time-divisionally conducts one group of data buses among the multiple groups of data buses according to the selection signal, and transmits the corresponding data instructions to the corresponding flash memory particles via the conducted group of data buses, so as to perform data reading and writing on the corresponding flash memory particles.

[0064] Since the process of controlling the controller using the control method of the embodiment of the present disclosure has been described in detail in the device embodiment above, it will not be repeated here.

[0065] Figure 6 The schematic diagram shows a control device for a memory of a solid-state drive provided according to an embodiment of the present disclosure. The solid-state drive includes the controller and the storage medium. The controller includes: at least one controller channel, under each of which multiple groups of flash memory particles in the storage medium are mounted. Each controller channel provides multiple groups of data buses and a group of control buses. The multiple groups of flash memory particles are all connected to the group of control buses, and the multiple groups of flash memory particles are respectively connected to the multiple groups of data buses. Each controller channel includes a control bus control unit connected to the group of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple groups of data buses. As Figure 6 shown, the control device 600 includes:

[0066] A control instruction transmission unit 610, configured to generate corresponding control instructions by the control bus control unit and transmit the corresponding control instructions to the multiple groups of flash memory particles via the group of control buses.

[0067] A data instruction generation unit 620, configured to generate corresponding data instructions by the data bus control unit.

[0068] A data instruction transmission unit 630, configured to generate a selection signal by the data bus selection unit based on the host transmission requirement, time-divisionally conduct one of the multiple groups of data buses according to the selection signal, and transmit the corresponding data instructions to the corresponding flash memory particles via the conducted one of the data buses, so as to facilitate data reading and writing of the corresponding flash memory particles.

[0069] Since the process of controlling the controller by using the control method of the embodiments of the present disclosure has been described in detail in the device embodiments above, it will not be repeated here.

[0070] The embodiments of the present disclosure further provide an electronic device, as Figure 7 shown, including a memory 720, a processor 710, and a program stored on the memory 720 and executable on the processor 710. When the program is executed by the processor 710, it can implement each process of the above embodiments of the method and achieve the same technical effects. To avoid repetition, it will not be repeated here.

[0071] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions or by controlling relevant hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. For this purpose, the embodiments of the present disclosure further provide a storage medium, on which a computer program or instructions are stored. When the computer program or instructions are executed by a processor, it can implement each process of the above embodiments of the method.

[0072] Since the instructions stored in the storage medium can execute the steps in the method provided by the embodiments of the present disclosure, the beneficial effects that can be achieved by the method provided by the embodiments of the present disclosure can be realized. For details, see the previous embodiments and will not be repeated here. The specific implementation of each of the above operations can refer to the previous embodiments and will not be repeated here.

[0073] In summary, for the controller for a solid-state drive provided by the present disclosure, by setting two or more sets of data buses on each controller channel without adding control buses, it can support controlling more flash memory particles, just like increasing the number of controller channels, to achieve storage capacity expansion. For a large-capacity SSD that has already been designed, compared with adding controller channels, it can reduce the physical layer for setting control buses, and by adding a data bus selection unit between the physical layer and the protocol layer, there is no need to change the control bus control unit and the data bus control unit, which reduces the design difficulty. There is no need to integrate the control circuit and line layout of the corresponding channel inside the controller chip, reducing the chip area and production cost of the controller. There is no need to set more wiring, interfaces, and related components on the PCB to support the corresponding channel, reducing the overall area and production cost of the PCB, improving the system integration and space utilization, and can improve the performance in terms of system heat dissipation, electrical performance, etc.

[0074] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present disclosure, rather than limiting the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present disclosure.

Claims

1. A controller for a solid-state drive, the solid-state drive including the controller and a storage medium, comprising: At least one controller channel, under each of which multiple groups of flash memory particles in the storage medium are mounted. Each controller channel provides multiple groups of data buses and a group of control buses. The multiple groups of flash memory particles are all connected to the group of control buses, and the multiple groups of flash memory particles are respectively connected to the multiple groups of data buses. Each of the controller channels includes: A control bus control unit, connected to the group of control buses, for generating corresponding control instructions and transmitting the corresponding control instructions to the multiple groups of flash memory particles via the group of control buses; A data bus control unit, for generating corresponding data instructions; A data bus selection unit, connected to the data bus control unit and the multiple groups of data buses, for generating a selection signal based on the host transmission requirement, time-divisionally conducting one group of data buses among the multiple groups of data buses according to the selection signal, and transmitting the corresponding data instructions to the corresponding flash memory particles via the conducted group of data buses, so as to facilitate data reading and writing of the corresponding flash memory particles.

2. The controller according to claim 1, wherein, When a group of data buses and a group of flash memory particles are added to the controller channel, the data bus selection unit is connected to the added group of data buses, and the added group of data buses is connected to the added group of flash memory particles. The data bus selection unit is further configured to time-divisionally conduct the added group of data buses according to the selection signal, and transmit the corresponding data instructions to the corresponding added flash memory particles via the added group of data buses, so as to facilitate data reading and writing of the corresponding added flash memory particles.

3. The controller according to claim 2, wherein, When a group of data buses and a group of flash memory particles are added to the controller channel, the group of control buses is connected to the added group of flash memory particles, and the control bus control unit is further configured to transmit the corresponding control instructions to the added group of flash memory particles via the group of control buses.

4. The controller according to claim 3, wherein, The bandwidth design of the added group of data buses for the controller channel is the same as that of the multiple groups of data buses originally set in the controller channel.

5. The controller according to claim 2, wherein, When a group of data buses and a group of flash memory particles are deleted from the controller channel, the data bus selection unit is disconnected from the deleted group of data buses.

6. The controller according to claim 5, wherein, When a group of data buses and a group of flash memory particles are deleted from the controller channel, the group of control buses is disconnected from the deleted group of flash memory particles.

7. A solid-state drive, comprising: A storage medium; A controller, including at least one controller channel, under each of which multiple groups of flash memory particles in the storage medium are mounted. Each controller channel provides multiple groups of data buses and a group of control buses. The multiple groups of flash memory particles are all connected to the group of control buses, and the multiple groups of flash memory particles are respectively connected to the multiple groups of data buses. Each of the controller channels includes: A control bus control unit, connected to the group of control buses, for generating corresponding control instructions and transmitting the corresponding control instructions to the multiple groups of flash memory particles via the group of control buses; A data bus control unit, for generating corresponding data instructions; A data bus selection unit, connected to the data bus control unit and the multiple groups of data buses, is configured to generate a selection signal based on the host transmission requirement, time-division conduct one group of data buses among the multiple groups of data buses according to the selection signal, and transmit the corresponding data instruction to the corresponding flash memory particle via the conducted group of data buses, so as to facilitate data reading and writing of the corresponding flash memory particle.

8. A control method for a controller of a solid-state drive, the solid-state drive includes the controller and a storage medium, and the controller includes: At least one controller channel, under each controller channel, multiple groups of flash memory particles in the storage medium are mounted. Each controller channel provides multiple groups of data buses and a group of control buses. The multiple groups of flash memory particles are all connected to the group of control buses, and the multiple groups of flash memory particles are respectively connected to the multiple groups of data buses. Each controller channel includes a control bus control unit connected to the group of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple groups of data buses; The control method includes: Generating a corresponding control instruction by the control bus control unit, and transmitting the corresponding control instruction to the multiple groups of flash memory particles via the group of control buses; Generating a corresponding data instruction by the data bus control unit; Generating a selection signal by the data bus selection unit based on the host transmission requirement, time-division conduct one group of data buses among the multiple groups of data buses according to the selection signal, and transmit the corresponding data instruction to the corresponding flash memory particle via the conducted group of data buses, so as to facilitate data reading and writing of the corresponding flash memory particle.

9. A control device for a controller of a solid-state drive, the solid-state drive includes the controller and a storage medium, and the controller includes: At least one controller channel, under each controller channel, multiple groups of flash memory particles in the storage medium are mounted. Each controller channel provides multiple groups of data buses and a group of control buses. The multiple groups of flash memory particles are all connected to the group of control buses, and the multiple groups of flash memory particles are respectively connected to the multiple groups of data buses. Each controller channel includes a control bus control unit connected to the group of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple groups of data buses; The control device includes: A control instruction transmission unit, configured to generate a corresponding control instruction by the control bus control unit, and transmit the corresponding control instruction to the multiple groups of flash memory particles via the group of control buses; A data instruction generation unit, configured to generate a corresponding data instruction by the data bus control unit; A data instruction transmission unit, configured to generate a selection signal by the data bus selection unit based on the host transmission requirement, time-division conduct one group of data buses among the multiple groups of data buses according to the selection signal, and transmit the corresponding data instruction to the corresponding flash memory particle via the conducted group of data buses, so as to facilitate data reading and writing of the corresponding flash memory particle.

10. An electronic device, comprising: A processor, a memory, and a program stored on the memory and executable on the processor, wherein when the program is executed by the processor, the steps of the method described in claim 8 are implemented.

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