Special high-performance storage device designed for intelligent calculation training and reasoning

Abstract

The invention provides special high-performance storage equipment designed for intelligent calculation training and reasoning. The special high-performance storage equipment comprises a case and at least two storage nodes arranged in the case, each storage node comprises the following components on the mainboard: a storage unit comprising a plurality of high-speed interface hard disk drive slots, the hard disk drive slots are located at the front part of the case and configured to accommodate a plurality of drivers, and each driver exclusively occupies a high-speed data bus channel, is directly connected with the processor and supports non-blocking concurrent data access; the processor is connected with the storage unit and the memory unit and supports at least one extensible processor; the memory unit is connected with the processor and supports an error correction code (ECC) memory; and the high-speed expansion slot is connected with the processor and the storage unit. The equipment improves the data processing speed through a high-speed data bus and a concurrent access design, has good expansibility and reliability, is suitable for intelligent calculation training and reasoning application, and can meet the requirements of large-scale data storage and efficient processing.

Description

Technical Field

[0001] The present invention relates to computer storage technology, and particularly to a dedicated high-performance storage device designed for intelligent computing training and inference. Background Art

[0002] In the field of modern computing, with the rapid development of artificial intelligence, cloud computing, and big data, especially the increasing demand for intelligent computing training and inference, traditional storage technologies are facing huge challenges. To achieve efficient and fast data processing, especially when training and inferring on massive data, the performance of the storage system has become one of the key bottlenecks. An efficient storage system not only requires fast data reading and writing capabilities but also needs to be able to handle a large number of concurrent requests to meet the needs of large-scale intelligent computing.

[0003] Currently, traditional storage devices mostly adopt architectures based on a combination of hard disk drives (HDDs) or solid-state drives (SSDs). These devices have certain performance limitations when dealing with large amounts of data, especially in application scenarios that require high throughput and low latency. Although SSDs are faster than HDDs, existing storage systems are still difficult to provide sufficient performance guarantees when facing ultra-large-scale data concurrent access and high computing requirements. In addition, traditional storage systems also have certain deficiencies in terms of scalability, data concurrent access, and fault tolerance.

[0004] Most of the storage devices in the prior art are optimized for traditional application scenarios and do not fully consider the high-performance data transmission requirements in intelligent computing. Although some high-performance storage solutions have been proposed, they often cannot simultaneously meet the requirements of multiple aspects such as high-concurrency data access, storage system scalability, and fault tolerance. There is generally a lack of optimized designs for the specific requirements of intelligent computing training and inference in the prior art, resulting in existing storage systems being difficult to meet the requirements of high-speed, reliable, and efficient data storage in practical applications. Therefore, there is an urgent need for a new type of storage device to meet the growing demand for storage performance in the field of intelligent computing. Summary of the Invention

[0005] In view of this, the purpose of the embodiments of the present invention is to provide a dedicated high-performance storage device designed for intelligent computing training and inference to solve at least one of the above technical problems.

[0006] To achieve the above object, there is provided a dedicated high-performance storage device designed for intelligent computing training and inference, which includes:

[0007] A chassis, and at least two storage nodes disposed within the chassis;

[0008] Each of the storage nodes includes the following components disposed on a motherboard:

[0009] A storage unit, including multiple high-speed interface hard disk drive slots, which are located at the front of the chassis and are configured to accommodate multiple drives. Each drive exclusively occupies a high-speed data bus channel and is directly connected to the processor, supporting non-blocking concurrent data access;

[0010] A processor, connected to the storage unit and the memory unit, supporting at least one expandable processor;

[0011] A memory unit, connected to the processor, supporting Error Correction Code (ECC) memory;

[0012] A high-speed expansion slot, connected to the processor and the storage unit, for installing an external inference acceleration card.

[0013] In some possible implementation manners, each storage node has a built-in remote diagnosis function, supporting real-time feedback of fault codes;

[0014] The remote diagnosis function is implemented through a Baseboard Management Controller (BMC). The BMC is an integrated component of the motherboard of the storage node, runs independently of the operating system, and is remotely accessed through the IPMI LAN port;

[0015] The BMC is used to collect the hardware status data of the processor, the memory unit, the storage unit, and the power module in real time, obtain hardware exception events according to the hardware status data, convert the hardware exception events into standardized fault codes, and record them in the System Event Log (SEL);

[0016] The storage device supports viewing the fault codes in the SEL of the hardware event log in real time through IPMI tools or a web interface.

[0017] In some possible implementation manners, the hardware status data includes: the temperature of the processor, the fan speed, and the status of the power module; the storage device supports fault alarm through LED indicators, Simple Network Management Protocol (SNMP) traps, or email notifications.

[0018] In some possible implementation manners, the remote diagnosis function supports power module control and hardware status diagnosis through out-of-band management functions in the case of an operating system crash or failure to start;

[0019] The BMC supports ensuring the security of remote management sessions through encryption protocols. The encryption protocols include HTTPS or IPMI over LAN encryption modes, and provide the location of hardware faults through BIOS POST codes.

[0020] In some possible embodiments, each of the storage nodes is equipped with 24 PCIe 5.0 NVMe drives, and each drive exclusively occupies one PCIe channel, supporting multi-task concurrent data access;

[0021] An independent disk redundant array RAID controller is built into the motherboard of the storage node. The RAID controller executes a dynamic load balancing algorithm, and the dynamic load balancing algorithm dynamically allocates storage bandwidth resources according to the priorities of computing tasks.

[0022] In some possible embodiments, the motherboard of the storage device provides 4 PCIe 5.0 expansion slots. The first slot and the second slot are 2 PCIe 5.0 x16 slots, and the third slot and the fourth slot are 2 PCIe 5.0 x8 slots. The expansion slots are located in the rear area of the motherboard and are used to install external inference acceleration cards;

[0023] The dynamic load balancing algorithm dynamically configures PCIe bandwidth resources through the following steps:

[0024] The baseboard management controller BMC monitors the task loads of the GPU acceleration cards or FPGA acceleration cards connected to the expansion slots in real time. The task loads are quantified by the following metrics: the number of I / O requests for inference tasks per unit time; the utilization rate of the computing units of the acceleration cards; the occupancy rate of the PCIe channel bandwidth of the acceleration cards;

[0025] When any one of the metrics in the task load exceeds a preset threshold, the BMC sends a PCIe resource configuration instruction to the BIOS;

[0026] The BIOS performs the following operations according to the source configuration instruction: switches the PCIe 5.0 x16 link of the first slot or the second slot from the default x16 single-channel mode to two independent x8 channels; dedicates one of the x8 channels to the high-priority inference acceleration card; reserves the other x8 channel for other expansion cards other than the inference acceleration card; the bandwidth resource configuration process is implemented through the PCIe link splitting function of the BIOS;

[0027] When the task load drops below the preset threshold, the BMC notifies the BIOS to restore the default x16 single-channel mode.

[0028] In some possible embodiments, the BMC is used to continuously collect utilization data of the processor, memory unit, storage unit, and network, and provide an API externally through the IPMI interface, enabling an external management system to perform the following operations through the API: query the real-time utilization data; trigger the dynamic load balancing algorithm to adjust the PCIe bandwidth resource configuration; receive real-time alarms of hardware exception events.

[0029] In some possible embodiments, the storage device is equipped with dual 2000W titanium power supplies and multiple fans;

[0030] The BMC is also used to automatically trigger load migration when an abnormal power module or abnormal heat dissipation is detected.

[0031] In some possible embodiments, the storage unit, the processor, and the memory unit achieve coordinated scheduling through an optimized BIOS.

[0032] The above technical solution has the following beneficial effects:

[0033] The above technical solution provides a dedicated high-performance storage device designed for intelligent computing training and inference. By configuring multiple high-speed interface hard drive slots at the front of the chassis and adopting interfaces that support hot plugging, the installation and replacement of the drives are made more convenient; the connection design between the processor and the storage unit and the memory unit can support scalable processors and ECC memory, enhancing the computing performance and data integrity of the device; the configuration of high-speed expansion slots further improves the scalability of the storage system; each of the multiple drives exclusively occupies a high-speed data bus channel, supporting concurrent data access, thus significantly improving the data processing speed and the overall performance of the system, being able to meet high-performance storage requirements, and being particularly suitable for large-scale intelligent computing training and inference tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. The drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 is the front view of the front panel of the storage device according to an embodiment of the present invention;

[0036] Figure 2 is the rear view of the storage device according to an embodiment of the present invention;

[0037] Figure 3 is the schematic diagram of the inner rail installed inside the chassis according to an embodiment of the present invention;

[0038] Figure 4 is the schematic diagram of the process of installing the storage device onto the rack according to an embodiment of the present invention;

[0039] Figure 5 is the schematic diagram of removing the top cover of the storage device for maintenance according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0041] Intelligent computing training and inference refer to the process of processing, analyzing, and learning a large amount of data in the field of intelligent computing, especially in the applications of artificial intelligence and machine learning. Intelligent computing training refers to using a large amount of labeled or unlabeled data to learn and train through an algorithm model, so that the model can extract rules, features, or knowledge from the data, and then be used for predicting or classifying future data. Inference refers to after the model training is completed, using the model to perform real-time processing and prediction on the newly input data, so as to provide support for decision-making or operations. Intelligent computing training and inference require efficient data storage and processing capabilities, so dedicated high-performance storage devices are needed to meet the high-speed reading and writing requirements of massive data and ensure the efficiency and accuracy of the training and inference processes.

[0042] Embodiment 1

[0043] Figure 1 Shows the front panel of the storage device. Labels 0 to 23 correspond to 24 2.5-inch PCIe 5.0 NVMe hard drive slots. The control panel is provided with: a power button, and the main power switch is used to enable or remove the server power. Pressing this button turns off the system power but keeps the standby power. A UID button, used to turn on or off the UID LED indicator. A power LED, used to indicate that the system power supply unit is powered. When the system is running, this LED should be normally lit. A drive LED, which blinks when the storage drive is active. A NIC2 LED, which blinks when there is network activity on LAN port 2. A NIC1 LED, used when there is network activity on LAN port 1, the NIC1 LED blinks. An overheat LED, used to indicate that the system has an overheat situation. An information LED, used to alert the operator of different states.

[0044] Figure 2 Shows the rear view of the storage device, equipped with PCIe 5.0 expansion slots, 10GbE LAN ports, etc. Figure 2Among them, the power supply corresponds to two 2000-watt high-efficiency power supplies (PWS0 on the left and PWS1 on the right); the IPMI LAN port corresponds to one RJ45 1GbE dedicated IPMI LAN port; the COM port corresponds to one COM (serial port) port; the LAN port corresponds to two RJ45 10GbE LAN ports; the USB port corresponds to two USB 3.0 ports; the VGA port corresponds to one video graphics port. Figure 2 In it, label 1 is a PCIe 5.0 x16 low-profile slot, label 2 is a PCIe 5.0 x16 low-profile slot, label 3 is a PCIe 5.0 x8 low-profile slot, and label 4 is a PCIe 5.0 x8 low-profile slot.

[0045] Figure 3 It shows the inner rails installed inside the chassis, which support the smooth installation of hardware components. The process of installing the inner rails onto the chassis includes: confirming that the left and right inner rails are correctly identified. Place the inner rails tightly against the sides of the chassis, aligning the pins on the inner rails with the slotted holes on the sides of the chassis. Slide the inner rails to the rear of the chassis until the pins reach the end of the narrow slots, which can fix the inner rails to the chassis. Optional screws can be additionally added to ensure higher security.

[0046] Figure 4 It shows the process of installing the storage device onto the rack, which includes: pulling out two middle rails from the front of the outer rails until each buckle stops. Align the inner rails on the chassis with the front ends of the middle rails. Slide the inner rails on the chassis into the middle rails, ensuring even pressure on both sides. When partially inserted, the locking lever will stop further movement. Press the locking lever inside the inner rail and push the chassis into the rear of the rack.

[0047] Figure 5 It shows the process of removing the top cover of the storage device for maintenance. The top cover consists of a front cover and a rear cover, which are connected by hinges. Its maintenance process includes: turning off the system power supply and unplugging the power cord from the rear of the power supply; removing three screws at the front of the hinge part of the top cover; lifting the hinge cover to access the fan area.

[0048] An embodiment of the present invention provides a dedicated high-performance storage device designed for intelligent computing training and inference, which includes:

[0049] A chassis, and at least two storage nodes arranged inside the chassis;

[0050] Each of the storage nodes includes the following components arranged on the motherboard:

[0051] A storage unit, including a plurality of high-speed interface hard disk drive slots located at the front of the chassis, configured to accommodate a plurality of drives, each drive exclusive to a high-speed data bus channel and directly connected to the processor, supporting non-blocking concurrent data access;

[0052] A processor, connected to the storage unit and the memory unit, supporting at least one expandable processor;

[0053] A memory unit, connected to the processor, supporting Error Correction Code (ECC) memory;

[0054] A high-speed expansion slot, connected to the processor and the storage unit, for installing an external inference acceleration card.

[0055] Furthermore, each storage node has a built-in remote diagnosis function, supporting real-time feedback of fault codes;

[0056] The remote diagnosis function is implemented through a Baseboard Management Controller (BMC), which is an integrated component of the motherboard of the storage node, runs independently of the operating system, and is remotely accessible through the IPMI LAN port; IPMI refers to the Intelligent Platform Management Interface.

[0057] The BMC is used to collect hardware status data of the processor, memory unit, storage unit, and power module in real time, obtain abnormal events based on the hardware status data, convert the abnormal events into standardized fault codes, and record them in the System Event Log (SEL);

[0058] The storage device supports real-time viewing of the fault codes in the SEL through IPMI tools or a web interface.

[0059] Furthermore, the fault codes include: critical error codes and non-critical error codes. Critical error codes are caused by fatal errors that prevent the storage node from passing hardware self-checks, including processor failure, uncorrectable ECC errors in memory, and power module power-off. Non-critical error codes are triggered by anomalies that allow the storage node to operate in a degraded state, including fan speed exceeding the threshold, NVMe drive temperature warning, and PCIe link speed reduction; the storage device supports real-time viewing of the fault codes in the SEL through IPMI tools or a web interface, and triggers LED alarms, SNMP notifications, or email alarms based on the severity level of the codes.

[0060] Furthermore, the BMC is specifically configured to: collect in real time hardware status data including the temperature and operating status of the processor, the ECC status of the memory unit, the temperature and health metrics of the NVMe drives in the storage unit, the status of the power module and the load, the speed and fault signals of the system fans, etc. When these data exceed the preset thresholds or device anomalies are detected, the BMC determines them as abnormal events and generates critical error codes or non-critical error codes according to the severity of the events. Critical error codes indicate that there are fatal faults in the storage node, such as the processor temperature exceeding the safety threshold (≥95°C) and remaining over the limit continuously, the memory unit having uncorrectable ECC errors, or the power module output being powered off or the voltage exceeding the tolerance range (±10%); non-critical error codes indicate tolerable anomalies, such as the NVMe drive temperature exceeding the warning threshold (≥70°C) but not reaching the critical value, the system fan speed deviating from the set value (±15%) but not stopping, or the PCIe link rate degrading to the low-bandwidth mode. These fault codes correspond one-to-one with the abnormal events, are recorded in the hardware event log (SEL), and support real-time query through IPMI tools or the Web interface, while triggering LED alarms, SNMP notifications, or email alerts.

[0061] Furthermore, the drives are physically deployed in the hot-swap trays at the front of the chassis and are directly connected to the processor / controller through exclusive PCIe 5.0 channels. Each drive is installed in an independent hot-swap tray, fixed to the front panel of the chassis through a slide rail, and supports online replacement. Each drive is directly connected to the processor or the storage controller through an independent PCIe 5.0x4 channel without interference from intermediate switching chips. Each drive has an exclusive PCIe 5.0 channel (non-shared bus) to ensure full-bandwidth access and avoid performance degradation caused by multi-device contention. The drives are connected to the PCIe hot-swap connectors on the motherboard through SFF-8639 (U.2) interfaces, supporting hot plugging and automatic recognition.

[0062] Furthermore, the storage unit includes multiple high-speed interface hard drive slots, and at least one slot supports non-volatile storage devices such as NVMe or Serial Advanced Technology Attachment (SATA) interfaces.

[0063] Furthermore, the high-speed expansion slots, connected to the processor and the storage unit, include multiple slots supporting high-speed data transfer standards and at least one low-profile slot.

[0064] Furthermore, the storage device also includes a heat dissipation module, connected to the processor and the memory unit, including multiple heat dissipation fans.

[0065] Furthermore, the storage device also includes a power module, connected to each component, including at least two redundant power modules.

[0066] Further, the storage device further includes a network interface unit, connected to the processor and the power module, and includes a plurality of high-speed local area network (LAN) ports and at least one base management control (BMC) LAN port.

[0067] Further, the storage device further includes a remote management unit, connected to the network interface unit, for supporting BMC remote monitoring through the Intelligent Platform Management Interface (IPMI) protocol.

[0068] Further, the storage device further includes a redundant array of independent disks (RAID) module, connected to the storage unit, the power module, and the processor, for performing disk array configuration through the RAID configuration function.

[0069] Further, the hardware status data includes: the temperature of the processor, the fan speed, and the status of the power module; the storage device supports fault alarm through LED indicators, Simple Network Management Protocol (SNMP) traps, or email notifications.

[0070] Further, the remote diagnosis function of the storage device supports power control and hardware diagnosis through the out-of-band management function in the case of the host operating system crashing or not starting.

[0071] The BMC of the storage device supports ensuring the security of the remote management session through an encryption protocol, and the encryption protocol includes HTTPS or IPMI over LAN encryption mode, preventing security threats during the remote management process, and providing the location of hardware faults through the BIOS POST code.

[0072] Further, each storage node is equipped with 24 PCIe 5.0 NVMe drives, and each drive exclusively occupies one PCIe channel, supporting multi-task concurrent data access.

[0073] An independent disk redundant array (RAID) controller is built into the motherboard of the storage node, and the RAID controller executes a dynamic load balancing algorithm. The dynamic load balancing algorithm dynamically allocates storage bandwidth according to the priority of the computing tasks, and preferentially allocates more channel bandwidth resources to high-priority computing tasks.

[0074] Further, the RAID controller is specifically used to allocate storage bandwidth through the following steps:

[0075] Real-time monitor the PCIe channel utilization rate of each NVMe drive and the task priority label of the computing task;

[0076] According to the task priority label, route the data requests of high-priority tasks to the NVMe drive with a higher proportion of idle channels;

[0077] Dynamically allocate additional PCIe channel bandwidth resources for high-priority tasks, specifically including: within a RAID group, split the x4 channels of low-priority tasks into x2 mode to free up bandwidth for high-priority tasks; aggregate multiple x4 channels into an x8 / x16 link through a PCIe switch for exclusive use by high-priority tasks; the channel bandwidth resource refers to the bandwidth allocation permission of the PCIe 5.0 x4 channel corresponding to a single NVMe drive, and the allocation process does not interrupt the concurrent access of other computing tasks.

[0078] Furthermore, the motherboard of the storage device provides 4 PCIe 5.0 expansion slots, where the first slot and the second slot are 2 PCIe 5.0 x16 slots, and the third slot and the fourth slot are 2 PCIe 5.0 x8 slots. The expansion slots are located in the rear area of the motherboard and are used to install external inference acceleration cards;

[0079] The dynamic load balancing algorithm dynamically configures PCIe bandwidth resources through the following steps:

[0080] The baseboard management controller BMC monitors the task load of the GPU acceleration card or FPGA acceleration card connected to the expansion slot in real time. The task load is quantified by the following metrics: the number of I / O requests for inference tasks per unit time; the utilization rate of the computing units of the acceleration card; the PCIe channel bandwidth occupancy rate of the acceleration card;

[0081] When any one of the metrics in the task load exceeds the preset threshold, the BMC sends a PCIe resource configuration instruction to the BIOS;

[0082] The BIOS performs the following operations according to the source configuration instruction: switch the PCIe 5.0 x16 link of the first slot or the second slot from the default x16 single-channel mode to two independent x8 channels; dedicate one of the x8 channels to the high-priority inference acceleration card to ensure that its exclusive bandwidth is not less than 32GB / s; reserve the other x8 channel for other expansion cards other than the inference acceleration card; the bandwidth resource configuration process is implemented through the PCIe link splitting function of the BIOS;

[0083] When the task load drops below the preset threshold, the BMC notifies the BIOS to restore the default x16 single-channel mode.

[0084] Furthermore, the storage device adopts intelligent RAID and data sharding management. The intelligent RAID supports hardware-level RAID 0 / 1 / 5 / 10, and combines firmware algorithms to dynamically adjust the data sharding strategy to balance the I / O load, or automatically optimize the data distribution according to the type of computing tasks.

[0085] Further, the BMC is used to continuously collect utilization data of the processor, memory unit, storage unit, and network, and provide an API externally through the IPMI interface, enabling an external management system to perform the following operations through the API: query the real-time utilization data; trigger the dynamic load balancing algorithm to adjust the PCIe bandwidth resource configuration; receive real-time alerts of hardware exception events.

[0086] Further, the dynamic load balancing algorithm dynamically adjusts task allocation based on the data through a third-party scheduling system. For example, when a storage bandwidth bottleneck is detected, some tasks are migrated to low-load nodes.

[0087] Further, the storage device supports NVMe based on the network architecture and storage pooling. Through the M.2 expansion slot combined with hyper-converged architecture software, the storage device dynamically allocates storage resources through the virtualization layer and allocates cache space for GPU computing nodes.

[0088] Further, the storage device supports the NVMe (NVMe-oF) protocol based on the network architecture and storage pooling function, and realizes dynamic resource allocation of the virtualization layer through the following steps:

[0089] In the storage pool construction step, multiple NVMe drives are connected through the M.2 expansion slot to form a unified storage pool; the storage pool is divided into logical volumes (LUNs) by using hyper-converged infrastructure (HCI) software, and each logical volume is associated with a specific GPU computing node;

[0090] In the virtualization layer monitoring step, the I / O load, cache hit rate, and task priority data of GPU computing nodes are collected in real time; the storage resource requirements are analyzed through a virtualization manager (such as VMware vSAN or Ceph);

[0091] In the dynamic allocation mechanism step, exclusive NVMe-oF channels and cache space (≥64GB DRAM cache) are allocated for high-priority GPU tasks; hot data is migrated to low-latency NVMe drives as needed in the storage pool to optimize the data access path; when it is detected that the cache of a GPU node is insufficient, the virtualization layer dynamically expands the idle storage resources to this node;

[0092] In the resource recovery and rebalancing step, after the task is completed, the exclusive channels and cache space are released to the common resource pool; the QoS policy (such as IOPS upper limit, latency threshold) of the logical volume is automatically adjusted based on the load change.

[0093] Furthermore, the storage device is equipped with dual 2000W titanium power supplies and six high-speed fans to ensure the stability of resource allocation. When the BMC detects power or heat dissipation anomalies, it automatically triggers load migration to prioritize resource supply for core computing tasks.

[0094] Furthermore, the BMC is also used to perform the following operations:

[0095] The BMC monitors the input voltage (110 - 240V AC) and output load rate of the power supply module, collects temperature data of the processor, NVMe drives, and memory unit, and detects the rotation speed and fault status of the cooling fans;

[0096] When an abnormal state is detected, the BMC performs response operations, specifically including: when it detects the failure of any power supply module or the output load rate exceeds 95%, the BMC triggers the dynamic transfer of the load of the failed power supply to the normal power supply module, restricts the power consumption quota of non-critical tasks, and prioritizes the supply of the following resources: Turbo Boost power supply for the processor; PCIe channel bandwidth for high-priority computing tasks (AI training / inference); overclocking mode power supply for the memory unit; when it detects that the processor temperature ≥ 90 degrees, the NVMe drive temperature ≥ 75 degrees, or the fan rotation speed < 3000 RPM, the BMC triggers the following operations: turn off the hyper-threading or GPU acceleration function of non-critical tasks; migrate high-priority tasks to cooler NVMe drives or processor cores;

[0097] The BMC predefines task priority tags through the BIOS (for example, AI training is P0, data backup is P3). During resource contention, it allocates power and heat dissipation resources from high to low priority to ensure that high-priority tasks are not affected by frequency reduction or interruption.

[0098] Furthermore, the storage unit, processor, and memory achieve coordinated scheduling through an optimized BIOS.

[0099] Furthermore, each 2.5-inch PCIe 5.0 NVMe hard disk drive slot of the storage unit supports a maximum storage capacity of 32TB; the processor supports multi-node configuration and is suitable for distributed computing tasks; the memory unit uses error correction code ECC technology to correct data errors; the redundant array of independent disks RAID module supports RAID 0, RAID1, RAID5, RAID10 configuration modes; the network interface unit supports data parallel transmission and load balancing; LED indicators are set at the front of the chassis to display the hard disk drive status and I / O activities.

[0100] The above technical solutions are described in detail below:

[0101] The storage device in this embodiment supports 24 2.5-inch PCIe 5.0 NVMe hard drive slots, and each hard drive slot supports a storage capacity of up to 32TB. These hard drive slots use the PCIe 5.0 interface, which can provide high bandwidth and fast storage access, and are particularly suitable for large-scale data set storage and high-performance computing tasks. Through this design, the system can process massive amounts of data and support fast data reading and writing, meeting the storage device requirements of high-performance computing and AI training tasks. In addition, the system also supports M.2 PCIe 3.0 x4 NVMe / SATA slots, further adapting to different types of storage requirements and ensuring flexible storage configuration and strong scalability of the device.

[0102] The system is equipped with multiple PCIe 5.0 expansion slots, including 2 x16 slots and 2 x8 low-profile slots, supporting expansion cards and efficient data transmission. These expansion slots are very important for high-speed computing and data access in AI inference and training tasks, and can provide a stable and fast data transmission channel. In compute-intensive applications, the expansion card can achieve additional accelerated computing capabilities, further improving the performance of the device, supporting different types of AI hardware acceleration cards, such as GPUs and FPGAs, thus meeting the growing AI computing needs.

[0103] The storage device of this embodiment supports the fourth and fifth generations of Intel Xeon scalable processors, and is equipped with up to 2TB of ECC DDR5 memory, with a memory speed of up to 4800MT / s and 5600MT / s. These configurations can provide powerful computing support for AI training and inference workloads. The memory uses ECC technology to ensure that data in the memory can be corrected in a timely manner when errors occur, improving the accuracy of computing and avoiding data corruption. The high-performance processor and memory configurations enable the system to operate efficiently when processing large-scale parallel computing tasks, meeting the requirements of AI applications for high-bandwidth and highly reliable memory.

[0104] To ensure the stable operation of the system under high load, the storage device of this embodiment is equipped with six efficient 6-cm fans. AI training and inference tasks require a large amount of computing resources, and the heat generated inside the system is relatively high. Therefore, a powerful cooling system is very crucial. Through the fan design, the system can effectively discharge heat, keep the temperature of components within a reasonable range, avoid performance degradation or hardware failure caused by overheating, and ensure the long-term stability and reliability of the system.

[0105] The device is equipped with two 2000-watt redundant power modules, ensuring that the system can supply power stably under high load conditions. High-performance computing and AI training systems consume a large amount of power. The redundant power design can ensure that even if one power module fails, the other module can still continue to supply power, thus avoiding system downtime caused by power problems and enhancing the stability and reliability of the system.

[0106] In this embodiment, the storage device adopts an efficient power management system and is equipped with 2000-watt redundant power modules. Under high-performance computing requirements, the system can maintain a stable power supply while effectively controlling energy consumption. Through the redundant power design, when one power supply fails, the other power module can automatically take over the power supply, avoiding system downtime caused by power failure. In addition, the design of redundant fans further ensures the heat dissipation capacity of the device under high load conditions, extends the service life of the device and improves system stability.

[0107] This system adopts a modular design and supports multiple modular components, including storage drives, expansion cards, memory, etc., and can be flexibly configured and expanded according to the needs of AI training and inference tasks. The nodes have the hot-swap function, allowing replacement or installation without interrupting the system operation. Whether it is for hardware maintenance, upgrade, or expanding storage and computing capabilities, users can operate without affecting the system stability, improving the system maintainability and flexibility, and ensuring that the system is always in the best working state during long-term and high-load tasks.

[0108] The storage device is equipped with multiple high-speed network interfaces, including two RJ45 10GbE LAN ports and a dedicated BMC LAN port. Through these high-speed network interfaces, the system can achieve fast data transmission in AI training and inference tasks, meeting the needs of large amounts of data concurrent access. The efficient data transmission ability is crucial for improving the data reading speed, reducing latency, and accelerating the calculation process.

[0109] The system is equipped with BMC support and is remotely managed and monitored through IPMI. Administrators can view the health status of the system in real time through IPMI tools and the Web interface, including key parameters such as temperature, fan speed, and power status. This function is particularly important in the data center environment, capable of effectively preventing hardware failures and diagnosing faults, ensuring the stable progress of AI training and inference tasks.

[0110] This system supports hot-pluggable NVMe hard disk drives, allowing for hard disk replacement or upgrade without interrupting services to adapt to the dynamic storage capacity and speed requirements of AI tasks. Intelligent RAID and data sharding management support hardware-level RAID 0 / 1 / 5 / 10, dynamically adjusting the data sharding strategy through firmware algorithms to optimize I / O performance. This design can balance the storage load according to the needs of computing tasks during AI training and inference, improving the utilization efficiency of storage resources.

[0111] This system is equipped with multiple PCIe 5.0 slots, M.2 slots, and a design that supports multiple expansion cards and storage drives, featuring high scalability and flexible configuration capabilities. It can expand resources according to the needs of AI tasks to meet the growing demands for storage capacity, computing power, and high-speed data access. The supported expansion cards include computing acceleration cards such as GPUs and FPGAs, which can significantly enhance the system's computing power and data processing efficiency.

[0112] This system is designed with a complete troubleshooting mechanism, providing detailed troubleshooting guides to help users solve common problems such as power issues and memory errors. Through the remote diagnosis function and IPMI interface, the system can monitor the hardware health status in real-time and generate corresponding fault logs, ensuring stability in intelligent computing training and inference tasks and providing quick maintenance support to reduce downtime.

[0113] Example Two

[0114] The storage device has a built-in remote diagnosis function, supporting real-time feedback of fault codes.

[0115] 1. IPMI Remote Management Function

[0116] This storage device supports remote management based on the IPMI 2.0 standard, implemented through an independent BMC (Baseboard Management Controller). Administrators can remotely access the system health status through the IPMI LAN port (RJ45 1 GbE), including real-time monitoring of hardware parameters (such as temperature, voltage, fan speed) and fault logs.

[0117] Regarding the feedback of fault codes, the BMC records the hardware event log (SEL) and generates specific fault codes when detecting anomalies (such as overheating, power failure), supporting real-time viewing through IPMI tools or the web interface.

[0118] Specifically, the system supports the IPMI 2.0 standard through a dedicated Baseboard Management Controller (BMC), providing remote management capabilities. Administrators can access the BMC interface through a dedicated IPMI LAN port (RJ45 1 GbE) without relying on the host operating system. This design makes the remote management function independent of the state of the host operating system, thus improving the management efficiency and flexibility of the system.

[0119] Specifically, IPMI 2.0 provides the function of remotely monitoring hardware status, enabling real-time acquisition of hardware health data such as CPU temperature, voltage, fan speed, and power status to ensure the stability of system operation. In addition, administrators can also access the System Event Log (SEL) to record important events such as hardware failures and temperature alarms, facilitating problem tracking and troubleshooting. The alarm notification function supports triggering critical error notifications such as overheating and power failures through SNMP traps, emails, or LED indicators, promptly alerting administrators to take action.

[0120] Specifically, the Out-of-Band management function enables administrators to remotely control the server power (such as power on, power off, restart) through IPMI even when the host operating system is down or not started. In addition, IPMI 2.0 also supports remotely accessing the server console through KVM over IP technology for BIOS configuration or fault diagnosis, greatly improving the system's maintainability and fault recovery capabilities.

[0121] Specifically, IPMI 2.0 provides strong security features, supporting hierarchical user permission management, including administrators, operators, and ordinary users, ensuring that only authorized users can perform management operations. To ensure the security of remote management sessions, IPMI 2.0 can encrypt session data through encryption protocols (such as HTTPS / IPMI over LAN), effectively preventing potential security threats during remote management.

[0122] 2. BMC Interface

[0123] The BMC provides out-of-band management capabilities, allowing access to diagnostic information through the network even when the host operating system is down. It supports real-time alarms (such as LED indicator changes, SNMP traps, email notifications) to ensure that fault codes can be immediately reported to the management platform.

[0124] Specifically, the BMC (Baseboard Management Controller) provides remote management functions independent of the host operating system, enabling administrators to access the BMC through a dedicated IPMI LAN port (RJ45 1GbE) even when the system is powered off or the operating system crashes, and perform operations such as power control (power on, power off, restart) and hardware diagnostics. This out-of-band management ensures that administrators can still effectively control and manage the system even when the operating system fails to start, improving the reliability and maintainability of the server.

[0125] Specifically, the BMC continuously monitors the key hardware parameters of the system, including the temperature of the CPU, memory, and system environment, the input / output voltage of the power module, the rotation speed and fault alarm of the fan, and the health status of the redundant power supply. By monitoring these hardware data in real time, the BMC can promptly detect potential hardware problems, and abnormal data will trigger an alarm and be recorded in the System Event Log (SEL) for subsequent fault troubleshooting and system maintenance.

[0126] Specifically, all hardware events, such as overheating, fan failure, or power abnormality, will be recorded by the BMC in the System Event Log (SEL). Administrators can view these logs through IPMI tools (such as ipmitool) or the BMC Web interface, and support filtering by time, event type, etc., thus helping administrators quickly locate the cause of the fault, trace historical events, and ensure the continuous stable operation of the system.

[0127] Specifically, the BMC supports multiple alarm notification methods, including LED indicators, SNMP traps, email notifications, and log triggers. By displaying red or blue through the "Information LED" on the control panel to indicate serious errors or UID activation, etc., administrators can quickly identify problems. In addition, the BMC can also send alarm information to the network management platform through SNMP traps, or receive alarm details through pre-configured emails to ensure timely response to hardware failures.

[0128] Specifically, the BMC provides KVM over IP function, allowing administrators to remotely access the server console through the network, view the BIOS interface or operating system in real time, support keyboard, video, and mouse operations, and achieve comprehensive remote management. In addition, the BMC also supports virtual media mounting, allowing remote loading of ISO images or virtual drives, facilitating system installation or repair without the need for physical contact with the server.

[0129] Specifically, the BMC has strict security and permission management functions, supports multi-role user grading (such as administrators, operators, ordinary users), can restrict sensitive operations, such as firmware updates, to ensure system security. In addition, the BMC also ensures the security of data transmission through encryption protocols (such as HTTPS, IPMI over LAN encryption mode) to prevent the leakage of sensitive data during transmission. Through the IP filtering function, administrators can configure the IP address range allowed to access the BMC to further prevent unauthorized access.

[0130] Specifically, the BMC supports remote firmware updates through a Web interface or command-line tools (such as the Redfish API) to ensure that the system always runs on the latest firmware version, improving system performance and security. The BMC also provides a hardware reset function, supporting remote forced restart or restoring the BIOS default settings, simplifying the troubleshooting and system recovery processes. In addition, combined with the BIOS POST code, the BMC can provide accurate location of hardware faults, helping administrators diagnose and handle hardware problems more quickly.

[0131] 3. BIOS POST Code

[0132] It can achieve hardware self-check feedback. That is, during system startup, the BIOS indicates detected hardware problems through POST codes. These codes can be displayed through LEDs on the motherboard or by connecting a diagnostic card to assist in quickly locating the source of the fault and are part of local / remote diagnosis.

[0133] Specifically, the BIOS POST (Power-On Self-Test) code is the core feedback mechanism for hardware self-check during the system startup process. During the power-on phase, the BIOS indicates the initialization status of the hardware through specific hexadecimal or decimal codes. Each code represents a different detection step, such as CPU initialization, memory detection, and peripheral identification. If a certain detection step fails, the code will stop at the error location, helping administrators quickly locate the source of the fault. This function is a crucial feedback mechanism during the system self-check process and can provide real-time information on the hardware health status.

[0134] Specifically, the POST code is presented in two formats: 2-digit hexadecimal numbers (e.g., 0x55 indicates a memory detection error) or 4-digit decimal numbers (e.g., 0800 indicates the completion of PCI device initialization). There are two options for the display method of the code, depending on the device configuration. Some motherboards integrate LEDs that can directly display the POST code, but the motherboard manual needs to be referred to for decoding. For devices without integrated LEDs, an external PCIe or USB diagnostic card can be used to capture and display the POST code in real time, helping administrators monitor the system status and diagnose problems.

[0135] Specifically, POST codes are divided into critical errors and non-critical errors. Critical errors refer to problems that must be resolved during the system startup process, and the code will remain at a non-zero value continuously. For example, 0x55 indicates a memory fault, and 0xCC indicates that the CPU is not recognized. The system will stop starting and trigger an alarm (such as a beeping sound or a continuously lit red LED). Non-critical errors are problems that occur during system startup. The code may appear briefly and then the system continues to execute. For example, 0xA0 indicates a delay in detecting SATA devices. The system starts normally but will record relevant logs. For non-critical errors, the system usually does not stop starting, but administrators should check the logs in a timely manner and conduct troubleshooting.

[0136] Specifically, POST codes are tightly integrated with the BMC (Baseboard Management Controller) to provide remote diagnostic support. The POST codes will be recorded by the BMC into the System Event Log (SEL) and support remote viewing through IPMI tools (such as ipmitool sel list). Administrators can observe the changes in POST codes during the startup phase through the KVM over IP function in the out-of-band management mode without physically touching the device.

[0137] Specifically, when encountering a startup failure, administrators should record the last displayed POST code and analyze the specific error in combination with the motherboard manual or the code table provided by the manufacturer. The basic methods for troubleshooting include: if the code indicates a memory error (such as 0x55), try to re-plug the memory or change the slot; if the code indicates a CPU failure (such as 0xCC), check the CPU installation or the radiator pressure, etc.

[0138] Embodiment Three

[0139] The storage device supports a dynamic load balancing algorithm and allocates resources according to computing tasks.

[0140] Specifically, the system is equipped with 24 PCIe 5.0 NVMe drives, which are connected to the CPU through a Multipath I / O (MPIO) architecture. Each NVMe drive exclusively occupies a PCIe channel and supports concurrent data access. This design allows the algorithm to dynamically allocate storage bandwidth according to task priorities. For example, allocate more channel resources to high-priority AI training tasks to achieve load balancing.

[0141] Specifically, the motherboard provides 4 PCIe 5.0 expansion slots (2 x16 and 2 x8), supporting acceleration cards such as GPUs / FPGAs. Through the PCIe resource partitioning function of the BMC and BIOS, the bandwidth allocation of different slots can be dynamically adjusted. For example, when the inference tasks surge, give priority to allocating the bandwidth of the x16 slot to the inference acceleration card, and the training tasks use the remaining resources.

[0142] Specifically, intelligent RAID and data sharding management are adopted, which support hardware-level RAID 0 / 1 / 5 / 10 through the Intel RAID Key (JR). Combining with firmware algorithms, the RAID group can dynamically adjust the data sharding strategy. For example, hot data can be distributed across multiple NVMe drives to balance the I / O load; or the data distribution can be automatically optimized according to the type of computing task (random read / sequential write).

[0143] Specifically, the BMC continuously collects CPU / memory / storage / network utilization data and provides APIs externally through the IPMI interface. The third-party scheduling system can achieve dynamic load balancing based on this data. For example, when detecting a storage bandwidth bottleneck, some tasks can be migrated to low-load nodes.

[0144] Specifically, the hardware supports the NVMe (NVMe-oF) protocol based on the network architecture and storage pooling (through M.2 expansion slots). Combining with the hyper-converged infrastructure (HCI) software, storage resources can be dynamically allocated through the virtualization layer. For example, cache space can be allocated on demand for GPU computing nodes.

[0145] Specifically, the dual 2000W titanium power supplies and 6 high-speed fans ensure the stability of resource allocation. When detecting power or heat dissipation anomalies, the BMC can automatically trigger load migration (such as reducing the resource quota of non-critical tasks) to prioritize the resource supply for core computing tasks.

[0146] Embodiment 4

[0147] In the dedicated high-performance storage device designed for intelligent computing training and inference, the storage unit, processor, and memory achieve coordinated scheduling through an optimized BIOS.

[0148] Specifically, the BIOS of the motherboard (X13SEB-TF) supports PCIe resource partitioning and priority adjustment. The PCIe 5.0 channel bandwidth can be manually or automatically allocated through the UEFI interface. For example, fixed channels are reserved for 24 NVMe drives, and the remaining bandwidth is dynamically adjusted to the GPU / FPGA acceleration cards directly connected to the CPU to ensure resource balance between storage and computing tasks.

[0149] Specifically, the BIOS provides NUMA (Non-Uniform Memory Access) configuration options, allowing the association between memory and CPU cores to be bound according to the processor topology. For example, in AI training tasks, high-frequency memory is allocated to specific CPU cores to reduce data access latency, and at the same time, the storage bandwidth utilization is improved through the memory interleaving mode.

[0150] Specifically, the queue depth and prefetch policy of the configurable NVMe controller in the BIOS can be adjusted. For example, for inference tasks with intensive random reads, a high queue depth (e.g., 1024) and aggressive prefetching are enabled; for training tasks with sequential writes, the write cache flush frequency is optimized to reduce latency.

[0151] Specifically, dynamic power consumption regulation is achieved through the CPU C-state / P-state settings in the BIOS and the energy-saving mode of the storage device (e.g., NVMe APST). For example, the CPU frequency is reduced and the active links of some NVMe drives are turned off under low load, and the Turbo mode is enabled and full bandwidth is allocated under high load to balance performance and energy efficiency.

[0152] Specifically, the BIOS cooperates with the BMC to collect data such as CPU temperature, memory error rate, and NVMe latency in real time. Based on the threshold trigger strategy, adjustments are made. For example, when the CPU overheats, the storage bandwidth priority is restricted, or when the memory ECC error rate increases, data is migrated to a healthy channel.

[0153] Specifically, the BIOS enables the Volume Management Device (VMD) technology, allowing the CPU to directly manage the NVMe drive and bypassing the bottleneck of the traditional storage controller. At the same time, it supports DDIO, directly writing storage data into the CPU cache, reducing the memory transfer latency and improving the cooperation efficiency.

[0154] This technical solution provides a dedicated high-performance storage device designed for intelligent computing training and inference. By configuring multiple high-speed interface hard drive slots and independent data bus channels in each storage node, it ensures that each drive can be directly connected to the processor, achieving non-blocking concurrent data access, thereby improving the data processing efficiency. The processor supports scalability and can be flexibly configured according to different requirements. At the same time, it is equipped with ECC memory, enhancing the reliability and data integrity of the system. The high-speed expansion slot provides an installation interface for external inference acceleration cards, further optimizing the computing performance of intelligent inference tasks. In short, this storage device has the advantages of high concurrency, high performance, scalability, and high reliability, and can meet the data storage and fast processing requirements in large-scale intelligent computing tasks.

[0155] Those skilled in the art can clearly understand that, for the convenience and conciseness of description, only the above division of each functional unit and module is taken as an example. In actual applications, the above functions can be assigned to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiments can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0156] As mentioned above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A dedicated high-performance storage device designed for intelligent computing training and inference, characterized in that, Including: A chassis, and at least two storage nodes disposed within the chassis; Each of the storage nodes includes the following components disposed on a motherboard: A storage unit, including a plurality of high-speed interface hard disk drive slots located at the front of the chassis, configured to accommodate a plurality of drives, each drive exclusive of one high-speed data bus channel and directly connected to a processor, supporting non-blocking concurrent data access; A processor, connected to the storage unit and the memory unit, supporting at least one scalable processor; A memory unit, connected to the processor, supporting error correction code ECC memory; A high-speed expansion slot, connected to the processor and the storage unit, for installing an external inference acceleration card.

2. The dedicated high-performance storage device designed for intelligent computing training and inference according to claim 1, wherein Each of the storage nodes has a built-in remote diagnosis function, supporting real-time feedback of fault codes; The remote diagnosis function is implemented through a baseboard management controller BMC, which is an integrated component of the motherboard of the storage node, operates independently of the operating system, and is remotely accessible through an IPMI local area network port; The BMC is used to collect hardware status data of the processor, the memory unit, the storage unit and the power module in real time, obtain hardware exception events according to the hardware status data, convert the hardware exception events into standardized fault codes, and record them in the hardware event log SEL; The storage device supports viewing the fault codes in the hardware event log SEL in real time through an IPMI tool or a network interface.

3. The storage device according to claim 2, wherein The hardware status data includes: the temperature of the processor, the fan speed, and the status of the power module; the storage device supports fault alerts through indicator lights, simple network management protocol SNMP traps, or email notifications.

4. The storage device according to claim 3, wherein, The remote diagnosis function supports power module control and hardware status diagnosis through an out-of-band management function in the case of an operating system outage or failure to start; The BMC supports ensuring the security of remote management sessions through an encryption protocol, which includes HTTPS or the IPMI protocol encryption mode of the baseboard management controller BMC through a local area network, and provides hardware fault location through BIOS POST codes.

5. The storage device according to claim 1, wherein Each of the storage nodes is equipped with 24 PCIe5.0 NVMe drives, each drive exclusive of one PCIe channel, supporting multi-task concurrent data access; An independent disk redundant array RAID controller is built into the motherboard of the storage node, and the RAID controller executes a dynamic load balancing algorithm, which dynamically allocates storage bandwidth resources according to the calculation task priority.

6. The storage device according to claim 5, wherein The motherboard of the storage device provides 4 PCIe5.0 expansion slots, where the first slot and the second slot are 2 PCIe 5.0x16 slots, and the third slot and the fourth slot are 2 PCIe5.0x8 slots. The expansion slots are located in the rear area of the motherboard for installing external inference acceleration cards.

7. The storage device according to claim 6, wherein The dynamic load balancing algorithm dynamically configures PCIe bandwidth resources through the following steps: The Baseboard Management Controller (BMC) monitors the task load of the GPU acceleration card or FPGA acceleration card connected to the expansion slot in real time, and the task load is quantified by the following metrics: the number of I / O requests for inference tasks per unit time; the utilization rate of the computing units of the acceleration card; the occupancy rate of the PCIe channel bandwidth of the acceleration card; When any one of the metrics in the task load exceeds a preset threshold, the BMC sends a PCIe resource configuration instruction to the BIOS; The BIOS performs the following operations according to the source configuration instruction: switches the PCIe 5.0x16 link of the first slot or the second slot from the default x16 single-channel mode to two independent x8 channels; dedicates one of the x8 channels to the high-priority inference acceleration card; reserves the other x8 channel for other expansion cards other than the inference acceleration card; the bandwidth resource configuration process is implemented through the PCIe link splitting function of the BIOS; When the task load drops below the preset threshold, the BMC notifies the BIOS to restore the default x16 single-channel mode.

8. The storage device according to claim 7, characterized in that, The BMC is used to continuously collect the utilization data of the processor, memory unit, storage unit, and network, and provide an API externally through the IPMI interface, enabling an external management system to perform the following operations through the API: query the real-time utilization data; trigger the dynamic load balancing algorithm to adjust the PCIe bandwidth resource configuration; Receive real-time alarms of hardware exception events.

9. The storage device according to claim 1, characterized in that, The storage device is equipped with dual 2000W titanium power supplies and multiple fans; The BMC is also used to automatically trigger load migration when a power module exception or a heat dissipation exception is detected.

10. The dedicated high-performance storage device designed for intelligent computing training and inference according to claim 1, wherein The storage unit, processor, and memory unit achieve coordinated scheduling through an optimized BIOS.

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