Instruction processing method, apparatus and device, and computer readable storage medium

Abstract

The invention discloses an instruction processing method, device and equipment and a computer readable storage medium, and belongs to the technical field of computers. The method comprises the steps of obtaining a to-be-processed first instruction; according to a memory structure and a required rate for reading the first instruction, determining a compression level of a memory in the memory structure, the memory structure being used for storing the compressed first instruction; and compressing the first instruction by adopting the compression hierarchy. By compressing the first instructions, the size of the storage space occupied by the first instructions is reduced, the number of the compressed first instructions which can be stored by the memory structure with the same capacity is larger than that of the first instructions before compression, the instruction storage number of the memory structure is increased, and the storage overhead of the memory structure is reduced. Since the compression of the first instruction is performed based on the compression level of the memory, the process of restoring the compressed first instruction meets the required rate, and the process of restoring the compressed first instruction does not affect the normal operation of the memory.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to an instruction processing method, apparatus, device, and computer-readable storage medium. Background Art

[0002] In the field of computer technologies, a processor includes an instruction memory module (IMEM), a decoder module (DEC), and arithmetic and logic units (ALUs). Among them, the instruction memory module is used to store instructions obtained by compiling an application program, the decoder module is used to parse multiple instructions in parallel, and the arithmetic and logic units are used to perform parallel calculations based on the information obtained by parsing the multiple instructions to obtain multiple result data, so as to implement the operation of the application program based on the multiple result data. As the complexity of the application program increases, the number of instructions obtained by compiling the application program is larger, and the instruction memory module stores more instructions. Summary of the Invention

[0003] This application provides an instruction processing method, apparatus, device, and computer-readable storage medium to store more instructions. The technical solutions are as follows:

[0004] In a first aspect, an instruction processing method is provided. The method includes: obtaining a first instruction to be processed; determining a compression level of a memory in a memory structure according to the memory structure and the demand rate for reading the first instruction, where the memory structure is used to store the compressed first instruction; and compressing the first instruction using the compression level.

[0005] By compressing the first instruction, the size of the storage space occupied by the first instruction is reduced. The number of compressed first instructions that can be stored in a memory structure with the same capacity is larger than the number of uncompressed first instructions, improving the instruction storage quantity of the memory structure and reducing the storage overhead of the memory structure. Since the compression of the first instruction is based on the compression level of the memory, and the compression level is determined based on the demand rate, the process of restoring the compressed first instruction meets the demand rate of the memory structure, and the process of restoring the compressed first instruction does not affect the normal operation of the memory in the memory structure.

[0006] In a possible implementation, before determining the compression level of the memories in the memory structure according to the memory structure and the required rate for reading the first instruction, it further includes: obtaining at least one of the path attributes of the read paths of the respective memories included in the memory structure or the read efficiency of the memory structure, where the read path of a memory is the path connecting the memory and the read module, and the read module is used to read the instructions stored in the memory and process the read instructions; determining the required rate for reading the first instruction according to at least one of the path attributes or the read efficiency. By determining the required rate for reading the first instruction according to at least one of the path attributes or the read efficiency, the determined required rate is more in line with the actual operating conditions of the memory structure, and the accuracy of the determined required rate is high.

[0007] In a possible implementation, determining the compression level of the memories in the memory structure according to the memory structure and the required rate for reading the first instruction includes: determining the read rate of each memory included in the memory structure; determining the decompression rate of each memory according to the required rate for reading the first instruction and the read rate of each memory, where the decompression rate of a memory is the rate of decompressing the instructions stored in the memory on the read path of the memory; determining the compression level of each memory according to the decompression rate of each memory, and the compression rate corresponding to the compression level of the memory matches the decompression rate corresponding to the memory.

[0008] Completely reading the first instruction from the memory structure includes reading the first instruction and decompressing the first instruction. Therefore, according to the required rate for reading the first instruction from the memory structure and the read rate of each memory, the decompression rate that can be used to decompress the instructions while ensuring the normal operation of the memory can be determined, so as to select a compression level that matches the decompression rate. By combining the overall memory structure with the local memories, the determined compression level has high accuracy, and the compression level matches the decompression rate of each memory. The compression performed based on the compression level does not affect the normal operation of each memory.

[0009] In a possible implementation, the memory structure includes a storage module and a cache module. The compression level of the storage module is two - layer compression, and the compression level of the cache module is one - layer compression. The restoration rate of one - layer compression is higher than that of two - layer compression. Compressing the first instruction using the compression level includes: compressing the first instruction using the compression method of one - layer compression to obtain a second instruction; compressing the second instruction using the compression method of two - layer compression to obtain a third instruction. The compression rate of the compression method of two - layer compression is greater than that of the compression method of one - layer compression. When the memory structure includes multiple memories, such as a storage module and a cache module, the first instruction can be compressed in multiple segments, and the bit width of the obtained third instruction is smaller than that of the first instruction, and the storage overhead is also smaller. For different memories, such as a storage module and a cache module, different compression methods can be used, and the flexibility of the compression process is high.

[0010] In a possible implementation, the ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. Before compressing the first instruction using the compression method of one - layer compression to obtain the second instruction, it further includes: obtaining the service characteristics of the first instruction, where the service characteristics indicate the running quality requirements of the service running based on the first instruction; determining the compression ratio according to the service characteristics of the first instruction. Determining the compression ratio according to the service characteristics of the first instruction ensures the running quality of the service running based on the first instruction.

[0011] In a possible implementation, compressing the first instruction using the compression method of one - layer compression to obtain a second instruction includes: obtaining the instruction characteristics of the first instruction; in the case where it is determined according to the instruction characteristics that fixed - length compression is supported, compressing the first instruction using the fixed - length compression method to obtain a second instruction, or, in the case where it is determined according to the instruction characteristics that fixed - length compression is not supported, splitting the first instruction into multiple second instructions, and the bit widths of the respective second instructions in the multiple second instructions are the same. Determining whether the first instruction supports fixed - length compression according to the instruction characteristics, performing fixed - length compression on the first instruction that supports fixed - length compression, and splitting the first instruction that does not support fixed - length compression, so as to flexibly process the first instruction according to the instruction characteristics. Whether the first instruction supports fixed - length compression or not, the first instruction can be processed to obtain a second instruction with a unified bit width, and the generality is wide.

[0012] In a possible implementation, the instruction characteristics include at least one of the instruction type, usage frequency, or field utilization rate of the first instruction. The instruction characteristics in this method are diverse and highly flexible.

[0013] In a possible implementation, the first instruction is compressed using a fixed-length compression method to obtain a second instruction, including: determining the valid fields of the first instruction to obtain a second instruction including the valid fields, where the valid fields are the fields used to execute the first instruction. Based on the valid fields, the second instruction is determined, ensuring that the fields carried by the second instruction are the necessary fields for instruction execution, improving the field utilization rate of the second instruction and the reliable execution of the second instruction.

[0014] In a possible implementation, the second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by fixed-length compression or splitting. By means of the compression flag bit, the way to obtain the second instruction is clearly defined, the determination process is simple and efficient, and it is convenient for subsequent instruction restoration and improves the restoration efficiency.

[0015] In a possible implementation, the second instruction is compressed using a two-layer compression method to obtain a third instruction, including: obtaining the occurrence frequency of each field included in the second instruction; obtaining the third instruction according to the occurrence frequency of each field, where the third instruction includes the encoding of each field, and the encoding of each field is determined based on the occurrence frequency of each field, and the length of the encoding of each field is inversely proportional to the occurrence frequency of each field. Since the length of the encoding of each field is inversely proportional to the occurrence frequency of each field, the more times a field appears, the shorter the corresponding encoding length, effectively reducing the length of the third instruction.

[0016] In a possible implementation, before obtaining the third instruction according to the occurrence frequency of each field, it further includes: constructing an encoding dictionary corresponding to the second instruction according to the occurrence frequency of each field, where the encoding dictionary includes each field and the occurrence frequency of each field; determining the encoding of each field according to the encoding dictionary. By counting the occurrence frequency of each field through the encoding dictionary, subsequent compression of the second instruction can be achieved by looking up the encoding dictionary, and the compression process is simple and efficient.

[0017] In a possible implementation, the third instruction includes an encoding index, and the encoding index is used to find the field corresponding to the encoding included in the third instruction during the decompression of the third instruction. Since the encoding index is carried in the third instruction, during the subsequent decompression of the third instruction, parsing the encoding index can determine the field corresponding to the encoding included in the third instruction to achieve the decompression of the third instruction, and the decompression process is simple and the decompression efficiency is high.

[0018] In a possible implementation, after compressing the first instruction using a compression level, the following steps are further included: obtaining the instruction length of the compressed first instruction; determining, according to the instruction length, a storage unit in the memory structure for storing the compressed first instruction, and storing the compressed first instruction in the determined storage unit. According to the instruction length of the compressed first instruction, the storage unit for storage is first determined, and then the compressed first instruction is stored in the storage unit, realizing the precise storage of the compressed first instruction.

[0019] In a possible implementation, the first instruction includes an instruction for forwarding an application program. By compressing the first instruction, the reading efficiency of the first instruction is improved, and the forwarding efficiency based on the first instruction is higher.

[0020] In a possible implementation, obtaining the first instruction to be processed includes: obtaining at least one instruction included in an instruction bundle, any one of the at least one instruction being the first instruction to be processed, and the at least one instruction being instructions for parallel execution. The first instruction to be processed can be an instruction included in the instruction bundle, and the number of instructions to be processed is not limited. It can be one first instruction or multiple first instructions, with a wide degree of generality. For at least one instruction to be executed in parallel, the instruction processing method can also be used for compression, reducing the storage space occupied by the instruction bundle while ensuring the parallel processing efficiency. And the instruction bundle including at least one instruction is, for example, a very long instruction word, and this method can also be applied to the application scenario of very long instruction words.

[0021] In a second aspect, another instruction processing method is provided, which includes: obtaining the compressed first instruction, where the compression of the first instruction is implemented based on a compression level, the compression level is determined based on the memory structure and the required rate for reading the first instruction, and the memory structure is used to store the compressed first instruction; restoring the compressed first instruction.

[0022] The storage space occupied by the compressed first instruction is smaller than the storage space occupied by the first instruction. A memory structure with the same memory size can store more compressed first instructions, improving the instruction storage quantity of the memory structure. For the compressed first instruction, it can be restored to ensure the normal implementation of subsequent operations related to the first instruction.

[0023] In a possible implementation, the memory structure includes a storage module and a cache module. The compression level of the storage module is two - layer compression, and the compression level of the cache module is one - layer compression. The restoration rate of one - layer compression is higher than that of two - layer compression. The compressed first instruction includes a third instruction. Restoring the compressed first instruction includes: restoring the third instruction using the restoration method corresponding to the two - layer compression method to obtain a second instruction; restoring the second instruction using the restoration method corresponding to the one - layer compression method to obtain the first instruction. The compression rate of the two - layer compression method is greater than that of the one - layer compression method. Even if the memory structure includes multiple memories, for example, a storage module and a cache module, multi - stage restoration can be performed on the third instruction, and each stage of restoration is the restoration method corresponding to the compression level of the memory, that is, each stage of restoration does not affect the normal operation of the memory.

[0024] In a possible implementation, the third instruction includes a coding index. Restoring the third instruction using the restoration method corresponding to the two - layer compression method to obtain a second instruction includes: parsing the coding index included in the third instruction; determining each field corresponding to each coding included in the third instruction according to the coding index, and determining the second instruction according to each field corresponding to each coding. The length of the coding of each field is inversely proportional to the occurrence frequency of each field. The correspondence between the coding and the field can be determined through the coding index, realizing the restoration of the third instruction. The restoration process is simple and efficient.

[0025] In a possible implementation, the restoration method corresponding to the one - layer compression method includes decompression corresponding to fixed - length compression or splicing corresponding to splitting. Restoring the second instruction using the restoration method corresponding to the one - layer compression method to obtain the first instruction includes: in the case where the second instruction is obtained by fixed - length compression, decompressing the second instruction using the decompression corresponding to fixed - length compression to obtain the first instruction; or, in the case where the second instruction is obtained by splitting, splicing multiple second instructions obtained by splitting the first instruction to obtain the first instruction. The bit widths of each of the multiple second instructions are the same. Whether using fixed - length compression or splitting, there is a corresponding restoration method. The types of second instructions that can be restored are diverse and the generality is high.

[0026] In a possible implementation, the second instruction includes a compression flag bit, which indicates that the second instruction is obtained by fixed-length compression or splitting. Before restoring the second instruction by using the restoration method corresponding to the compression method of one-layer compression for the second instruction to obtain the first instruction, it further includes: parsing the compression flag bit included in the second instruction, and determining the method for obtaining the second instruction from fixed-length compression and splitting according to the compression flag bit. By parsing the compression flag bit, the compression method adopted by the second instruction can be determined. The determination process is simple, the determination efficiency is high, and it is convenient for subsequent restoration of the instruction, thereby improving the restoration efficiency.

[0027] In a possible implementation, obtaining the compressed first instruction includes: extracting at least one instruction stored in a row of storage units of the memory structure; separating each instruction according to the instruction length of each instruction in the at least one instruction to obtain at least one instruction, and the at least one instruction includes the compressed first instruction. Instructions stored in a row of storage units can be extracted at one time, and the number of extracted instructions is large, and the instruction extraction efficiency is high.

[0028] In a possible implementation, after restoring the compressed first instruction, it further includes: determining an instruction bundle corresponding to the first instruction, where the instruction bundle includes at least one instruction, the compression results of the at least one instruction are stored in the same row of storage units of the memory structure, the compression result of any instruction in the compression results of the at least one instruction is the compressed first instruction, and the at least one instruction is an instruction for parallel execution; sending the at least one instruction included in the instruction bundle to a decoding module, and the decoding module is used to parse the at least one instruction. After the first instruction is restored, at least one instruction is also sent to the decoding module in units of the instruction bundle, so that the decoding module can perform parallel parsing on the at least one instruction included in the instruction bundle. By controlling the parallel parsing of the at least one instruction, it is ensured that the at least one instruction can be successfully executed in parallel, and the processing efficiency of the at least one instruction is improved through parallel execution. Moreover, this method can also be applied in the scenario of instruction bundles, and the application range is wide.

[0029] In a possible implementation, the first instruction includes an instruction for forwarding an application program. When the first instruction is used to forward an application program, by compressing the first instruction, the reading efficiency of the first instruction is improved, and the forwarding efficiency based on the first instruction is higher.

[0030] In a third aspect, an instruction processing device is provided, and the device includes: an acquisition module, configured to acquire a first instruction to be processed; a determination module, configured to determine a compression level of a memory in the memory structure according to the memory structure and the required rate for reading the first instruction, where the memory structure is used to store the compressed first instruction; and a compression module, configured to compress the first instruction by using the compression level.

[0031] In a possible implementation, the obtaining module is further configured to obtain at least one of the path attributes of the read paths of the respective memories included in the memory structure or the read efficiency of the memory structure, where the read path of a memory is the path connecting the memory and the read module, and the read module is configured to read the instructions stored in the memory and process the read instructions; the determining module is further configured to determine the required rate for reading the first instruction according to at least one of the path attributes or the read efficiency.

[0032] In a possible implementation, the determining module is configured to determine the read rate of each memory included in the memory structure; determine the decompression rate of each memory according to the required rate for reading the first instruction and the read rate of each memory, where the decompression rate of a memory is the rate of decompressing the instructions stored in the memory on the read path of the memory; determine the compression level of each memory according to the decompression rate of each memory, and the compression rate corresponding to the compression level of the memory matches the decompression rate corresponding to the memory.

[0033] In a possible implementation, the memory structure includes a storage module and a cache module. The compression level of the storage module is two - layer compression, and the compression level of the cache module is one - layer compression. The decompression rate of one - layer compression is higher than that of two - layer compression; the compression module is configured to compress the first instruction using the compression method of one - layer compression to obtain a second instruction; compress the second instruction using the compression method of two - layer compression to obtain a third instruction, and the compression rate of the compression method of two - layer compression is greater than that of the compression method of one - layer compression.

[0034] In a possible implementation, the ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. The obtaining module is further configured to obtain the service characteristic of the first instruction, where the service characteristic indicates the operation quality requirement of the service running based on the first instruction; the determining module is further configured to determine the compression ratio according to the service characteristic of the first instruction.

[0035] In a possible implementation, the compression module is configured to obtain the instruction characteristic of the first instruction; in the case where it is determined according to the instruction characteristic that fixed - length compression is supported, compress the first instruction using the fixed - length compression method to obtain a second instruction, or, in the case where it is determined according to the instruction characteristic that fixed - length compression is not supported, split the first instruction into multiple second instructions, and the bit widths of the respective second instructions in the multiple second instructions are the same.

[0036] In a possible implementation, the instruction characteristic includes at least one of the instruction type, usage frequency, or field utilization rate of the first instruction.

[0037] In a possible implementation, a compression module is configured to determine a valid field of a first instruction, and obtain a second instruction including the valid field, where the valid field is a field used to execute the first instruction.

[0038] In a possible implementation, the second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by fixed-length compression or splitting.

[0039] In a possible implementation, a compression module is configured to obtain the occurrence frequency of each field included in the second instruction; obtain a third instruction according to the occurrence frequency of each field, where the third instruction includes the encoding of each field, the encoding of each field is determined based on the occurrence frequency of each field, and the length of the encoding of each field is inversely proportional to the occurrence frequency of each field.

[0040] In a possible implementation, a determination module is further configured to construct an encoding dictionary corresponding to the second instruction according to the occurrence frequency of each field, where the encoding dictionary includes each field and the occurrence frequency of each field; determine the encoding of each field according to the encoding dictionary.

[0041] In a possible implementation, the third instruction includes an encoding index, and the encoding index is used to find the field corresponding to the encoding included in the third instruction during the decompression of the third instruction.

[0042] In a possible implementation, the apparatus further includes: a storage module, configured to obtain the instruction length of the compressed first instruction; determine a storage unit in the memory structure for storing the compressed first instruction according to the instruction length, and store the compressed first instruction in the determined storage unit.

[0043] In a possible implementation, the first instruction includes an instruction for forwarding an application program.

[0044] In a possible implementation, an obtaining module is configured to obtain at least one instruction included in an instruction bundle, where any one of the at least one instruction is a first instruction to be processed, and the at least one instruction is an instruction for parallel execution.

[0045] In a fourth aspect, another instruction processing apparatus is provided, where the apparatus includes: an obtaining module, configured to obtain a compressed first instruction, where the compression of the first instruction is implemented based on a compression level, and the compression level is determined based on a memory structure and a required rate for reading the first instruction, and the memory structure is used to store the compressed first instruction; a restoring module, configured to restore the compressed first instruction.

[0046] In a possible implementation, the memory structure includes a storage module and a cache module. The compression level of the storage module is two-level compression, and the compression level of the cache module is one-level compression. The restoration rate of one-level compression is higher than that of two-level compression. The compressed first instruction includes a third instruction. A restoration module is configured to restore the third instruction by using the restoration method corresponding to the two-level compression method to obtain a second instruction, and restore the second instruction by using the restoration method corresponding to the one-level compression method to obtain the first instruction. The compression rate of the two-level compression method is greater than that of the one-level compression method.

[0047] In a possible implementation, the third instruction includes a coding index. The restoration module is configured to parse the coding index included in the third instruction, determine each field corresponding to each coding included in the third instruction according to the coding index, and determine the second instruction according to each field corresponding to each coding. The length of the coding of each field is inversely proportional to the occurrence frequency of each field.

[0048] In a possible implementation, the restoration method corresponding to the one-level compression method includes decompression corresponding to fixed-length compression or splicing corresponding to splitting. The restoration module is configured to, when the second instruction is obtained by the fixed-length compression method, decompress the second instruction by using the decompression corresponding to the fixed-length compression to obtain the first instruction; or, when the second instruction is obtained by the splitting method, splice a plurality of second instructions obtained by splitting the first instruction to obtain the first instruction. The bit widths of the respective second instructions among the plurality of second instructions are the same.

[0049] In a possible implementation, the second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by the fixed-length compression or splitting method. The restoration module is further configured to parse the compression flag bit included in the second instruction and determine the method for obtaining the second instruction from the fixed-length compression and splitting according to the compression flag bit.

[0050] In a possible implementation, an acquisition module is configured to extract at least one instruction stored in a row of storage units of the memory structure, and separate each instruction according to the instruction length of each instruction in the at least one instruction to obtain at least one instruction, where the at least one instruction includes the compressed first instruction.

[0051] In a possible implementation, the apparatus further includes: a sending module configured to determine an instruction bundle corresponding to the first instruction. The instruction bundle includes at least one instruction, and the compression results of the at least one instruction are stored in the same row of storage units of the memory structure. The compression result of any instruction among the compression results of the at least one instruction is the compressed first instruction, and the at least one instruction is an instruction for parallel execution. The sending module is configured to send the at least one instruction included in the instruction bundle to a decoding module, and the decoding module is configured to parse the at least one instruction.

[0052] In a possible implementation, the first instruction includes an instruction for forwarding an application.

[0053] In a fifth aspect, there is provided an instruction processing device, which includes a processor for loading and executing at least one instruction, so that the instruction processing device executes the method in the first aspect or any possible implementation manner of the first aspect, or executes the method in the second aspect or any possible implementation manner of the second aspect.

[0054] In a possible implementation, the device includes a memory coupled to the processor, and the memory stores at least one instruction.

[0055] In a sixth aspect, there is provided a computer-readable storage medium storing at least one instruction, and the instruction is loaded and executed by a processor to implement the instruction processing method in the first aspect or any possible implementation manner of the first aspect, or to implement the instruction processing method in the second aspect or any possible implementation manner of the second aspect.

[0056] In a seventh aspect, there is provided a computer program (product), and the computer program (product) includes a computer program / instructions, and the computer program / instructions are executed by a processor, so that the computer implements the instruction processing method in the first aspect or any possible implementation manner of the first aspect, or implements the instruction processing method in the second aspect or any possible implementation manner of the second aspect.

[0057] In an eighth aspect, there is provided a communication device, which includes: a transceiver, a memory, and a processor. Among them, the transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals. And when the processor executes the instructions stored in the memory, the processor executes the method in the first aspect or any possible implementation manner of the first aspect, or executes the method in the second aspect or any possible implementation manner of the second aspect.

[0058] Optionally, the processor is one or more, and the memory is one or more.

[0059] Optionally, the memory may be integrated with the processor, or the memory is separately provided from the processor.

[0060] In the specific implementation process, the memory can be a non-transitory memory, such as a read only memory (ROM), which can be integrated with the processor on the same chip or can be separately arranged on different chips. The present application does not limit the type of the memory and the arrangement manner of the memory and the processor.

[0061] In a ninth aspect, a chip is provided, including a processor configured to call and run the operating program instructions or code stored in the memory, so that a communication device installed with the chip executes the methods in the above aspects.

[0062] In a tenth aspect, another chip is provided, including: an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The processor is configured to execute the code in the memory. When the code is executed, the processor is configured to execute the methods in the above aspects.

[0063] It should be understood that the beneficial effects obtained by the technical solutions of the third aspect to the tenth aspect of the present application and the corresponding possible implementation manners can refer to the technical effects of the first aspect and its corresponding possible implementation manner or the second aspect and its corresponding possible implementation manner described above, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A schematic diagram of an implementation environment provided by an embodiment of the present application;

[0065] Figure 2 A schematic diagram of another implementation environment provided by an embodiment of the present application;

[0066] Figure 3 A flowchart of an instruction processing method provided by an embodiment of the present application;

[0067] Figure 4 A schematic structural diagram of a processor provided by an embodiment of the present application;

[0068] Figure 5 A schematic diagram of an instruction processing process provided by an embodiment of the present application;

[0069] Figure 6 A schematic structural diagram of a first instruction and a second instruction provided by an embodiment of the present application;

[0070] Figure 7 A schematic diagram of a two-stage compression process provided by an embodiment of the present application;

[0071] Figure 8 A flowchart of an instruction compression provided by an embodiment of the present application;

[0072] Figure 9 Flow chart of an instruction processing method provided by an embodiment of the present application;

[0073] Figure 10 Schematic diagram of a process for reading an instruction provided by an embodiment of the present application;

[0074] Figure 11 Schematic diagram of a decompression process provided by an embodiment of the present application;

[0075] Figure 12 Schematic diagram of the effect of fixed-length restoration provided by an embodiment of the present application;

[0076] Figure 13 Flow chart of a fixed-length restoration provided by an embodiment of the present application;

[0077] Figure 14 Another flow chart of fixed-length restoration provided by an embodiment of the present application;

[0078] Figure 15 Effect comparison diagram of instruction storage provided by an embodiment of the present application;

[0079] Figure 16 Schematic diagram of the structure of an instruction processing device provided by an embodiment of the present application;

[0080] Figure 17 Another schematic diagram of the structure of an instruction processing device provided by an embodiment of the present application;

[0081] Figure 18 Schematic diagram of the structure of a network device provided by an embodiment of the present application;

[0082] Figure 19 Another schematic diagram of the structure of a network device provided by an embodiment of the present application. Detailed implementation manners

[0083] The terms used in the implementation manners part of the present application are only used to explain the specific embodiments of the present application, rather than aiming to limit the present application. To make the purpose, technical solutions and advantages of the present application clearer, the following will further describe the implementation manners of the present application in detail with reference to the accompanying drawings.

[0084] In the field of computer technology, a processor is the computing and control core of a network device and is used to run application programs. Exemplarily, the processor includes an instruction storage module, a decoding module, and a parallel computing module. Among them, the instruction storage module is used to store the instructions after the application program is compiled to achieve a programmable effect. The decoding module is used to parse the instructions stored in the instruction storage module, obtain the parsing result, and send the parsing result to the parallel computing module. The parallel computing module performs parallel computing based on the parsing results of multiple instructions to obtain multiple result data, so as to run the application program according to the multiple result data.

[0085] In the related art, for a run to complete (RTC) architecture forwarding processor, the RTC architecture forwarding processor includes multiple processor cores and multiple instruction cache modules. One processor core is connected to one instruction cache module, and multiple instruction cache modules are connected to one instruction storage module. Among them, the hardware overhead of the instruction cache module is less than that of the instruction storage module. Replacing multiple large-capacity instruction storage modules with multiple small-capacity instruction cache modules can reduce the hardware overhead of the processor. However, in a high-performance service scenario with a large amount of stored instructions, the instruction cache module still needs to provide a large capacity, the hardware overhead of the instruction cache module increases, and the storage overhead is still high.

[0086] An embodiment of the present application provides an instruction processing method. Please refer to Figure 1 , which shows a schematic diagram of an implementation environment of the instruction processing method provided by an embodiment of the present application. The implementation environment includes a compression module 01, a memory structure 02, and a restoration module 03. The compression module 01, the memory structure 02, and the restoration module 03 can establish a communication connection relationship as shown in Figure 1 through an effective or wireless network. In a possible implementation manner, the compression module 01 is used to compress the first instruction to be processed by using the method provided by the embodiment of the present application, and store the compressed first instruction in the memory structure 02. The restoration module 03 can perform a restoration operation on the compressed first instruction stored in the memory structure 02 by using the method provided by the embodiment of the present application to obtain the first instruction.

[0087] Exemplarily, Figure 1 the memory included in the memory structure 02 in Figure 2 can be one or more. Figure 2 is another schematic diagram of an implementation environment provided by an embodiment of the present application. Refer to Figure 2 , the processor includes a storage module, a cache module, and a decoding module. Among them, the storage module and the cache module can be used to store instructions (inst). In this case, Figure 1 the memory included in the memory structure 02 in Figure 2The storage module and cache module in the left and right figures. In a possible scenario, the cache module can be referred to as an instruction cache (ICACHE), which is used to cache the instructions to be processed by the decoding module, so as to improve the rate at which the decoding module reads instructions, and thus improve the instruction parsing rate. Figure 2 In the left figure of Figure 2 , the instruction interaction between the storage module, cache module, and decoding module is carried out with the instruction word as a whole. An instruction word refers to multiple instructions located in the same row of storage units, and this same row of storage units can be the storage units in the storage module or the cache units in the cache module.

[0088] For Figure 1 the case where the memory structure 02 shown includes multiple memories, the restoration module 03 can establish communication connections with each of the memories included in the memory structure 02 respectively. Refer to Figure 2 the right figure of Figure 2 , Figure 2 in which the storage module and the cache module are respectively connected to the restoration module 03. Figure 2 The multiple restoration modules 03 in the right figure of Figure 2 refer to different operation units of the restoration module 03, and the restoration operations performed by different operation units are different. Optionally, the number of storage modules and cache modules can be the same, that is, the storage modules and cache modules are in one-to-one correspondence, or the number of storage modules and cache modules can be different. For example, multiple cache modules share one storage module, and the embodiments of the present application do not limit this.

[0089] Optionally, Figure 1 the compression module 01, memory structure 02, and restoration module 03 in Figure 1 can be integrated on the same network device. This network device can be any network device configured with a processor, and the configured processor can be a programmable processor of any structure, such as an RTC architecture forwarding processor, or other types of processors. Exemplarily, the network device can be a server, such as a central server, edge server, or a local server in a local data center. The server can be a physical server or a cloud server providing cloud computing services in a cloudified scenario. In some embodiments, the network device can also be a terminal device such as a desktop computer, laptop computer, or smartphone, or a switch, router, and gateway (GW), etc. The instruction processing operation performed by the compression module 01 can be implemented based on a compiler program, so the compression module 01 is, for example, a compiler, and the instruction processing operation performed by the restoration module 03 can be implemented based on hardware operation, so the restoration module 03 is, for example, a decoder.

[0090] The embodiments of the present application provide an instruction processing method, and this instruction processing method can be applied to the above Figure 1 or Figure 2In the implementation environment shown in FIG. 1 , the method is executed by the compression module as an example. The flowchart of the method is as follows: Figure 3 As shown, it includes S301-S303.

[0091] S301: Obtain a first instruction to be processed.

[0092] Exemplarily, an instruction refers to a command obtained after compiling an application program to instruct a network device to work, and the network device is, for example, a personal terminal or a server. The first instruction to be processed may be an instruction obtained by compiling any application program, for example, an instruction for forwarding an application program, and the application program includes but is not limited to a game application program, a video playback software application program, or a social application software program. Optionally, the compression module may obtain the code to be run, convert the obtained code into an instruction, and obtain the first instruction to be processed. The code to be run may be a code input manually, or may be a code obtained by accessing a code library based on manually input operation requirements. The compression module may also receive the first instruction to be processed sent from other devices or modules. The embodiment of the present application does not limit the method for obtaining the first instruction.

[0093] The embodiments of the present application do not limit the number of first instructions to be processed; the number of first instructions to be processed can be one. For example, the compression module determines, based on the code, that executing a move (mov) instruction can command the network device to operate, and determines the one mov instruction as the first instruction to be processed. Optionally, the number of first instructions to be processed can be multiple, and the multiple first instructions can belong to the same instruction bundle or different instruction bundles, such as very long instruction words (VLIWs). The instructions included in the instruction bundle can be divided according to the function corresponding to the instruction, the application corresponding to the instruction, or other methods. By connecting multiple instructions together through instruction bundles, the multiple instructions included in an instruction bundle are executed in parallel, thereby improving the computing speed of executing multiple instructions. Parallel execution of multiple instructions can mean executing multiple instructions in parallel once. For example, an instruction bundle includes three instructions, and the three instructions are executed in parallel within a beat to achieve synchronous execution of the three instructions. Parallel execution of multiple instructions can also mean executing multiple instructions in parallel multiple times, that is, the method adopted is a combination of parallel and serial methods. For example, an instruction bundle includes eight instructions. Since at most four instructions can be executed in one beat, the first four instructions are executed in parallel first, and then after the first four instructions are completed, the last four instructions are executed in parallel.

[0094] Exemplarily, the compression module obtains at least one instruction included in the instruction bundle. The at least one instruction is an instruction to be executed in parallel, and any one of the at least one instructions is a first instruction to be processed. That is, each instruction included in the instruction bundle will be processed as a first instruction using the instruction processing method provided in the embodiments of the present application. Since the process of processing one first instruction is similar to that of processing multiple first instructions, hereinafter, taking any one instruction included in the instruction bundle as the first instruction to be processed as an example, the processing process of one first instruction will be illustrated. The processing process of other instructions included in the instruction bundle except any one instruction can refer to similar descriptions and will not be repeated here.

[0095] S302. Determine the compression level of the memory in the memory structure according to the memory structure and the required rate for reading the first instruction. The memory structure is used to store the compressed first instruction.

[0096] In a possible case, the network device commanded by the first instruction includes a memory structure for storing the first instruction to be processed to achieve a programmable effect. Taking the RTC architecture forwarding processor configured as shown in Figure 4 as an example, the RTC forwarding architecture processor includes a scheduler (input scheduler), a processor core (RTC core), and a storage module, etc. The storage module, that is, the memory included in the memory structure. Optionally, a communication connection is established between the processor core and the storage module. The established communication connection can be a direct connection or an indirect connection implemented based on a restoration module, that is, the processor core is connected to the restoration module, and the restoration module is connected to the storage module. Optionally, there can be one restoration module, that is, one restoration module is respectively connected to multiple storage modules and multiple processor cores. There can also be multiple restoration modules, and the number of multiple restoration modules can be the same as the number of storage modules, that is, the restoration modules are in one-to-one correspondence with the processor cores and the storage modules as shown in Figure 4 One restoration module is used to connect one processor core and one storage module. The number of multiple restoration modules can also be less than the number of storage modules, that is, there is a situation where one restoration module is connected to multiple storage modules and there is also a situation where one restoration module is connected to one storage module.

[0097] During the process of storing the first instruction in the memory structure, the compression module may compress the first instruction according to the memory structure and the required rate for reading the first instruction. Optionally, the rate mentioned in this application can be understood as a time delay or a clock cycle. The required rate for reading the first instruction refers to the number of clock cycles required to read the first instruction from the memory structure. The measurement unit of the clock cycle is, for example, a beat or other time units. In a possible case, reading the first instruction from the memory structure includes multiple processes of reading the first instruction from the memory included in the memory structure and processing the read first instruction. The processing is, for example, an operation such as restoration.

[0098] The embodiments of this application do not limit the process for the compression module to obtain the required rate for reading the first instruction, including but not limited to: obtaining at least one of the path attributes of the reading paths of each memory included in the memory structure or the reading efficiency of the memory structure. The reading path of the memory is the path connecting the memory and the reading module. The reading module is used to read the instructions stored in the memory and process the read instructions; determining the required rate for reading the first instruction according to at least one of the path attributes or the reading efficiency.

[0099] Exemplarily, the reading module of the memory refers to the reading module connected to the memory and used to read the instructions stored in the memory. Taking the memory structure shown in the left figure of Figure 2 as an example, when the memory is a storage module, the reading module is a cache module; when the memory is a cache module, the reading module is a decoding module. Taking the memory structure shown in the right figure of Figure 2 as an example, when the memory is a storage module, the reading module is the restoration module 03 connected to the storage module; when the memory is a cache module, the reading module is the restoration module 03 connected to the memory.

[0100] Optionally, the compression module may determine the reading paths connecting each memory and the reading module, and determine the path attributes of the reading paths. Among them, the path attribute is a feature affecting the reading delay of the reading path, and the path attribute includes but is not limited to the length or width of the reading path, etc. In a possible implementation manner, the reading efficiency is related to the network processor (NP) corresponding to the memory structure. The compression module may obtain the processing performance of the NP corresponding to the memory structure, determine the reading efficiency of the memory structure according to the processing performance, and determine the required rate for reading the first instruction stored in the memory structure according to the reading efficiency and the path attributes of the reading paths of each memory.

[0101] Exemplarily, the required rate for reading the first instruction stored in the memory structure refers to the overall rate required to completely read the first instruction from the memory structure. When there is one memory in the memory structure, the required rate for reading the first instruction refers to the rate of reading the first instruction from the one memory and the rate of restoring the read first instruction. When there are multiple memories in the memory structure, for example Figure 2 as shown in the storage module and cache module, the required rate for reading the first instruction from the memory structure includes the rate 1 of reading the first instruction from the storage module, the rate 2 of restoring the read first instruction, the rate 3 of sending the first instruction stored in the storage module to the cache module, the rate 4 of reading the first instruction stored in the cache module, and the rate 5 of restoring the read first instruction. Optionally, the required rate for reading the first instruction can also be set based on experience. For example, the compression module provides an information input control, and the operation and maintenance personnel set the required rate for reading the first instruction based on experience and the implementation environment, and input the required rate through the information input control. The compression module thus obtains the required rate for reading the first instruction. Among them, the implementation environment can refer to the hardware configuration of the memory structure, such as the type of NP used or the model of the memory structure, etc.

[0102] Regardless of how the compression module obtains the required rate for reading the first instruction, the compression level of the memories in the memory structure can be determined based on the memory structure and the required rate for reading the first instruction. Exemplarily, the compression module determines the reading rate of each memory included in the memory structure; determines the restoration rate of each memory according to the required rate for reading the first instruction and the reading rate of each memory. The restoration rate of the memory is the rate of decompressing the instruction stored in the memory on the reading path of the memory; determines the compression level of each memory according to the restoration rate of each memory. The restoration rate corresponding to the compression level of the memory matches the restoration rate corresponding to the memory.

[0103] Optionally, the compression module determines the memory in the memory structure where the first instruction is to be stored. Taking the memory structure including one storage module and multiple cache modules as an example, the multiple cache modules share one storage module. In this case, a first instruction will first be stored in the storage module and then stored in any one of the multiple cache modules. Therefore, the memory in the memory structure where the first instruction is to be stored is one storage module and one cache module.

[0104] After that, the compression module can determine the reading rate required to read instructions from each memory according to the hardware structure of each memory. Since the required rate for reading the first instruction is the overall rate of completing the reading of the first instruction from the memories included in the memory structure, that is, the required rate includes the reading rate of reading the first instruction from the memory and the processing rate of processing the read first instruction. Processing the first instruction includes restoring the first instruction, etc. Therefore, the sum of the restoration rate and the reading rate of each memory is not greater than the required rate for reading the first instruction. The difference obtained by subtracting the sum of the required rate and the reading rate of each memory can represent the maximum value of the sum of the restoration rates of each memory. Then, according to the hardware structure of each memory, such as the reading path of each memory and the reading rate required for the reading module of each memory to read instructions, the restoration rate of each memory is determined. The restoration rate of any memory indicates the rate of restoring the instructions stored in any memory, and this restoration rate does not affect the original forwarding performance of the memory.

[0105] Since the restoration rate is negatively correlated with the compression complexity, the higher the compression complexity of the compression method, the lower the corresponding restoration rate of this compression method. Therefore, the corresponding compression complexity can be determined according to the restoration rate, and the compression level can be determined according to the compression complexity. Optionally, the higher the compression level, the higher the compression complexity, the lower the restoration rate, and the higher the compression ratio. Among them, the compression ratio refers to the ratio of the compressed instruction to the uncompressed instruction.

[0106] Optionally, the compression module can also obtain the rate range corresponding to each compression level. According to the restoration rate of each memory and the rate range corresponding to each compression level, the compression level of each memory is determined. Taking the compression level including one-layer compression and two-layer compression as an example, the rate range corresponding to one-layer compression is range A, and the rate range corresponding to two-layer compression is range B. Since the restoration rate of the storage module is the rate included in range B, the compression module determines that the compression level of the storage module is two-layer compression. Based on the restoration rate of the cache module being the rate included in range A, the compression module determines that the compression level of the cache module is one-layer compression.

[0107] In a possible case, the compression module can also directly determine the compression level of each memory according to the reading rate of each memory. Continuing to take the memory including the cache module and the storage module as an example, since the reading rate of the storage module is lower than that of the cache module, the compression level of the storage module is higher than that of the cache module. For example, the compression level of the storage module is two-layer compression, and the compression level of the cache module is one-layer compression. The restoration rate of one-layer compression is higher than that of the two-layer compression.

[0108] S303, compress the first instruction using the compression level.

[0109] Exemplarily, the compression module determines the compression method for each memory's compression level, and compresses the first instruction according to the determined compression method. The compression methods for different compression levels can be different. For example, the compression method for one-level compression is fixed-length processing, and the compression method for two-level compression is variable-length compression. The compression methods for different compression levels can also be the same, that is, the number of compression times indicated by different compression levels is different. For example, the compression method for one-level compression is to compress using compression algorithm 1, and the compression method for two-level compression is to perform one compression using compression algorithm 1 to obtain compression result 1, and then perform a second compression on compression result 1 to obtain compression result 2. Compression result 2 is the result obtained by compressing using the two-level compression method.

[0110] In the case where the memory structure includes multiple memories, there is a compression order for the multiple memories. Continuing with the example where the memory structure includes a storage module and a cache module, refer to Figure 5 , after the first instruction is compressed using compression algorithm 1 and compression algorithm 2 respectively to obtain the third instruction, the third instruction will be stored in the storage module. The third instruction stored in the storage module will be sent to the cache module for caching after being read, and during the transmission process, the third instruction will also be restored, that is, the decompression logic 2 corresponding to compression algorithm 2 is executed to restore the third instruction to the second instruction, and then the second instruction is cached in the cache module. After that, for the second instruction stored in the cache module, it will be sent to the decoding module for parsing after being read, and during the transmission process, the second instruction is restored, that is, the decompression logic 1 corresponding to compression algorithm 1 is executed to restore the second instruction to the first instruction, and the decoding module decodes the first instruction. In this case, since the decompression corresponding to the compression method of the storage module is performed first, and then the decompression corresponding to the compression method of the cache module is performed, and the decompression order is opposite to the compression order, that is, the later the compression is performed, the earlier the corresponding restoration is performed. Therefore, the compression module first executes the compression method of the cache module, and then performs the compression method of the storage module.

[0111] Optionally, for a memory structure including multiple memories, the compression module can first determine the compression method for each memory, and then determine the compression order for each memory, or can first determine the compression order for each memory, and then determine the compression method for each memory. Or determine the compression order and compression method in parallel based on multiple threads. And regardless of the method by which the compression module determines the compression order and compression method, it can compress the first instruction using the compression methods of each memory according to the compression order to obtain the compressed first instruction.

[0112] Since the processes of compressing the first instruction once and compressing it multiple times are similar, hereinafter, taking a memory structure including a storage module and a cache module as an example, where the compression level of the storage module is two - layer compression and the compression level of the cache module is one - layer compression, and the restoration rate of one - layer compression is higher than that of two - layer compression, the process of compressing the first instruction will be introduced by way of example.

[0113] In a possible implementation manner, the compression module compresses the first instruction using a one - layer compression method to obtain a second instruction; and compresses the second instruction using a two - layer compression method to obtain a third instruction. The compression rate of the two - layer compression method is greater than that of the one - layer compression method. Exemplarily, the one - layer compression method is fixed - length processing, and the ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. The compression ratio is, for example, any integer set based on experience and the implementation environment. The compression ratio can also be determined based on service characteristics. Optionally, the compression module obtains the service characteristics of the first instruction, and the service characteristics indicate the running quality requirements of the service based on which the first instruction runs; and determines the compression ratio according to the service characteristics of the first instruction. Among them, the service characteristics can be determined based on a service - level agreement (SLA), and the service characteristics include, but are not limited to, the running delay and packet loss rate of the service. The compression module obtains the service characteristics and determines the compression ratio that can be performed without affecting the running quality of the service based on the service characteristics. Exemplarily, the compression ratio determined based on the service characteristics can be 2. When the first instruction is 64 bits, the second instruction obtained by fixed - length processing is 32 bits; when the first instruction is 8 bits, the second instruction obtained by fixed - length processing is 4 bits. In this case, the second instruction obtained by performing fixed - length processing on the first instruction can also be called a half - width instruction.

[0114] In a possible case, the fixed - length processing includes fixed - length compression or splitting. In this case, the compression module can obtain the instruction characteristics of the first instruction; in the case where it is determined according to the instruction characteristics that fixed - length compression is supported, the first instruction is compressed using a fixed - length compression method to obtain a second instruction; or, in the case where it is determined according to the instruction characteristics that fixed - length compression is not supported, the first instruction is split into multiple second instructions, and the bit widths of the respective second instructions in the multiple second instructions are the same.

[0115] Exemplarily, the instruction features of the first instruction include at least one of the instruction type, usage frequency, or field utilization rate of the first instruction. Among them, the instruction type can be the functional classification of the instruction. For example, the instruction type includes transfer instructions or memory access instructions, etc. The instruction type can also be classified according to the instruction format. For example, the instruction type includes two-operand instructions, single-operand instructions, or program transfer instructions, etc. Optionally, the usage frequency of the first instruction can reflect the number of times the instructions with the same function are used within the reference time. The reference time can be any time unit set according to experience and the implementation environment. For example, the reference time is 1 second. Taking the first instruction as the move (mov) instruction as an example, the compression module counts the number of mov instructions executed within 1 second and calculates the usage frequency of the mov instructions. The usage frequency can also refer to the proportion of the functional instructions corresponding to the first instruction among multiple instructions for running the application program. In a possible case, the field utilization rate is used to reflect the number of blank fields included in the first instruction.

[0116] The compression module can select to determine whether fixed-length compression can be performed on the first instruction according to at least one of the instruction type, usage frequency, or field utilization rate. Next, the implementation methods for determining whether fixed-length compression can be performed on the first instruction according to the three instruction features will be introduced separately.

[0117] Implementation method 1: Obtain the instruction types that support fixed-length compression; in the case where the obtained instruction types include the instruction type of the first instruction, determine to perform fixed-length compression on the first instruction.

[0118] Exemplarily, the instruction types that support fixed-length compression can be input manually. For example, the network device where the compression module is located provides an information input control. The operation and maintenance personnel input the instruction types that support fixed-length compression according to the information input control, and the compression module thereby obtains the set of instruction types that support fixed-length compression. Taking the instruction types including mov instructions and add instructions as an example, since the size of the unused blank fields in the mov instruction is greater than the first threshold set based on experience, there is more unused space in the mov instruction, and fixed-length compression can be performed. However, the size of the unused blank fields in the add instruction is less than the first threshold set based on experience, and the unused space in the add instruction is small, so fixed-length compression cannot be adopted. Based on this, the operation and maintenance personnel input the instruction types that support fixed-length compression through the information input control, including mov instructions. In a possible case, the compression module can also obtain the set of instruction types that support fixed-length compression through the learning of historical data. The historical data is, for example, the compression results of each instruction type using fixed-length compression. By machine learning, the success rate of different instruction types using fixed-length compression is statistically calculated to determine the instruction types that support fixed-length compression.

[0119] Implementation Method 2: When the usage frequency is greater than the second threshold, it is determined to use fixed-length compression for the first instruction; or, when the usage frequency is not greater than the second threshold, it is determined not to use fixed-length compression for the first instruction.

[0120] Optionally, the second threshold can be any value set based on experience, such as 70% or 50%. When the usage frequency of the first instruction is greater than the second threshold, the first instruction belongs to the frequently used instructions. The first instruction is cached in the cache module more times and occupies a large storage overhead. Therefore, fixed-length compression is performed on the first instruction to reduce the cache space occupied by the first instruction in the cache module, thereby reducing the storage overhead of the first instruction. When the usage frequency of the first instruction is not greater than the second threshold, it indicates that the first instruction does not belong to the frequently used instructions. The first instruction is cached in the cache module fewer times. If fixed-length compression is used for the first instruction, the first instruction after fixed-length compression needs to be restored later. Even if the storage overhead is reduced, the restoration overhead increased by restoring the compressed first instruction is higher than the reduced storage overhead, and the instruction overhead is still large.

[0121] Implementation Method 3: When the field utilization rate is less than the third threshold, it is determined to use fixed-length compression for the first instruction; or, when the field utilization rate is not less than the third threshold, it is determined not to use fixed-length compression for the first instruction.

[0122] Optionally, the third threshold can be set according to the compression ratio. When fixed-length compression is used to compress the first instruction into a half-width instruction with a half bit width, the third threshold can be 50%. When the field utilization rate is less than 50%, it indicates that there are many unused idle fields in the first instruction. The first instruction can be compressed into a half-width instruction by deleting the idle fields. When the field utilization rate is greater than 50%, since there are few unused idle fields in the first instruction, even if all the idle fields are deleted, a half-width instruction cannot be obtained, but further processing is required. The processing process is redundant and complex, and the efficiency is low. Therefore, fixed-length compression is not performed on the first instruction.

[0123] The compression module can determine whether the first instruction can be compressed to a fixed length according to any one of implementation method 1, implementation method 2, and implementation method 3 based on the instruction characteristics. It can also combine multiple implementation methods. For example, it can judge whether the first instruction can be compressed to a fixed length by combining the instruction type and the field utilization rate. In this case, one instruction characteristic corresponds to one judgment result. When different judgment results occur, for example, it is determined according to the instruction type that the first instruction cannot be compressed to a fixed length, and it is determined according to the field utilization rate that the first instruction can be compressed to a fixed length. The judgment result can be determined according to the weights of different instruction types. Assuming that the weight of the instruction type set according to experience is lower than the weight of the field utilization rate, since the field utilization rate indicates that the first instruction can be compressed to a fixed length, the compression module determines to perform fixed-length compression on the first instruction.

[0124] Regardless of the method based on which the compression module determines whether the first instruction can be compressed to a fixed length, the first instruction can be processed to a fixed length according to the judgment result. Exemplarily, the process of compressing the first instruction to a fixed length includes: determining the valid fields of the first instruction to obtain a second instruction including the valid fields. Herein, the valid fields refer to the fields used to execute the first instruction. Such fields are, for example, non-blank fields, or can be repeated fields, or essential fields that are indispensable during the execution of the instruction.

[0125] Figure 6 FIG. is a schematic diagram of a valid field provided by an embodiment of the present application. Figure 6 Four instructions are shown, namely mov instruction, merge (mrg) instruction, compare (cmp) instruction, and jump (jmp) instruction. Refer to Figure 6 , the mov instruction includes an opcode field, an ineffective condition (cond) field, a destination (Dst) operand field, and a source (Src) 1 operand / immediate (IMM) field. Figure 6 The slash shading in [[ ]] indicates a blank field. Figure 6 In [[ ]], the non-blank fields in the mov instruction include the opcode field, the ineffective cond field, the Dst field, and the Src1 / IMM field. Since the mov instruction only needs to use the opcode field, the Dst field, and the Src1 field and does not need to use the ineffective cond field, the valid fields in the mov instruction are the opcode field, the Dst field, and the Src1 field. Regarding the valid fields in the mrg instruction, cmp instruction, and jmp instruction, they can be determined in combination with the mrg instruction, cmp instruction, and jmp instruction after fixed-length compression in [[ ]]. Figure 6 the mrg instruction, cmp instruction, and jmp instruction in [[ ]] and the mrg instruction, cmp instruction, and jmp instruction after fixed-length compression.

[0126] After the compression module determines the valid field of the first instruction, the second instruction can be determined based on the valid field. Optionally, the compression module can extract the valid field included in the first instruction and splice the valid fields to obtain the second instruction. The valid field can also be shrunk, and the shrunk valid fields can be spliced to obtain the second instruction. Here, shrinking the valid field means reducing the number of bits occupied by the valid field, determining the first number of bits occupied by the information carried in the valid field, determining the second number of bits occupied by the valid field, and adjusting the number of bits occupied by the valid field from the second number of bits to the first number of bits. For example, if the field size of the valid field is 6 bits and the information carried in the valid field occupies 4 bits, the valid field can be shrunk to 4 bits. Figure 6 In Figure 6 , the compression module extracts the opcode field, Dst field, and Src1 field, shrinks the opcode field, Dst field, and Src1 field, and splices the shrunk opcode field, Dst field, and Src1 field to form Figure 6 the fixed-length compressed mov instruction shown, which is also the second instruction. In a possible case, the compression module can also shrink the data selection range of the valid field. For example, it determines the common selection range in the valid field where the usage frequency is greater than the reference threshold, and uses the common selection range as the data selection range indicated by the valid field. For example Figure 6 in the mrg instruction in Figure 6 , since the data selection uses the low address space and small immediate numbers, where the small immediate number refers to an immediate number with a value less than the fourth threshold, and the low address space refers to an address space with a value less than the fifth threshold. The fourth threshold and the fifth threshold can be values set based on experience and the implementation environment. In this case, the small immediate number can be modified into a field to achieve the shrinking of the data selection range. In a possible case, the above process of fixed-length compression can also be referred to as instruction set architecture compression (ISA compression) or instruction set compression.

[0127] For the first instruction that cannot be compressed with a fixed length, the compression module will also split the first instruction into second instructions with the same bit width for the units digit of the compression ratio. The above splitting process can be based on the instruction structure of the first instruction. For example, the splitting position of the first instruction can be determined in the instruction structure according to the compression ratio, and the first instruction can be split at the splitting position to obtain multiple second instructions. Taking the compression ratio of 2 and the first instruction of 8 bits as an example, based on 8 divided by 2 equals 4, the splitting position of the first instruction is determined to be the midpoint of the instruction structure, that is, the position of the 4th bit. The first 4-bit field of the first instruction is split into the first second instruction, and the last 4 bits of the first instruction are split into the second second instruction. By splitting or performing fixed-length compression on the first instruction, the instruction sizes of the second instructions are unified. By normalizing the bit width ratio of the instructions, the subsequent compression process for the second instructions with a unified bit width ratio is simpler and the compression efficiency is higher.

[0128] Since the compression module may perform fixed-length compression on the first instruction to obtain a second instruction, or may split the first instruction to obtain a second instruction, therefore, the second instruction includes a compression flag bit, and the compression flag bit indicates the way the second instruction is obtained by fixed-length compression or splitting. See Figure 7 , Figure 7 which includes 8 first instructions to be processed. Among them, the number after inst is used to distinguish different first instructions, and the English in the parentheses is the instruction type of the first instruction, that is, mov means the first instruction is a mov instruction, add means the first instruction is an add instruction, and jmp means the first instruction is a jmp instruction. Figure 7 The 0 and 1 after each first instruction in Figure 7 are used as the boundary bits of the instruction bundle. When the boundary bit is equal to 0, it is determined that the instruction is not the last instruction in the instruction bundle. When the boundary bit is equal to 1, it is determined that the instruction is the last instruction in the instruction bundle, that is,

[0129] In Figure 7 , inst0, inst1, inst2, and inst3 belong to the same instruction bundle, inst4 and inst5 belong to the same instruction bundle, and inst6 and inst7 belong to the same instruction bundle. Figure 7 The second instructions in

[0130] Figure 7 Among them, the method for obtaining the second instruction of the mov instruction is fixed-length compression, and the compression flag bit before inst0_C is assigned the first value 1, while the method for obtaining the second instruction of the add instruction is splitting, and the compression flag bit before inst2(add) is assigned the second value 0. Figure 7 Among them, the compression module splits the add instruction. Therefore, there are two second instructions corresponding to the add instruction. Figure 7 Among them, C in the second instructions of the mov instruction and the jmp instruction indicates one-time compression.

[0131] After obtaining the second instruction by performing fixed-length processing on the first instruction, a two-layer compression method can be performed on the second instruction to reduce the size of the second instruction. Since the reduction method corresponding to the two-layer compression is executed on the read path from the storage module to the cache module, and the instruction reading rate requirement of the cache module is low, the reduction rate of the two-layer compression method adopted by the compression module can be lower than that of the one-layer compression method. The two-layer compression method includes, but is not limited to, variable-length compression, where the length of the compressed instruction is not fixed.

[0132] Exemplarily, the compression module can perform sequential variable-length compression on each second instruction according to the instruction position of each second instruction, or perform variable-length compression on each second instruction randomly, or perform variable-length compression on each second instruction from high to low or from low to high according to the occurrence frequency of each second instruction. See Figure 8 After performing fixed-length processing on multiple first instructions according to the instruction characteristics, select to perform fixed-length compression on some first instructions, compress them into the original half-width, and add an instruction compression flag to obtain the second instruction. For the uncompressed full-width instructions, that is, the first instructions, the first instructions are split into two segments according to the half-width to obtain two second instructions. For the obtained second instructions, the compression module will count the second instructions with high frequencies, that is, the occurrence frequency is higher than the frequency threshold, and preferentially perform variable-length compression on the second instructions with high frequencies.

[0133] Optionally, the process of variable-length compression includes, but is not limited to: obtaining the occurrence frequency of each field included in the second instruction; obtaining a third instruction according to the occurrence frequency of each field, the third instruction includes the encoding of each field, the encoding of each field is determined based on the occurrence frequency of each field, and the length of the encoding of each field is inversely proportional to the occurrence frequency of each field.

[0134] Exemplarily, the occurrence frequency of a field may refer to the occurrence frequency of the field in all instructions. The all instructions refer to all instructions to be stored in the memory structure, and the all instructions include the second instruction. In a possible case, different instructions include the same field. The same field may refer to a field with exactly the same value, or a field with the same function, or a field with similar functions. For any field included in the second instruction, the compression module counts the first quantity of any field and the second quantity of the fields included in the all instructions, and divides the first quantity by the second quantity. The obtained quotient is the occurrence frequency of any field.

[0135] After determining the occurrence frequency of each field, the compression module may perform encoding according to the occurrence frequency of each field. In a possible case, the compression module may construct a coding dictionary corresponding to the second instruction according to the occurrence frequency of each field. The coding dictionary includes each field and the occurrence frequency of each field; determine the encoding of each field according to the coding dictionary. The compression module may use the occurrence frequency of each field as the index of the field, store the field and the index together in the coding dictionary, or determine the storage position of each field in the compression dictionary according to the occurrence frequency of each field. Taking the compression dictionary as a multi-way tree as an example, the field with the highest occurrence frequency is used as the root node, and then starting from the highest to the lowest occurrence frequency of each field, the leaf nodes are constructed from bottom to top.

[0136] Regardless of the manner in which the compression module constructs the coding dictionary, it can be as Figure 8 shown, perform variable-length compression on the second instruction based on the constructed coding dictionary to obtain the third instruction. Optionally, the compression module determines the occurrence frequency of each field according to the coding dictionary, and determines the encoding corresponding to the field according to the occurrence frequency. Among them, the higher the occurrence frequency of the field, the shorter the length of the encoding. Taking the field including field A, field B, and field C as an example, the occurrence frequency of field A is higher than that of field B, and the occurrence frequency of field B is higher than that of field C. In this case, the encoding of field A is 0, the encoding of field B is 1, and the encoding of field C is 01. In a possible implementation manner, the above variable-length compression may be referred to as Huffman compression.

[0137] By determining the encoding corresponding to each field according to the occurrence frequency, the fields with higher occurrence frequencies have a larger quantity in the all instructions. Therefore, the fields with a larger quantity are encoded with a shorter length, and then the encodings corresponding to multiple fields are concatenated into the third instruction, effectively reducing the overall length of the all instructions. In addition, the second instruction may include one or more fields, and the embodiments of the present application do not limit this. When the second instruction includes one field, the above process of encoding according to the occurrence frequency of the field can be understood as performing overall instruction encoding on the second instruction according to the occurrence frequency of the second instruction in the all instructions, that is, one second instruction corresponds to one encoding, and this encoding is the third instruction.

[0138] In a possible implementation, the third instruction includes an encoded index, which is used to find the field corresponding to the encoding included in the third instruction during the decompression of the third instruction. In the case where the encoding uses a compression dictionary, this encoded index can be referred to as information for looking up a dictionary index. Continuing to refer to Figure 7 , Figure 7 in, the encoded index is the information carried in a tag, and the tag can also be referred to as a fixed-length encoding compression header (code compress tag) in some cases.

[0139] In a possible case, after compressing the first instruction, the compression module can store the compressed first instruction in a memory structure so that the compressed first instruction achieves a programmable effect, facilitating the parsing by a subsequent decoding module and the calculation by a parallel computing module, thereby ensuring the smooth execution of the application program corresponding to the first instruction. Exemplarily, the compression module obtains the instruction length of the compressed first instruction; determines a storage unit in the memory structure for storing the compressed first instruction according to the instruction length, and stores the compressed first instruction in the determined storage unit.

[0140] Optionally, continuing to take the compressed first instruction as the third instruction in the above embodiment as an example, on the basis of including an encoded index, the third instruction further includes a length field of the third instruction. The encoding module can determine the instruction length of the third instruction by parsing the length field of the third instruction, and then store the third instruction in a storage unit whose free memory size in the storage module is not less than the instruction length. In a possible case, in the case where the third instruction is an instruction obtained by compressing the first instruction included in an instruction bundle, the compression module will store multiple third instructions belonging to the same instruction bundle in the same row of storage units. Optionally, the compression module can determine multiple third instructions belonging to the same instruction bundle according to the boundary bits of each third instruction, or can also determine the third instructions with the same instruction bundle identifier as the third instructions belonging to the same instruction bundle according to the instruction bundle identifier carried by each third instruction. Since the subsequent parsing of the instructions in the storage module is based on a row of storage units as a unit, by storing multiple third instructions belonging to the same instruction bundle in the same row, it is ensured that the third instructions belonging to the same instruction bundle can be processed in parallel at the same time. Continuing to refer to Figure 7 , Figure 7 in, the compression module stores multiple third instructions obtained by variable-length compression in the same row of storage units. And Figure 7 in, the uncompressed first instruction occupies two rows of storage units. By compressing the first instruction, the storage space occupied by the first instruction is effectively reduced, thereby reducing the storage overhead.

[0141] In summary, for the instruction processing method provided in the embodiments of the present application, before storing the first instruction, the first instruction is compressed to reduce its size. The same-capacity memory structure can store a larger number of compressed first instructions than uncompressed first instructions, which improves the instruction storage capacity of the memory structure and reduces the storage overhead of the memory structure. Moreover, more instructions are stored in the same row of storage units. Subsequently, during the process of reading instructions row by row, the number of instruction reads is small and the read overhead is low. Since the compression of the first instruction is based on the compression level of the memory, and the compression level of the memory is determined according to the demand rate for reading the first instruction from the memory structure, the process of restoring the compressed first instruction meets the demand rate of the memory structure. Even if the compressed first instruction needs to be restored during the process of reading the compressed first instruction, it does not affect the normal operation of the memory in the memory structure and ensures the smooth operation of the application program running based on the first instruction.

[0142] The embodiments of the present application provide an instruction processing method, which can be applied to the Figure 1 or Figure 2 illustrated implementation environment. Taking the method being executed by the restoration module as an example, the flowchart of the method is as Figure 9 shown, including S901 - S902.

[0143] S901, Obtain the compressed first instruction. The compression of the first instruction is implemented based on a compression level, and the compression level is determined based on the memory structure and the demand rate for reading the first instruction. The memory structure is used to store the compressed first instruction.

[0144] Exemplarily, the restoration module obtains the instruction identifier to be processed and determines the compressed first instruction to be processed according to the instruction identifier. The restoration module can determine the instruction identifier that is currently allowed to be calculated according to the program loading situation inside the device, or can also receive the instruction identifier input manually. Among them, the instruction identifier can be the identifier of the instruction bundle to which the compressed first instruction belongs, or can be the location identifier of the storage unit where the instruction is located, such as the identifier of the row storage unit, and the instruction identifier can also be other identifiers that can distinguish different instructions.

[0145] Regardless of the manner in which the restoration module obtains the instruction identifier to be processed and determines the compressed first instruction to be processed according to the instruction identifier, the restoration module can extract the compressed first instruction from the memory structure. In a possible implementation manner, the restoration module can extract at least one instruction stored in a row of storage units of the storage module; separate each instruction according to the instruction length of each instruction in the at least one instruction to obtain at least one instruction, and the at least one instruction includes the compressed first instruction.

[0146] At least one instruction stored in a row of storage units is 0100001110101, where 0 is the compression flag bit, the beginning of the first instruction is 1, and since the instruction length of the first instruction is 3, the first instruction is 100. The 0 after 100 is the boundary bit, from which the compression flag bit of the second instruction is determined to be 0, and then the second instruction is determined according to the instruction length of the second instruction, thus realizing the separation of multiple instructions.

[0147] Figure 10 This is a schematic diagram of the process of instruction processing provided by an embodiment of the present application. Refer to Figure 10 , multiple compressed instructions are stored in the storage module in units of instruction words. Figure 10 One instruction word in it includes eight half-width instructions (halfinst), because only eight half-width instructions can be stored in a row of storage units in the cache module. Figure 10 The reason why the lengths of the instruction words corresponding to the eight half-width instructions in it are different is that the lengths of the instructions obtained by variable-length compression of the half-width instructions included in different instruction words are different.

[0148] Figure 10 Taking the read instruction word IW_C4 as an example for illustration, the restoration module locates the instruction word IW_C4 through the program counter (PC), extracts the located instruction word IW_C4, and separates each instruction according to the instruction length of each instruction included in the instruction word IW_C4. For Figure 7 The instruction length of the instruction shown is the information included in the tag of the instruction. The restoration module can determine the instruction length of each instruction through tag parsing, realizing the separation of multiple instructions. For example Figure 10 a tag parser is adopted in it. Since the separation of multiple instructions is executed sequentially, the process of tag parsing can be called serial parsing in some cases. After the restoration module separates multiple instructions, it can determine the first compressed instruction to be processed from the multiple instructions. Continuing with Figure 10 as an example, Figure 10 Among the eight instructions separated in it, the first five instructions are the instructions included in instruction bundle 1. Since the instruction identifier indicates that the currently to-be-processed instruction bundle is instruction bundle 1, the restoration module thus determines that the first five instructions are the first compressed instruction to be processed. Optionally, the first instruction includes an instruction for forwarding the application program.

[0149] In a possible implementation manner, the restoration module can also receive the first compressed instruction sent by the memory structure to obtain the first compressed instruction to be restored. Continuing with Figure 4Taking the memory structure shown with a storage module as an example, the processor core sends an instruction read request to the storage module. The storage module determines, based on the instruction read request, that the instruction to be read is the first compressed instruction, and reads the first compressed instruction. Since the instruction format that the processor core can process is an uncompressed instruction format, before returning the instruction to the processor core, the first compressed instruction also needs to be restored to the uncompressed first instruction. Based on this, the storage module sends the extracted first compressed instruction to the restoration module, and the restoration module thereby obtains the first compressed instruction.

[0150] S902, restore the first compressed instruction.

[0151] Exemplarily, the restoration module obtains the compression method corresponding to the first compressed instruction, and uses the restoration method corresponding to the compression method to restore the first compressed instruction. Among them, the compression method corresponding to the first instruction matches the compression level of the memory storing the first instruction. The restoration module can determine the compression method used by the compression module for the first instruction based on the communication connection with the compression module. For the case where the first compressed instruction is obtained by compressing the first instruction using multiple compression methods, the restoration module can determine the corresponding restoration order for each memory according to the reading order of each memory, and sequentially execute the restoration method corresponding to the compression method on the first compressed instruction according to the restoration order.

[0152] Regarding Figure 3 In the embodiment shown, the memory structure includes a storage module and a cache module. The compression level of the storage module is two - layer compression, and the compression level of the cache module is one - layer compression. The restoration rate of one - layer compression is higher than that of two - layer compression. For the case where the first compressed instruction includes a third instruction, the process of restoring the first compressed instruction includes but is not limited to: restoring the third instruction using the restoration method corresponding to the two - layer compression method to obtain a second instruction; restoring the second instruction using the restoration method corresponding to the one - layer compression method to obtain the first instruction. The compression rate of the two - layer compression method is greater than the compression rate of the one - layer compression method.

[0153] Exemplarily, when the two - layer compression method is variable - length compression, the corresponding restoration method one for variable - length compression includes: the restoration module parses the coding index included in the third instruction; determines each field corresponding to each coding included in the third instruction according to the coding index, and determines the second instruction according to each field corresponding to each coding. The length of the coding of each field is inversely proportional to the occurrence frequency of each field.

[0154] In a possible implementation, the third instruction includes an encoded index. For example, the third instruction includes a tag field, and the restoration module parses the tag field to determine the encoded index carried in the tag field. Optionally, the encoded index can directly indicate the correspondence between the encoding and the field. In the case where the compression module performs encoding based on an encoding dictionary, the encoded index can indicate the encoding dictionary used in the process of encoding to obtain the third instruction, and the restoration module determines the correspondence between the encoding and the field according to the encoding dictionary.

[0155] In a possible case, since there are different situations for the second instruction obtained by compressing the first instruction by the compression module, which are respectively: Case 1 of the second instruction obtained by performing fixed-length compression on the first instruction, Case 2 of the high-order part of the second instruction obtained by splitting the first instruction, and Case 3 of the low-order part of the second instruction obtained by splitting the first instruction. And the corresponding encoding dictionaries for encoding different situations of the second instruction are stored in different locations. In this case, the restoration module first determines the situation corresponding to the second instruction corresponding to the third instruction according to the compression flag bit carried in the third instruction, and sends the encoded index to the storage location of the encoding dictionary corresponding to the determined situation to obtain the encoding dictionary.

[0156] Exemplarily, the restoration module parses the compression flag bit, determines the storage location of the encoding dictionary of the third instruction according to the compression flag bit and the information carried in the third instruction, accesses the determined storage location, and obtains the encoding dictionary of the third instruction according to the encoded index. When the value of the compression flag bit is the first value, it is determined that the second instruction corresponding to the third instruction is Case 1, and the encoding dictionary for decompressing the third instruction is determined from multiple fixed-length compression encoding dictionaries according to the encoded index of the third instruction. When the value of the compression flag bit is the second value, it is determined whether the second instruction corresponding to the third instruction belongs to the high-order part or the low-order part according to the information carried in the second instruction. When the second instruction corresponding to the third instruction belongs to the high-order part, it is determined that the second instruction corresponding to the third instruction is Case 2, and the encoding dictionary for decompressing the third instruction is determined from the high-width encoding dictionary according to the encoded index. When the second instruction corresponding to the third instruction belongs to the low-order part, it is determined that the second instruction corresponding to the third instruction is Case 3, and the encoding dictionary for decompressing the third instruction is determined from the low-width encoding dictionary according to the encoded index.

[0157] Figure 11 This is a process for restoring the third instruction provided by the embodiments of the present application. Figure 11The process of decompressing the third instruction included in the instruction word to obtain the second instruction is shown. Among them, the instruction word includes 9 third instructions. The restoration module determines the fixed-length processing corresponding to each third instruction according to the compression flag bit of each third instruction. When the fixed-length processing corresponding to the third instruction is fixed-length compression, the encoded index carried in the tag is parsed, and the encoded index is sent to the storage space for storing the encoding dictionary for fixed-length compression, and the encoding dictionary for decompressing the third instruction found and returned according to the encoded index is received. When the fixed-length processing corresponding to the third instruction is splitting, for the third instruction obtained by compressing the second instruction with a high bit width, the encoded index is sent to the storage space for storing the encoding dictionary for the high bit width, and the encoding dictionary for decompressing the third instruction found and returned according to the encoded index is received. For the third instruction obtained by compressing the second instruction with a low bit width, the encoded index is sent to the storage space for storing the encoding dictionary for the low bit width, and the encoding dictionary for decompressing the third instruction found and returned according to the encoded index is received.

[0158] Regardless of the method by which the restoration module obtains the encoding dictionary for decompressing the third instruction, the corresponding relationship between the encoding and the field can be obtained according to the encoding dictionary. Taking the encoding dictionary as an example that constructs the storage location of each field according to the occurrence frequency of each field, the restoration module determines the occurrence frequency of each field according to the storage location of each field in the encoding dictionary, and determines the corresponding relationship between each field and the encoding according to the corresponding relationship between the occurrence frequency of each field and the encoding. After that, the restoration module looks up the fields corresponding to each encoding included in the third instruction according to the corresponding relationship between the field and the encoding, and splices the corresponding fields to obtain the second instruction.

[0159] Exemplarily, after the restoration module restores the third instruction to obtain the second instruction, the second instruction can be sent to the cache module for caching. Optionally, since the restoration module takes the instruction word as the dimension during the process of restoring the third instruction, and the instruction word refers to at least one instruction stored in a row of cache units of the cache module, the multiple restored second instructions can be stored in the same row of the cache module. For example Figure 10 as shown Figure 10 in, the instruction word IW_4 including multiple second instructions obtained by decompression is stored in a row in the cache module.

[0160] After the restoration module restores the third instruction to obtain the second instruction, the second instruction can also be restored. For example, the second instruction is extracted from the cache module, and the restoration method corresponding to the compression method of one-layer compression is used to restore the second instruction. Exemplarily, when the compression method of one-layer compression is fixed-length processing, the corresponding restoration method 2 for fixed-length processing includes: determining the method for obtaining the second instruction from fixed-length compression or splitting; performing the restoration operation corresponding to the determined method on the second instruction.

[0161] In a possible implementation, for a second instruction including a compression flag bit, when the compression flag bit indicates that the second instruction is obtained by fixed-length compression or splitting, the restoration module can parse the compression flag bit included in the second instruction, thereby determining the method for obtaining the second instruction from fixed-length compression and splitting according to the compression flag bit, and then selecting a restoration operation for restoring the second instruction.

[0162] Exemplarily, the restoration module reads the compression flag bit. When the compression flag bit is a first value, it is determined that the method for obtaining the second instruction is fixed-length compression. When the compression flag bit is a second value, it is determined that the method for obtaining the second instruction is splitting. Figure 12 A schematic diagram for restoring a second instruction provided by an embodiment of this application Figure 12 One instruction word includes eight second instructions. The restoration module parses the compression flag bit before inst0_C. Since the value of the compression flag bit is the first value 1, it is determined that the fixed-length processing corresponding to the second instruction is fixed-length compression. Parse the compression flag bit before inst2. The value of this compression flag bit is the second value 0, and it is determined that the fixed-length processing corresponding to the second instruction is splitting.

[0163] After the restoration module determines the fixed-length processing corresponding to the second instruction, it can perform the fixed-length restoration corresponding to the fixed-length processing. In a possible case, the restoration methods corresponding to the compression methods of one-layer compression include decompression corresponding to fixed-length compression or splicing corresponding to splitting. Then, performing restoration method two on the second instruction includes but is not limited to the following two restoration operations.

[0164] Restoration operation one: When the second instruction is obtained by fixed-length compression, perform decompression corresponding to fixed-length compression on the second instruction to obtain a first instruction. For the second instruction obtained by fixed-length compression, decompression corresponding to fixed-length compression can be performed on the second instruction. Continuing with Figure 6 the second instruction shown as an example, determine the instruction structure corresponding to the second instruction, restore the invalid fields corresponding to the second instruction according to the instruction structure, splice the invalid fields and the valid fields included in the second instruction to obtain a first instruction. Among them, the restoration module can determine the instruction structure according to the instruction type of the second instruction. For example, based on the second instruction belonging to a mov instruction, it is determined that the non-blank fields of the second instruction further include an ineffective cond field. The restoration module determines the information carried by the ineffective cond field according to the valid fields carried by the second instruction, and splices the ineffective cond field, other blank fields, and valid fields to obtain Figure 6 the first instruction shown.

[0165] Restore operation two. In the case where the second instruction is obtained by splitting, the multiple second instructions obtained by splitting the first instruction are spliced to obtain the first instruction, and the bit widths of the respective second instructions among the multiple second instructions are the same. For the split second instruction, the restoration module determines the multiple second instructions obtained by splitting the same first instruction, and splices the multiple second instructions to obtain the first instruction. Optionally, the restoration module may, according to the storage location of the second instruction, for example, the multiple second instructions obtained by splitting the same first instruction are stored adjacent to each other, and the restoration module thereby determines that the second instructions stored adjacent to each other and having the compression flag bits all being the second value are the second instructions obtained by splitting the same first instruction. Alternatively, the restoration module may also determine the second instructions belonging to the same first instruction according to the information carried by the second instruction.

[0166] In a possible implementation manner, after restoring the first instruction, the restoration module further sends the first instruction to the decoding module, and the decoding module parses the first instruction. Since the decoding module processes instructions in units of instruction bundles during the process of parsing instructions, the process of the restoration module sending the first instruction includes but is not limited to: determining the instruction bundle corresponding to the first instruction, the instruction bundle includes at least one instruction, the compression results of the at least one instruction are stored in the same row of storage units of the memory structure, the compression result of any one of the compression results of the at least one instruction is the compressed first instruction, and the at least one instruction is an instruction to be executed in parallel; sending the at least one instruction included in the instruction bundle to the decoding module, and the decoding module is used to parse the at least one instruction.

[0167] Figure 13 FIG. is a schematic diagram of an instruction processing procedure provided by an embodiment of the present application. Figure 13 In, after performing fixed-length restoration on multiple second instructions to obtain multiple first instructions, the first instructions included in the instruction bundle are extracted from the multiple first instructions. For example, according to the boundary bit included in the first instruction, when the boundary bit is 0, it is determined that the first instruction is not the last instruction included in the instruction bundle, and continue to search backward until a first instruction with a boundary bit of 1 is read, and the first instruction and the previous first instructions are determined to be the first instructions included in the same instruction bundle. Figure 13 In, the four first instructions included in the extracted instruction bundle are respectively inst0, inst1, inst2, and inst3, and the decoding module receives the multiple first instructions included in the instruction bundle.

[0168] Optionally, the restoration module may first perform fixed-length restoration on the second instruction as shown in Figure 13 , and then determine the instruction bundle to which the restored first instruction belongs, or may first determine the instruction bundles to which the respective second instructions belong, and then perform fixed-length restoration on the second instructions included in each instruction bundle to obtain the first instructions included in each instruction bundle. Take Figure 14Taking the multiple second instructions shown in the figure as an example, the restoration module extracts instruction bundle 1 including inst0, inst1, inst2, and inst3, and instruction bundle 2 including inst4 and inst5 according to the boundary bits of the multiple second instructions. And instruction bundle decompression is adopted to perform fixed-length restoration on each second instruction included in the instruction bundle to obtain multiple first instructions. The multiple first instructions included in one instruction bundle are synchronously sent to the decoding module. In addition, the embodiments of the present application do not limit the manner of determining the instructions included in the instruction bundle, which may be based on boundary bits in the above embodiments, or other manners may be adopted, such as according to the instruction bundle identifier, etc.

[0169] In summary, for the instruction processing method provided by the embodiments of the present application, the storage space occupied by the compressed first instructions is smaller than the storage space occupied by the first instructions. A memory structure with the same memory size can store more compressed first instructions, and the instruction storage quantity of the memory structure is high. Since there are more instructions in the same row stored in the memory structure, when reading the instructions stored in the memory structure in units of rows, the efficiency of reading instructions is high, and the instruction reading power consumption is saved.

[0170] For Figure 15 As shown, in the case where multiple RTC cores in the RTC processor architecture share a cache module, since the speed of each RTC core reading the instructions stored in the cache module is fast, for example Figure 15 In the upper figure of [reference], the uncompressed first instructions are stored in the cache module. Multiple first instructions occupy four rows of cache units, and the RTC core needs to read four times to fetch multiple first instructions. Figure 15 In the lower figure of [reference], the compressed first instructions are stored in the cache module. The multiple compressed first instructions occupy two rows of cache units, and the RTC core can fetch multiple first instructions by reading twice. The reading rate of the RTC core is increased, and the conflict probability when the RTC core accesses the cache module simultaneously is small. More RTC cores can share the cache module, saving the number of more cache modules. In addition, the restoration method for restoring the compressed first instructions meets the processing requirements of the reading modules of each memory in the memory structure. Even if the compressed first instructions are decompressed, it will not affect the normal operation of the reading modules, ensuring the processing performance of the reading modules and the normal operation of the services corresponding to the first instructions.

[0171] The above introduces the instruction processing method of the embodiments of the present application. Corresponding to the above method, the embodiments of the present application also provide an instruction processing device. Figure 16 FIG. [reference] is a schematic structural diagram of an instruction processing device provided by an embodiment of the present application. Based on Figure 16 the following multiple modules shown in the figure, the Figure 16 instruction processing device shown in the figure can execute the aboveFigure 3 All or part of the operations shown. It should be understood that the device may include more additional modules than those shown or omit some of the modules shown, and the embodiments of the present application do not limit this. As Figure 16 shown, the device includes:

[0172] An acquisition module 1601, configured to acquire a first instruction to be processed;

[0173] A determination module 1602, configured to determine a compression level of a memory in the memory structure according to the memory structure and the required rate for reading the first instruction, where the memory structure is used to store the compressed first instruction;

[0174] A compression module 1603, configured to compress the first instruction by using the compression level.

[0175] In a possible implementation manner, the acquisition module 1601 is further configured to acquire at least one of path attributes of read paths of each memory included in the memory structure or the read efficiency of the memory structure, where the read path of the memory is a path connected between the memory and a read module, and the read module is configured to read an instruction stored in the memory and process the read instruction; the determination module 1602 is further configured to determine the required rate for reading the first instruction according to at least one of the path attributes or the read efficiency.

[0176] In a possible implementation manner, the determination module 1602 is configured to determine the read rate of each memory included in the memory structure; determine the decompression rate of each memory according to the required rate for reading the first instruction and the read rate of each memory, where the decompression rate of the memory is the rate of decompressing the instruction stored in the memory on the read path of the memory; and determine the compression level of each memory according to the decompression rate of each memory, where the compression rate corresponding to the compression level of the memory matches the decompression rate corresponding to the memory.

[0177] In a possible implementation manner, the memory structure includes a storage module and a cache module, the compression level of the storage module is two - layer compression, the compression level of the cache module is one - layer compression, and the decompression rate of one - layer compression is higher than that of two - layer compression; the compression module 1603 is configured to compress the first instruction by using the one - layer compression method to obtain a second instruction; and compress the second instruction by using the two - layer compression method to obtain a third instruction, and the compression rate of the two - layer compression method is greater than the compression rate of the one - layer compression method.

[0178] In a possible implementation, the ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. The obtaining module 1601 is further configured to obtain the service feature of the first instruction, where the service feature indicates the operation quality requirement of the service running based on the first instruction. The determining module 1602 is further configured to determine the compression ratio according to the service feature of the first instruction.

[0179] In a possible implementation, the compression module 1603 is configured to obtain the instruction feature of the first instruction. When it is determined according to the instruction feature that fixed-length compression is supported, the first instruction is compressed in a fixed-length compression manner to obtain the second instruction. Or, when it is determined according to the instruction feature that fixed-length compression is not supported, the first instruction is split into multiple second instructions, and the bit widths of the respective second instructions among the multiple second instructions are the same.

[0180] In a possible implementation, the instruction feature includes at least one of the instruction type, usage frequency, or field utilization rate of the first instruction.

[0181] In a possible implementation, the compression module 1603 is configured to determine the valid field of the first instruction to obtain the second instruction including the valid field, where the valid field is the field used to run the first instruction.

[0182] In a possible implementation, the second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by fixed-length compression or splitting.

[0183] In a possible implementation, the compression module 1603 is configured to obtain the occurrence frequency of each field included in the second instruction; obtain the third instruction according to the occurrence frequency of each field, where the third instruction includes the encoding of each field, the encoding of each field is determined based on the occurrence frequency of each field, and the length of the encoding of each field is inversely proportional to the occurrence frequency of each field.

[0184] In a possible implementation, the determining module 1602 is further configured to construct a coding dictionary corresponding to the second instruction according to the occurrence frequency of each field, where the coding dictionary includes each field and the occurrence frequency of each field; determine the encoding of each field according to the coding dictionary.

[0185] In a possible implementation, the third instruction includes a coding index, and the coding index is used to find the field corresponding to the encoding included in the third instruction during the decompression of the third instruction.

[0186] In a possible implementation, the apparatus further includes: a storage module, configured to obtain the instruction length of the compressed first instruction; determine the storage unit in the memory structure for storing the compressed first instruction according to the instruction length, and store the compressed first instruction in the determined storage unit.

[0187] In a possible implementation, the first instruction includes an instruction for forwarding an application.

[0188] In a possible implementation, an obtaining module 1601 is configured to obtain at least one instruction included in a bundle of instructions. Any one of the at least one instruction is a first instruction to be processed, and the at least one instruction is an instruction to be executed in parallel.

[0189] The above device compresses the first instruction to reduce the storage space occupied by the first instruction. The number of compressed first instructions that can be stored in a memory structure with the same capacity is greater than the number of uncompressed first instructions, improving the instruction storage capacity of the memory structure and reducing the storage overhead of the memory structure. Since the compression of the first instruction is based on the compression level of the memory, and the compression level is determined based on the demand rate, the process of restoring the compressed first instruction meets the demand rate of the memory structure, and the process of restoring the compressed first instruction does not affect the normal operation of the memory in the memory structure.

[0190] The embodiment of the present application further provides another instruction processing device. Figure 17 It is a schematic structural diagram of an instruction processing device provided by the embodiment of the present application. Based on Figure 17 the following multiple modules shown, the Figure 17 instruction processing device shown can perform all or part of the operations shown above Figure 9 shown. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown. The embodiment of the present application does not limit this. As Figure 17 shown, the device includes:

[0191] An obtaining module 1701 is configured to obtain a compressed first instruction. The compression of the first instruction is implemented based on a compression level, and the compression level is determined based on a memory structure and the demand rate for reading the first instruction. The memory structure is used to store the compressed first instruction;

[0192] A restoring module 1702 is configured to restore the compressed first instruction.

[0193] In a possible implementation, the memory structure includes a storage module and a cache module. The compression level of the storage module is two - layer compression, and the compression level of the cache module is one - layer compression. The restoration rate of one - layer compression is higher than that of two - layer compression. The compressed first instruction includes a third instruction. The restoring module 1702 is configured to restore the third instruction using the restoration method corresponding to the two - layer compression method to obtain a second instruction; and restore the second instruction using the restoration method corresponding to the one - layer compression method to obtain a first instruction. The compression rate of the two - layer compression method is greater than that of the one - layer compression method.

[0194] In a possible implementation, the third instruction includes an encoded index, and a restoration module 1702 is configured to parse the encoded index included in the third instruction; determine each field corresponding to each encoding included in the third instruction according to the encoded index, and determine the second instruction according to each field corresponding to each encoding, where the length of the encoding of each field is inversely proportional to the occurrence frequency of each field.

[0195] In a possible implementation, the restoration method corresponding to the compression method of one-layer compression includes decompression corresponding to fixed-length compression or splicing corresponding to splitting. The restoration module 1702 is configured to, when the second instruction is obtained by means of fixed-length compression, perform decompression corresponding to fixed-length compression on the second instruction to obtain the first instruction; or, when the second instruction is obtained by means of splitting, splice a plurality of second instructions obtained by splitting the first instruction to obtain the first instruction, and the bit widths of each of the plurality of second instructions are the same.

[0196] In a possible implementation, the second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by means of fixed-length compression or splitting. The restoration module 1702 is further configured to parse the compression flag bit included in the second instruction, and determine the method for obtaining the second instruction from fixed-length compression and splitting according to the compression flag bit.

[0197] In a possible implementation, an acquisition module 1701 is configured to extract at least one instruction stored in a row of storage units of a memory structure; separate each instruction according to the instruction length of each instruction in the at least one instruction to obtain at least one instruction, and the at least one instruction includes a compressed first instruction.

[0198] In a possible implementation, the apparatus further includes: a sending module, configured to determine an instruction bundle corresponding to the first instruction, where the instruction bundle includes at least one instruction, the compression results of the at least one instruction are stored in the same row of storage units of the memory structure, the compression result of any one of the compression results of the at least one instruction is the compressed first instruction, and the at least one instruction is an instruction for parallel execution; send the at least one instruction included in the instruction bundle to a decoding module, and the decoding module is configured to parse the at least one instruction.

[0199] In a possible implementation, the first instruction includes an instruction for forwarding an application program.

[0200] The storage space occupied by the compressed first instruction is smaller than the storage space occupied by the first instruction. A memory structure with the same memory size can store more compressed first instructions, improving the instruction storage quantity of the memory structure. For the compressed first instruction, restoration can be performed to ensure the normal implementation of subsequent operations based on the first instruction.

[0201] It should be understood that the above Figure 16 or Figure 17 When the provided device realizes its functions, only the division of the above-mentioned functional modules is used for illustration. In actual applications, the above functions can be assigned to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device provided in the above embodiment and the method embodiment belong to the same concept. For the specific implementation process, please refer to the method embodiment, which will not be elaborated here.

[0202] See Figure 18 , Figure 18 which shows a schematic structural diagram of a network device 1800 provided by an exemplary embodiment of the present application. Figure 18 The shown network device 1800 is used to execute the operations involved in the above Figure 3 or Figure 9 shown instruction processing method. The network device 1800 is, for example, a switch, a router, etc. The network device 1800 can be implemented by a general bus architecture.

[0203] As Figure 18 shown, the network device 1800 includes at least one processor 1801, a memory 1803, and at least one communication interface 1804.

[0204] The processor 1801 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solutions of this application. For example, the processor 1801 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in connection with the disclosed content of the embodiments of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.

[0205] Optionally, the network device 1800 further includes a bus. The bus is used to transfer information between the components of the network device 1800. The bus can be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 18 only a thick line is shown in [description], but it does not mean that there is only one bus or one type of bus.

[0206] The memory 1803 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, such as a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, such as an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM), or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1803 is, for example, independent and connected to the processor 1801 via a bus. The memory 1803 can also be integrated with the processor 1801.

[0207] The communication interface 1804 uses any device such as a transceiver to communicate with other devices or communication networks, and the communication network can be an Ethernet, a radio access network (RAN), or a wireless local area network (WLAN), etc. The communication interface 1804 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 1804 can be an Ethernet interface, a fast ethernet (FE) interface, a gigabit ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In the embodiments of the present application, the communication interface 1804 can be used for the network device 1800 to communicate with other devices.

[0208] In a specific implementation, as an embodiment, the processor 1801 can include one or more CPUs, such as Figure 18 the CPU0 and CPU1 shown in. Each of these processors can be a single-CPU processor or a multi-CPU processor. Here, the processor can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0209] In a specific implementation, as an example, the network device 1800 may include multiple processors, such as Figure 18 the processors 1801 and 1805 shown in. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0210] In a specific implementation, as an example, the network device 1800 may further include an output device and an input device. The output device communicates with the processor 1501 and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with the processor 1801 and can receive user input in various ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensing device, etc.

[0211] In some embodiments, the memory 1803 is used to store the program code 1810 for executing the solution of this application, and the processor 1801 can execute the program code 1810 stored in the memory 1803. That is, the network device 1800 can implement the instruction processing method provided by the method embodiment through the processor 1801 and the program code 1810 in the memory 1803. The program code 1810 may include one or more software modules. Optionally, the processor 1801 itself may also store the program code or instructions for executing the solution of this application.

[0212] In a specific embodiment, the network device 1800 of the embodiment of this application may correspond to the computing device in each of the above method embodiments.

[0213] Among them, Figure 3 or Figure 9Each step of the instruction processing method shown is completed by the integrated logic circuit of the hardware in the processor of the network device 1800 or the instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by the hardware processor, or executed and completed by the combination of the hardware and software modules in the processor. The software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0214] See Figure 19 , Figure 19 shows a schematic structural diagram of a network device 1900 provided by another exemplary embodiment of the present application, Figure 19 The network device 1900 shown is used to execute all or part of the operations involved in the above Figure 3 or Figure 9 instruction processing method shown. The network device 1900 is, for example, a switch, a router, etc., and the network device 1900 can be implemented by a general bus architecture.

[0215] As Figure 19 shown, the network device 1900 includes: a main control board 1910 and an interface board 1930.

[0216] The main control board is also called the main processing unit (MPU) or the route processor card. The main control board 1910 is used for the control and management of each component in the network device 1900, including routing calculation, device management, device maintenance, and protocol processing functions. The main control board 1910 includes: a central processor 1911 and a memory 1912.

[0217] The interface board 1930 is also called the line processing unit (LPU), line card, or service board. The interface board 1930 is used to provide various service interfaces and implement the forwarding of data packets. The service interfaces include, but are not limited to, Ethernet interfaces, POS (Packet over SONET / SDH) interfaces, etc. The Ethernet interface is, for example, a Flexible Ethernet Clients (FlexE Clients). The interface board 1930 includes: a central processor 1931, a network processor 1932, a forwarding table entry memory 1934, and a physical interface card (PIC) 1933.

[0218] The central processor 1931 on the interface board 1930 is used to control and manage the interface board 1930 and communicate with the central processor 1911 on the main control board 1910.

[0219] The network processor 1932 is used to implement the forwarding processing of packets. The form of the network processor 1932 can be a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 1932 is used to forward the received packets based on the forwarding table entries stored in the forwarding table entry memory 1934. If the destination address of the packet is the address of the network device 1900, the packet is sent to the CPU (such as the central processor 1631) for processing; if the destination address of the packet is not the address of the network device 1900, the next hop and the outgoing interface corresponding to the destination address are found from the forwarding table according to the destination address, and the packet is forwarded to the outgoing interface corresponding to the destination address. Among them, the processing of the upstream packets can include: the processing of the packet incoming interface, the forwarding table lookup; the processing of the downstream packets can include: the forwarding table lookup, etc. In some embodiments, the central processor can also perform the function of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that there is no need for a forwarding chip in the interface board.

[0220] The physical interface card 1933 is used to implement the docking function at the physical layer. The original traffic enters the interface board 1930 from here, and the processed packets are sent out from the physical interface card 1933. The physical interface card 1933 is also called a daughter card and can be installed on the interface board 1930. It is responsible for converting the optical and electrical signals into packets, performing a legality check on the packets, and then forwarding them to the network processor 1932 for processing. In some embodiments, the central processor 1931 can also perform the function of the network processor 1932, such as implementing software forwarding based on a general-purpose CPU, so that there is no need for the network processor 1932 in the physical interface card 1933.

[0221] Optionally, the network device 1900 includes multiple interface boards. For example, the network device 1900 further includes an interface board 1940, and the interface board 1940 includes: a central processor 1941, a network processor 1942, a forwarding table entry memory 1944, and a physical interface card 1943. The functions and implementation manners of the components in the interface board 1940 are the same as or similar to those in the interface board 1930, and will not be described in detail here.

[0222] Optionally, the network device 1900 further includes a switching fabric board 1920. The switching fabric board 1920 may also be referred to as a switch fabric unit (SFU). When the network device 1900 has multiple interface boards, the switching fabric board 1920 is used to complete data exchange between the interface boards. For example, the interface board 1930 and the interface board 1940 may communicate through the switching fabric board 1920.

[0223] The main control board 1910 is coupled to the interface board. For example. The main control board 1910, the interface board 1930, the interface board 1940, and the switching fabric board 1920 are interconnected through a system bus and a system backplane. In a possible implementation, an inter-process communication (IPC) channel is established between the main control board 1910 and the interface board 1930 and the interface board 1940, and the main control board 1910 communicates with the interface board 1930 and the interface board 1940 through the IPC channel.

[0224] Logically, the network device 1900 includes a control plane and a forwarding plane. The control plane includes the main control board 1910 and the central processing unit 1911. The forwarding plane includes various components that perform forwarding, such as a forwarding table entry memory 1934, a physical interface card 1933, and a network processor 1932. The control plane performs functions such as acting as a router, generating a forwarding table, processing signaling and protocol packets, and configuring and maintaining the state of the network device. The control plane sends the generated forwarding table to the forwarding plane. In the forwarding plane, the network processor 1932 looks up the packets received by the physical interface card 1933 based on the forwarding table sent by the control plane and forwards them. The forwarding table sent by the control plane may be stored in the forwarding table entry memory 1934. In some embodiments, the control plane and the forwarding plane may be completely separated and not on the same network device.

[0225] It should be noted that there may be one or more main control boards. When there are multiple main control boards, it may include an active main control board and a standby main control board. There may be one or more interface boards. The stronger the data processing capacity of the network device, the more interface boards are provided. There may also be one or more physical interface cards on the interface board. There may be no switching fabric board, or there may be one or more switching fabric boards. When there are multiple switching fabric boards, they can jointly implement load sharing and redundant backup. In a centralized forwarding architecture, the network device may not require a switching fabric board, and the interface board undertakes the processing function of the service data of the entire system. In a distributed forwarding architecture, the network device may have at least one switching fabric board, and data exchange between multiple interface boards is achieved through the switching fabric board, providing a large-capacity data exchange and processing capacity. Therefore, the data access and processing capacity of the network device in the distributed architecture is greater than that of the network device in the centralized architecture. Optionally, the form of the network device may also be a single board card, that is, there is no switching fabric board, and the functions of the interface board and the main control board are integrated on this single board card. At this time, the central processing unit on the interface board and the central processing unit on the main control board can be combined into a single central processing unit on this single board card to execute the functions after the superposition of the two. The data exchange and processing capacity of this form of network device is relatively low (for example, network devices such as low-end switches or routers). Which architecture to specifically adopt depends on the specific networking deployment scenario and is not limited here.

[0226] In a specific embodiment, the network device 1900 corresponds to the instruction processing device described above Figure 16 or Figure 17 shown. In some embodiments, Figure 16 the compression module 1602 in the instruction processing device shown is equivalent to the central processing unit 1911 or the network processor 1932 in the network device 1900.

[0227] An embodiment of the present application further provides a communication device, which includes: a transceiver, a memory, and a processor. Among them, the transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals. And when the processor executes the instructions stored in the memory, the processor is caused to execute an instruction processing method.

[0228] It should be understood that the above-mentioned processor may be a CPU, or may also be other general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It should be noted that the processor may be a processor that supports the advanced RISC machines (ARM) architecture.

[0229] Further, in an alternative embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0230] The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an EEPROM, or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0231] The embodiments of the present application also provide an instruction processing device, which includes a processor for loading and running at least one instruction so that the instruction processing device implements as Figure 3 or Figure 9 any one of the instruction processing methods shown. Optionally, the device further includes a memory coupled to the processor, and the memory is used to store at least one instruction.

[0232] The embodiments of the present application also provide a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor so that a computer implements as Figure 3 or Figure 9 any one of the instruction processing methods shown.

[0233] The embodiments of the present application also provide a computer program (product), which when executed by a computer, may cause the processor or the computer to execute the corresponding steps and / or processes in the above method embodiments.

[0234] An embodiment of the present application also provides a chip, which includes a processor for calling and running instructions stored in a memory, so that a communication device installed with the chip executes the instruction processing method as shown in Figure 3 or Figure 9 any one of them.

[0235] Another embodiment of the present application also provides a chip, including: an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The processor is configured to execute code in the memory. When the code is executed, the processor is configured to execute the instruction processing method as shown in Figure 3 or Figure 9 any one of them.

[0236] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk).

[0237] It should be noted that the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.), and signals involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant laws, regulations, and standards of relevant countries and regions. For example, the first instruction and the like involved in the present application are obtained under full authorization.

[0238] Those of ordinary skill in the art can realize that, in combination with the method steps and modules described in the embodiments disclosed herein, they can be implemented in software, hardware, firmware, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, the steps and components of the embodiments have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0239] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a disk, an optical disc, etc.

[0240] When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the methods of the embodiments of this application can be described in the context of machine-executable instructions, such as program modules executed in devices on a target real or virtual processor. Generally speaking, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., which perform specific tasks or implement specific abstract data structures. In the embodiments, the functions of the program modules can be merged or split among the described program modules. The machine-executable instructions for the program modules can be executed within local or distributed devices. In a distributed device, the program modules can be located in both local and remote storage media.

[0241] The computer program code for implementing the methods of the embodiments of this application can be written in one or more programming languages. These computer program codes can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable instruction processing devices, so that when the program code is executed by the computer or other programmable instruction processing devices, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0242] In the context of the embodiments of this application, the computer program code or related data can be carried by any suitable carrier, so that the device, apparatus, or processor can execute the various processes and operations described above. Examples of carriers include signals, computer-readable media, and so on.

[0243] Examples of signals can include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.

[0244] A machine-readable medium can be any tangible medium that contains or stores a program for or relating to an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. More specific examples of machine-readable storage media include electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0245] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0246] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or modules, and can also be electrical, mechanical, or other forms of connection.

[0247] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.

[0248] In addition, the functional modules in the various embodiments of the present application can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0249] When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of this application. The aforementioned storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0250] In this application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor are the quantity and execution order limited. It should also be understood that although the following description uses terms like first and second to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various described examples, the first image can be referred to as the second image, and similarly, the second image can be referred to as the first image. Both the first image and the second image can be images, and in some cases, they can be separate and different images.

[0251] It should also be understood that in various embodiments of this application, the magnitude of the sequence numbers of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0252] In this application, the meaning of the term "at least one" refers to one or more, and the meaning of the term "multiple" refers to two or more. For example, multiple second messages refer to two or more second messages. In this article, the terms "system" and "network" are often used interchangeably.

[0253] It should be understood that the terms used in the description of various described examples in this article are only for describing specific examples and are not intended to be restrictive. As used in the description of various described examples and the appended claims, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0254] It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and / or" is a correlative relationship describing associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0255] It should also be understood that the term "comprises" (also referred to as "includes", "including", "comprises", and / or "comprising") when used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups.

[0256] It should also be understood that the terms "if" and "when" can be interpreted to mean "when" ("when" or "upon") or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined..." or "if [the stated condition or event] is detected" can be interpreted to mean "when it is determined..." or "in response to determining..." or "when [the stated condition or event] is detected" or "in response to detecting [the stated condition or event]".

[0257] It should be understood that determining B based on A does not mean determining B solely based on A. B can also be determined based on A and / or other information.

[0258] It should also be understood that the "one embodiment", "an embodiment", "a possible implementation" mentioned throughout the specification means that the specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of this application. Therefore, the "in one embodiment" or "in an embodiment", "a possible implementation" that appear throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner.

Claims

1. An instruction processing method, characterized in that, The method includes: Obtaining a first instruction to be processed; Determining a compression level of a memory in the memory structure according to the memory structure and the required rate for reading the first instruction, where the memory structure is used to store the compressed first instruction; Compressing the first instruction using the compression level.

2. The method according to claim 1, wherein Before determining the compression level of the memory in the memory structure according to the memory structure and the required rate for reading the first instruction, it further includes: Obtaining at least one of the path attributes of the reading paths of each memory included in the memory structure or the reading efficiency of the memory structure, where the reading path of the memory is the path connected between the memory and the reading module, and the reading module is used to read the instructions stored in the memory and process the read instructions; Determining the required rate for reading the first instruction according to at least one of the path attributes or the reading efficiency.

3. The method according to claim 1 or 2, characterized in that, Determining the compression level of the memory in the memory structure according to the memory structure and the required rate for reading the first instruction includes: Determining the reading rates of each memory included in the memory structure; Determining the decompression rates of each memory according to the required rate for reading the first instruction and the reading rates of each memory, where the decompression rate of the memory is the rate of decompressing the instructions stored in the memory on the reading path of the memory; Determining the compression level of each memory according to the decompression rates of each memory, and the compression rate corresponding to the compression level of the memory matches the decompression rate corresponding to the memory.

4. The method according to any one of claims 1-3, characterized in that The memory structure includes a storage module and a cache module. The compression level of the storage module is two - layer compression, and the compression level of the cache module is one - layer compression. The decompression rate of the one - layer compression is higher than that of the two - layer compression; Compressing the first instruction using the compression level includes: Compressing the first instruction using the compression method of the one - layer compression to obtain a second instruction; Compressing the second instruction using the compression method of the two - layer compression to obtain a third instruction, and the compression rate of the compression method of the two - layer compression is greater than that of the compression method of the one - layer compression.

5. The method according to claim 4, characterized in that The ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. Before compressing the first instruction using the compression method of the one - layer compression to obtain a second instruction, it further includes: Obtaining the service characteristics of the first instruction, where the service characteristics indicate the running quality requirements of the service running based on the first instruction; Determining the compression ratio according to the service characteristics of the first instruction.

6. The method according to claim 4 or 5, characterized in that, Compressing the first instruction using the compression method of the one - layer compression to obtain a second instruction includes: Obtaining the instruction characteristics of the first instruction; When it is determined according to the instruction characteristics that fixed-length compression is supported, the first instruction is compressed in a fixed-length compression manner to obtain the second instruction; or when it is determined according to the instruction characteristics that the fixed-length compression is not supported, the first instruction is split into multiple second instructions, and each of the multiple second instructions has the same bit width.

7. The method according to claim 6, characterized in that, The instruction characteristics include at least one of the instruction type, usage frequency, or field utilization rate of the first instruction.

8. The method according to claim 6 or 7, characterized in that, The step of compressing the first instruction in a fixed-length compression manner to obtain the second instruction includes: Determining the valid field of the first instruction to obtain a second instruction including the valid field, where the valid field is the field used to execute the first instruction.

9. The method according to any one of claims 4-8, characterized in that The second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by fixed-length compression or splitting.

10. The method according to any one of claims 4-9, characterized in that, The step of compressing the second instruction using the two-layer compression method to obtain a third instruction includes: Obtaining the occurrence frequency of each field included in the second instruction; Obtaining a third instruction according to the occurrence frequency of each field, where the third instruction includes the encoding of each field, the encoding of each field is determined based on the occurrence frequency of each field, and the length of the encoding of each field is inversely proportional to the occurrence frequency of each field.

11. The method according to claim 10, wherein Before obtaining the third instruction according to the occurrence frequency of each field, it further includes: Constructing a coding dictionary corresponding to the second instruction according to the occurrence frequency of each field, where the coding dictionary includes each field and the occurrence frequency of each field; Determining the encoding of each field according to the coding dictionary.

12. The method according to claim 10 or 11, characterized in that The third instruction includes a coding index, and the coding index is used to find the field corresponding to the encoding included in the third instruction during the decompression of the third instruction.

13. According to the method described in any one of claims 1-12, characterized in that, After compressing the first instruction using the compression level, it further includes: Obtaining the instruction length of the compressed first instruction; Determining the storage unit in the memory structure for storing the compressed first instruction according to the instruction length, and storing the compressed first instruction in the determined storage unit.

14. The method according to any one of claims 1-13, characterized in that, The first instruction includes instructions for forwarding application programs.

15. The method according to any one of claims 1-14, characterized in that, The step of obtaining the first instruction to be processed includes: Obtaining at least one instruction included in the instruction bundle, where any one of the at least one instruction is the first instruction to be processed, and the at least one instruction is an instruction for parallel execution.

16. An instruction processing method, characterized in that, The method includes: Obtaining a compressed first instruction, where the compression of the first instruction is implemented based on a compression level, and the compression level is determined based on the memory structure and the required rate for reading the first instruction, and the memory structure is used to store the compressed first instruction; Restoring the compressed first instruction.

17. The method according to claim 16, wherein The memory structure includes a storage module and a cache module. The compression level of the storage module is two-layer compression, and the compression level of the cache module is one-layer compression. The restoration rate of the one-layer compression is higher than that of the two-layer compression. The compressed first instruction includes a third instruction; Restoring the compressed first instruction includes: Restoring the third instruction by using the restoration method corresponding to the compression method of the two - layer compression to obtain a second instruction; Restoring the second instruction by using the restoration method corresponding to the compression method of the one - layer compression to obtain the first instruction, where the compression ratio of the compression method of the two - layer compression is greater than the compression ratio of the compression method of the one - layer compression.

18. The method according to claim 17, wherein The third instruction includes a coding index. Restoring the third instruction by using the restoration method corresponding to the compression method of the two - layer compression to obtain a second instruction includes: Parsing the coding index included in the third instruction; Determining each field corresponding to each coding included in the third instruction according to the coding index, and determining the second instruction according to each field corresponding to each coding, where the length of the coding of each field is inversely proportional to the occurrence frequency of each field.

19. The method according to claim 17 or 18, characterized in that, The restoration method corresponding to the compression method of the one - layer compression includes decompression corresponding to fixed - length compression or splicing corresponding to splitting. Restoring the second instruction by using the restoration method corresponding to the compression method of the one - layer compression to obtain the first instruction includes: In the case where the second instruction is obtained by fixed - length compression, decompressing the second instruction by using the decompression corresponding to the fixed - length compression to obtain the first instruction; Or, in the case where the second instruction is obtained by splitting, splicing a plurality of second instructions obtained by splitting the first instruction to obtain the first instruction, and the bit widths of each of the plurality of second instructions are the same.

20. The method according to claim 19, wherein The second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by fixed - length compression or splitting. Before restoring the second instruction by using the restoration method corresponding to the compression method of the one - layer compression to obtain the first instruction, it further includes: Parsing the compression flag bit included in the second instruction, and determining the method for obtaining the second instruction from fixed - length compression and splitting according to the compression flag bit.

21. The method according to any one of claims 16-20, characterized in that, Obtaining the compressed first instruction includes: Extracting at least one instruction stored in a row of storage units of the memory structure; Separating each of the at least one instruction according to the instruction length of each instruction in the at least one instruction to obtain the at least one instruction, and the at least one instruction includes the compressed first instruction.

22. The method according to any one of claims 16-21, characterized in that, After restoring the compressed first instruction, it further includes: Determining the instruction bundle corresponding to the first instruction, where the instruction bundle includes at least one instruction, the compression results of the at least one instruction are stored in the same row of storage units of the memory structure, the compression result of any one of the compression results of the at least one instruction is the compressed first instruction, and the at least one instruction is an instruction for parallel execution; Sending the at least one instruction included in the instruction bundle to a decoding module, and the decoding module is used to parse the at least one instruction.

23. The method according to any one of claims 16-22, characterized in that, The first instruction includes an instruction for forwarding an application program.

24. An instruction processing device, characterized in that, The device includes: An acquisition module, configured to acquire a first instruction to be processed; A determination module, configured to determine a compression level of a memory in the memory structure according to the memory structure and the required rate for reading the first instruction, where the memory structure is used to store the compressed first instruction; A compression module, configured to compress the first instruction by using the compression level.

25. An instruction processing device, characterized in that, The apparatus includes: An acquisition module, configured to acquire the compressed first instruction, where the compression of the first instruction is implemented based on a compression level, and the compression level is determined according to the memory structure and the required rate for reading the first instruction, and the memory structure is used to store the compressed first instruction; A restoration module, configured to restore the compressed first instruction.

26. An instruction processing device, characterized in that, The device includes a processor, and the processor is configured to load and execute at least one instruction, so that the instruction processing device implements the instruction processing method according to any one of claims 1-15, or implements the instruction processing method according to any one of claims 16-23.

27. A computer-readable storage medium, characterized in that, At least one instruction is stored in the computer-readable storage medium, and the instruction is loaded and executed by a processor to implement the instruction processing method according to any one of claims 1-15, or to implement the instruction processing method according to any one of claims 16-23.

28. A chip, characterized in that, The chip includes a processor, and the processor is configured to run program instructions or codes, so that a device including the chip executes the instruction processing method according to any one of claims 1-15, or executes the instruction processing method according to any one of claims 16-23.

29. A computer program product, characterized in that, The computer program product includes a computer program / instruction, and the computer program / instruction is executed by a processor, so that a computer executes the instruction processing method according to any one of claims 1-15, or executes the instruction processing method according to any one of claims 16-23.

Images