Interrupt processing method, interrupt controller and processor

Abstract

The invention provides an interrupt processing method, an interrupt controller and a processor, which can be applied to the technical field of computer interrupt distribution and interrupt virtualization, and comprises the following steps: acquiring a target MSI, and sending the target MSI to a target processor based on a preset distribution strategy when the target MSI is in a first state (the distribution of the MSI is allowed), and sending the target MSI to a target processor, so that the target processor processes the target MSI, immediately updating the status bit of the target MSI object to a second state (a state in which the distribution of the MSI is prohibited) after sending the target MSI, and updating the corresponding status bit to the first state again after the target MSI is processed. According to the method, the MSI migration efficiency is improved by adding the status bit in the interrupt controller, the problem of MSI loss in the MSI migration process is solved, and the performance problem of MSI state migration is solved. The MSI corresponding to the same status bit can be ensured to be Pending or processed on only one processor at the same time, the setting of interrupt affinity software is simple to realize, and only the distribution target of the interrupt routing table item needs to be modified.

Description

Technical Field

[0001] This application relates to the technical field of computer interrupt distribution and interrupt virtualization, and particularly to a method for interrupt processing, an interrupt controller, and a processor. Background Art

[0002] Interrupt processing is a very important part of a computer system. When the computer system receives a message signaled interrupt (MSI), it will temporarily interrupt the program currently being executed and instead execute a specific interrupt handler to handle the interrupt event.

[0003] The process of interrupt processing generally includes steps such as interrupt request, interrupt response, interrupt handler call, interrupt handler execution, and interrupt processing completion. On the central processing units (CPU) side, each CPU is associated with an interrupt controller, which generally has two states: Idle and Pending. When no MSI is received, the interrupt is in the Idle state; when the CPU side receives an MSI write, the interrupt will switch from the Idle state to the Pending state until the software executes an acknowledgment (ACK) operation to respond to the interrupt, and then the interrupt Pending state switches back to the Idle state. During this process, the states corresponding to MSIs with the same interrupt number are scattered and managed on all CPUs on the CPU side, and the hardware cannot perceive whether the MSI has been processed by the software. This has many deficiencies: 1. The computer system needs to maintain the consistency of MSI states on different CPU sides; 2. After modifying the interrupt CPU affinity, the MSI will be processed simultaneously on the new and old CPUs, which may cause abnormal software behavior; 3. If multiple CPUs initiate migration operations for the same MSI, data inconsistency problems may occur due to competition during the MSI state migration process. The reason for these deficiencies is that the hardware cannot perceive whether the interrupt processing has ended. After modifying the interrupt affinity, when a certain MSI is still being processed on the old CPU, the new CPU will also receive an MSI corresponding to the same interrupt number, which may cause abnormal software behavior.

[0004] Based on this, the industry has adopted different architectures such as GICv3 MSI interrupt distribution, LAPIC MSI interrupt distribution, and IMSIC interrupt distribution to solve the above problems. However, these architectures still have the following problems: 1. The process of setting interrupt affinity in existing different architectures is complex. Software or hardware methods are required to ensure that the MSIs being processed are still completed. The hardware method using memory barrier operations is not easy to program and affects system performance. At the same time, the software method has a complex process and is prone to introducing bugs. 2. The state of the CPU processing MSIs is not synchronized with the MSI distribution process. New MSIs can be distributed and Pending while the MSIs are not yet processed, resulting in data competition problems and interrupt loss problems during the MSI migration process. Summary of the Invention

[0005] The present application provides a method for interrupt processing, an interrupt controller, and a processor. By adding a new status bit in the interrupt controller (the newly added status bit is used to represent the status of MSI processing), the efficiency of MSI migration is improved, the problem of MSI loss during the MSI migration process, and the performance problem of MSI status migration are solved.

[0006] Based on this, the embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, the present application first provides a method for interrupt processing. The method may specifically include: First, the interrupt controller obtains an MSI. The currently obtained MSI may be referred to as a target MSI. Next, the interrupt controller further determines what state the status bit corresponding to the received target MSI is currently in. The status bit is used to represent the status of MSI processing. When it is determined that the status bit corresponding to the target MSI is in a first state (also referred to as the status bit being cleared), the interrupt controller sends the target MSI to the target CPU based on a preset distribution policy, so that the target CPU processes the target MSI. Here, the first state is used to represent that the MSI is in a state allowing distribution. After the interrupt controller sends the target MSI to the target CPU, it immediately updates the status bit corresponding to the target MSI from the original first state to a second state. Here, the second state is used to represent that the MSI is in a state prohibiting distribution, which means that when the interrupt controller receives a new MSI corresponding to this status bit during this period, the new MSI needs to queue up on the interrupt controller for distribution. When the target MSI is processed, the interrupt controller updates the status bit corresponding to the MSI from the second state to the first state. It should be noted that in the embodiments of the present application, a specific form of the interrupt controller may be a specific form such as an interrupt router node or an interrupt distributor. The present application does not limit this.

[0008] In the above embodiments of the present application, by adding a new status bit in the interrupt controller, the efficiency of MSI migration is improved, the problem of MSI loss during MSI migration, and the performance problem of MSI status migration are solved. Specifically, the interrupt controller maintains the status bit corresponding to each MSI. Only when the status bit is cleared (i.e., the first state) can the MSI be distributed. During the process of the processor processing the MSI after distribution, the status bit remains set (i.e., the second state). Only after the MSI is processed can the status bit be cleared, which ensures that the MSIs corresponding to the same status bit will only be pending or processed on one processor at the same time. In the present application, since it is necessary to ensure that the already distributed MSIs have been processed before distributing an MSI. Therefore, after modifying the interrupt affinity, when distributing an MSI next time, the already distributed MSIs have been processed, so there will be no same MSI pending on the old CPU. Therefore, there is no need for software to ensure that the unprocessed old MSIs are processed on the old CPU like the LAPIC MSI interrupt distribution architecture, nor is there a need for hardware to ensure that the MSIs pending on the old CPU are migrated to the new CPU like the GIC ITS interrupt distribution architecture. The method of the present application ensures that the same MSI cannot be processed or pending on different CPUs at the same time. Therefore, setting the interrupt affinity in the present application is simple to implement in software. It only needs to modify the distribution target of the interrupt routing table entry of the interrupt controller to the target processor, and the software does not need to consider the data inconsistency problem that may be caused by modifying the interrupt affinity.

[0009] In a possible implementation manner of the first aspect, the implementation manner of updating the status bit corresponding to the target MSI from the second state to the first state may be: First, the interrupt controller obtains the target information sent by the target processor, and this target information is used to indicate that the target MSI has been processed; based on this target information, the interrupt controller can update the status bit corresponding to the target MSI from the second state back to the first state.

[0010] In the above embodiments of the present application, it is specifically described how the interrupt controller senses that the target processor has processed the target MSI, which is feasible.

[0011] In a possible implementation manner of the first aspect, after obtaining the target MSI and before based on the preset distribution policy, the method of the embodiment of the present application may further include: If the interrupt controller determines that the status bit corresponding to the target MSI is in the second state (which can also be referred to as the status bit being set), then the distribution of the target MSI is prohibited, the target MSI is cached, and queued on the interrupt controller until the status corresponding to the target MSI is updated to the first state before distribution.

[0012] In the above embodiments of the present application, if, after obtaining the target MSI, the corresponding status bit is in the second state, the target MSI is queued on the interrupt controller for distribution, avoiding the loss of MSIs and improving the user experience.

[0013] In a possible implementation manner of the first aspect, the specific implementation manner of obtaining the target MSI may be: receiving, through a physical connection, a line interrupt (which may be referred to as a target line interrupt) sent by a line interrupt device (which may be one or more) corresponding to the interrupt controller, and then converting the target line interrupt into the target MSI.

[0014] In the above embodiments of the present application, a specific implementation manner of obtaining the target MSI is specifically described, which has wide applicability.

[0015] In a possible implementation manner of the first aspect, the specific implementation manner of obtaining the target MSI may also be: directly receiving the target MSI sent by a PCIe device (which may be one or more) corresponding to the interrupt controller.

[0016] In the above embodiments of the present application, another specific implementation manner of obtaining the target MSI is specifically described, which has flexibility.

[0017] In a possible implementation manner of the first aspect, the preset distribution policy includes at least one of the following: the preset distribution priority of the MSI, the type of the MSI, and the interrupt number corresponding to the MSI.

[0018] In the above embodiments of the present application, several typical types of the preset distribution policy are specifically described, which has selectivity.

[0019] In a possible implementation manner of the first aspect, the status bit corresponding to each MSI may occupy an n-bit register space on the interrupt controller, where n ≥ 1.

[0020] In the above embodiments of the present application, the advantage of occupying the register space is that there is no need to introduce a memory barrier operation to ensure global visibility, improving the distribution performance of the MSI. Moreover, the hardware behavior of the register ensures that the modification of interrupt affinity takes effect serially, so fundamentally, data competition will not occur.

[0021] In a possible implementation manner of the first aspect, the status bit corresponding to each MSI may also occupy the memory space of the interrupt controller.

[0022] In the above embodiments of the present application, the advantage of occupying the memory space is that it can reduce the consumption of registers and avoid excessive transistors in the target processor (such as the CPU) being consumed on the interrupt controller.

[0023] In a possible implementation of the first aspect, the initial state of the status of each MSI may be the first state.

[0024] In the above implementation manner of the present application, setting the initial state of the status of each MSI to the first state is for the convenience of the timely distribution of the MSI.

[0025] The second aspect of the embodiments of the present application further provides a method for interrupt processing. Specifically, the method may include: First, a target processor receives a target MSI sent by an interrupt controller. The target MSI is sent by the interrupt controller based on a preset distribution policy when the status bit corresponding to the target MSI is in the first state, and the first state is used to represent that the MSI is in a state allowing distribution. After that, the target processor processes the target MSI, and when the processing of the target MSI is completed, the target processor sends target information to the interrupt controller so that the interrupt controller updates the status bit corresponding to the target MSI based on the target information, and the target information is used to indicate that the target MSI has been processed.

[0026] In the above implementation manner of the present application, after the target CPU finishes processing the target MSI, the target information sent triggers the interrupt controller to update the status bit corresponding to the target MSI. The present application improves the efficiency of MSI migration, solves the problem of MSI loss during the MSI migration process, and the performance problem of MSI status migration by adding a new status bit (the newly added status bit is used to represent the status of MSI processing) in the interrupt controller.

[0027] In a possible implementation of the second aspect, the preset distribution policy includes at least one of the following: the preset distribution priority of the MSI, the type of the MSI, and the interrupt number corresponding to the MSI.

[0028] In the above implementation manner of the present application, several typical types of the preset distribution policy are specifically described, which are selectable.

[0029] In a possible implementation of the second aspect, the status bit corresponding to each MSI may occupy the n-bit register space on the interrupt controller, where n≥1.

[0030] In the above implementation manner of the present application, the advantage of occupying the register space is that there is no need to introduce a memory barrier operation to ensure global visibility, which improves the distribution performance of the MSI. Moreover, the hardware behavior of the register ensures that the modification of interrupt affinity takes effect serially, so fundamentally, data competition will not occur.

[0031] In a possible implementation of the second aspect, the status bit corresponding to each MSI may also occupy the memory space of the interrupt controller.

[0032] In the above embodiments of the present application, the advantage of occupying memory space is that it can reduce the consumption of registers and avoid excessive transistors in the target processor (such as CPU) being consumed by the interrupt controller.

[0033] In a possible implementation manner of the second aspect, the initial state of the status of each MSI may be the first state.

[0034] In the above embodiments of the present application, setting the initial state of the status of each MSI to the first state is for the convenience of the timely distribution of MSIs.

[0035] The third aspect of the embodiments of the present application provides an interrupt controller, which has the function of implementing the method of the above first aspect or any possible implementation manner of the first aspect. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0036] The fourth aspect of the embodiments of the present application provides a processor. For example, the processor may be a CPU, and the processor has the function of implementing the method of the above second aspect or any possible implementation manner of the second aspect. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0037] The fifth aspect of the embodiments of the present application provides a computer device, which may include an interrupt controller, a memory, a processor (such as a CPU), and a bus system. Among them, the memory is used to store programs, the interrupt controller is used to call the programs stored in the memory to execute the method of the first aspect or any possible implementation manner of the first aspect of the embodiments of the present application, or the processor is used to call the programs stored in the memory to execute the method of the second aspect or any possible implementation manner of the second aspect of the embodiments of the present application.

[0038] The sixth aspect of the embodiments of the present application provides a computer-readable storage medium, in which instructions are stored. When the instructions run on a computer, the computer can execute the method of the above first aspect or any possible implementation manner of the first aspect, or the computer can execute the method of the above second aspect or any possible implementation manner of the second aspect.

[0039] The seventh aspect of the embodiments of the present application provides a computer program or a computer program product. When the computer program or the computer program product runs on a computer, the computer is caused to execute the method of the above first aspect or any possible implementation manner of the first aspect, or the computer can be caused to execute the method of the above second aspect or any possible implementation manner of the second aspect.

[0040] In the eighth aspect of the embodiments of the present application, a chip is provided. The chip includes at least one interrupt controller and at least one interface circuit. The interface circuit is coupled to the interrupt controller. The at least one interface circuit is configured to perform transceiver functions and send instructions to the at least one interrupt controller. The at least one interrupt controller is configured to run a computer program or instructions, and has the function of implementing the method according to the first aspect or any one of the possible implementation manners of the first aspect. This function can be implemented by hardware, or by software, or by a combination of hardware and software. The hardware or software includes one or more modules corresponding to the above functions. In addition, the interface circuit is used to communicate with other modules outside the chip.

[0041] In the ninth aspect of the embodiments of the present application, a chip is provided. The chip includes at least one processor and at least one interface circuit. The interface circuit is coupled to the processor. The at least one interface circuit is configured to perform transceiver functions and send instructions to the at least one processor. The at least one processor is configured to run a computer program or instructions, and has the function of implementing the method according to the first aspect or any one of the possible implementation manners of the first aspect. This function can be implemented by hardware, or by software, or by a combination of hardware and software. The hardware or software includes one or more modules corresponding to the above functions. In addition, the interface circuit is used to communicate with other modules outside the chip. Description of the Drawings

[0042] Figure 1 It is a schematic diagram of the system architecture provided by the embodiments of the present application;

[0043] Figure 2 It is a schematic diagram of the interrupt processing flow provided by the embodiments of the present application;

[0044] Figure 3 It is a flowchart of the method for interrupt processing provided by the embodiments of the present application;

[0045] Figure 4 It is an implementation schematic diagram of the improved interrupt state machine provided by the embodiments of the present application;

[0046] Figure 5 It is an example schematic diagram of the MSI new state occupying 1-bit register space provided by the embodiments of the present application;

[0047] Figure 6 It is an example schematic diagram of the MSI new state and the existing state together occupying 2-bit register space provided by the embodiments of the present application;

[0048] Figure 7 It is another flowchart of the method for interrupt processing provided by the embodiments of the present application;

[0049] Figure 8 A flowchart for modifying interrupt affinity provided by an embodiment of the present application;

[0050] Figure 9 A timing diagram for modifying interrupt affinity when an MSI corresponding to the same status bit is being processed in the interrupt handling method provided by an embodiment of the present application;

[0051] Figure 10 A timing diagram for the interrupt handling method provided by an embodiment of the present application when data competition occurs during MSI migration;

[0052] Figure 11 A component structure diagram provided by an embodiment of the present application;

[0053] Figure 12 Another flowchart for the interrupt handling method provided by an embodiment of the present application;

[0054] Figure 13 A structural diagram of an interrupt controller provided by an embodiment of the present application;

[0055] Figure 14 A structural diagram of a processor provided by an embodiment of the present application;

[0056] Figure 15 A structural diagram of a computer device provided by an embodiment of the present application. Detailed implementation manners

[0057] The present application provides an interrupt handling method, an interrupt controller, and a processor. By adding a new status bit in the interrupt controller, the efficiency of MSI migration is improved, the problem of MSI loss during MSI migration, and the performance problem of MSI state migration are solved. Specifically, the interrupt controller maintains the status bit corresponding to each MSI. Only when the status bit is in the first state can the MSI be distributed. During the process of the processor processing the MSI after distribution, the status bit always remains in the second state. Only after the MSI is processed can the status bit be updated back to the first state. This ensures that the same MSI will only be pending or processed on one processor at the same time. Therefore, the implementation of setting interrupt affinity in the present application is simple. It only needs to modify the distribution target of the interrupt routing table entry of the interrupt controller to the target processor, and the software does not need to consider the data inconsistency problem that may be caused by modifying the interrupt affinity. Moreover, the method of the present application can also ensure that the modification of the interrupt affinity takes effect serially, thus fundamentally ensuring that data competition will not occur.

[0058] In the description, claims and the above-mentioned drawings of the present application, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or device including a series of units does not have to be limited to those units, but may include other units not clearly listed or inherent to these processes, methods, products or devices.

[0059] To better understand the solutions of the embodiments of the present application, the following first introduces relevant terms and concepts that may be involved in the embodiments of the present application. It should be understood that the relevant concept explanations may be limited by the specific circumstances of the embodiments of the present application, but this does not mean that the present application can only be limited to this specific situation. There may also be differences in the specific circumstances of different embodiments, and no specific limitation is made here.

[0060] (1) Interrupt Idle state

[0061] The state where the interrupt controller has not received an interrupt signal.

[0062] (2) Interrupt Pending state

[0063] The state where the interrupt controller receives an interrupt signal and records it. The interrupt Pending state is a temporary state of interrupt response, waiting for the CPU to respond to the interrupt.

[0064] (3) Interrupt priority

[0065] Interrupt priority refers to the order of determining which interrupt should be processed when multiple interrupts in the Pending state occur simultaneously. When multiple interrupts arrive at the same time, the system needs to determine which interrupt to process first according to the interrupt priority, that is, the interrupt controller reports to the CPU for processing according to the priority level.

[0066] (4) Interrupt threshold

[0067] The interrupt threshold is a necessary condition for the interrupt controller to report an interrupt to the CPU. Only interrupts with an interrupt priority exceeding the interrupt threshold will be reported to the CPU for processing.

[0068] (5) Interrupt affinity

[0069] Bind the interrupt source to a specific one or more CPUs, and the interrupt generated by this interrupt source can only be processed by these specific CPUs.

[0070] (6) Interrupt state machine

[0071] A state machine for interrupt status change, which can perform state transition according to the change of the interrupt signal of the peripheral device and the actions of the CPU or software, and is the control center for the interrupt controller to process interrupts.

[0072] (7) Interrupt balancing

[0073] Modify the interrupt affinity by periodically running user-space software, so that interrupts are evenly processed on different CPUs.

[0074] (8) Line interrupt

[0075] Device interrupt that reports interrupts to the interrupt controller through a physical connection (i.e., hard connection).

[0076] (9) Line interrupt device

[0077] A device that reports interrupts through line interrupts, and it is physically connected to the interrupt controller through the interrupt controller pins.

[0078] (10) Message signal interrupt

[0079] Instead of sending interrupt signals through physical pins, it sends interrupts by writing data (including interrupt numbers) to an address, avoiding the limitation of the number of interrupts caused by physical pin connections, and can support a larger number of interrupts. Generally, it is edge-triggered interrupts.

[0080] The embodiments of the present application will be described below in conjunction with the accompanying drawings. Those of ordinary skill in the art can know that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0081] First, the system architecture and the overall process applied by the method of the embodiments of the present application will be described. For the convenience of description, the processors involved in the following embodiments are all described by taking the CPU as an example, and will not be elaborated later. Specifically, please refer to Figure 1 , Figure 1 is a schematic diagram of the system architecture provided by the embodiments of the present application. This system architecture may include the following hardware units: a central processing unit CPU die (CPU Die), a system bus, an interrupt controller, one or more PCIe devices, one or more line interrupt devices, an input / output die (I / O Die). Among them, the CPU Die may include one or more CPUs ( Figure 1It shows a scenario with multiple cases. The interrupt controllers correspond one-to-one with the I / O Dies. The functions of the interrupt controllers can be implemented based on the I / O Dies. The PCIe devices and the line interrupt devices are connected to the I / O Dies through interfaces. There is a physical connection between the line interrupt devices and the interrupt controllers, and a wireless connection between the PCIe devices and the interrupt controllers. Moreover, the PCIe devices do not directly report MSIs to the CPU via the bus, but only report them to the interrupt controllers via the bus.

[0082] Specifically, the functions of the above-mentioned hardware units are as follows: Each I / O Die has its own independent interrupt controller. The line interrupt devices are physically connected to the interrupt controllers through pins. The line interrupts generated by the line interrupt devices are converted into MSIs by the interrupt controllers and then distributed to the target CPU for processing. The MSIs generated by the PCIe devices can also only be distributed to the target CPU through the interrupt controllers. That is to say, all the interrupts generated by the devices on the I / O Die are distributed through the interrupt controllers (if it is a line interrupt, it is converted into an MSI), and are not directly reported to the target CPU.

[0083] In addition, a new status bit is maintained for all MSIs on the interrupt controller. For example, a status bit can be reserved in the register of the interrupt controller to control the distribution of MSIs. This status bit can correspond to the interrupt number, one interrupt number corresponds to one status bit, and each interrupt number can correspond to the MSIs of the same device (for example, multiple MSIs sent by the same device at different times before and after). For example, the same MSIs obtained in different orders can all correspond to the same interrupt number. The specific correspondence relationship can be defined in advance, and this application does not limit it. For the specific process, please refer to Figure 2 the shown interrupt handling process. After the interrupt controller distributes the MSI (i.e., the target MSI, also known as the old MSI), it locks the distribution operation of the subsequent MSIs (which can be called new MSIs) with the same interrupt number, and unlocks it by executing an EOI operation through software after the old MSI is processed to clear this status bit, ensuring that the same MSI will only be pending or processed on one CPU at the same time. It should be noted that in Figure 2 it, the shown devices include both line interrupt devices and PCIe devices. In practical applications, there can be only line interrupt devices or only PCIe devices. This application does not limit this, Figure 2 only for illustration.

[0084] Through Figure 1 the described distributed interrupt routing architecture, it is possible to avoid a certain interrupt controller becoming a bottleneck in interrupt processing, and also reduce the requirements of a single interrupt controller for hardware resources. Each interrupt controller can directly use the device memory to maintain the status of the interrupt sources, avoiding the overhead of accessing Double Data Rate (DDR).

[0085] It should be noted that in Figure 1 , it is illustrated that there are multiple CPU Dies, and each CPU Die includes multiple CPUs; there are multiple I / O Dies, and each I / O Die is connected to multiple PCIe devices and multiple line interrupt devices through an interface. However, in the embodiments of the present application, Figure 1 the system architecture shown is only illustrative, and there are no limitations on the deployment methods of each unit and the number of each unit. Specifically, in some other embodiments of the present application, as an example, there may be one CPU Die, which may include one or more CPUs. As another example, there may be one I / O Die. As another example, each I / O Die may be connected to only PCIe devices through an interface, and the PCIe device may be one or multiple, and the present application does not limit this; or, each I / O Die may be connected to only line interrupt devices through an interface, and the line interrupt device may be one or multiple, and the present application does not limit this.

[0086] Based on the above system architecture, the method for interrupt processing provided by the embodiments of the present application will be introduced below. For the convenience of description, the processor is taken as the CPU as an example below. Specifically, please refer to Figure 3 , Figure 3 which is a schematic flowchart of the method for interrupt processing provided by the embodiments of the present application, and specifically includes the following steps:

[0087] 301. The interrupt controller obtains the target MSI.

[0088] First, the interrupt controller will obtain the MSI, and the currently obtained MSI can be referred to as the target MSI. The specific obtaining method may be: 1) Receive the line interrupt (which can be one or more) sent by the line interrupt device corresponding to the interrupt controller through a physical connection, and then convert the target line interrupt into the target MSI; 2) Directly receive the target MSI sent by the PCIe device (which can be one or more) corresponding to the interrupt controller.

[0089] It should be noted that if the interrupt controller receives too many MSIs within a short period of time and does not distribute them all, the currently received target MSI will queue up on the interrupt controller waiting for distribution.

[0090] 302. When the status bit corresponding to the target MSI is in the first state, the interrupt controller sends the target MSI to the target CPU based on a preset distribution policy.

[0091] Next, the interrupt controller further determines what state the status bit corresponding to the received target MSI is currently in. This status bit is used to represent the status of MSI processing. When it is determined that the status bit corresponding to the target MSI is in the first state (which can also be referred to as clearing the status bit), the interrupt controller sends the target MSI to the target CPU based on a preset distribution policy, so that the target CPU processes the target MSI. Here, the first state is used to represent that the MSI is in a state allowing distribution. Specifically, in some embodiments of the present application, the preset distribution policy can be the preset distribution priority of the MSI, the type of the MSI, or the interrupt number corresponding to the MSI. The present application does not specifically limit this.

[0092] It should be noted that, in some embodiments of the present application, if the interrupt controller determines that the status bit corresponding to the target MSI is in the second state (i.e., the status bit is set), then the distribution of the target MSI is prohibited, and the target MSI is cached and queued on the interrupt controller until the status corresponding to the target MSI is updated to the first state and then distributed. The distribution process is similar to the above and will not be elaborated here.

[0093] It should also be noted that, in some embodiments of the present application, for the convenience of timely distribution of MSIs, the initial state of the status of each MSI can be the first state, that is, when initializing, the status bits of all MSIs of the interrupt controller are in a cleared state.

[0094] 303. The interrupt controller updates the status bit corresponding to the target MSI from the first state to the second state.

[0095] After the interrupt controller sends the target MSI to the target CPU, it immediately updates the status bit corresponding to the target MSI from the original first state to the second state. Here, the second state is used to represent that the MSI is in a state prohibiting distribution, which means that when the interrupt controller receives a new MSI corresponding to this status bit during this period, the new MSI needs to queue on the interrupt controller waiting for distribution and cannot be distributed temporarily.

[0096] It should be noted that, in the embodiments of the present application, this update method can be executed by software or by hardware. The present application does not limit this.

[0097] 304. The target CPU processes the target MSI.

[0098] After the target CPU receives the target MSI sent by the interrupt controller, it performs interrupt processing on the target MSI.

[0099] 305. When the processing of the target MSI is completed, the interrupt controller updates the status bit corresponding to the MSI from the second state to the first state.

[0100] After the target CPU finishes processing the target MSI, the interrupt controller updates the status bit corresponding to the MSI from the second state back to the original first state.

[0101] As an example, after the target CPU finishes processing the target MSI, it sends a target message to the interrupt controller, and this target message is used to indicate that the target MSI has been processed. The interrupt controller can then update the status bit corresponding to the target MSI from the second state back to the first state based on this target information. Specifically, it can be the device driver of the interrupt controller that clears the status bit corresponding to the target MSI in the interrupt controller when the software executes EOI. For example, assume that the status bit occupies the register space of the interrupt controller. Then, when the processing of the target MSI is completed, the target CPU can achieve the purpose of clearing the status bit by writing to the EOI register of the interrupt controller through software.

[0102] It should be noted that the status bit described in steps 301 to 305 is an additional status bit newly added on the interrupt controller, and the interrupt controller maintains an additional status bit for all MSIs. As an example, this status bit can be added to the original interrupt state machine of the interrupt controller. The additional status bit can be called the Ongoing state, and the distribution and status update of the MSI are controlled according to the interrupt state machine. For example, refer to Figure 4 , Figure 4 FIG. is an implementation schematic diagram of an improved interrupt state machine provided by an embodiment of the present application. A1 or A2 represents a peripheral generating an MSI; B represents the MSI being distributed from the interrupt controller, and C1 or C2 represents that the MSI has been processed and the software executes the EOI operation. The main change is that the MSI can be distributed only when the interrupt Ongoing is not set (i.e., the first state). After the MSI is distributed, Ongoing is set (i.e., updated to the second state), and the Ongoing state of the MSI is cleared only when the software executes the EOI operation after the MSI is processed.

[0103] It should be noted that in some embodiments of the present application, the status bit corresponding to each MSI can occupy the memory space of the interrupt controller. The advantage of occupying the memory space is that it can reduce the consumption of registers and avoid excessive transistors in the CPU being consumed by the interrupt controller.

[0104] It should also be noted that in some other embodiments of the present application, the status bits corresponding to each MSI can also occupy the n-bit register space on the interrupt controller. The advantage of occupying the register space is that there is no need to introduce memory barrier operations to ensure global visibility, which improves the distribution performance of MSIs. Moreover, the hardware behavior of the register ensures that the modification of interrupt affinity takes effect serially, thus fundamentally ensuring that data competition does not occur.

[0105] For ease of understanding, taking the case where the status bits corresponding to each MSI occupy the n-bit register space on the interrupt controller as an example, the following describes how the status bits are added and how they exist in the interrupt controller.

[0106] A. The case where each MSI occupies 1-bit register space (i.e., n = 1).

[0107] In the embodiment of the present application, the interrupt controller maintains an Ongoing register table for all local MSIs. That is, before specifically implementing the interrupt handling method in step 301 above, an Ongoing register table is added to each interrupt controller in advance. Each MSI corresponding to each interrupt number occupies 1-bit register space, which is used to indicate whether the MSI is being processed by the CPU side. When the MSI is distributed, the corresponding status bit is set (i.e., updated to the second state). In the reset case, the Ongoing register table is cleared (i.e., updated back to the first state).

[0108] As an example, specifically refer to Figure 5 , assuming that each interrupt controller supports at most 256 (in actual cases, the number is not limited, and this is only for illustration) MSI interrupts, then the size of the Ongoing register table is 256 bits, and each bit represents the interrupt handling status corresponding to an MSI. For example, 1 indicates being processed, and 0 indicates having been processed or not being processed yet; it can also be that 0 indicates being processed, and 1 indicates having been processed or not being processed yet. In addition to using 1 and 0 for representation, other characters can also be used for representation, and the present application does not limit the specific representation method.

[0109] It should be noted that Figure 5 illustrates a specific implementation manner in which each MSI occupies 1-bit register space. The occupation manner can be implemented in the form of a register table or in the form of a queue, etc. Specifically, the present application does not limit this, Figure 5 only for illustration.

[0110] B. The case where each MSI occupies 2-bit register space (i.e., n = 2).

[0111] In the embodiments of the present application, the interrupt controller maintains an Ongoing state for all local MSI extensions. That is, before specifically implementing the method of interrupt processing in step 301 above, an Ongoing state is added to each interrupt controller on the basis of the Pending state in advance, and it is extended to an interrupt status register table, so that the state corresponding to each MSI occupies 2-bit register space.

[0112] As an example, specifically refer to Figure 6 , assuming that 00 represents the MSI Idle state, that is, no MSI is received or the MSI has been processed; 01 represents MSI Pending waiting for distribution; 10 represents that the MSI has been distributed and is being processed by the CPU side; 11 represents that after the MSI has been distributed, it has not been processed yet and the MSI corresponding to the same status bit is triggered again. Among them, no new MSI will be distributed in the two states of 10 and 11. As Figure 6 shown, assuming that each interrupt controller supports at most 256 MSIs, the size of the interrupt status register table is 512 bits, and every 2 bits represent the interrupt status corresponding to an MSI.

[0113] It should be noted that Figure 6 illustrates a specific implementation manner in which each MSI occupies 2-bit register space. The occupation manner can be implemented in the form of a register table or in the form of a queue such as a queue. Specifically, the present application does not make any limitations in this regard, Figure 6 only for illustration.

[0114] In summary, for the convenience of understanding the core process of the above interrupt processing method, a specific implementation manner of the interrupt processing method provided by the embodiments of the present application can be as shown in the flowchart in Figure 7 , which may include the following steps:

[0115] 701. Set the initial status bit of the interrupt controller to the first status.

[0116] First, the interrupt controller initializes and sets each status bit, and these status bits can be initialized to the first status.

[0117] 702. Determine whether an MSI is obtained. If so, execute step 703; if not, return to step 702.

[0118] After that, the interrupt controller determines whether it has obtained an MSI sent by the PCIe device (or converted from a line interrupt). If an MSI is obtained, step 703 is executed. If no MSI is obtained, return to step 702 to continue monitoring whether an MSI is obtained.

[0119] 703. The MSI queues up waiting for distribution.

[0120] After the interrupt controller obtains an MSI, if there is still an MSI obtained previously on the interrupt controller that has not been distributed, the newly obtained MSI currently needs to be queued for distribution.

[0121] 704. Select a target MSI for distribution based on a preset distribution policy.

[0122] The interrupt controller can distribute interrupts based on a preset distribution policy, such as the distribution priority of the MSI, the type of the MSI, the interrupt number corresponding to the MSI, etc. When it is the turn to distribute a specific MSI (i.e., the target MSI) in the queue, select the target MSI for distribution.

[0123] 705. Determine whether the status bit corresponding to the target MSI is in the first state. If so, execute step 706; if not, return to step 704.

[0124] The interrupt controller also needs to further determine whether the status bit corresponding to the target MSI to be distributed currently is in the first state, that is, whether the status bit is cleared. If so, execute step 706; if not, it means that the target MSI to be distributed currently is prohibited from being distributed, so return to step 704 and select a new target MSI for distribution.

[0125] 706. Distribute the target MSI and update the status bit corresponding to the target MSI to the second state.

[0126] Because the status bit corresponding to the target MSI is in the first state, it indicates that the target MSI can be distributed to the target CPU. At this time, the interrupt controller distributes the target MSI, and at the same time updates the status bit corresponding to the target MSI from the first state to the second state, that is, the status bit is set, indicating prohibited distribution.

[0127] 707. Receive the target information sent by the target CPU. The target information is used to indicate that the target MSI has been completed, and update the status bit corresponding to the target MSI to the first state.

[0128] After the target CPU receives the target MSI distributed by the interrupt controller, it will process the target MSI. After the processing is completed, the interrupt controller will receive a target information sent by the target CPU. The target information is used to indicate that the target MSI has been processed and instruct the interrupt controller to update the status bit corresponding to the target MSI to the first state. The specific implementation of this process can be that the software executes an EOI operation.

[0129] In the above embodiments of the present application, since the interrupt controller must ensure that the old MSI corresponding to the same status bit has been processed before distributing the MSI, when the interrupt affinity is modified and the next MSI is distributed, all the MSIs of the same device that have been distributed have been processed. Therefore, there will be no same MSI Pending on the old CPU. Thus, there is no need for software to ensure that the unprocessed old MSIs are processed on the old CPU as in the LAPIC MSI interrupt distribution architecture, nor is there a need for hardware to ensure that the Pending MSIs on the old CPU are migrated to the new CPU as in the GIC ITS MSI interrupt distribution architecture. The method of the embodiment of the present application ensures that the MSIs corresponding to the same status bit cannot be processed or Pending on different CPUs simultaneously. Therefore, the implementation of setting the interrupt affinity in the present application is simple. Specifically, as Figure 8 shown, it only needs to modify the distribution target of the interrupt routing table entry of the interrupt controller to the target CPU, and the software does not need to consider the data inconsistency problem that may be caused by modifying the interrupt affinity. If the register is used to maintain the interrupt status of the status bit, there is no need to introduce a memory barrier operation to ensure global visibility.

[0130] In Figure 8 On the basis of the modified interrupt affinity shown in the schematic diagram, the timing of modifying the interrupt affinity when there is an MSI being processed will be described below. For details, please refer to Figure 9 Steps ① to ⑧ in Figure 9 FIG.

[0131] Figure 10 is a timing diagram of modifying the interrupt affinity when there is an MSI corresponding to the same status bit being processed in the interrupt processing method provided by the embodiment of the present application. The hardware of the interrupt controller in the embodiment of the present application ensures that when the MSI is being processed and the software modifies the interrupt affinity, the hardware distribution logic of the interrupt controller ensures that the next generated MSI will not be processed on the new CPU until the previous MSI interrupt of the same device is processed. Because when the status bit of the MSI is set (i.e., the second state), the distribution of the MSI needs to wait for the currently distributed MSI to continue to be processed on the original CPU, and the interrupt affinity will only take effect at the next MSI distribution after the status bit of the MSI is cleared (i.e., the first state).

[0131] Figure 10 FIG.Figure 10 Steps ① to ⑥ shown in Case 1 in [reference], the last interrupt affinity setting before distribution is valid; if MSI is distributed after concurrent modification, then as shown in Steps ① to ⑤ in Case 2 in [reference], the last interrupt affinity modification before distribution is also valid. In the embodiments of the present application, the hardware ensures that the modification of interrupt affinity takes effect serially, thus fundamentally ensuring that data competition will not occur. Figure 10 Steps ① to ⑤ shown in Case 2 in [reference], the last interrupt affinity modification before distribution is also valid. In the embodiments of the present application, the hardware ensures that the modification of interrupt affinity takes effect serially, thus fundamentally ensuring that data competition will not occur.

[0132] The product implementation form of the embodiments of the present application can be included in the interrupt controller driver software and deploy the interrupt controller hardware that supports the methods of the embodiments of the present application. For details, please refer to Figure 11 , Figure 11 FIG. [reference] is a component structure diagram provided by the embodiments of the present application. In the operating system (OS) software, the components involved in the embodiments of the present application include: a kernel interrupt framework 1101, an interrupt controller driver 1102 (software), and a device driver 1103 (software) of a PCIe device 1106; in the server / embedded platform 110 hardware, the components involved in the embodiments of the present application include: a CPU 1104, an interrupt controller 1105, and a PCIe device 1106.

[0133] Among them, a server is a machine that can run an operating system or other software programs, including hardware and software (it can run an operating system or be a bare machine without running an operating system); the PCIe device 1106 can be a peripheral device that can send MSI (such as a network card), and run the device driver of this device (such as a network card driver) in the kernel operating system (or a bare machine); the PCIe device 1106 can also be a device that converts line interrupts into MSI (such as mbigen or APLIC of RISCV), and run the device driver of this device (such as mbigen driver or APLIC driver) in the kernel operating system; the device driver 1103 of the PCIe device 1106 registers the interrupt handling function of the MSI of this device (or runs the interrupt handling program on a bare machine) through the interface provided by the kernel interrupt framework 1101; the interrupt controller 1105 can receive the MSI sent by the PCIe device 1106 and report it to the CPU 1104. The interrupt controller driver 1102 that runs the interrupt controller 1105 in the kernel operating system initializes, configures, and processes the MSI of the interrupt controller 1105; the device driver 1103 of the PCIe device 1106, the interrupt controller driver 1102, and the kernel interrupt framework 1101 (running the operating system) run on the CPU. The CPU 1104 can receive the MSI reported by the interrupt controller 1105; the kernel interrupt framework 1101 of the operating system provides a general framework code implementation for interrupt handling, and the interrupt controller driver 1102 performs interrupt handling with the help of the interrupt framework.

[0134] The software program code of the embodiment of the present application exists in the interrupt controller driver 1102, and the hardware logic code exists in the interrupt controller 1105. During operation, the program code of the embodiment of the present application runs in the host memory of the server / embedded platform 110. Figure 11 The implementation form of the embodiment of the present application in the server or embedded platform and OS software is given. The part shown by the dotted box is the module modified by the embodiment of the present application on the basis of the existing platform software. In the interrupt controller 1105, the embodiment of the present application adds a status bit to all MSIs local to the I / O Die to record whether the MSI is being processed, and locks the distribution of the MSI when this status bit is set (i.e., the second state), so as to avoid distributing new MSIs when the MSI is being processed. In the interrupt controller driver 1102, the embodiment of the present application implements an EOI operation for the interrupt controller driver 1102, and clears the status bit of the MSI being processed (i.e., updates to the first state) when the MSI processing is completed. For example, based on the modified interrupt controller 1105 and related drivers, the device driver 1103 can register the interrupt processing function of the MSI under the kernel interrupt framework 1101, and the interrupt controller driver 1102 can register the callback function of the interrupt EOI. Among them, the interrupt controller 1105 maintains an Ongoing register table for all local MSIs, and each bit indicates whether the MSI is being processed. The interrupt controller driver 1102 clears the Ongoing status of the MSI in the EOI callback function. The embodiment of the present application can ensure that the MSI can only be processed on one CPU 1104, avoiding lost interrupts and data competition in interrupt migration.

[0135] Based on Figure 11 the component structure shown, as an example, the method of the embodiment of the present application can be implemented by modifying the interrupt controller driver 1102. For details, please refer to Figure 12 , assuming that the newly added status bit is the above-mentioned Ongoing status, when the interrupt controller driver 1102 is initialized, clear the Ongoing status of all MSIs, register the callback function of the interrupt EOI, and perform the operation of clearing the Ongoing status of the MSI therein. When the MSI processing is completed, the EOI operation will be executed, and at this time, the Ongoing status of the MSI will be cleared, so that the new MSI can continue to be distributed from the interrupt controller 1105 to the CPU 1104 side for processing. For details, please refer to Figure 12 Steps 1201 to 1208 therein, which will not be elaborated here.

[0136] On the basis of the above embodiment, in order to better implement the above solution of the embodiment of the present application, the following also provides related devices for implementing the above solution. For details, please refer to Figure 13 , Figure 13FIG. 0 is a schematic structural diagram of an interrupt controller provided by an embodiment of the present application. The interrupt controller 1300 may specifically include: an acquisition module 1301, a distribution module 1303, and an update module 1304. Among them, the acquisition module 1301 is configured to acquire a target MSI; the distribution module 1303 is configured to, when the status bit corresponding to the target MSI is in a first state, send the target MSI to a target processor based on a preset distribution policy, so that the target processor processes the target MSI, and the first state is used to indicate that the MSI is in a state allowing distribution; the update module 1304 is configured to update the status bit corresponding to the target MSI from the first state to a second state, and the second state is used to indicate that the MSI is in a state prohibiting distribution; the update module 1304 is further configured to, when the processing of the target MSI is completed, update the status bit corresponding to the target MSI from the second state to the first state.

[0137] In a possible design, the update module 1304 is specifically configured to: acquire target information sent by the target processor, where the target information is used to indicate that the processing of the target MSI is completed; based on the target information, update the status bit corresponding to the target MSI from the second state to the first state.

[0138] In a possible design, the interrupt controller 1300 further includes a queuing module 1302. The queuing module 1302 is configured to, after the acquisition module 1301 acquires a target MSI and before the distribution module 1303 sends the target MSI to the target processor based on a preset distribution policy, cache the target MSI when the status corresponding to the target MSI is in the second state until the status corresponding to the target MSI is updated to the first state.

[0139] In a possible design, the acquisition module 1301 is specifically configured to: receive a target line interrupt sent by a line interrupt device, where the line interrupt device is a device that generates a line interrupt; convert the target line interrupt into the target MSI.

[0140] In a possible design, the acquisition module 1301 is specifically further configured to: receive a target MSI sent by a PCIe device.

[0141] In a possible design, the preset distribution policy at least includes one of the following: the distribution priority of the preset MSI, the type of the MSI, and the interrupt number corresponding to the MSI.

[0142] In a possible design, the status bit corresponding to each MSI occupies n-bit register space, where n≥1.

[0143] In a possible design, the status bit corresponding to each MSI occupies memory space.

[0144] In a possible design, the initial state of the status bit of each such MSI is the first state.

[0145] It should be noted that the information interaction, execution process, etc. between the modules / units in the interrupt controller 1300 are based on the same concept as the above method embodiments in this application. For specific content, reference can be made to the descriptions in the method embodiments shown above in this application, and details will not be elaborated here.

[0146] Next, the processor provided in the embodiments of this application will be introduced. Please refer to Figure 14 , Figure 14 which is a schematic structural diagram of the processor provided in the embodiments of this application. The processor 1400 may specifically include: a receiving module 1401, an interrupt processing module 1402, and a sending module 1403. Among them, the receiving module 1401 is configured to receive a target MSI sent by the interrupt controller, and the target MSI is sent by the interrupt controller based on a preset distribution policy when the status bit corresponding to the target MSI is in the first state, and the first state is used to indicate that the MSI is in a state allowing distribution; the interrupt processing module 1402 is configured to process the target MSI; the sending module 1403 is configured to send target information to the interrupt controller when the target MSI is processed, so that the interrupt controller updates the status bit corresponding to the target MSI based on the target information, and the target information is used to indicate that the target MSI has been processed.

[0147] In a possible design, the preset distribution policy includes at least one of the following: the distribution priority of the preset MSI, the type of the MSI, and the interrupt number corresponding to the MSI.

[0148] In a possible design, the status bit corresponding to each such MSI occupies n-bit register space of the interrupt controller, where n≥1.

[0149] In a possible design, the status bit corresponding to each such MSI occupies the memory space of the interrupt controller.

[0150] In a possible design, the initial state of the status bit of each such MSI is the first state.

[0151] In a possible design, the processor 1400 may specifically be a CPU.

[0152] It should be noted that the information interaction, execution process, etc. between the modules / units in the processor 1400 are based on the same concept as the above method embodiments in this application. For specific content, reference can be made to the descriptions in the method embodiments shown above in this application, and details will not be elaborated here.

[0153] Next, another computer device provided by the embodiment of the present application is introduced. Figure 15 , Figure 15 A schematic diagram of the structure of a computer device provided in an embodiment of the present application, wherein the computer device 1500 may be deployed with Figure 13 The interrupt controller 1300 described in the corresponding embodiment is used to implement Figure 13 Corresponding to the function of the interrupt controller 1300 in the embodiment, the computer device 1500 may also be deployed with Figure 14 The processor 1400 (such as a CPU) described in the corresponding embodiment is used to implement Figure 14 The functions of the processor 1400 in the corresponding embodiment. Specifically, the computer device 1500 is implemented by one or more servers. The computer device 1500 may vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1522 and memory 1532, one or more storage media 1530 (e.g., one or more mass storage devices) storing application programs 1542 or data 1544, and one or more interrupt controllers 1560. The memory 1532 and storage medium 1530 may be temporary storage or permanent storage. The program stored in the storage medium 1530 may include one or more modules (not shown), each module may include a series of instruction operations in the computer device 1500. Furthermore, the CPU 1522 may be configured to communicate with the storage medium 1530 to execute the series of instruction operations in the storage medium 1530 on the computer device 1500.

[0154] The computer device 1500 may also include one or more power supplies 1526, one or more wired or wireless network interfaces 1550, one or more input and output interfaces 1558, and / or one or more operating systems 1541, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0155] In the embodiment of the present application, the interrupt controller 1560 is used to execute the steps executed by the interrupt controller in the above method embodiment; the central processing unit 1522 is used to execute the steps executed by the CPU in the above method embodiment. The specific implementation of the interrupt controller 1560 and the central processing unit 1522 to execute the above steps is the same as that in the present application. Figures 2 to 12 The corresponding method embodiments are based on the same concept, and the technical effects they bring are also the same as the above-mentioned embodiments of this application. For specific contents, please refer to the description in the method embodiments shown above in this application, and will not be repeated here.

[0156] In addition, it should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that they have a communication connection, which can be specifically implemented as one or more communication buses or signal lines.

[0157] Through the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures for implementing the same function can also be various, such as analog circuits, digital circuits or dedicated circuits. However, for this application, in more cases, software program implementation is a better implementation method. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, or a combination of a software product and a hardware product. This computer software product is stored in a readable storage medium, such as a floppy disk, USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disc of a computer, etc., and includes several instructions to enable a computer device (which can be a personal computer, training device, or network device, etc.) to execute the methods described in various embodiments of this application.

[0158] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product.

[0159] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

Claims

1. A method for interrupt handling, characterized in that, Including: Obtaining that the target message signal is interrupted; When the status bit corresponding to the target message signal interruption is in the first state, based on a preset distribution policy, sending the target message signal interruption to a target processor so that the target processor processes the target message signal interruption, where the first state is used to represent that the message signal interruption is in a state allowing distribution; Updating the status bit corresponding to the target message signal interruption from the first state to a second state, where the second state is used to represent that the message signal interruption is in a state prohibiting distribution; When the processing of the target message signal interruption is completed, updating the status bit corresponding to the target message signal interruption from the second state to the first state.

2. The method according to claim 1, wherein The updating the status bit corresponding to the target message signal interruption from the second state to the first state includes: Obtaining target information sent by the target processor, where the target information is used to indicate that the target message signal interruption has been processed; Based on the target information, updating the status bit corresponding to the target message signal interruption from the second state to the first state.

3. The method according to any one of claims 1-2, characterized in that, Before the preset distribution policy and after obtaining the target message signal interruption, the method further includes: When the status corresponding to the target message signal interruption is in the second state, caching the target message signal interruption until the status corresponding to the target message signal interruption is updated to the first state.

4. The method according to any one of claims 1-3, characterized in that The obtaining the target message signal interruption includes: Receiving a target line interruption sent by a line interruption device, where the line interruption device is a device generating a line interruption; Converting the target line interruption into the target message signal interruption.

5. The method according to any one of claims 1 to 3, characterized in that, The obtaining the target message signal interruption includes: Receiving a target message signal interruption sent by a PCIe device.

6. The method according to any one of claims 1-5, characterized in that, The preset distribution policy includes at least one of the following: The preset distribution priority of the message signal interruption, the type of the message signal interruption, and the interrupt number corresponding to the message signal interruption.

7. The method according to any one of claims 1-6, characterized in that, The status bit corresponding to each message signal interruption occupies n-bit register space, where n≥1.

8. The method according to any one of claims 1-6, characterized in that, The status bit corresponding to each message signal interruption occupies memory space.

9. The method according to any one of claims 1-8, characterized in that, The initial state of the status bit of each message signal interruption is the first state.

10. A method for interrupt handling, characterized in that, Including: Receiving a target message signal interruption sent by an interrupt controller, where the target message signal interruption is sent by the interrupt controller based on a preset distribution policy when the status bit corresponding to the target message signal interruption is in the first state, and the first state is used to represent that the message signal interruption is in a state allowing distribution; Processing the target message signal interruption; When the processing of the target message signal interruption is completed, sending target information to the interrupt controller so that the interrupt controller updates the status bit corresponding to the target message signal interruption based on the target information, where the target information is used to indicate that the target message signal interruption has been processed.

11. The method according to claim 10, wherein The preset distribution policy includes at least one of the following: The preset distribution priority of the message signal interruption, the type of the message signal interruption, and the interrupt number corresponding to the message signal interruption.

12. The method according to any one of claims 10-11, characterized in that Each status bit corresponding to each of the message signal interrupts occupies an n-bit register space of the interrupt controller, where n≥1.

13. The method according to any one of claims 10-11, characterized in that, Each status bit corresponding to each of the message signal interrupts occupies the memory space of the interrupt controller.

14. The method according to any one of claims 10 - 13, characterized in that The initial state of each status bit of each of the message signal interrupts is the first state.

15. An interrupt controller, characterized in that, Comprising: An acquisition module, configured to acquire a target message signal interrupt; A distribution module, configured to, when the status bit corresponding to the target message signal interrupt is in the first state, send the target message signal interrupt to a target processor based on a preset distribution policy, so that the target processor processes the target message signal interrupt, where the first state is used to indicate that the message signal interrupt is in a state allowing distribution; An update module, configured to update the status bit corresponding to the target message signal interrupt from the first state to a second state, where the second state is used to indicate that the message signal interrupt is in a state prohibiting distribution; The update module is further configured to, when the processing of the target message signal interrupt is completed, update the status bit corresponding to the target message signal interrupt from the second state to the first state.

16. The interrupt controller according to claim 15, characterized in that, The update module is specifically configured to: Acquire target information sent by the target processor, where the target information is used to indicate that the processing of the target message signal interrupt is completed; Based on the target information, update the status bit corresponding to the target message signal interrupt from the second state to the first state.

17. The interrupt controller according to any one of claims 15-16, characterized in that The interrupt controller further includes a queuing module; The queuing module is configured to, after the acquisition module acquires a target message signal interrupt and before the distribution module sends the target message signal interrupt to a target processor based on a preset distribution policy, cache the target message signal interrupt when the status corresponding to the target message signal interrupt is in the second state until the status corresponding to the target message signal interrupt is updated to the first state.

18. The interrupt controller according to any one of claims 15-17, characterized in that The acquisition module is specifically configured to: Receive a target line interrupt sent by a line interrupt device, where the line interrupt device is a device that generates a line interrupt; Convert the target line interrupt into the target message signal interrupt.

19. The interrupt controller according to any one of claims 15-17, characterized in that, The acquisition module is specifically further configured to: Receive a target message signal interrupt sent by a PCIe device.

20. The interrupt controller according to any one of claims 15-19, characterized in that, The preset distribution policy at least includes one of the following: The preset distribution priority of the message signal interrupt, the type of the message signal interrupt, and the interrupt number corresponding to the message signal interrupt.

21. The interrupt controller according to any one of claims 15-20, characterized in that, Each status bit corresponding to each of the message signal interrupts occupies an n-bit register space, where n≥1.

22. The interrupt controller according to any one of claims 15-20, characterized in that, Each status bit corresponding to each of the message signal interrupts occupies the memory space.

23. The interrupt controller according to any one of claims 15-22, characterized in that, The initial state of each status bit of each of the message signal interrupts is the first state.

24. A processor, characterized in that, Comprising: A receiving module, configured to receive a target message signal interrupt sent by an interrupt controller, where the target message signal interrupt is sent by the interrupt controller based on a preset distribution policy when the status bit corresponding to the target message signal interrupt is in the first state, and the first state is used to indicate that the message signal interrupt is in a state allowing distribution; An interrupt processing module, configured to process the target message signal interrupt; A sending module, configured to send target information to the interrupt controller when the processing of the target message signal interruption is completed, so that the interrupt controller updates the status bit corresponding to the target message signal interruption based on the target information, where the target information is used to indicate that the processing of the target message signal interruption is completed.

25. The processor according to claim 24, wherein The preset distribution policy at least includes one of the following: The distribution priority of the preset message signal interruption, the type of the message signal interruption, and the interrupt number corresponding to the message signal interruption.

26. The processor according to any one of claims 24-25, characterized in that, The status bit corresponding to each message signal interruption occupies the n-bit register space of the interrupt controller, where n≥1.

27. The processor according to any one of claims 24-25, characterized in that, The status bit corresponding to each message signal interruption occupies the memory space of the interrupt controller.

28. The processor according to any one of claims 24-27, characterized in that, The initial state of the status bit of each message signal interruption is the first state.

29. The processor according to any one of claims 24-28, characterized in that, The processor includes: A CPU.

30. A computer device, including an interrupt controller, a processor, and a memory, characterized in that The memory is used to store programs; The processor is configured to execute the programs in the memory and run the hardware logic of the interrupt controller, so that the computer device executes the method according to any one of claims 1-14.

31. A computer-readable storage medium, comprising a program, characterized in that, When it runs on a computer, it causes the computer to execute the method according to any one of claims 1-14.

32. A computer program product comprising instructions, characterized in that, When it runs on a computer, it causes the computer to execute the method according to any one of claims 1-14.

33. A chip, the chip includes an interrupt controller and a data interface, characterized in that, The interrupt controller reads the instructions stored on the memory through the data interface, and / or executes the method according to any one of claims 1-9 through the hardware logic of the interrupt controller.

34. A chip, the chip comprising a processor and a data interface, characterized in that, The processor reads the instructions stored on the memory through the data interface and executes the method according to any one of claims 10-14.

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