Interrupt control device and method based on RISC-V architecture

Abstract

The invention discloses an interrupt control device and method based on an RISC-V framework, and relates to the technical field of interrupt processing. The device comprises a processor, an interrupt controller and a data preparation module; the interrupt controller is used for acquiring a first interrupt request and enabling information sent by a first interrupt source; querying data loading address information and data loading length information corresponding to the corresponding interrupt processing program based on the enabling information and an interrupt source ID corresponding to the first interrupt source; generating a first interrupt signal based on the obtained first interrupt request; the data preparation module is used for loading target data corresponding to the interrupt processing program from the memory to the data preparation module based on the enabling information, the data loading address information and the data loading length information; the processor is used for suspending the general program after the current instruction of the general program is executed; and responding to the first interrupt signal, executing an interrupt processing program, and obtaining target data corresponding to the interrupt processing program from the data preparation module.

Description

Technical Field

[0001] This application relates to the technical field of interrupt handling, and particularly to an interrupt control device and method based on the RISC-V architecture. Background Art

[0002] With the development of CPUs based on the RISC-V architecture, their applications in chips with high real-time performance are also increasing. However, when traditional CPUs based on the RISC-V architecture complete real-time tasks, especially interrupt handling tasks, since they need to wait for the current instruction of the general program to be executed first before responding to the interrupt, the time to respond to the interrupt is too long, resulting in a poor user experience. Summary of the Invention

[0003] In view of this, embodiments of this application provide an interrupt control device and method based on the RISC-V architecture.

[0004] According to the first aspect of this application, embodiments of this application provide an interrupt control device based on the RISC-V architecture, including: A processor, an interrupt controller, and a data preparation module; The interrupt controller is configured to obtain a first interrupt request and enable information sent by a first interrupt source; query corresponding data loading address information and data loading length information of an interrupt handling program based on the enable information and the interrupt source ID corresponding to the first interrupt source; send the enable information, the data loading address information, and the data loading length information to the data preparation module; and generate a first interrupt signal based on the obtained first interrupt request, and send the first interrupt signal to the processor; The data preparation module is configured to load target data corresponding to the interrupt handling program from the memory to the data preparation module based on the enable information, the data loading address information, and the data loading length information; The processor is configured to obtain the first interrupt signal, suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handling program, and obtain the target data corresponding to the interrupt handling program from the data preparation module.

[0005] Optionally, the interrupt controller is further configured to, based on the interrupt source ID, count the time interval between the first interrupt source sending interrupt requests and the time of the most recent sending of an interrupt request; predict the time when the first interrupt source will send the next interrupt request based on the time interval and the time of the most recent sending of an interrupt request; and generate enable information when the predicted time for the first interrupt source to send the next interrupt request arrives and no first interrupt request sent by the first interrupt source is obtained.

[0006] Optionally, the interrupt controller is further configured to generate a deletion signal if it fails to obtain a first interrupt request sent by the first interrupt source within the maximum time for the next interrupt request sent by the first interrupt source preset, and send the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handler from the memory into the data preparation module and deletes the target data corresponding to the interrupt handler already loaded in the data preparation module.

[0007] Optionally, the interrupt controller includes an interrupt validity judgment and priority judgment module and an interrupt pre-parsing address information table control module; The interrupt validity judgment and priority judgment module is configured to obtain a first interrupt request and enable information sent by the first interrupt source; send the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parsing address information table control module; and generate a first interrupt signal based on the obtained first interrupt request and send the first interrupt signal to the processor; The interrupt pre-parsing address information table control module is configured to query the data loading address information and data loading length information corresponding to the corresponding interrupt handler based on the enable information and the interrupt source ID corresponding to the first interrupt source; and send the enable information, the data loading address information, and the data loading length information to the data preparation module.

[0008] Optionally, the interrupt controller further includes an interrupt prediction module; The interrupt prediction module is configured to, based on the interrupt source ID, count the time interval between interrupt requests sent by the first interrupt source and the time of the most recent interrupt request sent; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request sent; and generate enable information if the predicted time of the next interrupt request sent by the first interrupt source arrives and the first interrupt request sent by the first interrupt source is not obtained.

[0009] Optionally, the data preparation module includes a control signal reception and parsing module, a data loading module, a data caching module, and an interface module; The control signal reception and parsing module is configured to receive the enable information, the data loading address information, and the data loading length information, and based on the enable information, send the data loading address information and the data loading length information to the data loading module; The data loading module is configured to load the target data corresponding to the interrupt handler from the memory into the data caching module based on the data loading address information and the data loading length information; The data caching module is configured to cache the target data corresponding to the interrupt handler; The interface module is configured to, in response to a read request from the processor, output the target data corresponding to the interrupt handler from the data caching module to the processor.

[0010] Optionally, the interrupt control device based on the RISC-V architecture includes a synchronous execution module; Before the processor finishes executing the current instruction of the general program, it is also used to, if it determines that the current instruction is a load instruction or a first store instruction, send the current instruction to the synchronous execution module for execution and respond to the first interrupt signal; The synchronous execution module is used to execute the current instruction based on the original address information, target address information, and data length information corresponding to the current instruction.

[0011] Optionally, the interrupt controller is further used to obtain a second interrupt request sent by a second interrupt source, generate a second interrupt signal based on the obtained second interrupt request, and send the second interrupt signal to the processor; The processor is further used to, in response to obtaining the second interrupt signal, when obtaining the second store instruction of the interrupt handler, send the second store instruction to the synchronous execution module for execution and respond to the second interrupt signal.

[0012] Optionally, the synchronous execution module includes: A shunt request processing module, configured to receive the current instruction sent by the processor; and when determining that the current instruction is a load instruction, send the current instruction to the load shunt control module; when determining that the current instruction is a first store instruction, send the current instruction to the store shunt control module; The load shunt control module is configured to parse the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; The store shunt control module is configured to parse the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; The address decoding module is configured to obtain the physical address information corresponding to the current instruction sent by the processor, and convert the original address information and target address information corresponding to the current instruction into physical address information; The bus interface control module is configured to execute the current instruction according to the physical address information and data length information of the current instruction.

[0013] Optionally, the processor is further used to count the frequencies of interrupt requests initiated by different interrupt sources, and store the addresses of the interrupt handlers corresponding to the target interrupt sources whose frequencies of initiating interrupt requests are greater than the threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signals corresponding to the target interrupt sources to the processor, it can synchronously send the addresses of the interrupt handlers corresponding to the target interrupt sources.

[0014] According to the second aspect of the present application, an embodiment of the present application provides an interrupt control method based on the RISC-V architecture, which is applied to an interrupt control device based on the RISC-V architecture. The device includes a processor, an interrupt controller, and a data preparation module. The method includes: The interrupt controller obtains a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, queries the data loading address information and data loading length information corresponding to the corresponding interrupt handling program; sends the enable information, data loading address information, and data loading length information to the data preparation module; and generates a first interrupt signal based on the obtained first interrupt request, and sends the first interrupt signal to the processor; The data preparation module loads the target data corresponding to the interrupt handling program from the memory to the data preparation module based on the enable information, data loading address information, and data loading length information; The processor obtains the first interrupt signal, suspends the general program after executing the current instruction of the general program; and responds to the first interrupt signal, executes the interrupt handling program, and obtains the target data corresponding to the interrupt handling program from the data preparation module.

[0015] Optionally, the interrupt control method based on the RISC-V architecture further includes: the interrupt controller statistically calculates the time interval between the first interrupt source sending interrupt requests and the time of the most recent sending of an interrupt request based on the interrupt source ID; predicts the time when the first interrupt source will send the next interrupt request based on the time interval and the time of the most recent sending of an interrupt request; and generates enable information when the predicted time for the first interrupt source to send the next interrupt request arrives and no first interrupt request sent by the first interrupt source is obtained.

[0016] Optionally, the interrupt control method based on the RISC-V architecture further includes: If the interrupt controller does not obtain the first interrupt request sent by the first interrupt source within the maximum time for the first interrupt source to send the next interrupt request preset, generates a deletion signal, and sends the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handling program from the memory to the data preparation module, and deletes the target data corresponding to the interrupt handling program that has been loaded in the data preparation module.

[0017] Optionally, the interrupt controller includes an interrupt validity judgment and priority judgment module, and an interrupt pre-parsed address information table control module; The interrupt validity judgment and priority judgment module obtains the first interrupt request and enable information sent by the first interrupt source; sends the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parsed address information table control module; and generates a first interrupt signal based on the obtained first interrupt request, and sends the first interrupt signal to the processor; The interrupt pre - parsing address information table control module queries the data loading address information and data loading length information corresponding to the corresponding interrupt handling program based on the enabling information and the interrupt source ID corresponding to the first interrupt source; and sends the enabling information, data loading address information, and data loading length information to the data preparation module.

[0018] Optionally, the interrupt controller further includes an interrupt prediction module; the interrupt control method based on the RISC - V architecture further includes: The interrupt prediction module counts the time interval of the first interrupt source sending an interrupt request and the time of the most recent sending of an interrupt request based on the interrupt source ID; predicts the time of the first interrupt source sending the next interrupt request based on the time interval and the time of the most recent sending of an interrupt request; and generates enabling information when the predicted time of the first interrupt source sending the next interrupt request arrives and the first interrupt request sent by the first interrupt source is not obtained.

[0019] Optionally, the data preparation module includes a control signal receiving and parsing module, a data loading module, a data caching module, and an interface module; The control signal receiving and parsing module receives the enabling information, data loading address information, and data loading length information, and based on the enabling information, sends the data loading address information and data loading length information to the data loading module; The data loading module loads the target data corresponding to the interrupt handling program from the memory to the data caching module based on the data loading address information and data loading length information; The data caching module caches the target data corresponding to the interrupt handling program; The interface module outputs the target data corresponding to the interrupt handling program from the data caching module to the processor in response to a read request from the processor.

[0020] Optionally, the device further includes a synchronous execution module; the interrupt control method based on the RISC - V architecture further includes: Before the processor finishes executing the current instruction of the general program, if it determines that the current instruction is a load instruction or a first store instruction, it sends the current instruction to the synchronous execution module for execution and responds to the first interrupt signal; The synchronous execution module executes the current instruction based on the original address information, target address information, and data length information corresponding to the current instruction.

[0021] Optionally, the interrupt control method based on the RISC - V architecture further includes: The interrupt controller obtains a second interrupt request sent by a second interrupt source, generates a second interrupt signal based on the obtained second interrupt request, and sends the second interrupt signal to the processor; In response to obtaining the second interrupt signal, when the processor obtains the second storage instruction of the interrupt handler, it sends the second storage instruction to the synchronous execution module for execution and responds to the second interrupt signal.

[0022] Optionally, the synchronous execution module includes a shunt request processing module, a load shunt control module, a storage shunt control module, an address decoding module, and a bus interface control module; The shunt request processing module receives the current instruction sent by the processor; and when it determines that the current instruction is a load instruction, it sends the current instruction to the load shunt control module; when it determines that the current instruction is the first storage instruction, it sends the current instruction to the storage shunt control module; The load shunt control module parses the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; The storage shunt control module parses the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; The address decoding module obtains the physical address information corresponding to the current instruction sent by the processor and converts the original address information and target address information corresponding to the current instruction into physical address information; The bus interface control module executes the current instruction according to the physical address information and data length information of the current instruction.

[0023] Optionally, the interrupt control method based on the RISC-V architecture further includes: The processor counts the frequencies of interrupt requests initiated by different interrupt sources and stores the addresses of the interrupt handlers corresponding to the target interrupt sources with interrupt request frequencies greater than the threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signals corresponding to the target interrupt sources to the processor, it can synchronously send the addresses of the interrupt handlers corresponding to the target interrupt sources.

[0024] The interrupt control device and method based on the RISC-V architecture provided by the embodiments of the present application set a processor, an interrupt controller, and a data preparation module; the interrupt controller is used to obtain a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, query the data loading address information and data loading length information corresponding to the corresponding interrupt handling program; send the enable information, data loading address information, and data loading length information to the data preparation module; and generate a first interrupt signal based on the obtained first interrupt request, and send the first interrupt signal to the processor; the data preparation module is used to load the target data corresponding to the interrupt handling program from the memory to the data preparation module based on the enable information, data loading address information, and data loading length information; the processor is used to obtain the first interrupt signal, suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handling program, and obtain the target data corresponding to the interrupt handling program from the data preparation module; thus, when the processor executes the current instruction of the general program, the data preparation module can synchronously load the target data required when the interrupt handling program is executed from the memory to the data preparation module, which is convenient for the processor to no longer obtain the target data required by the interrupt handling program from the memory after executing the current instruction of the general program, greatly reducing the time for the processor to obtain the target data required by the interrupt handling program, and can greatly improve the execution speed of the processor executing the interrupt handling program, thereby accelerating the response speed of the interrupt request and improving the user experience.

[0025] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically exemplified below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic hardware structure diagram of an interrupt control device based on the RISC-V architecture in an embodiment of the present application; Figure 2 It is a schematic structure diagram of the interrupt controller in an embodiment of the present application; Figure 3 It is a schematic structure diagram of the data preparation module in an embodiment of the present application; Figure 4 It is a schematic hardware structure diagram of another interrupt control device based on the RISC-V architecture in an embodiment of the present application; Figure 5 It is a schematic structure diagram of the synchronous execution module in an embodiment of the present application; Figure 6 It is a schematic flow diagram of an interrupt control method based on the RISC-V architecture in an embodiment of the present application. Detailed implementation manners

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, rather than all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0028] The embodiment of the present application provides an interrupt control device based on the RISC-V architecture, as Figure 1 shown, including: a processor 11, an interrupt controller 12, and a data preparation module 13.

[0029] The interrupt controller 12 is configured to obtain a first interrupt request and enable information sent by a first interrupt source; query corresponding data loading address information and data loading length information of an interrupt handling program based on the enable information and the interrupt source ID corresponding to the first interrupt source; send the enable information, the data loading address information, and the data loading length information to the data preparation module 13; and generate a first interrupt signal based on the obtained first interrupt request, and send the first interrupt signal to the processor 11.

[0030] The data preparation module 13 is configured to load target data corresponding to the interrupt handling program from the memory to the data preparation module 13 based on the enable information, the data loading address information, and the data loading length information.

[0031] The processor 11 is configured to obtain the first interrupt signal, suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handling program, and obtain the target data corresponding to the interrupt handling program from the data preparation module.

[0032] In this embodiment, the interrupt control device based on the RISC-V architecture may be a CPU based on the RISC-V architecture, or a chip, an electronic device, etc. including a CPU based on the RISC-V architecture.

[0033] In this embodiment, as Figure 1 shown, the processor 11 may include at least one processor core (RISC-V Core), and a first-level cache unit (L1 Cache) exclusive to the processor core and a second-level cache unit (L2 Cache) shared by the processor cores.

[0034] In this embodiment, the address of the first instruction for the power-on reset of the RISC-V Core points to the starting address of the interrupt vector table cached in the memory, and pre-execution processing is performed on all interrupt handlers indicated in the interrupt vector table. By pre-execution, it means pre-executing the load instructions in the interrupt handlers, that is, only monitoring the starting address (Load_addr) and load length (Load_Length) of the load instructions in all interrupt handlers, and creating an interrupt pre-parsing address information table as shown in Table 1 below according to the interrupt source ID (Inter_ID) corresponding to the interrupt handler. After completing the preprocessing of all interrupt handlers, the RISC-V Core jumps to the starting address of the regular program again for normal operation, and caches the interrupt pre-parsing address information table in the interrupt controller 12.

[0035] Table 1

[0036] In some embodiments, as Figure 2 shown, the interrupt controller 12 may include an interrupt validity judgment and priority judgment module, and an interrupt pre-parsing address information table control module. The interrupt validity judgment and priority judgment module is used to obtain the first interrupt request and enable information sent by the first interrupt source; send the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parsing address information table control module; and generate a first interrupt signal based on the obtained first interrupt request and send the first interrupt signal to the processor; the interrupt pre-parsing address information table control module is used to query the corresponding data loading address information and data loading length information of the interrupt handler based on the enable information and the interrupt source ID corresponding to the first interrupt source; and send the enable information, data loading address information and data loading length information to the data preparation module.

[0037] Specifically, when implemented, after the interrupt validity judgment and priority judgment module of the interrupt controller 12 obtains the first interrupt request and enable information sent by the first interrupt source, it performs an interrupt enable information judgment. After judgment, if the first interrupt request is normally enabled, a first interrupt signal is generated to the RISC-V Core.

[0038] The interrupt pre-parsing address information table and control module of the interrupt controller 12 queries the interrupt pre-parsing address information table based on the enable information and the ID information of the first interrupt source, and finds the corresponding data loading address information and data loading length information of the interrupt handler. And send the enable information, data loading address information and data loading length information to the data preparation module 13.

[0039] In this embodiment, the data preparation module 13 is used to initiate a direct memory access (DMA) operation based on the enable information, and load the target data corresponding to the data load address information and the data load length information from the memory into the data preparation module 13 in advance, so that when the RISC-V Core officially processes the first interrupt signal, it can directly obtain the data used by the Load instruction from the data preparation module, without having to load it from the memory again. Among them, the Load instruction is very clock cycle-consuming, and one memory operation requires dozens or even hundreds of clock cycles, thus greatly accelerating the processing speed of the interrupt handling program.

[0040] The interrupt control device based on the RISC-V architecture provided by the embodiments of the present application sets a processor, an interrupt controller, and a data preparation module; the interrupt controller is used to obtain the first interrupt request and the enable information sent by the first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, query the data load address information and the data load length information corresponding to the corresponding interrupt handling program; send the enable information, the data load address information, and the data load length information to the data preparation module; and generate a first interrupt signal based on the obtained first interrupt request, and send the first interrupt signal to the processor; the data preparation module is used to load the target data corresponding to the interrupt handling program from the memory into the data preparation module based on the enable information, the data load address information, and the data load length information; the processor is used to obtain the first interrupt signal, suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handling program, and obtain the target data corresponding to the interrupt handling program from the data preparation module; thus, when the processor executes the current instruction of the general program, the data preparation module can synchronously load the target data required when the interrupt handling program is executed from the memory into the data preparation module, so that after the processor executes the current instruction of the general program, it does not have to obtain the target data required by the interrupt handling program from the memory again, greatly reducing the time for the processor to obtain the target data required by the interrupt handling program, and can greatly improve the execution speed of the processor when executing the interrupt handling program, thereby accelerating the response speed of the interrupt request and improving the user experience.

[0041] In an optional embodiment, the interrupt controller 12 is further used to count the time interval between the interrupt requests sent by the first interrupt source and the time of the most recent interrupt request based on the interrupt source ID; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generate the enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and the first interrupt request sent by the first interrupt source is not obtained.

[0042] In this embodiment, the interrupt controller 12 may also have a function of predicting and processing interrupts.

[0043] During specific implementation, as Figure 2 shown, the interrupt controller may further include an interrupt prediction module. The interrupt prediction module is used to count the time interval between the interrupt requests sent by the first interrupt source and the time of the most recent interrupt request based on the interrupt source ID; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generate enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and the first interrupt request sent by the first interrupt source is not obtained. For example, the interrupt prediction module may record the time interval between the interrupt requests initiated by the interrupt source, T_0---T_N-1 (record N times, N can be a default value or a register configuration), and perform a weighted average on the N intervals: T_mid = T_0×PARAM_0 + T_1×PARAM_1……T_N-1×PARAM_N-1; where it is required that PARAM_0 < PARAM_1 < PARAM_2……PARAM_N-1, that is, the closer to the current moment, the greater its weight.

[0044] When N statistics are completed, T_mid is obtained, and the time T_Cur when the Nth interrupt request occurs is recorded. When the time (T_Cur + T_mid) of the next interrupt request arrives and the corresponding interrupt source has not initiated an interrupt request for the time being, the interrupt prediction module will issue enable information, that is, pre_inter_en, and use this enable information as a query signal to input to the interrupt pre-parse address information table and the control module, and then perform the address and length query of the corresponding Load instruction. Then, the enable information, the address and length of the corresponding Load instruction are passed to the data preparation module.

[0045] At the same time, the interrupt prediction module is also used to perform feedback adjustment on the interrupt prediction mechanism, and monitor in real time whether there is another interrupt from the predicted interrupt source: The interrupt prediction module is also used to generate a deletion signal when the first interrupt request sent by the first interrupt source is not obtained within the maximum time of the next interrupt request sent by the first interrupt source preset, and send the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handling program from the memory to the data preparation module, and deletes the target data corresponding to the interrupt handling program already loaded in the data preparation module.

[0046] That is, if the maximum time for the next interrupt request (T_Cur + T_max) (T_max can use the default value or be configured through registers), and the corresponding interrupt source has not yet issued a real interrupt request, a deletion signal pre_inter_detect is generated to indicate that the current predicted interrupt is incorrect. The pre_inter_detect signal is also passed to the interrupt pre-parse address information table and the control module, and then to the data preparation module, pausing the ongoing Load operation and deleting the data that has been Loaded back. At the same time, the prediction formula is feedback modified as follows: T_mid = T_0×PARAM_0 + T_1×PARAM_1……T_N-1×PARAM_N-1. Expand the relevant parameters and expand T_max at the same time.

[0047] If the corresponding interrupt source has issued an interrupt request before the time of T_Cur + T_max, and at this time the data preparation module has normally performed the loading operation, then feedback to the interrupt pre-parse address information table and the control module, and it is no longer necessary to send the enable information, data loading address information, and data loading length information to the data preparation module. And feedback to modify the prediction formula as follows: T_mid = T_0×PARAM_0 + T_1×PARAM_1……T_N-1×PARAM_N-1. Shrink the relevant parameters and shrink T_max at the same time.

[0048] In this embodiment, the interrupt controller can realize the anticipation of the interrupt request in advance. When the time of the predicted interrupt request arrives, it can trigger the preparation of the target data of the corresponding interrupt handling program, instead of waiting until the actual interrupt request arrives to trigger the preparation of the target data, which can further improve the execution speed of the processor executing the interrupt handling program, thereby accelerating the response speed of the interrupt request.

[0049] In an alternative embodiment, as Figure 3 shown, the data preparation module 13 includes a control signal receiving and parsing module 131, a data loading module 132, a data caching module 133, and an interface module 134.

[0050] The control signal receiving and parsing module 131 is used to receive the enable information, data loading address information, and data loading length information, and based on the enable information, send the data loading address information and data loading length information to the data loading module.

[0051] The data loading module 132 is used to load the target data corresponding to the interrupt handling program from the memory to the data caching module based on the data loading address information and data loading length information.

[0052] The data cache module 133 is used to cache the target data corresponding to the interrupt handler.

[0053] The interface module 134 is used to respond to the read request of the processor, and output the target data corresponding to the interrupt handler from the data cache module to the processor.

[0054] In this embodiment, the control signal receiving and parsing module 131 can also receive a deletion signal, send the deletion signal to the data loading module 132. The data loading module 132 stops loading data from the memory based on the deletion signal. The control signal receiving and parsing module 131 also sends the deletion signal to the data cache module 133. The data cache module 133 deletes the corresponding stored data based on the deletion signal.

[0055] In this embodiment, by setting that the data preparation module includes multiple sub-modules, each sub-module can operate mutually or independently, so as to quickly realize the function of the data preparation module.

[0056] In an alternative embodiment, as Figure 4 shown, the interrupt control device based on the RISC-V architecture includes a synchronous execution module 14.

[0057] Before the processor 11 finishes executing the current instruction of the general program, it is also used to, if it is determined that the current instruction is a load instruction or a first store instruction, send the current instruction to the synchronous execution module 14 for execution, and respond to the first interrupt signal.

[0058] The synchronous execution module 14 is used to execute the current instruction based on the original address information, target address information and data length information corresponding to the current instruction.

[0059] During specific implementation, after the interrupt controller 12 obtains the first interrupt request, the RISC-V Core needs to finish the current instruction of the general program and then respond to the first interrupt request. However, if the RISC-V Core is running a load instruction or a store instruction of the general program at this time, the completion of these two instructions usually requires hundreds of clock cycles. To accelerate the response speed to interrupts, in this embodiment, if the RISC-V Core is not running a load / store instruction of the general program, it can suspend the general program after executing the current instruction of the general program, respond to the first interrupt signal, and execute the interrupt handler. If the RISC-V Core is running a load / store instruction of the general program, the execution of the load / store instruction can be diverted to the synchronous execution module 14 to complete, and the RISC-V Core can immediately respond to the first interrupt signal. In this way, the processor 11 does not need to wait until the current instruction of the general program is executed before responding to the first interrupt request, and the response speed to the first interrupt signal can be accelerated.

[0060] In some embodiments, the specific architecture of the synchronous execution module is as Figure 5 shown, including: A diversion request processing module 141, configured to receive the current instruction sent by the processor; and when determining that the current instruction is a load instruction, send the current instruction to the load diversion control module 142; when determining that the current instruction is a first store instruction, send the current instruction to the store diversion control module 143.

[0061] The load diversion control module 142 is configured to parse the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction.

[0062] The store diversion control module 143 is configured to parse the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction.

[0063] An address decoding module 144, configured to obtain the physical address information corresponding to the current instruction sent by the processor, and convert the original address information and target address information corresponding to the current instruction into physical address information; A bus interface control module 145, configured to execute the current instruction according to the physical address information and data length information of the current instruction.

[0064] In this embodiment, the shunt request processing module 141 is used to receive the shunt request of the RISC-V Core and monitor whether the load shunt control module 142 and the store shunt control module 143 are idle. The load shunt control module 142 is used to parse the relevant information of the Load instruction transmitted by the RISC-V Core, including the source address, destination address, length, etc. of the Load. Its source address is the memory address, and the destination address is the buffer cache inside the RISC-V Core. The store shunt control module 143 is used to parse the relevant information of the Store instruction transmitted by the RISC-V Core, including the source address, destination address, length, etc. of the Store. Its source address is the RISC-V Core buffer space, and the destination address is the memory address. The address decoding module 144, because the virtual address is obtained when the RISC-V Core executes the Load instruction or the Store instruction, and the physical address is required for the operation with the memory, so what the address decoding module 144 needs to complete is the conversion between the virtual address and the physical address of the Load / Store instruction. In this embodiment, the RISC-V Core also has a function that when the first interrupt processing request is obtained, within the same clock cycle, the physical address of the current Load / Store instruction is queried in the memory management unit (MMU), and the physical address is synchronously sent to the address decoding module 144 of the synchronous execution module. The bus interface control module 145 forms the interface timing corresponding to the RISC-V Core interface and the memory bus interface. When the Load instruction is executed, a read operation on the memory is initiated according to the converted physical address, and the read-back data is written back to the internal cache of the RISC-V Core. When the Store instruction is executed, the internal cache data in the RISC-V Core is read, and a write operation on the memory is initiated by writing to the converted physical address.

[0065] In this embodiment, by setting the synchronous execution module to include multiple sub-modules, the multiple sub-modules can operate independently or jointly, which is convenient for realizing the function of the synchronous execution module faster.

[0066] In some embodiments, the interrupt controller 12 is further used to obtain the second interrupt request sent by the second interrupt source, generate a second interrupt signal based on the obtained second interrupt request, and send the second interrupt signal to the processor 11.

[0067] The processor 11 is further used to respond to the acquisition of the second interrupt signal, and when the second store instruction of the interrupt handling program is obtained, send the second store instruction to the synchronous execution module 14 for execution and respond to the second interrupt signal.

[0068] In this embodiment, after the interrupt controller 12 transmits the first interrupt signal corresponding to the first interrupt source to the RISC-V Core, before the first interrupt signal is completely processed, if the interrupt controller 12 receives a second interrupt request from the second interrupt source, it will still generate a second interrupt signal and transmit the second interrupt signal to the RISC-V Core.

[0069] In this embodiment, when the RISC-V Core receives the first interrupt signal transmitted by the interrupt controller 12 and executes the interrupt handling program in response to the first interrupt signal, when it encounters a Store instruction (this instruction writes data from the RISC-V Core to the memory, which takes a long time, and one piece of data requires hundreds of clock cycles, and Store instructions usually require multiple data transmissions), it will transfer the execution operation of the Store instruction of the interrupt handling program to the synchronous execution module 14 for execution. Thus, the RISC-V core can continue to respond to the second interrupt signal and execute the interrupt handling program corresponding to the second interrupt signal (because the instruction fetching, decoding and other hardware units in the RISC-V Core are idle at this time). After the Load instruction corresponding to the first interrupt signal is executed, the RISC-V core saves the execution status of the instruction corresponding to the second interrupt signal and the values of relevant registers to the synchronous execution module 14, so that the RISC-V core can continue to execute the interrupt handling program corresponding to the first interrupt signal. Until the next Store instruction of the interrupt handling program corresponding to the first interrupt signal is executed, the RISC-V Core reloads the status of the instruction of the interrupt handling program corresponding to the second interrupt signal and the values of relevant registers back to the RISC-V Core, and at the same time, it distributes the execution of the Store instruction corresponding to the first interrupt signal to the synchronous execution module 14 for processing.

[0070] In this embodiment, it is possible to realize the synchronous parallel execution of different interrupt handling programs corresponding to different interrupt sources, which can ensure that high-priority interrupt requests and medium-priority interrupt requests can be synchronously responded to, and both have high real-time performance, thereby further ensuring and improving the overall real-time performance of the RISC-V Core.

[0071] In an alternative embodiment, the processor is further configured to count the frequencies of interrupt requests initiated by different interrupt sources, and store the addresses of the interrupt handling programs corresponding to the target interrupt sources whose interrupt request frequencies are greater than the threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signals corresponding to the target interrupt sources to the processor, it can synchronously send the addresses of the interrupt handling programs corresponding to the target interrupt sources.

[0072] In this embodiment, in order to further accelerate the execution speed of the RISC-V Core for the interrupt handler, the RISC-V Core has an additional main function, which is to monitor the frequency of interrupt requests initiated by the interrupt source, and copy the address of the interrupt handler with a higher interrupt request (this address is in the interrupt vector table and in the memory DDR) to the inside of the interrupt controller through the L1 Cache. Thus, when the interrupt controller transmits the interrupt signal to the RISC-V Core, it also synchronously transmits the address of the interrupt handler corresponding to the interrupt signal to the RISC-V Core, avoiding the step of the RISC-V Core querying the memory to obtain the interrupt handler address, which also takes dozens or even hundreds of clock cycles; thereby greatly accelerating the execution speed of the interrupt handler and further enhancing the real-time processing ability of the RISC-V CPU.

[0073] An embodiment of the present application provides an interrupt control method based on the RISC-V architecture, which is applied to an interrupt control device based on the RISC-V architecture. The device includes a processor, an interrupt controller, and a data preparation module, as Figure 6 shown. The interrupt control method based on the RISC-V architecture includes: S601, the interrupt controller obtains a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, queries the corresponding data loading address information and data loading length information of the interrupt handler; sends the enable information, data loading address information, and data loading length information to the data preparation module; and generates a first interrupt signal based on the obtained first interrupt request, and sends the first interrupt signal to the processor.

[0074] S602, the data preparation module loads the target data corresponding to the interrupt handler from the memory to the data preparation module based on the enable information, data loading address information, and data loading length information.

[0075] S603, the processor obtains the first interrupt signal, suspends the general program after executing the current instruction of the general program; and responds to the first interrupt signal, executes the interrupt handler, and obtains the target data corresponding to the interrupt handler from the data preparation module.

[0076] For a detailed description of the embodiments of the present application, please refer to the above-mentioned interrupt control device based on the RISC-V architecture, and details will not be repeated here.

[0077] The interrupt control method based on the RISC-V architecture provided by the embodiments of the present application sets a processor, an interrupt controller, and a data preparation module; the interrupt controller is used to obtain a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, query the data loading address information and data loading length information corresponding to the corresponding interrupt handling program; send the enable information, data loading address information, and data loading length information to the data preparation module; and generate a first interrupt signal based on the obtained first interrupt request and send the first interrupt signal to the processor; the data preparation module is used to load the target data corresponding to the interrupt handling program from the memory to the data preparation module based on the enable information, data loading address information, and data loading length information; the processor is used to obtain the first interrupt signal, suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handling program, and obtain the target data corresponding to the interrupt handling program from the data preparation module; thus, when the processor executes the current instruction of the general program, the data preparation module can synchronously load the target data required when the interrupt handling program is executed from the memory to the data preparation module, which is convenient for the processor to no longer need to obtain the target data required by the interrupt handling program from the memory after executing the current instruction of the general program, greatly reducing the time for the processor to obtain the target data required by the interrupt handling program, and can greatly improve the execution speed of the processor executing the interrupt handling program, thereby accelerating the response speed of the interrupt request and improving the user experience.

[0078] In an optional embodiment, the interrupt controller counts the time interval between the first interrupt source sending interrupt requests and the time of the most recent sending of an interrupt request based on the interrupt source ID; predicts the time when the first interrupt source will send the next interrupt request based on the time interval and the time of the most recent sending of an interrupt request; and generates enable information when the predicted time for the first interrupt source to send the next interrupt request arrives and the first interrupt request sent by the first interrupt source is not obtained.

[0079] In an optional embodiment, the interrupt control method based on the RISC-V architecture further includes: If the interrupt controller does not obtain the first interrupt request sent by the first interrupt source within the maximum time for the first interrupt source to send the next interrupt request preset, it generates a deletion signal and sends the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handling program from the memory to the data preparation module and deletes the target data corresponding to the interrupt handling program already loaded in the data preparation module.

[0080] In an optional embodiment, the interrupt controller includes an interrupt validity judgment and priority judgment module, and an interrupt pre-parsing address information table control module.

[0081] The interrupt validity judgment and priority judgment module obtains the first interrupt request and enabling information sent by the first interrupt source; sends the enabling information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parsing address information table control module; and generates a first interrupt signal based on the obtained first interrupt request, and sends the first interrupt signal to the processor; the interrupt pre-parsing address information table control module queries the data loading address information and data loading length information corresponding to the corresponding interrupt handling program based on the enabling information and the interrupt source ID corresponding to the first interrupt source; and sends the enabling information, data loading address information and data loading length information to the data preparation module.

[0082] In an alternative embodiment, the interrupt controller further includes an interrupt prediction module; the interrupt control method based on the RISC-V architecture further includes: The interrupt prediction module counts the time interval between the interrupt requests sent by the first interrupt source and the time of the most recent interrupt request based on the interrupt source ID; predicts the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generates enabling information when the predicted time of the next interrupt request sent by the first interrupt source arrives and the first interrupt request sent by the first interrupt source is not obtained.

[0083] In an alternative embodiment, the data preparation module includes a control signal reception and parsing module, a data loading module, a data cache module and an interface module; The control signal reception and parsing module receives the enabling information, data loading address information and data loading length information, and based on the enabling information, sends the data loading address information and data loading length information to the data loading module; the data loading module loads the target data corresponding to the interrupt handling program from the memory to the data cache module based on the data loading address information and data loading length information; the data cache module caches the target data corresponding to the interrupt handling program; the interface module outputs the target data corresponding to the interrupt handling program from the data cache module to the processor in response to a read request from the processor.

[0084] In an alternative embodiment, the device further includes a synchronous execution module; the interrupt control method based on the RISC-V architecture further includes: Before the processor finishes executing the current instruction of the general program, if it is determined that the current instruction is a load instruction or a first store instruction, the current instruction is sent to the synchronous execution module for execution and responds to the first interrupt signal; the synchronous execution module executes the current instruction based on the original address information, target address information and data length information corresponding to the current instruction.

[0085] In an alternative embodiment, the interrupt control method based on the RISC-V architecture further includes: The interrupt controller receives a second interrupt request sent by a second interrupt source, generates a second interrupt signal based on the received second interrupt request, and sends the second interrupt signal to the processor; in response to receiving the second interrupt signal, when the processor receives a second storage instruction of the interrupt handler, it sends the second storage instruction to the synchronous execution module for execution and responds to the second interrupt signal.

[0086] In an alternative embodiment, the synchronous execution module includes a shunt request processing module, a load shunt control module, a storage shunt control module, an address decoding module, and a bus interface control module.

[0087] The shunt request processing module receives the current instruction sent by the processor; and when determining that the current instruction is a load instruction, it sends the current instruction to the load shunt control module; when determining that the current instruction is a first storage instruction, it sends the current instruction to the storage shunt control module; the load shunt control module parses the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; the storage shunt control module parses the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; the address decoding module obtains the physical address information corresponding to the current instruction sent by the processor, and converts the original address information and target address information corresponding to the current instruction into physical address information; the bus interface control module executes the current instruction according to the physical address information and data length information of the current instruction.

[0088] In an alternative embodiment, the interrupt control method based on the RISC-V architecture further includes: The processor counts the frequencies of interrupt requests initiated by different interrupt sources, and stores the addresses of the interrupt handlers corresponding to the target interrupt sources whose interrupt request frequencies are greater than the threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signals corresponding to the target interrupt sources to the processor, it can synchronously send the addresses of the interrupt handlers corresponding to the target interrupt sources.

[0089] It should be understood that the various forms of the flow shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in this application can be achieved, and no limitations are imposed herein.

[0090] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, "a plurality" means two or more, unless otherwise specifically defined.

[0091] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claimed rights.

Claims

1. An interrupt control device based on the RISC-V architecture, characterized in that, Comprising: A processor, an interrupt controller, and a data preparation module; The interrupt controller is used to obtain a first interrupt request and enable information sent by a first interrupt source; Based on the enable information and the interrupt source ID corresponding to the first interrupt source, query the data loading address information and data loading length information corresponding to the corresponding interrupt handling program; Send the enable information, the data loading address information, and the data loading length information to the data preparation module; and generate a first interrupt signal based on the obtained first interrupt request, and send the first interrupt signal to the processor; The data preparation module is used to load the target data corresponding to the interrupt handling program from the memory to the data preparation module based on the enable information, the data loading address information, and the data loading length information; The processor is used to obtain the first interrupt signal, and suspend the general program after executing the current instruction of the general program; And respond to the first interrupt signal, execute the interrupt handling program, and obtain the target data corresponding to the interrupt handling program from the data preparation module.

2. The interrupt control device based on the RISC-V architecture according to claim 1, wherein The interrupt controller is further used to, based on the interrupt source ID, count the time interval between the interrupt requests sent by the first interrupt source and the time of the most recent interrupt request sent; based on the time interval and the time of the most recent interrupt request sent, predict the time of the next interrupt request sent by the first interrupt source; and generate the enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and the first interrupt request sent by the first interrupt source is not obtained.

3. The interrupt control device based on the RISC-V architecture according to claim 2, wherein The interrupt controller is further used to generate a deletion signal when the first interrupt request sent by the first interrupt source is not obtained within the maximum time of the next interrupt request sent by the first interrupt source preset, and send the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handling program from the memory to the data preparation module, and deletes the target data corresponding to the interrupt handling program already loaded in the data preparation module.

4. The interrupt control device based on the RISC-V architecture according to claim 1, characterized in that The interrupt controller includes an interrupt validity judgment and priority judgment module, and an interrupt pre-parsing address information table control module; The interrupt validity judgment and priority judgment module is used to obtain a first interrupt request and enable information sent by a first interrupt source; send the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parsing address information table control module; and generate a first interrupt signal based on the obtained first interrupt request, and send the first interrupt signal to the processor; The interrupt pre-parsing address information table control module is used to query the data loading address information and data loading length information corresponding to the corresponding interrupt handling program based on the enable information and the interrupt source ID corresponding to the first interrupt source; Send the enabling information, the data loading address information, and the data loading length information to the data preparation module.

5. The interrupt control device based on the RISC-V architecture according to claim 4, wherein The interrupt controller further includes an interrupt prediction module; The interrupt prediction module is configured to, based on the interrupt source ID, count the time interval between the interrupt requests sent by the first interrupt source and the time of the most recent interrupt request sent; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request sent; and generate the enabling information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request sent by the first interrupt source is obtained.

6. The interrupt control device based on the RISC-V architecture according to claim 1, characterized in that, The data preparation module includes a control signal receiving and parsing module, a data loading module, a data caching module, and an interface module; The control signal receiving and parsing module is configured to receive the enabling information, the data loading address information, and the data loading length information, and based on the enabling information, send the data loading address information and the data loading length information to the data loading module; The data loading module is configured to, based on the data loading address information and the data loading length information, load the target data corresponding to the interrupt handling program from the memory to the data caching module; The data caching module is configured to cache the target data corresponding to the interrupt handling program; The interface module is configured to, in response to a read request from the processor, output the target data corresponding to the interrupt handling program from the data caching module to the processor.

7. The interrupt control device based on the RISC-V architecture according to claim 1, characterized in that, It further includes a synchronous execution module; Before the processor finishes executing the current instruction of the general program, if it is determined that the current instruction is a load instruction or a first store instruction, the processor is further configured to send the current instruction to the synchronous execution module for execution and respond to the first interrupt signal; The synchronous execution module is configured to execute the current instruction based on the original address information, the target address information, and the data length information corresponding to the current instruction.

8. The interrupt control device based on the RISC-V architecture according to claim 7, wherein The interrupt controller is further configured to obtain a second interrupt request sent by a second interrupt source, generate a second interrupt signal based on the obtained second interrupt request, and send the second interrupt signal to the processor; The processor is further configured to, in response to obtaining the second interrupt signal, when obtaining the second store instruction of the interrupt handling program, send the second store instruction to the synchronous execution module for execution and respond to the second interrupt signal.

9. The interrupt control device based on the RISC-V architecture according to claim 7, characterized in that The synchronous execution module includes: A shunt request processing module, configured to receive the current instruction sent by the processor; and when it is determined that the current instruction is the load instruction, send the current instruction to the load shunt control module; when it is determined that the current instruction is the first store instruction, send the current instruction to the store shunt control module; The load shunt control module is configured to parse the current instruction to obtain the original address information, the target address information, and the data length information corresponding to the current instruction; A storage shunt control module for parsing the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; An address decoding module for obtaining the physical address information corresponding to the current instruction sent by the processor and converting the original address information and target address information corresponding to the current instruction into the physical address information; A bus interface control module for executing the current instruction according to the physical address information and the data length information of the current instruction.

10. The interrupt control device based on the RISC-V architecture according to claim 1, characterized in that The processor is further configured to count the frequencies of interrupt requests initiated by different interrupt sources, and store the addresses of the interrupt handling programs corresponding to the target interrupt sources with interrupt request frequencies greater than the threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signals corresponding to the target interrupt sources to the processor, the addresses of the interrupt handling programs corresponding to the target interrupt sources can be synchronously sent.

11. An interrupt control method based on the RISC-V architecture, characterized in that, Applied to an interrupt control device based on the RISC-V architecture, the device includes a processor, an interrupt controller, and a data preparation module, and the method includes: The interrupt controller obtains a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, queries the data loading address information and data loading length information corresponding to the corresponding interrupt handling program; sends the enable information, the data loading address information, and the data loading length information to the data preparation module; and generates a first interrupt signal based on the obtained first interrupt request and sends the first interrupt signal to the processor; The data preparation module loads the target data corresponding to the interrupt handling program from the memory to the data preparation module based on the enable information, the data loading address information, and the data loading length information; The processor obtains the first interrupt signal, suspends the general program after executing the current instruction of the general program; and responds to the first interrupt signal, executes the interrupt handling program, and obtains the target data corresponding to the interrupt handling program from the data preparation module.

12. The interrupt control method based on the RISC-V architecture according to claim 11, wherein Further includes: The interrupt controller counts the time interval between the interrupt requests sent by the first interrupt source and the time of the most recent interrupt request based on the interrupt source ID; Based on the time interval and the time of the most recent interrupt request, predicts the time of the next interrupt request sent by the first interrupt source; and generates the enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and the first interrupt request sent by the first interrupt source is not obtained.

13. The interrupt control method based on the RISC-V architecture according to claim 12, wherein, Further includes: If the interrupt controller does not receive the first interrupt request sent by the first interrupt source within the maximum time for the next interrupt request of the preset first interrupt source, it generates a deletion signal and sends the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handler from the memory into the data preparation module and deletes the target data corresponding to the interrupt handler that has been loaded in the data preparation module.

14. The interrupt control method based on the RISC-V architecture according to claim 11, characterized in that The interrupt controller includes an interrupt validity judgment and priority judgment module and an interrupt pre-parsing address information table control module; The interrupt validity judgment and priority judgment module receives the first interrupt request and the enabling information sent by the first interrupt source; sends the enabling information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parsing address information table control module; and generates a first interrupt signal based on the received first interrupt request and sends the first interrupt signal to the processor; The interrupt pre-parsing address information table control module queries the data loading address information and data loading length information corresponding to the corresponding interrupt handler based on the enabling information and the interrupt source ID corresponding to the first interrupt source; Sends the enabling information, the data loading address information, and the data loading length information to the data preparation module.

15. The interrupt control method based on the RISC-V architecture according to claim 14, wherein The interrupt controller further includes an interrupt prediction module; the method further includes: The interrupt prediction module counts the time interval between the interrupt requests sent by the first interrupt source and the time of the most recent interrupt request based on the interrupt source ID; predicts the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generates the enabling information when the predicted time of the next interrupt request sent by the first interrupt source arrives and the first interrupt request sent by the first interrupt source is not received.

16. The interrupt control method based on the RISC-V architecture according to claim 14, wherein The data preparation module includes a control signal reception and parsing module, a data loading module, a data caching module, and an interface module; The control signal reception and parsing module receives the enabling information, the data loading address information, and the data loading length information, and based on the enabling information, sends the data loading address information and the data loading length information to the data loading module; The data loading module loads the target data corresponding to the interrupt handler from the memory into the data caching module based on the data loading address information and the data loading length information; The data caching module caches the target data corresponding to the interrupt handler; The interface module outputs the target data corresponding to the interrupt handler from the data caching module to the processor in response to a read request from the processor.

17. The interrupt control method based on the RISC-V architecture according to claim 11, wherein The device further includes a synchronous execution module; the method further includes: Before the processor finishes executing the current instruction of the general program, if it determines that the current instruction is a load instruction or a first storage instruction, it sends the current instruction to the synchronous execution module for execution and responds to the first interrupt signal; The synchronization execution module executes the current instruction based on the original address information, target address information, and data length information corresponding to the current instruction.

18. The interrupt control method based on the RISC-V architecture according to claim 17, characterized in that, It further includes: The interrupt controller obtains a second interrupt request sent by a second interrupt source, generates a second interrupt signal based on the obtained second interrupt request, and sends the second interrupt signal to the processor; The processor, in response to obtaining the second interrupt signal, when obtaining a second storage instruction of the interrupt handler, sends the second storage instruction to the synchronization execution module for execution and responds to the second interrupt signal.

19. The interrupt control method based on the RISC-V architecture according to claim 17, characterized in that, The synchronization execution module includes a shunt request processing module, a load shunt control module, a storage shunt control module, an address decoding module, and a bus interface control module; The shunt request processing module receives the current instruction sent by the processor; and when determining that the current instruction is the load instruction, sends the current instruction to the load shunt control module; when determining that the current instruction is the first storage instruction, sends the current instruction to the storage shunt control module; The load shunt control module parses the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; The storage shunt control module parses the current instruction to obtain the original address information, target address information, and data length information corresponding to the current instruction; The address decoding module obtains the physical address information corresponding to the current instruction sent by the processor, and converts the original address information and target address information corresponding to the current instruction into the physical address information; The bus interface control module executes the current instruction according to the physical address information and data length information of the current instruction.

20. The interrupt control method based on the RISC-V architecture according to claim 11, characterized in that, It further includes: The processor counts the frequencies of interrupt requests initiated by different interrupt sources, and stores the addresses of the interrupt handlers corresponding to the target interrupt sources whose frequencies of initiating interrupt requests are greater than a threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signal corresponding to the target interrupt source to the processor, it can synchronously send the address of the interrupt handler corresponding to the target interrupt source.

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