Data processing method and device, chip and electronic equipment
By using a larger buffer with storage units for data transmission during cache miss, the problem of low bandwidth utilization during cache miss is solved and system performance is improved.
Patent Information
- Application Number
- CN202410133785.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-30
- Publication Date
- 2025-08-01
AI Technical Summary
In the prior art, the transmission of data from the main memory to the cache when the cache is missed requires a fixed length command, address and dummy, resulting in low bandwidth utilization.
In the case of a cache miss, the amount of data transmitted at one time is increased by using a buffer with a storage unit larger than the cache line.
Improve bandwidth utilization, reduce unnecessary command and address transmission time, and improve system performance.
Smart Images
Figure CN120407135A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of data processing, and in particular, to a data processing method, apparatus, chip, and electronic device. Background Art
[0002] In order to improve the access speed, reduce the load on the main memory, and balance the system performance, many chips interact with the main memory through an intermediate cache unit.
[0003] In the related art, when a cache miss occurs, it is usually necessary to transfer data from the main memory to the cache. Each time data is transferred, a fixed-length command, address, and dummy (an address or command used as a placeholder) need to be sent before the cache can receive the data. To read a cache line of data, whose storage unit is generally 32 bytes, taking an 8-bit dual-edge main memory as an example, the command, address, and dummy approximately require 7 clks (clock signals), and 32 bytes of data require 16 clks, and its corresponding bandwidth utilization rate is 69%, resulting in the problem of low bandwidth utilization. Summary of the Invention
[0004] To overcome the problems existing in the related art, the present disclosure provides a data processing method, apparatus, chip, and electronic device.
[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a data processing method, including:
[0006] Receiving operation information sent by a processor, where the operation information includes a data operation instruction and a main memory address corresponding to the data operation instruction;
[0007] Judging whether a cache hit occurs in an intermediate cache unit according to the main memory address, where the intermediate cache unit is connected to the processor and the main memory, the intermediate cache unit includes a cache and a buffer, the cache includes a plurality of cache lines, and wherein the storage unit of the buffer is larger than the storage unit of the cache line;
[0008] In the case of a cache miss, executing the data operation instruction in the buffer.
[0009] Optionally, the operation information includes a read operation instruction and a main memory address corresponding to the read operation instruction, and the executing the data operation instruction in the buffer in the case of a cache miss includes:
[0010] In the case of a cache miss, determining whether the buffer stores first data;
[0011] When the first data is stored in the buffer, compare the first part of the main memory address with the base address of the first data;
[0012] When the first part of the address is equal to the base address of the first data, send the data corresponding to the second part of the main memory address in the first data to the processor;
[0013] When the first data is not stored in the buffer, or when the first part of the address is not equal to the base address of the first data, send a first read instruction to the main memory according to the main memory address, store the read-back data in the buffer and send it to the processor, and update the base address of the first data, where the first read instruction is a request instruction for obtaining the data of the storage unit of the buffer.
[0014] Optionally, the buffer includes a read buffer, and the read buffer includes a first read register, a second read register, and a third read register;
[0015] The first read register is used to store the first data;
[0016] The second read register is used to record the storage state of whether the first read register stores the first data;
[0017] The third read register is used to record the base address of the first data;
[0018] Determining whether the buffer stores the first data includes:
[0019] Determine whether the first read register stores the first data through the storage state recorded by the second read register;
[0020] Storing the read-back data in the buffer includes:
[0021] Store the read-back data in the first read register, and set the storage state of the second read register to have.
[0022] Optionally, the read buffer further includes a fourth read register;
[0023] The fourth read register is used to record the first enable value in the read operation;
[0024] Determining whether the buffer stores the first data in the case of cache miss includes:
[0025] In the case of cache miss and the first enable value being equal to the enable preset value, determine whether the buffer stores the first data;
[0026] The method further includes:
[0027] When there is a cache miss and the first enable value is not equal to the enable preset value, a second read instruction is sent to the main memory according to the main memory address, and the data read back is stored in the cache line and sent to the processor, where the second read instruction is a request instruction for obtaining data of the storage unit of the cache line.
[0028] Optionally, the read buffer further includes a fifth read register and a sixth read register;
[0029] The fifth read register is used to record a first historical address, and the first historical address is the main memory address corresponding to the last execution of the read operation instruction;
[0030] The sixth read register is used to record a first consecutive count, and the first consecutive count is the number of consecutive addresses in the read operation;
[0031] The update of the first enable value includes:
[0032] Receiving the operation information sent by the processor, and comparing the main memory address with the first historical address;
[0033] When the main memory address and the first historical address satisfy a first preset relationship, increment the first consecutive count by one to obtain a new first consecutive count, and when the new first consecutive count is greater than or equal to a preset count threshold, set the first enable value to the enable preset value;
[0034] When the main memory address and the first historical address do not satisfy the first preset relationship, set the first consecutive count to zero and set the first enable value to a non - enable preset value.
[0035] Optionally, the operation information includes data to be written, a write operation instruction, and the main memory address corresponding to the write operation instruction. When there is a cache miss, executing the data operation instruction in the buffer includes:
[0036] When there is a cache miss, determining whether the buffer stores second data;
[0037] When the buffer does not store second data, writing the data to be written into the buffer, and updating the base address of the second data according to the first part of the address in the main memory address;
[0038] When the buffer stores second data, comparing the first part of the address in the main memory address with the base address of the second data;
[0039] When the first part of the address is equal to the base address of the second data, write the data to be written into the buffer;
[0040] When the first part of the address is not equal to the base address of the second data, send the second data stored in the buffer to the main memory, write the data to be written into the buffer, and update the base address of the second data according to the first part of the address in the main memory address.
[0041] Optionally, the buffer includes a write buffer, and the write buffer includes a first write register, a second write register, and a third write register;
[0042] The first write register is used to store the second data;
[0043] The second write register is used to record the storage state of whether the first write register stores the second data;
[0044] The third write register is used to record the base address of the second data;
[0045] Determining whether the buffer stores second data includes:
[0046] Determining whether the first write register stores second data through the storage state recorded by the second write register;
[0047] Writing the data to be written into the buffer includes:
[0048] Writing the data to be written into the first write register and setting the storage state of the second write register to having.
[0049] Optionally, the write buffer further includes a fourth write register;
[0050] The fourth write register is used to record the second enable value in the write operation;
[0051] In the case of cache miss, determining whether the buffer stores second data includes:
[0052] In the case of cache miss and the second enable value being equal to the enable preset value, determining whether the buffer stores second data;
[0053] The method further includes:
[0054] In the case of a cache miss and the second enable value not being equal to the enable preset value, a third read instruction is issued to the main memory according to the main memory address, the data read back is stored in the cache line, and the data to be written is written into the cache line, where the third read instruction is a request instruction for obtaining data of the storage unit of the cache line.
[0055] Optionally, the write buffer further includes a fifth write register and a sixth write register;
[0056] The fifth write register is used to record a second historical address, where the second historical address is the main memory address corresponding to the previous write operation instruction;
[0057] The sixth write register is used to record a second consecutive count, where the second consecutive count is the number of consecutive addresses in the write operation;
[0058] The update of the second enable value includes:
[0059] Receiving the operation information sent by the processor, and comparing the main memory address with the second historical address;
[0060] In the case where the main memory address and the second historical address satisfy a second preset relationship, the second consecutive count is incremented by one to obtain a new second consecutive count, and when the new second consecutive count is greater than or equal to a preset count threshold, the second enable value is set to the enable preset value;
[0061] In the case where the main memory address and the second historical address do not satisfy the second preset relationship, the second consecutive count is set to zero, and the second enable value is set to a non-enable preset value.
[0062] Optionally, the write buffer further includes a seventh write register;
[0063] The seventh write register is used to record the change status of each bit of the second data.
[0064] Optionally, the storage unit of the buffer is 256 bytes, and the storage unit of the cache line is 32 bytes or 64 bytes.
[0065] According to a second aspect of the embodiments of the present disclosure, a data processing device is provided, including:
[0066] A first processing module, configured to receive operation information sent by a processor, where the operation information includes a data operation instruction and the main memory address corresponding to the data operation instruction;
[0067] A second processing module, configured to determine whether there is a cache hit in an intermediate cache unit according to the main memory address, where the intermediate cache unit is connected to the processor and the main memory, and the intermediate cache unit includes a cache and a buffer area, the cache includes a plurality of cache lines, and wherein, a storage unit of the buffer area is larger than a storage unit of the cache line;
[0068] A third processing module, configured to execute the data operation instruction in the buffer area in the case of a cache miss.
[0069] According to a third aspect of the embodiments of the present disclosure, there is provided a chip, including:
[0070] A processor;
[0071] An intermediate cache unit;
[0072] The intermediate cache unit is connected to the processor and the main memory, the intermediate cache unit includes a cache and a buffer area, the cache includes a cache controller and a plurality of cache lines, and the cache controller is configured to execute the steps of implementing the data processing method provided in any one of the first aspects of the present disclosure.
[0073] According to a fourth aspect of the embodiments of the present disclosure, there is provided an electronic device, including:
[0074] A processor;
[0075] An intermediate cache unit;
[0076] A main memory;
[0077] The intermediate cache unit is connected to the processor and the main memory, the intermediate cache unit includes a cache and a buffer area, the cache includes a cache controller and a plurality of cache lines, and the cache controller is configured to execute the steps of implementing the data processing method provided in any one of the first aspects of the present disclosure when executed.
[0078] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:
[0079] By receiving operation information sent by a processor, the operation information includes a data operation instruction and a main memory address corresponding to the data operation instruction; determining whether there is a cache hit in an intermediate cache unit according to the main memory address, the intermediate cache unit is connected to the processor and the main memory, the intermediate cache unit includes a cache and a buffer area, the cache includes a plurality of cache lines, and wherein, a storage unit of the buffer area is larger than a storage unit of the cache line; and executing the data operation instruction in the buffer area in the case of a cache miss. When it is necessary to transfer data from the main memory to the intermediate cache unit in the case of a cache miss, a buffer area with a storage unit larger than that of the cache line can be used to carry a larger amount of data in one transfer, thereby improving the bandwidth utilization rate.
[0080] Other features and advantages of the present disclosure will be described in detail in the following detailed description section. BRIEF DESCRIPTION OF THE DRAWINGS
[0081] The accompanying drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:
[0082] Figure 1 is a block diagram of an electronic device shown according to an exemplary embodiment.
[0083] Figure 2 is a block diagram of an intermediate cache unit shown according to an exemplary embodiment.
[0084] Figure 3 is a flowchart of a data processing method shown according to an exemplary embodiment.
[0085] Figure 4 is a flowchart of another data processing method shown according to an exemplary embodiment.
[0086] Figure 5 is a flowchart of another data processing method shown according to an exemplary embodiment.
[0087] Figure 6 is a flowchart of the update of the first enable value shown according to an exemplary embodiment.
[0088] Figure 7 is a flowchart of another data processing method shown according to an exemplary embodiment.
[0089] Figure 8 is a flowchart of another data processing method shown according to an exemplary embodiment.
[0090] Figure 9 is a flowchart of the update of the second enable value shown according to an exemplary embodiment.
[0091] Figure 10 is a timing diagram of a read / write command shown according to an exemplary embodiment.
[0092] Figure 11 is a timing diagram of another read / write command shown according to an exemplary embodiment.
[0093] Figure 12 is a block diagram of a data processing device shown according to an exemplary embodiment. DETAILED DESCRIPTION
[0094] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustrating and explaining the present disclosure, and are not intended to limit the present disclosure.
[0095] The terms "first", "second", etc. used in the present disclosure are for distinguishing one element from another, and do not have an order or importance. In addition, in the following description, when referring to the accompanying drawings, unless otherwise explained, the same reference numerals in different drawings represent the same or similar elements.
[0096] In order to improve the access speed, reduce the load on the main memory, and balance the system performance, many chips interact with the main memory through an intermediate cache unit.
[0097] In the related art, when a cache miss occurs, it is usually necessary to transfer data from the main memory to the cache. Each time data is transferred, a fixed-length command, address, and dummy need to be sent before the cache can receive the data. To read a cache line of data from the main memory, the storage unit is generally 32 bytes. Taking an 8-bit dual-edge main memory as an example, the command, address, and dummy require approximately 7 clock cycles (clk), and 32 bytes of data require 16 clk. The corresponding bandwidth utilization rate is 69%, resulting in a problem of low bandwidth utilization.
[0098] To solve the above technical problems, when the cache miss requires transferring data from the main memory to the intermediate cache unit in the embodiments of the present disclosure, a buffer with a storage unit larger than that of the cache line can be used to carry a larger amount of data in one transfer, thereby improving the bandwidth utilization rate.
[0099] Please refer to Figure 1 and Figure 2 , the processor 11 is connected to the main memory 13 through the intermediate cache unit 12. The intermediate cache unit 12 is connected to the processor 11 and the main memory 13. The intermediate cache unit 12 includes a buffer 14 and a cache 15. The cache 15 includes a cache controller 17 and multiple cache lines 16 (illustrated by 3 in the figure). The multiple cache lines 16 are all connected to the cache controller 17, and the buffer 14 is connected to the cache controller 17. Among them, the storage unit of the buffer 14 is larger than that of the cache line 16. The storage unit of one buffer 14 is 256 bytes, and the storage unit of one cache line 16 is 32 bytes or 64 bytes. The main memory 13 can be a storage device with a serial interface, such as a pseudo-static random access memory (PSRAM). The processor 11 can be, for example, a central processing unit (CPU), and the cache 15 can be, for example, a cache memory.
[0100] Please refer to Figure 3 , Figure 3 which is a flowchart of a data processing method shown according to an exemplary embodiment. The data processing method can be applied to the above cache controller, and the data processing method may include steps S1 to S3.
[0101] Step S1, receive operation information sent by the processor.
[0102] The operation information includes a data operation instruction and a main memory address corresponding to the data operation instruction.
[0103] The data operation instruction can be, but is not limited to, a read operation instruction, a write operation instruction, a logical operation instruction, etc. The main memory address corresponding to the data operation instruction is the address in the main memory corresponding to the execution of the data operation instruction.
[0104] Exemplarily, when the data operation instruction is a read operation instruction, the main memory address corresponding to the data operation instruction is the target read address corresponding to the data to be read in the main memory; when the data operation instruction is a write operation instruction, the main memory address corresponding to the data operation instruction is the target write address corresponding to the preset data to be written into the main memory.
[0105] Step S2, determine whether there is a cache hit in the intermediate cache unit according to the main memory address.
[0106] A cache hit means whether the data at the target read address or the target write address already exists in the cache line of the cache.
[0107] The cache controller resolves the main memory address, generates a cache index according to the address resolution to determine the position of the data in the cache line, and then searches in the cache line according to the cache index to determine whether there is corresponding data, and further makes a cache hit judgment. If there is corresponding data, it indicates a cache hit; if there is no corresponding data, it indicates a cache miss.
[0108] Step S3, execute the data operation instruction in the buffer in the case of a cache miss.
[0109] In the case of a cache miss, execute the data operation instruction in the buffer, such as a read operation instruction, a write operation instruction, a logical operation instruction, etc.
[0110] When it is necessary to transfer data from the main memory to the intermediate cache unit in the case of a cache miss, a buffer with a storage unit larger than the cache line can be used to carry more data in one transfer, thereby improving the bandwidth utilization rate.
[0111] In other embodiments, the data processing method may further include:
[0112] Step S4. When the cache is hit, execute the data operation instruction in the cache line.
[0113] When the cache is hit, execute the corresponding data operation instruction in the cache line. For example, a read operation instruction, a write operation instruction, a logical operation instruction, etc.
[0114] In a possible implementation manner, the operation information may include a read operation instruction and the main memory address corresponding to the read operation instruction. Please refer to Figure 4 , Figure 4 is a flowchart of another data processing method shown according to an exemplary embodiment. This data processing method can be applied to a cache controller, and this data processing method may include Step S201 to Step S207.
[0115] Step S201. Receive the operation information sent by the processor.
[0116] The operation information includes a data operation instruction and the main memory address corresponding to the data operation instruction.
[0117] Step S202. Determine whether the cache is hit in the intermediate cache unit according to the main memory address.
[0118] When the cache is hit, execute Step S203. When the cache is not hit, execute Step S204.
[0119] Step S203. Execute the data operation instruction in the cache line.
[0120] Step S204. Determine whether the buffer stores the first data.
[0121] When the buffer does not store the first data, execute Step S205. When the buffer stores the first data, execute Step S206.
[0122] Step S205. Send a first read instruction to the main memory according to the main memory address, store the read-back data in the buffer and send it to the processor, and update the base address of the first data.
[0123] Wherein, the first read instruction is a request instruction for obtaining the data of the storage unit of the buffer.
[0124] Exemplarily, the first read instruction may be a request instruction for reading 256 bytes of data.
[0125] Sending a first read instruction to the main memory according to the main memory address can be understood as sending an instruction to the main memory for reading 256 bytes of data including the data corresponding to the main memory address.
[0126] Store the data read back into the buffer and send it to the processor. It can be understood that data with a quantity of 256 bytes read back is stored in the buffer, and data with a quantity of 256 bytes retrieved is sent to the processor. In other embodiments, it is also possible to only send the data corresponding to the main memory address read back to the processor, which is not limited herein.
[0127] Update the base address of the first data. It can be understood that the base address of the first data is updated according to the main memory address. Exemplarily, the updated base address of the first data is the first part of the address in the main memory address. The main memory address consists of the first part of the address and the second part of the address. The first part of the address in the main memory address is the base address, and the second part of the address in the main memory address is the relative address. Exemplarily, the first part of the address can be represented by the high 24-bit address, and the second part of the address can be represented by the low 8-bit address.
[0128] Step S206, determine whether the first part of the address is equal to the base address of the first data.
[0129] Compare the base address in the main memory address with the base address of the first data. In the case where the first part of the address is not equal to the base address of the first data, execute step S205. In the case where the first part of the address is equal to the base address of the first data, execute step S207.
[0130] Step S207, send the data in the first data corresponding to the second part of the address in the main memory address to the processor.
[0131] Send the data in the first data corresponding to the relative address in the main memory address to the processor.
[0132] It should be understood that in the case where the first data is not stored in the buffer or the first part of the address is not equal to the base address of the first data, step S205 is executed. For the detailed elaboration of step S201, step S202, and step S203, reference can be made to step S1, step S2, and step S4 respectively, which will not be elaborated herein.
[0133] In a possible implementation manner, the buffer includes a read buffer, and the read buffer includes a first read register, a second read register, and a third read register; the first read register is used to store the first data; the second read register is used to record the storage state of whether the first read register stores the first data; the third read register is used to record the base address of the first data.
[0134] The data stored in the first read register is the first data.
[0135] Determining whether the first data is stored in the buffer may include:
[0136] Determine whether the first read register stores the first data based on the storage status recorded by the second read register.
[0137] When the storage status recorded by the second read register is "yes", the first read register stores the first data; when the storage status recorded by the second read register is "no", the first read memory does not store the first data.
[0138] Storing the read-back data into the buffer may include:
[0139] Storing the read-back data into the first read register and setting the storage status of the second read register to "yes".
[0140] When the read-back data is stored into the first read register, at this time, the first read register stores the first data. Therefore, correspondingly, the storage status of the second read register is set to "yes".
[0141] In a possible implementation manner, the read buffer further includes a fourth read register, and the fourth read register is used to record the first enable value in the read operation.
[0142] Please refer to Figure 5 , Figure 5 which is a flowchart of another data processing method shown according to an exemplary embodiment. This data processing method can be applied to a cache controller, and this data processing method may include step S301 to step S309.
[0143] Step S301: Receive the operation information sent by the processor.
[0144] The operation information includes a data operation instruction and the main memory address corresponding to the data operation instruction.
[0145] Step S302: Determine whether there is a cache hit in the intermediate cache unit according to the main memory address.
[0146] When there is a cache hit, execute step S303; when there is no cache hit, execute step S304.
[0147] Step S303: Execute the data operation instruction in the cache line.
[0148] Step S304: Determine whether the first enable value is equal to the enable preset value.
[0149] The enable preset value can be user-defined, a value in an active enable state, for example, 1.
[0150] When the first enable value is not equal to the enable preset value, execute step S305; when the first enable value is equal to the enable preset value, execute step S306.
[0151] Step S305, send a second read instruction to the main memory according to the main memory address, store the read-back data in the cache line and send it to the processor.
[0152] Among them, the second read instruction is a request instruction for obtaining data of the storage unit of the cache line.
[0153] The second read instruction can be a request instruction for reading 32 bytes or 64 bytes of data.
[0154] Sending a second read instruction to the main memory according to the main memory address can be understood as sending an instruction to the main memory for reading data with a data volume of 32 bytes or 64 bytes including the data corresponding to the main memory address.
[0155] Storing the read-back data in the cache line and sending it to the processor can be understood as storing the read-back data with a data volume of 32 bytes or 64 bytes in the cache line and sending the read-back data with a data volume of 32 bytes or 64 bytes to the processor.
[0156] Step S306, determine whether the buffer stores the first data.
[0157] In the case where the buffer does not store the first data, execute step S307; in the case where the buffer stores the first data, execute step S308.
[0158] Step S307, send a first read instruction to the main memory according to the main memory address, store the read-back data in the buffer and send it to the processor, and update the base address of the first data.
[0159] Among them, the first read instruction is a request instruction for obtaining data of the storage unit of the buffer.
[0160] Store the read-back data in the first read register of the buffer. At this time, the first read register stores the first data. Therefore, correspondingly, set the storage state of the second read register to have.
[0161] Step S308, determine whether the first part of the address is equal to the base address of the first data.
[0162] Compare the first part of the address in the main memory address with the base address of the first data. In the case where the first part of the address is not equal to the base address of the first data, execute step S307; in the case where the first part of the address is equal to the base address of the first data, execute step S309.
[0163] Step S309, send the data corresponding to the second part of the address in the main memory address in the first data to the processor.
[0164] Send the data at the relative address in the corresponding main memory address in the first data to the processor.
[0165] It should be understood that step S307 is executed both when the buffer does not store the first data or when the first part of the address is not equal to the base address of the first data. For the detailed descriptions of step S301, step S302, step S303, step S306, step S307, step S308, and step S309, reference can be made to step S201, step S202, step S203, step S204, step S205, step S206, and step S207 respectively, which will not be elaborated herein in this embodiment.
[0166] In a possible implementation manner, the read buffer further includes a fifth read register and a sixth read register; the fifth read register is used to record the first historical address, where the first historical address is the main memory address corresponding to the last executed read operation instruction; the sixth read register is used to record the first consecutive count, where the first consecutive count is the number of consecutive addresses in the read operation.
[0167] Please refer to Figure 6 , the update of the first enable value may include steps S41 to S43:
[0168] Step S41, receive the operation information sent by the processor, and compare the main memory address with the first historical address.
[0169] Compare the main memory address in the operation information received from the processor this time with the main memory address corresponding to the last executed read operation instruction.
[0170] Step S42, when the main memory address and the first historical address satisfy the first preset relationship, increment the first consecutive count by one to obtain a new first consecutive count, and when the new first consecutive count is greater than or equal to the preset count threshold, set the first enable value to the enable preset value.
[0171] The first preset relationship may be that the main memory address = the first historical address + 1, that is, the main memory address in the operation information received from the processor this time is the next address of the main memory address corresponding to the last executed read operation instruction, indicating that the main memory address this time and the first historical address are in a consecutive relationship. Therefore, increment the first consecutive count by one to obtain a new second consecutive count.
[0172] The preset count threshold can be user-defined and can be a threshold for enabling the activation state. For example, 6. When the new first consecutive count is greater than or equal to the preset count threshold, set the first enable value to the enable preset value, for example, 1.
[0173] Step S43: When the main memory address and the first historical address do not satisfy the first preset relationship, set the first consecutive count to zero and set the first enable value to the non - enabled preset value.
[0174] When the main memory address and the first historical address do not satisfy the first preset relationship, it indicates that the current main memory address and the first historical address are not in a consecutive relationship. Therefore, set the first consecutive count to zero and set the first enable value to the non - enabled preset value, for example, 0.
[0175] In a possible implementation, the operation information may include the data to be written, the write operation instruction, and the main memory address corresponding to the write operation instruction. Please refer to Figure 7 , Figure 7 is a flowchart of another data processing method shown according to an exemplary embodiment. This data processing method can be applied to a cache controller, and this data processing method may include steps S501 to S508.
[0176] Step S501: Receive the operation information sent by the processor.
[0177] The operation information includes a data operation instruction and the main memory address corresponding to the data operation instruction.
[0178] Step S502: Determine whether there is a cache hit in the intermediate cache unit according to the main memory address.
[0179] When there is a cache hit, execute step S503; when there is no cache hit, execute step S504.
[0180] Step S503: Execute the data operation instruction in the cache line.
[0181] Step S504: Determine whether the buffer stores a second data.
[0182] When the buffer does not store the second data, execute step S505; when the buffer stores the second data, execute step S506.
[0183] Step S505: Write the data to be written into the buffer and update the base address of the second data according to the first part of the address in the main memory address.
[0184] Updating the base address of the second data according to the first part of the address in the main memory address can be understood as that the updated base address of the second data is the first part of the address in the main memory address, that is, the base address in the main memory address.
[0185] Step S506: Determine whether the first part of the address is equal to the base address of the second data.
[0186] Compare the first part of the main memory address with the base address of the second data. If the first part of the address is not equal to the base address of the second data, execute step S507; if the first part of the address is equal to the base address of the second data, execute step S508.
[0187] Step S507: Send the second data already stored in the buffer to the main memory, write the data to be written into the buffer, and update the base address of the second data according to the first part of the main memory address.
[0188] In order to be able to write the data to be written into the buffer, it is necessary to first send the second data already stored in the buffer to the main memory, thereby freeing up storage space in the buffer to store the data to be written. After the data to be written is written into the buffer, it becomes the new second data. Correspondingly, the updated base address of the second data is the first part of the main memory address, that is, the base address in the main memory address.
[0189] Step S508: Write the data to be written into the buffer.
[0190] It should be understood that for the detailed descriptions of steps S501, S502, and S503, reference can be made to steps S1, S2, and S4 respectively, and they will not be elaborated here in this embodiment.
[0191] In a possible implementation, the buffer includes a write buffer, and the write buffer includes a first write register, a second write register, and a third write register; the first write register is used to store the second data; the second write register is used to record the storage status of whether the first write register stores the second data; the third write register is used to record the base address of the second data.
[0192] The data stored in the first write register is the second data.
[0193] Determining whether the buffer stores the second data may include:
[0194] Determine whether the first write register stores the second data based on the storage status recorded by the second write register.
[0195] When the storage status recorded by the second write register is "yes", the first write register stores the second data; when the storage status recorded by the second write register is "no", the first write register does not store the second data.
[0196] Writing the data to be written into the buffer may include:
[0197] Write the data to be written into the first write register and set the storage status of the second write register to "yes".
[0198] Write the data to be written into the first write register. At this time, the second data is stored in the first write register. Therefore, correspondingly, set the storage state of the second write register to "occupied".
[0199] In a possible implementation, the write buffer further includes a fourth write register; the fourth write register is used to record the second enable value in the write operation.
[0200] Please refer to Figure 8 , Figure 8 which is a flowchart of another data processing method shown according to an exemplary embodiment. This data processing method can be applied to a cache controller, and this data processing method may include steps S601 to S610.
[0201] Step S601, receive the operation information sent by the processor.
[0202] The operation information includes a data operation instruction and the main memory address corresponding to the data operation instruction.
[0203] Step S602, determine whether there is a cache hit in the intermediate cache unit according to the main memory address.
[0204] In the case of a cache hit, execute step S603; in the case of a cache miss, execute step S604.
[0205] Step S603, execute the data operation instruction in the cache line.
[0206] Step S604, determine whether the second enable value is equal to the enable preset value.
[0207] The enable preset value can be user-defined, a value for enabling the active state, for example, 1.
[0208] In the case where the second enable value is not equal to the enable preset value, execute step S605; in the case where the second enable value is equal to the enable preset value, execute step S606.
[0209] Step S605, send a third read instruction to the main memory according to the main memory address, store the read-back data in the cache line, and write the data to be written into the cache line.
[0210] Among them, the third read instruction is a request instruction for obtaining the data of the storage unit of the cache line.
[0211] The third read instruction can be a request instruction for reading 32 bytes or 64 bytes of data.
[0212] Send a third read instruction to the main memory according to the main memory address, which can be understood as sending an instruction to the main memory to read a data volume of 32 bytes or 64 bytes including the data corresponding to the main memory address.
[0213] Store the read-back data in the cache line and write the data to be written into the cache line, which can be understood as storing the read-back data volume of 32 bytes or 64 bytes in the cache line and writing the data to be written into the cache line.
[0214] Step S606, determine whether the buffer stores the second data.
[0215] In the case where the buffer does not store the second data, execute step S607; in the case where the buffer stores the second data, execute step S608.
[0216] Step S607, write the data to be written into the buffer and update the base address of the second data according to the first part of the address in the main memory address.
[0217] Write the data to be written into the first write register. At this time, the first write register stores the second data. Therefore, correspondingly, set the storage state of the second write register to "yes".
[0218] Step S608, determine whether the first part of the address is equal to the base address of the second data.
[0219] [[ID=2I]]Compare the first part of the address in the main memory address with the base address of the second data. In the case where the first part of the address is not equal to the base address of the second data, execute step S609; in the case where the first part of the address is equal to the base address of the second data, execute step S610.
[0220] Step S609, send the second data already stored in the buffer to the main memory, write the data to be written into the buffer, and update the base address of the second data according to the first part of the address in the main memory address.
[0221] Step S610, write the data to be written into the buffer.
[0222] It should be understood that for the detailed elaboration of step S601, step S602, step S603, step S606, step S607, step S608, step S609, and step S610, reference can be made to step S501, step S5I2, step S503, step S504, step S505, step S506, step S507, and step S508 respectively, which will not be elaborated herein in this embodiment.
[0223] In a possible implementation, the write buffer further includes a fifth write register and a sixth write register; the fifth write register is used to record a second historical address, where the second historical address is the main memory address corresponding to the last executed write operation instruction; the sixth write register is used to record a second consecutive count, where the second consecutive count is the number of consecutive addresses in the write operation.
[0224] Please refer to Figure 9 , the update of the second enable value may include steps S71 to S73:
[0225] Step S71, receive the operation information sent by the processor, and compare the main memory address with the second historical address.
[0226] Compare the main memory address in the operation information received from the processor this time with the main memory address corresponding to the last executed write operation instruction.
[0227] Step S72, when the main memory address and the second historical address satisfy the second preset relationship, increment the second consecutive count by one to obtain a new second consecutive count, and when the new second consecutive count is greater than or equal to a preset count threshold, set the second enable value to an enable preset value.
[0228] The second preset relationship may be that the main memory address = the second historical address + 1, that is, the main memory address in the operation information received from the processor this time is the next address of the main memory address corresponding to the last executed write operation instruction, indicating that the current main memory address and the second historical address are consecutive. Therefore, increment the second consecutive count by one to obtain a new second consecutive count.
[0229] The preset count threshold can be user-defined, which is the threshold for enabling the activation state. For example, 6. When the new second consecutive count is greater than or equal to the preset count threshold, set the second enable value to an enable preset value, for example, 1.
[0230] Step S73, when the main memory address and the second historical address do not satisfy the second preset relationship, set the second consecutive count to zero and set the second enable value to a non-enable preset value.
[0231] [[ID=2,6]]When the main memory address and the second historical address do not satisfy the second preset relationship, it indicates that the current main memory address and the second historical address are not consecutive. Therefore, set the second consecutive count to zero and set the second enable value to a non-enable preset value, for example, 0.
[0232] In a possible implementation, the write buffer further includes a seventh write register; the seventh write register is used to record the change status of each bit of the second data.
[0233] Each cache line corresponds to a change state. When any bit of data in a cache line changes, the change state of that cache line is set to 1, indicating that the cache line has changed. Therefore, the different bits of data in a cache line are tied together. This embodiment uses a seventh register to record the change state of each bit of data in the second data. This allows the change state of each bit of data in the second data to be recorded separately and independently, thereby removing the inherent bundling relationship and increasing the flexibility of data changes.
[0234] During processor read and write operations on consecutive addresses, the cache controller sends 256-byte read and write instructions to main memory. This results in a calculated bandwidth utilization of 128 / (7+128) = 94.8%, a significant improvement over the 16 / (7+16) = 69% bandwidth utilization associated with the original 32-byte read and write instructions. Accelerating read and write operations for consecutive addresses significantly improves main memory bandwidth utilization, thereby enhancing overall performance.
[0235] See also Figure 10 and Figure 11 Each read / write command sequence consists of a command cycle, an address cycle, a dummy cycle, and a data cycle. In the diagram, INST represents the command cycle, A0-A3 represent the address cycle, D0-D7 represent the data cycle, T represents the time interval between two commands, CE represents enable, and A / DQ[7:0] represents the 8-bit signal multiplexed into command, address, and data.
[0236] Regardless of whether the command reads 1 byte of data or 100 bytes of data, the cycle of the command address dummy remains unchanged. For example, if the processor needs to read 10kbytes of data continuously from the external storage, it needs to be split into 320 read commands using the original cache method. Figure 10 The command cycle, address cycle, and dummy cycle require about 7 clks, and the estimated time required is 320*(16+7)=7360 cycles. Figure 11 The command cycle, address cycle, and dummy cycle require about 5 clks, and the estimated time required is 320*(16+5)=6720 cycles. By using the buffer method, it only needs to be split into 40 read commands, according to Figure 10 The command cycle, address cycle, and dummy cycle require about 7 clks, and the estimated time required is 40*(128+7)=5400 cycles. Figure 11The command cycle, address cycle, and dummy cycle approximately require 5 clks. The expected time is 40 * (128 + 5) = 5320 cycles. When it is predicted that continuous read and write operations are being performed, the data length of the command for accessing the main memory is increased, thereby reducing the number of split commands, and thus saving some time for unnecessary command address dummy cycles. For the same amount of data, less time is used, resulting in an increase in bandwidth utilization.
[0237] Based on the same inventive concept, to implement the above method embodiments, this embodiment provides a data processing device. The data processing device 800 can be applied to a cache controller. Please refer to Figure 12 and the data processing device 800 may include:
[0238] A first processing module 801, configured to receive operation information sent by a processor, where the operation information includes a data operation instruction and a main memory address corresponding to the data operation instruction;
[0239] A second processing module 802, configured to determine whether there is a cache hit in an intermediate cache unit according to the main memory address. The intermediate cache unit is connected to the processor and the main memory. The intermediate cache unit includes a cache and a buffer area. The cache includes multiple cache lines. Among them, the storage unit of the buffer area is larger than the storage unit of the cache line;
[0240] A third processing module 803, configured to execute the data operation instruction in the buffer area when there is a cache miss.
[0241] Optionally, the operation information includes a read operation instruction and a main memory address corresponding to the read operation instruction. The third processing module 803 may include:
[0242] A first sub - processing module, configured to determine whether a first data is stored in the buffer area when there is a cache miss;
[0243] A second sub - processing module, configured to compare a first part of the address in the main memory address with the base address of the first data when the first data is stored in the buffer area;
[0244] A third sub - processing module, configured to send the data corresponding to the second part of the address in the main memory address in the first data to the processor when the first part of the address is equal to the base address of the first data;
[0245] A fourth sub - processing module, configured to send a first read instruction to the main memory according to the main memory address, store the read - back data in the buffer area and send it to the processor, and update the base address of the first data when the first data is not stored in the buffer area, or when the first part of the address is not equal to the base address of the first data. Among them, the first read instruction is a request instruction for obtaining data in the storage unit of the buffer area.
[0246] Optionally, the buffer includes a read buffer, and the read buffer includes a first read register, a second read register, and a third read register;
[0247] The first read register is used to store first data;
[0248] The second read register is used to record the storage status of whether the first read register stores the first data;
[0249] The third read register is used to record the base address of the first data;
[0250] The first sub-processing module is specifically configured to:
[0251] Determine whether the first read register stores the first data according to the storage status recorded by the second read register;
[0252] The fourth sub-processing module is specifically configured to:
[0253] Store the read-back data into the first read register, and set the storage status of the second read register to having.
[0254] Optionally, the read buffer further includes a fourth read register;
[0255] The fourth read register is used to record the first enable value in the read operation;
[0256] The first sub-processing module is specifically configured to:
[0257] Determine whether the buffer stores the first data when the cache miss occurs and the first enable value is equal to the enable preset value;
[0258] The data processing device 800 may further include:
[0259] A fourth processing module, configured to issue a second read instruction to the main memory according to the main memory address when the cache miss occurs and the first enable value is not equal to the enable preset value, store the read-back data into the cache line and send it to the processor, where the second read instruction is a request instruction for obtaining the data of the storage unit of the cache line.
[0260] Optionally, the read buffer further includes a fifth read register and a sixth read register;
[0261] The fifth read register is used to record the first historical address, and the first historical address is the main memory address corresponding to the previous execution of the read operation instruction;
[0262] The sixth read register is used to record the first consecutive count, and the first consecutive count is the number of consecutive addresses in the read operation;
[0263] The fourth processing module may include:
[0264] A fifth sub - processing module, configured to receive operation information sent by a processor and compare a main memory address with a first historical address;
[0265] A sixth sub - processing module, configured to, when the main memory address and the first historical address satisfy a first preset relationship, increment a first consecutive count by one to obtain a new first consecutive count, and when the new first consecutive count is greater than or equal to a preset count threshold, set a first enable value to an enabled preset value;
[0266] A seventh sub - processing module, configured to, when the main memory address and the first historical address do not satisfy the first preset relationship, set the first consecutive count to zero and set the first enable value to a non - enabled preset value.
[0267] Optionally, the operation information includes data to be written, a write operation instruction, and a main memory address corresponding to the write operation instruction. The third processing module 803 may include:
[0268] An eighth sub - processing module, configured to determine whether a buffer stores second data in the case of a cache miss;
[0269] A ninth sub - processing module, configured to, when the buffer does not store second data, write the data to be written into the buffer and update a base address of the second data according to a first part of the address in the main memory address;
[0270] A tenth sub - processing module, configured to, when the buffer stores second data, compare a first part of the address in the main memory address with the base address of the second data;
[0271] An eleventh sub - processing module, configured to, when the first part of the address is equal to the base address of the second data, write the data to be written into the buffer;
[0272] A twelfth sub - processing module, configured to, when the first part of the address is not equal to the base address of the second data, send the second data already stored in the buffer to the main memory, write the data to be written into the buffer, and update the base address of the second data according to a first part of the address in the main memory address.
[0273] Optionally, the buffer includes a write buffer, and the write buffer includes a first write register, a second write register, and a third write register;
[0274] The first write register is used to store the second data;
[0275] The second write register is used to record a storage state indicating whether the first write register stores the second data;
[0276] The third write register is used to record the base address of the second data;
[0277] The eighth sub-processing module is specifically configured to:
[0278] Determine whether the first write register stores the second data according to the storage status recorded by the second write register;
[0279] The twelfth sub-processing module is specifically configured to:
[0280] Write the data to be written into the first write register, and set the storage status of the second write register to have.
[0281] Optionally, the write buffer further includes a fourth write register;
[0282] The fourth write register is used to record the second enable value in the write operation;
[0283] The eighth sub-processing module is specifically configured to:
[0284] Determine whether the buffer stores the second data when the cache misses and the second enable value is equal to the enable preset value;
[0285] The data processing device 800 may further include:
[0286] A fifth processing module, configured to issue a third read instruction to the main memory according to the main memory address when the cache misses and the second enable value is not equal to the enable preset value, store the read-back data into the cache line, and write the data to be written into the cache line, wherein the third read instruction is a request instruction for obtaining the data of the storage unit of the cache line.
[0287] Optionally, the write buffer further includes a fifth write register and a sixth write register;
[0288] The fifth write register is used to record the second historical address, and the second historical address is the main memory address corresponding to the previous execution of the write operation instruction;
[0289] The sixth write register is used to record the second consecutive count, and the second consecutive count is the number of consecutive addresses in the write operation;
[0290] The fifth processing module may include:
[0291] A thirteenth sub-processing module, configured to receive the operation information sent by the processor and compare the main memory address with the second historical address;
[0292] The fourteenth sub - processing module is configured to increment the second consecutive count by one when the main memory address and the second historical address satisfy a second preset relationship, to obtain a new second consecutive count, and to set the second enable value to an enable preset value when the new second consecutive count is greater than or equal to a preset count threshold;
[0293] The fifteenth sub - processing module is configured to set the second consecutive count to zero and set the second enable value to a non - enable preset value when the main memory address and the second historical address do not satisfy the second preset relationship.
[0294] Optionally, the write buffer further includes a seventh write register;
[0295] The seventh write register is used to record the change status of each bit of the second data.
[0296] Optionally, the storage unit of the buffer is 256 bytes, and the storage unit of the cache line is 32 bytes or 64 bytes.
[0297] Regarding the data processing device in the above - mentioned embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the data processing method, and will not be elaborated here.
[0298] In another exemplary embodiment, a chip 10 is further provided, including: a processor 11 and an intermediate cache unit 12. The intermediate cache unit 12 is connected to the processor 11 and the main memory 13. The intermediate cache unit 12 includes a cache 15 and a buffer 14. The cache 15 includes a cache controller 17 and a plurality of cache lines 16. The cache controller 17 is configured to implement the steps of the above - mentioned data processing method when executed.
[0299] In another exemplary embodiment, an electronic device 20 is further provided, including: a processor 11, an intermediate cache unit 12, and a main memory 13. The intermediate cache unit 12 is connected to the processor 11 and the main memory 13. The intermediate cache unit 12 includes a cache 15 and a buffer 14. The cache 15 includes a cache controller 17 and a plurality of cache lines 16. The cache controller 17 is configured to implement the steps of the above - mentioned data processing method when executed.
[0300] In another exemplary embodiment, a computer program product is further provided. The computer program product includes a computer program that can be executed by a programmable device, and the computer program has a code portion for executing the above - mentioned data processing method when executed by the programmable device.
[0301] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0302] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure will not separately describe various possible combination methods.
[0303] Furthermore, any combination can be made among the various different embodiments of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A data processing method, characterized in that, Including: Receiving operation information sent by a processor, where the operation information includes a data operation instruction and a main memory address corresponding to the data operation instruction; Judging whether there is a cache hit in an intermediate cache unit according to the main memory address, the intermediate cache unit is connected to the processor and the main memory, the intermediate cache unit includes a cache and a buffer, the cache includes a plurality of cache lines, and wherein, the storage unit of the buffer is larger than the storage unit of the cache line; In the case of a cache miss, executing the data operation instruction in the buffer.
2. The data processing method according to claim 1, wherein The operation information includes a read operation instruction and a main memory address corresponding to the read operation instruction, and in the case of a cache miss, executing the data operation instruction in the buffer includes: In the case of a cache miss, determining whether the buffer stores a first piece of data; In the case that the buffer stores the first piece of data, comparing a first part of the main memory address with a base address of the first piece of data; In the case that the first part of the address is equal to the base address of the first piece of data, sending the data corresponding to a second part of the main memory address in the first piece of data to the processor; In the case that the buffer does not store the first piece of data, or in the case that the first part of the address is not equal to the base address of the first piece of data, sending a first read instruction to the main memory according to the main memory address, storing the read-back data in the buffer and sending it to the processor, and updating the base address of the first piece of data, where the first read instruction is a request instruction for obtaining data in the storage unit of the buffer.
3. The data processing method according to claim 2, characterized in that, The buffer includes a read buffer, and the read buffer includes a first read register, a second read register, and a third read register; The first read register is used to store the first piece of data; The second read register is used to record a storage state of whether the first read register stores the first piece of data; The third read register is used to record the base address of the first piece of data; Determining whether the buffer stores a first piece of data includes: Determining whether the first read register stores a first piece of data through the storage state recorded by the second read register; Storing the read-back data in the buffer includes: Storing the read-back data in the first read register, and setting the storage state of the second read register to having.
4. The data processing method according to claim 3, wherein The read buffer further includes a fourth read register; The fourth read register is used to record a first enable value in a read operation; In the case of a cache miss, determining whether the buffer stores a first piece of data includes: In the case of a cache miss and the first enable value being equal to an enable preset value, determining whether the buffer stores a first piece of data; The method further includes: In the case of a cache miss and the first enable value not being equal to the enable preset value, sending a second read instruction to the main memory according to the main memory address, and storing the read-back data in the cache line and sending it to the processor, where the second read instruction is a request instruction for obtaining data in the storage unit of the cache line.
5. The data processing method according to claim 4, characterized in that The read buffer further includes a fifth read register and a sixth read register; The fifth read register is used to record a first historical address, and the first historical address is the main memory address corresponding to the last executed read operation instruction; The sixth read register is used to record a first consecutive count, and the first consecutive count is the number of consecutive addresses in the read operation; The update of the first enable value includes: Receiving the operation information sent by the processor, and comparing the main memory address with the first historical address; When the main memory address and the first historical address satisfy a first preset relationship, incrementing the first consecutive count to obtain a new first consecutive count, and when the new first consecutive count is greater than or equal to a preset count threshold, setting the first enable value to the enable preset value; When the main memory address and the first historical address do not satisfy the first preset relationship, setting the first consecutive count to zero and setting the first enable value to the non-enable preset value.
6. The data processing method according to claim 1, wherein The operation information includes data to be written, a write operation instruction, and the main memory address corresponding to the write operation instruction. When a cache miss occurs, executing the data operation instruction in the buffer includes: When a cache miss occurs, determining whether the buffer stores a second data; When the buffer does not store the second data, writing the data to be written into the buffer, and updating the base address of the second data according to the first part of the main memory address; When the buffer stores the second data, comparing the first part of the main memory address with the base address of the second data; When the first part of the address is equal to the base address of the second data, writing the data to be written into the buffer; When the first part of the address is not equal to the base address of the second data, sending the second data stored in the buffer to the main memory, writing the data to be written into the buffer, and updating the base address of the second data according to the first part of the main memory address.
7. The data processing method according to claim 6, characterized in that The buffer includes a write buffer, and the write buffer includes a first write register, a second write register, and a third write register; The first write register is used to store the second data; The second write register is used to record the storage state of whether the first write register stores the second data; The third write register is used to record the base address of the second data; Determining whether the buffer stores a second data includes: Determining whether the first write register stores a second data through the storage state recorded by the second write register; Writing the data to be written into the buffer includes: Writing the data to be written into the first write register, and setting the storage state of the second write register to having.
8. The data processing method according to claim 7, characterized in that The write buffer further includes a fourth write register; The fourth write register is used to record a second enable value in the write operation; When a cache miss occurs, determining whether the buffer stores a second data includes: In the case of a cache miss and the second enable value being equal to the enable preset value, determine whether the buffer stores second data; The method further includes: In the case of a cache miss and the second enable value not being equal to the enable preset value, issue a third read instruction to the main memory according to the main memory address, store the read-back data into the cache line, and write the data to be written into the cache line, where the third read instruction is a request instruction for obtaining data of a storage unit of the cache line.
9. The data processing method according to claim 8, wherein The write buffer further includes a fifth write register and a sixth write register; The fifth write register is used to record a second historical address, and the second historical address is the main memory address corresponding to the last execution of the write operation instruction; The sixth write register is used to record a second consecutive count, and the second consecutive count is the number of consecutive addresses in the write operation; The update of the second enable value includes: Receiving operation information sent by the processor, and comparing the main memory address with the second historical address; In the case where the main memory address and the second historical address satisfy a second preset relationship, increment the second consecutive count by one to obtain a new second consecutive count, and when the new second consecutive count is greater than or equal to a preset count threshold, set the second enable value to the enable preset value; In the case where the main memory address and the second historical address do not satisfy the second preset relationship, set the second consecutive count to zero and set the second enable value to a non-enable preset value.
10. The data processing method according to claim 7, characterized in that The write buffer further includes a seventh write register; The seventh write register is used to record the change status of each bit of the second data.
11. The data processing method according to any one of claims 1 to 10, characterized in that, The storage unit of the buffer is 256 bytes, and the storage unit of the cache line is 32 bytes or 64 bytes.
12. A data processing device, characterized in that, Including: A first processing module configured to receive operation information sent by the processor, where the operation information includes a data operation instruction and the main memory address corresponding to the data operation instruction; A second processing module configured to determine whether a cache hit occurs in the intermediate cache unit according to the main memory address, the intermediate cache unit is connected to the processor and the main memory, the intermediate cache unit includes a cache and a buffer, the cache includes a plurality of cache lines, and the storage unit of the buffer is larger than the storage unit of the cache line; A third processing module configured to execute the data operation instruction in the buffer in the case of a cache miss.
13. A chip, characterized in that, Including: A processor; An intermediate cache unit; The intermediate cache unit is connected to the processor and the main memory, the intermediate cache unit includes a cache and a buffer, the cache includes a cache controller and a plurality of cache lines, and the cache controller is used to implement the steps of the data processing method according to any one of claims 1 to 11 when executed.
14. An electronic device, characterized in that, Including: A processor; An intermediate cache unit; A main memory; The intermediate cache unit is connected to the processor and the main memory. The intermediate cache unit includes a cache and a buffer. The cache includes a cache controller and a plurality of cache lines. The cache controller is configured to implement the steps of the data processing method according to any one of claims 1 to 11 during execution.