NVMe memory management method and device, equipment and storage medium
By judging and aggregating the status of index pointer in NVMe memory management, the problems of unsafe resource recycling and low bus utilization efficiency are solved, and more efficient and secure memory resource management is achieved.
Patent Information
- Application Number
- CN202510581976.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-07
- Publication Date
- 2025-08-01
AI Technical Summary
There are problems in existing NVMe memory management that are unsafe, poor robustness and low bus utilization efficiency, especially in frequent AXI operations, resource repetitive access and management efficiency.
By normalizing the index label of the target free index pointer, using the index status lookup table to judge the status of the index pointer, avoiding duplicate allocation and recycling of resources, and using an aggregation recycling mechanism to improve resource utilization.
It improves the security and robustness of NVMe memory resource recycling, optimizes bus utilization efficiency, and reduces the possibility of duplicate resource processing.
Smart Images
Figure CN120407190A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of memory management, and in particular, to an NVMe memory management method, device, equipment, and storage medium. Background Art
[0002] The memory resource pool of NVMe (Non-Volatile Memory Express) can often be divided into DDR (Double Data Rate) and on-chip storage, such as the flash memory inside an NVMe SSD (Non-Volatile Memory Express Solid State Disk). In actual use, there are often various different storage media, and NVMe will uniformly manage them in the form of a prp-list (Physical Region Page List, a data structure used to describe the physical address of memory in the NVMe protocol).
[0003] The role of the NVMe memory management module is to allocate and recycle memory resources. Allocation means organizing index pointers into the form of a prp-list and placing them in certain fixed physical memory for other engines to use. Recycling means recycling the prp-list used by other engines, that is, reading back the used free index pointers, then clearing the prp-list that needs to be recycled, and finally returning the recycled index pointers to the corresponding index pointer pool. However, in the current process of allocating and recycling memory resources, the hardware needs to continuously initiate AXI (Advanced eXtensible Interface, a bus protocol) operations to manage the free index pointers. Long-term and frequent AXI operations often occupy a large bandwidth, have low utilization, and may have the situation of repeated resource access.
[0004] It can be seen that how to ensure the security and robustness of resource recycling and improve the bus utilization efficiency when allocating and recycling memory resources for NVMe memory is a problem that needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of the embodiments of the present invention is to provide an NVMe memory management method, device, equipment, and storage medium, which can effectively improve the security and robustness of the resource recycling system and improve the bus utilization efficiency. The specific solutions are as follows:
[0006] In a first aspect, the present application discloses an NVMe memory management method, including:
[0007] Parse the obtained NVMe memory allocation task to obtain the memory allocation task requirements, and read the target free index pointer from the corresponding index pointer pool based on the memory allocation task requirements;
[0008] Determine the index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer, and judge the status of the target free index pointer based on the target flag bit of the target free index pointer recorded in the index status lookup table;
[0009] If the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, construct a target physical area page list based on the target free index pointer to execute the NVMe memory allocation task.
[0010] Optionally, determining the index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer includes:
[0011] Normalize the target free index pointer to obtain the index label of the target free index pointer, and determine the index status lookup table corresponding to the index pointer pool based on the index label.
[0012] Optionally, judging the status of the target free index pointer based on the target flag bit of the target free index pointer recorded in the index status lookup table includes:
[0013] Locate and search the index status lookup table based on the index label to determine the target flag bit of the target free index pointer;
[0014] Detect the target flag bit at the preset pointer detection port to judge whether the target free index pointer is in an available state.
[0015] Optionally, locating and searching the index status lookup table based on the index label to determine the target flag bit of the target free index pointer includes:
[0016] Equally split the index label based on the preset bit width to obtain the split label;
[0017] Perform radix conversion on the first-dimensional label value, the second-dimensional label value, and the third-dimensional label value in the split label respectively to obtain the target coordinate values; the target coordinate values include the first coordinate value located on the preset X coordinate axis corresponding to the first-dimensional label value, the second coordinate value located on the preset Y coordinate axis corresponding to the second-dimensional label value, and the third coordinate value located on the preset Z coordinate axis corresponding to the third-dimensional label value;
[0018] In the first clock cycle, perform a search and positioning in the table area of the index status lookup table based on the first coordinate value to obtain the first-dimensional flag bit;
[0019] After buffering the second coordinate value in the first clock cycle, in the second clock cycle, based on the second coordinate value and the first dimension flag bit, perform a lookup and positioning in the table area of the index status lookup table to obtain the second dimension flag bit; the second clock cycle is the next clock cycle after the first clock cycle;
[0020] After buffering the third coordinate value in the second clock cycle, in the third clock cycle, based on the third coordinate value and the second dimension flag bit, perform a lookup and positioning in the table area of the index status lookup table to determine the target flag bit of the target free index pointer; the third clock cycle is the next clock cycle after the second clock cycle;
[0021] Correspondingly, detect the target flag bit at the preset pointer detection port to determine whether the target free index pointer is in an available state, including:
[0022] Obtain the flag value recorded by the target flag bit, and use the preset pointer detection port to detect the flag value to determine whether the target free index pointer is in an available state.
[0023] Optionally, the method further includes:
[0024] Parse the obtained NVMe memory reclaim task to obtain the memory reclaim task requirements, and based on the memory reclaim task requirements, read the current physical region page list from the corresponding memory pool;
[0025] Extract the current index pointer corresponding to the current physical region page list, and judge the status of the current index pointer based on the index status lookup table;
[0026] [[ID=2,2]]If the current index pointer is in an unavailable state, clear the current physical region page list, and after modifying the current index pointer to an available state, write the current index pointer into the corresponding index pointer pool based on the preset bus protocol.
[0027] Optionally, writing the current index pointer into the corresponding index pointer pool based on the preset bus protocol includes:
[0028] Based on the index pointer pool number corresponding to the current index pointer, write the current index pointer into the aggregation component corresponding to the index pointer pool number;
[0029] Judge whether the aggregation component meets the preset aggregation condition;
[0030] If the aggregation component meets the preset aggregation condition, write all the current index pointers in the aggregation component into the corresponding index pointer pool through the preset bus protocol.
[0031] Optionally, writing the current index pointer into the aggregation component corresponding to the index pointer pool number includes:
[0032] Write the current index pointer into the first-in, first-out queue of the aggregation component corresponding to the index pointer pool number;
[0033] Correspondingly, determine whether the aggregation component meets the preset aggregation conditions, including:
[0034] Determine whether the number of index pointers in the first-in, first-out queue reaches the maximum queue capacity;
[0035] Or, determine whether the current time reaches the preset request sending time threshold under the condition that the first-in, first-out queue is not empty.
[0036] In a second aspect, the present application discloses an NVMe memory management device, including:
[0037] A pointer reading module, configured to parse the obtained NVMe memory allocation task to obtain the memory allocation task requirements, and read the target free index pointer from the corresponding index pointer pool based on the memory allocation task requirements;
[0038] A pointer status judgment module, configured to determine the index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer, and judge the status of the target free index pointer based on the target flag bit of the target free index pointer recorded in the index status lookup table;
[0039] A task execution module, configured to, if the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, construct a target physical area page list based on the target free index pointer to execute the NVMe memory allocation task.
[0040] In a third aspect, the present application discloses an electronic device, including:
[0041] A memory, configured to store a computer program;
[0042] A processor, configured to execute the computer program to implement the foregoing NVMe memory management method.
[0043] In a fourth aspect, the present application discloses a computer-readable storage medium, configured to store a computer program, and when the computer program is executed by a processor, the foregoing NVMe memory management method is implemented.
[0044] It can be seen that in the present invention, the obtained NVMe memory allocation task is parsed to obtain the memory allocation task requirements, and the target free index pointer is read from the corresponding index pointer pool based on the memory allocation task requirements; the index status lookup table corresponding to the index pointer pool is determined based on the index label of the target free index pointer, and the status of the target free index pointer is judged based on the target flag bit of the target free index pointer recorded in the index status lookup table; if the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, a target physical area page list is constructed based on the target free index pointer to execute the NVMe memory allocation task. That is, by judging the index status recorded in the index status lookup table, it is further determined whether the target free index pointer is really in an available state. After being in an available state, a target physical area page list is constructed using the target free index pointer to execute the NVMe memory allocation task.
[0045] As can be seen from the above technical solution, by judging the pointer status of the target free index pointer, it is avoided to take and recycle resources when the target free index pointer is in an unavailable state, which may cause the situation of repeated resource processing in memory resource management, and can effectively improve the security and robustness of the resource recycling system. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.
[0047] Figure 1 Schematic diagram of an NVMe memory management component disclosed by the present invention;
[0048] Figure 2 Schematic diagram of the data organization format of a PRP-LIST disclosed by the present invention;
[0049] Figure 3 Flowchart of an NVMe memory management method disclosed by the present invention;
[0050] Figure 4 Schematic diagram of a specific target index pointer positioning disclosed by the present invention;
[0051] Figure 5 Schematic diagram of a specific target index pointer positioning disclosed by the present invention;
[0052] Figure 6 Schematic diagram of a specific target index pointer positioning disclosed by the present invention;
[0053] Figure 7 Flow chart of a specific NVMe memory management method disclosed by the present invention;
[0054] Figure 8 Schematic diagram of a specific NVMe memory management architecture disclosed by the present invention;
[0055] Figure 9 Schematic diagram of the structure of an NVMe memory management device disclosed by the present invention;
[0056] Figure 10 Schematic diagram of the structure of an electronic device disclosed by the present invention. Detailed implementation manners
[0057] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
[0058] The terms "including" and "having" in the specification of the present invention and any variations related to "including" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may include unlisted steps or units.
[0059] In order to enable those skilled in the art of the present technology to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.
[0060] In the prior art, in the scenario of NVMe memory resource management where it is necessary to access a multi-target physical memory resource pool through a bus to realize the acquisition and return of memory resources, situations such as duplicate memory acquisition or recycling may occur. Moreover, for multi-target memory recycling, the hardware needs to continuously initiate AXI operations to manage the free index pointers. Long-term and frequent AXI operations often occupy a large bandwidth and have low utilization. Therefore, the present application proposes an NVMe memory management method that can solve the above problems.
[0061] Before introducing the invention, the components of NVMe memory management in the present invention will be introduced first. As follows Figure 1As shown in the figure, there are four main blocks. The first area is the on-chip memory and DDR in the top layer of the figure, which correspond to the actual physical memory space. This memory space is often divided into units of 4KB or 8KB, etc. Each memory unit corresponds to an index pointer, and the index pointer points to the starting address of a continuous unit. Assuming there is an 8M space in the on-chip memory, there are 8192KB index pointers. If divided into units of 4KB, there are 2K index pointers. The space for storing these index pointers is called the index pointer pool, which is the second area described in the figure. The index pointer pool corresponds one-to-one with the physical memory space. The third area is the AXI bus, and the fourth area is the memory resource management module.
[0062] In addition, as Figure 2 shown, on the basis of organizing data with reference to the NVMe protocol PRP (Physical Region Page) list, the present invention defines the data organization format of PRP-LIST. Each free index value contains a valid data flag bit Valid (1bit), a resource pool ID (Identity Document, i.e., identification number) (pointing to the location where the prp_list is stored), an index pointer pool ID number (3bit), an index pointer (index, 12bit), and a CRC check (Cyclic Redundancy Check) bit (5bit). The index pointer pool ID number indicates which index pointer pool the index pointer was originally stored in. When returning resources, it is necessary to "return the item to its original owner" and return the index pointer to the corresponding resource pool. Among them, the received tasks can be divided into two types. The first type is memory allocation, that is, creating a prp-list after obtaining the index, and the second type is memory recovery, that is, returning the index after recovering the prp-list.
[0063] See Figure 3 shown, an embodiment of the present application discloses an NVMe memory management method, including:
[0064] Step S11: Analyze the obtained NVMe memory allocation task to obtain the memory allocation task requirements, and read the target free index pointer from the corresponding index pointer pool based on the memory allocation task requirements.
[0065] In this embodiment, first, after receiving the NVMe memory allocation task, the NVMe memory allocation task is parsed. According to the task requirements obtained by parsing, the required target free index pointer is read from the corresponding index pointer pool.
[0066] Step S12: Determine the index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer, and judge the status of the target free index pointer based on the target flag bit of the target free index pointer recorded in the index status lookup table.
[0067] In this embodiment, determining the index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer includes: normalizing the target free index pointer to obtain the index label of the target free index pointer, and determining the index status lookup table corresponding to the index pointer pool based on the index label. Specifically, first normalize the index pointer. Assuming there are 4k of them, the normalized index pointer can be represented as 1 to 4096, and this normalized result is defined as the index pointer label. Each index pointer label corresponds to an index pointer flag bit, and 4K index pointer flag bits form the index pointer status lookup table. Each index pointer pool corresponds to a status lookup table, and the status bits in the table are updated in real time according to the behavior of taking and returning the index.
[0068] In this embodiment, judging the status of the target free index pointer based on the target flag bit of the target free index pointer recorded in the index status lookup table includes: performing a positioning search on the index status lookup table based on the index label to determine the target flag bit of the target free index pointer; detecting the target flag bit at a preset pointer detection port to judge whether the target free index pointer is in an available state. Specifically, after detecting a valid index pointer, read the corresponding flag bit for judgment. The information we can obtain according to the 0 and 1 flags is as follows: when the index pointer flag bit is 1, it means that the index pointer has been taken to construct the prp-list but has not been recycled and returned. When the index pointer flag bit is 0, it means that it has never been taken or the recycling of the index pointer has been completed.
[0069] Among them, locating and searching the index status lookup table based on the index label to determine the target flag bit of the target free index pointer includes: equally splitting the index label based on a preset bit width to obtain the split label; performing radix conversion on the first-dimensional label value, the second-dimensional label value, and the third-dimensional label value in the split label respectively to obtain the target coordinate value; the target coordinate value includes a first coordinate value on a preset X coordinate axis corresponding to the first-dimensional label value, a second coordinate value on a preset Y coordinate axis corresponding to the second-dimensional label value, and a third coordinate value on a preset Z coordinate axis corresponding to the third-dimensional label value; performing a lookup and positioning in the table area of the index status lookup table based on the first coordinate value in the first clock cycle to obtain the first-dimensional flag bit; after data pipelining the second coordinate value in the first clock cycle, in the second clock cycle, performing a lookup and positioning in the table area of the index status lookup table based on the second coordinate value and the first-dimensional flag bit to obtain the second-dimensional flag bit; the second clock cycle is the next clock cycle of the first clock cycle; after data pipelining the third coordinate value in the second clock cycle, in the third clock cycle, performing a lookup and positioning in the table area of the index status lookup table based on the third coordinate value and the second-dimensional flag bit to determine the target flag bit of the target free index pointer; the third clock cycle is the next clock cycle of the second clock cycle; correspondingly, detecting the target flag bit at a preset pointer detection port to determine whether the target free index pointer is in an available state, including: obtaining the flag value recorded by the target flag bit, and detecting the flag value using the preset pointer detection port to determine whether the target free index pointer is in an available state.
[0070] Since there are approximately 4K flag bits in the table, if directly selecting the corresponding bit for judgment, it involves a 4K-to-1 data selector, which is not allowed in an actual circuit because it will make it difficult to converge the timing. Therefore, the present invention proposes a method for splitting a multiplexer, which gradually locates the flag bit to be searched through the form of {x, y, z} coordinates and in a pipelined manner. Among them, the first-dimensional label value is x, the second-dimensional label value is y, and the third-dimensional label value is z. That is, first, the bit width of the received index label after normalization is 12 bits. We equally split it in units of 4 bits. x represents the decimal value corresponding to [11:8], y represents the decimal value corresponding to [7:4], and z represents the decimal value corresponding to [3:0]. Next, taking {9, 6, 16} as an example, first, by searching for x, it is possible to locate which 256-bit table area it belongs to, as Figure 4 shown. After determining the x area, pipeline the y coordinate, and in the next clock cycle, continue to search for the y coordinate from these 256 flag bits to locate which 16-bit area it belongs to. The intersection of the shaded areas in the upper and lower figures is the 16 flag bits located by the invention, as Figure 5As shown. After determining y, the z coordinate is clocked, and in the third clock cycle, the desired tag bit is located according to the z coordinate, and finally the tag value corresponding to the target free index pointer as shown in Figure 6 is obtained. In addition, when performing index position positioning, the target tag bit of the target free index pointer can be determined, including: evenly splitting the index tag based on a preset bit width to obtain the split tag; performing radix conversion on the first-dimensional tag value, the second-dimensional tag value, and the third-dimensional tag value in the split tag respectively to obtain the target coordinate values. Then, in the first clock cycle, a search and positioning are performed in the table area of the index status lookup table based on the first coordinate value x to obtain the first positioning area; in the second clock cycle, a search and positioning are performed in the table area of the index status lookup table based on the second coordinate value y to obtain the second positioning area; in the third clock cycle, a search and positioning are performed in the table area of the index status lookup table based on the third coordinate value z to obtain the third positioning area; the overlapping area of the first positioning area, the second positioning area, and the third positioning area is determined to obtain the target tag bit of the target free index pointer. In this way, since directly using a 4K selection would result in an excessive number of combinational logic levels and make it difficult to converge the timing, adopting this method can quickly locate the tag bit status while optimizing the timing.
[0071] In this embodiment, after obtaining the tag value, it is possible to detect on the resource acquisition side and the resource return side according to whether the current target free index pointer is closed-loop. As shown in Figure 7 , if it is detected at the entrance that the tag bit of the current target free index pointer is 1 and it is not closed-loop, it means that the index pointer has been allocated and not recycled, and the index pointer points to a continuous physical space. Not being recycled means that there are still other engines operating on the physical space pointed to by the target free index pointer. If the target free index pointer is re-allocated at this time, it may cause two engines to operate on the same physical space, resulting in a conflict and modifying the data in the memory, causing subsequent errors. Therefore, if it is detected at the entrance that the tag bit of the current target free index pointer is 1, the data can be discarded or an interrupt can be directly reported. Similarly, if it is detected at the exit that the current index tag bit is 0, it means that the index pointer has been recycled or not allocated yet. If an index pointer that has never been allocated or may not exist is returned to the pointer pool, it may cause duplicate or non-existent index pointers in the pool. Each index in the pointer pool is initialized to point to the start address of a physical space. If an error occurs, it may lead to accessing a non-existent physical space or a piece of memory that can never be accessed. Therefore, if it is detected at the exit that the current index tag bit is 0, the data can be discarded or an interrupt can be directly reported.
[0072] Step S13: If the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, construct a target physical region page list based on the target free index pointer to perform the NVMe memory allocation task.
[0073] In this embodiment, when the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, construct a target physical region page list based on the target free index pointer and perform the NVMe memory allocation task.
[0074] In addition, in this embodiment, it further includes: parsing the obtained NVMe memory recycling task to obtain the memory recycling task requirements, and reading the current physical region page list from the corresponding memory pool based on the memory recycling task requirements; extracting the current index pointer corresponding to the current physical region page list, and judging the current index pointer state based on the index status lookup table; if the current index pointer is in an unavailable state, clear the current physical region page list, and after modifying the current index pointer to an available state, write the current index pointer into the corresponding index pointer pool based on the preset bus protocol. Because using a single initiating write bus will overly occupy the bus resources and have low utilization. Therefore, when the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, select the method of classified aggregation and recycling to return the target index pointer.
[0075] Among them, writing the current index pointer into the corresponding index pointer pool based on the preset bus protocol includes: writing the current index pointer into the aggregation component corresponding to the index pointer pool number based on the index pointer pool number corresponding to the current index pointer; judging whether the aggregation component meets the preset aggregation condition; if the aggregation component meets the preset aggregation condition, write all the current index pointers in the aggregation component into the corresponding index pointer pool through the preset bus protocol. At the moment of reading back the free index value, it can be judged whether it is the target index pointer that needs to be recycled according to the VALID bit, and then select which aggregation module corresponding to the index pointer pool the index should be placed in according to the POOL ID number. When passing the duplicate pointer exit detection of the index pointer pool and the subsequent FIFO (First Input First Output) is not full, the index can be sent to the data index pointer FIFO. If the FIFO is not full, it can be written. If the index pointer FIFO is full, it will backpressure the upper level and stop writing until the writable space of the FIFO is released again, then writing can continue.
[0076] Among them, writing the current index pointer into the aggregation component corresponding to the index pointer pool number includes: writing the current index pointer into the first-in, first-out queue of the aggregation component corresponding to the index pointer pool number; correspondingly, determining whether the aggregation component meets the preset aggregation condition includes: determining whether the number of index pointers in the first-in, first-out queue reaches the maximum queue capacity; or, determining whether the current time reaches the preset request sending time threshold under the condition that the first-in, first-out queue is not empty. That is, the judgment of the aggregation condition includes: successful handshake, that is, the index pointer pool (slave side) is valid. This is a necessary condition; the number of readable data in the index pointer cache FIFO reaches the aggregation threshold; the timeout timing is reached and the index pointer cache FIFO is not empty. Among them, the aggregation threshold should not be set too large, otherwise it will cause the index loop speed to be slow and slow down the system process; nor should it be too small, otherwise the effect of improving the bus utilization efficiency and reducing the bus occupation time cannot be achieved. Therefore, the aggregation threshold in this design is 16. When the number of index pointers in the FIFO reaches 16, the aggregation moment can be triggered to initiate an AXI write with a burst length of 16. Each time a data is sent, the counter is decremented by 1. When the counter reaches zero, it is judged again whether the next AXI write can be initiated. If the number of data in the FIFO never meets 16, then the timeout value can also be set. Under the condition that the FIFO is not empty, if the aggregation threshold is still not met after the countdown ends, the remaining valid data will be written out at one time. The counter is set to the number of valid data in the current FIFO. Each time an index is sent, the counter is decremented by 1. When the counter reaches zero, the aggregation condition can be judged again.
[0077] It can be seen that in this embodiment, such as Figure 8As shown, the obtained NVMe memory allocation task is parsed to obtain the memory allocation task requirements, and based on the memory allocation task requirements, the target free index pointer is read from the corresponding index pointer pool; the index status lookup table corresponding to the index pointer pool is determined based on the index label of the target free index pointer, and the status of the target free index pointer is judged based on the target flag bit of the target free index pointer recorded in the index status lookup table; if the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, a target physical area page list is constructed based on the target free index pointer to execute the NVMe memory allocation task. That is, by judging the index status recorded in the index status lookup table, it is further determined whether the target free index pointer is really in an available state. After being in an available state, a target physical area page list is constructed using the target free index pointer to execute the NVMe memory allocation task. By judging the pointer status of the target free index pointer, it is avoided to take and recycle resources when the target free index pointer is unavailable, which may cause resource duplication in memory resource management, and can effectively improve the security and robustness of the resource recycling system.
[0078] Reference Figure 9 , the embodiment of the present application also correspondingly discloses an NVMe memory management device, including:
[0079] A pointer reading module 11, configured to parse the obtained NVMe memory allocation task to obtain the memory allocation task requirements, and read the target free index pointer from the corresponding index pointer pool based on the memory allocation task requirements;
[0080] A pointer status judgment module 12, configured to determine the index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer, and judge the status of the target free index pointer based on the target flag bit of the target free index pointer recorded in the index status lookup table;
[0081] A task execution module 13, configured to, if the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, construct a target physical area page list based on the target free index pointer to execute the NVMe memory allocation task.
[0082] It can be seen that in this embodiment, by judging the pointer status of the target free index pointer, it is avoided to take and recycle resources when the target free index pointer is unavailable, which may cause resource duplication in memory resource management, and can effectively improve the security and robustness of the resource recycling system.
[0083] Furthermore, the embodiment of the present application also discloses an electronic deviceFigure 10 It is a structural diagram of an electronic device shown according to an exemplary embodiment. The content in the figure should not be regarded as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the NVMe memory management method disclosed in any of the foregoing embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.
[0084] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.
[0085] In addition, as a carrier for resource storage, the memory 22 can be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0086] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the NVMe memory management method executed by the electronic device disclosed in any of the foregoing embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks.
[0087] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the NVMe memory management method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.
[0088] Furthermore, this application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the alarm aggregation method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.
[0089] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.
[0090] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.
[0091] The steps of the methods or algorithms described in combination with the embodiments disclosed in this article can be directly implemented by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.
[0092] Finally, it should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.
[0093] The technical solutions provided in this application have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.
Claims
1. An NVMe memory management method, characterized in that, Including: Parsing the obtained NVMe memory allocation task to obtain memory allocation task requirements, and reading a target free index pointer from a corresponding index pointer pool based on the memory allocation task requirements; Determining an index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer, and judging the status of the target free index pointer based on a target flag bit of the target free index pointer recorded in the index status lookup table; If the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, constructing a target physical region page list based on the target free index pointer to execute the NVMe memory allocation task.
2. The NVMe memory management method according to claim 1, wherein The determining an index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer includes: Performing normalization processing on the target free index pointer to obtain an index label of the target free index pointer, and determining an index status lookup table corresponding to the index pointer pool based on the index label.
3. The NVMe memory management method according to claim 2, wherein The judging the status of the target free index pointer based on a target flag bit of the target free index pointer recorded in the index status lookup table includes: Performing a positioning search on the index status lookup table based on the index label to determine the target flag bit of the target free index pointer; Detecting the target flag bit at a preset pointer detection port to judge whether the target free index pointer is in an available state.
4. The NVMe memory management method according to claim 3, wherein The performing a positioning search on the index status lookup table based on the index label to determine the target flag bit of the target free index pointer includes: Equally splitting the index label based on a preset bit width to obtain a split label; Performing radix conversion on a first-dimensional label value, a second-dimensional label value, and a third-dimensional label value in the split label respectively to obtain target coordinate values; the target coordinate values include a first coordinate value located on a preset X coordinate axis corresponding to the first-dimensional label value, a second coordinate value located on a preset Y coordinate axis corresponding to the second-dimensional label value, and a third coordinate value located on a preset Z coordinate axis corresponding to the third-dimensional label value; Performing a search and positioning in a table area of the index status lookup table based on the first coordinate value in a first clock cycle to obtain a first-dimensional flag bit; After data beating the second coordinate value in the first clock cycle, in a second clock cycle, performing a search and positioning in the table area of the index status lookup table based on the second coordinate value and the first-dimensional flag bit to obtain a second-dimensional flag bit; the second clock cycle is the next clock cycle of the first clock cycle; After data beating the third coordinate value in the second clock cycle, in the third clock cycle, based on the third coordinate value and the second dimension flag bit, perform a lookup and positioning in the table area of the index status lookup table to determine the target flag bit of the target free index pointer; the third clock cycle is the next clock cycle of the second clock cycle; Correspondingly, the detecting the target flag bit at the preset pointer detection port to determine whether the target free index pointer is in an available state includes: Obtain the flag value recorded by the target flag bit, and use the preset pointer detection port to detect the flag value to determine whether the target free index pointer is in an available state.
5. The NVMe memory management method according to any one of claims 1 to 4, characterized in that, It further includes: Parse the obtained NVMe memory recovery task to obtain the memory recovery task requirements, and read the current physical area page list from the corresponding memory pool based on the memory recovery task requirements; Extract the current index pointer corresponding to the current physical area page list, and judge the status of the current index pointer based on the index status lookup table; If the current index pointer is in an unavailable state, clear the current physical area page list, and after modifying the current index pointer to an available state, write the current index pointer into the corresponding index pointer pool based on the preset bus protocol.
6. The NVMe memory management method according to claim 5, characterized in that, The writing the current index pointer into the corresponding index pointer pool based on the preset bus protocol includes: Based on the index pointer pool number corresponding to the current index pointer, write the current index pointer into the aggregation component corresponding to the index pointer pool number; Judge whether the aggregation component meets the preset aggregation condition; If the aggregation component meets the preset aggregation condition, write all the current index pointers in the aggregation component into the corresponding index pointer pool through the preset bus protocol.
7. The NVMe memory management method according to claim 6, wherein The writing the current index pointer into the aggregation component corresponding to the index pointer pool number includes: Write the current index pointer into the first-in, first-out queue of the aggregation component corresponding to the index pointer pool number; Correspondingly, the judging whether the aggregation component meets the preset aggregation condition includes: Judge whether the number of index pointers in the first-in, first-out queue reaches the maximum queue capacity; Or, judge whether the current time reaches the preset request sending time threshold under the condition that the first-in, first-out queue is not empty.
8. An NVMe memory management device, characterized in that, It includes: A pointer reading module, configured to parse the obtained NVMe memory allocation task to obtain memory allocation task requirements, and read a target free index pointer from the corresponding index pointer pool based on the memory allocation task requirements; A pointer status judging module, configured to determine the index status lookup table corresponding to the index pointer pool based on the index label of the target free index pointer, and judge the status of the target free index pointer based on the target flag bit of the target free index pointer recorded in the index status lookup table; A task execution module, which is configured to, if the target flag bit indicates that the target free index pointer is in an available state, after modifying the target flag bit to an unavailable state, construct a target physical area page list based on the target free index pointer to execute the NVMe memory allocation task.
9. An electronic device, characterized in that, Comprising: A memory for storing a computer program; A processor for executing the computer program to implement the steps of the NVMe memory management method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps of the NVMe memory management method according to any one of claims 1 to 7 are implemented.