On-chip interconnection system redundancy fault-tolerant method based on large-scale brain-like computing

Abstract

The invention relates to the technical field of communication fault tolerance of an on-chip interconnection system, in particular to an on-chip interconnection system redundancy fault tolerance method based on large-scale brain-like computing, which adopts an MIMO module to realize inter-chip multichannel communication, effectively distributes communication paths through a fixed priority selection mechanism, and improves the fault tolerance of the on-chip interconnection system. And reliable data transmission can still be realized when the channel fails or is congested. Meanwhile, the system realizes parallel caching and transmission of data by introducing an SRAM (Static Random Access Memory) cache and a transmission protocol conversion module, and provides a calculation fault-tolerant capability when the calculation unit fails or the current data exceeds the calculation capability of the calculation unit. By combining space redundancy, information redundancy and time redundancy, an efficient and flexible fault-tolerant mechanism can be realized in the large-scale brain-like computing system-on-chip. The method is suitable for on-chip interconnection systems of different scales, and the stability and the fault-tolerant capability of the system can be remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of communication fault tolerance for on-chip interconnection systems, and particularly to a redundant fault tolerance method for on-chip interconnection systems based on large-scale brain-like computing. Background Art

[0002] With the gradual increase in the scale of the System on Chip (SoC), the Network on Chip (NoC) has become an important infrastructure for handling tasks such as multi-core processors, large-scale data transmission, and complex brain-like computing. In these applications, the performance and reliability of the on-chip interconnection system directly determine the efficiency and stability of the entire system. However, in practical applications, the NoC architecture may face various communication failures and data transmission problems, resulting in a decline in the stability of the system.

[0003] Data transmission in the NoC mainly relies on inter-chip and on-chip interconnections. These interconnection devices may experience transient failures (such as soft errors, data packet loss, etc.) or permanent physical damage (such as link disconnection, node failure, etc.) under high load or long-term operation. This situation not only interrupts the normal transmission of data but may also cause the failure of the entire on-chip system's functions, and in severe cases, it will affect the system's lifespan and reliability. Therefore, how to ensure the stability of the NoC by designing an effective fault tolerance mechanism has become one of the important research directions.

[0004] In the prior art, redundant design is usually adopted to enhance the fault tolerance of the system, mainly including the following three redundant methods: (1) Spatial redundancy: By increasing physical resource redundancy, such as adding multiple parallel transmission paths or redundant routers, to ensure that when a certain path or node fails, data can still be transmitted through other paths or nodes. This method improves the reliability of the system but also increases the physical size and power consumption of the chip.

[0005] (2) Information redundancy: By adding extra check bits or redundant data to data packets to achieve error detection and correction of data. The advantage of this method is that it can improve the reliability of the system with less resource overhead. However, if the error incidence is too high, the error correction mechanism may not be able to repair all errors in time, thereby affecting the correctness of data transmission.

[0006] (3) Temporal redundancy: By repeating data transmission or delaying data processing to reduce the risk of data loss or transmission errors. This method effectively copes with temporary failures by introducing redundancy in the time dimension, but in scenarios with high real-time requirements, excessive temporal redundancy may affect the overall performance of the system.

[0007] Although the above redundancy techniques improve the reliability of the system to a certain extent, their flexibility and scalability in applications are insufficient. For example, spatial redundancy requires additional hardware resources, the verification complexity of information redundancy is relatively high, and time redundancy introduces additional delays. In addition, as the scale of the system-on-chip continues to expand, it is difficult for a single redundancy method to meet the comprehensive requirements of different systems for performance, resources, power consumption, and reliability.

[0008] Especially in large-scale brain-inspired computing systems, the stability and real-time performance of data transmission are particularly important. Brain-inspired computing systems usually need to process a large number of parallel data streams, which include routing tables, weight information, neuron states transmitted during the pre-simulation stage, as well as pulses and neuron states uploaded by the hardware platform after the simulation ends. This large-scale parallel data exchange poses higher requirements for the reliability of on-chip communication, and traditional fault-tolerant mechanisms are difficult to adapt to such high-density, complex computing and communication scenarios.

[0009] Therefore, there is an urgent need for a new technical solution to solve the above technical problems. Summary of the Invention

[0010] The purpose of the present invention is to overcome the problems of the above existing technologies, and provides a redundancy fault-tolerant method for on-chip interconnection systems based on large-scale brain-inspired computing, so as to solve the technical problem that traditional fault-tolerant mechanisms are difficult to adapt to such large-scale parallel data exchange, high-density, complex computing and communication scenarios.

[0011] The above purpose is achieved through the following technical solutions: A redundancy fault-tolerant method for on-chip interconnection systems based on large-scale brain-inspired computing, including inter-chip communication based on a communication redundancy mechanism and intra-chip fault tolerance based on a computing redundancy mechanism, where: The inter-chip communication based on the communication redundancy mechanism realizes multi-channel fault-tolerant communication between chips through an MIMO module. The MIMO module is deployed in the four directions of the east, west, south, and north of the system-on-chip and is connected to the system-on-chip through the AXI4-Stream protocol; a fixed-priority selection mechanism is used to dynamically allocate communication paths. When a channel is detected to be busy or faulty, the arbiter sequentially selects the channel with the sub-optimal priority and idle for data transmission; The intra-chip fault tolerance based on the computing redundancy mechanism is achieved by setting a dual SRAM cache and a protocol conversion module in the chip. When the computing unit is unable to process data, the routing and communication unit routes the unprocessed data to the control unit, realizes the data format conversion between the AXI4-Stream and AHB protocols through the protocol conversion module, and the control unit takes over the computing task.

[0012] Further, the MIMO module includes: MIMO_RX module. When the MIMO_RX module receives data from the host computer, it selects the output channel according to the channel identifier and priority arbitration, and preferentially uses the high-priority idle channel; MIMO_TX module. When the MIMO_TX module transmits on-chip data to the host computer, it records the data source channel and dynamically selects the idle output channel through the select signal.

[0013] Furthermore, the inter-chip communication based on the communication redundancy mechanism supports parametric design, including: The number of input and output ports is dynamically adjusted according to the fault tolerance requirements and hardware resources; The data bit width is adapted to the system bus bit width; The output port adopts a synchronous output mode, and the input port supports synchronous or asynchronous mode selection.

[0014] Furthermore, it also includes enhanced fault tolerance, including: Spatial redundancy mechanism: Deploy multiple MIMO modules in different directions, and add redundant paths more than the chip scale in the MIMO module to achieve multi-path transmission; Temporal redundancy mechanism: When all output channels are busy, the data will wait until a channel becomes idle; Information redundancy mechanism: Add an additional CID identifier during data transmission to achieve information distribution and routing.

[0015] Furthermore, the temporal redundancy mechanism is specifically: When all output channels are busy, the data is temporarily stored in the input buffer unit until an idle channel is detected and the transmission is restarted.

[0016] Furthermore, the information redundancy mechanism is specifically: Attach a CID identifier when transmitting data packets to identify the data source and target path during the distribution and routing process.

[0017] Furthermore, the working process of the dual SRAM cache includes: When writing data, if both SRAM caches are idle, select the one to write according to the SRAM priority; if one SRAM cache is occupied and the other is idle, select the idle SRAM cache to write; if both SRAM caches are occupied, it is in a waiting data state; Dynamically indicate the availability of the SRAM cache through the status signal to achieve automatic switching of the buffer area.

[0018] Furthermore, the protocol conversion module includes: AXI4-Stream to AHB protocol conversion bridge: Used to adapt the bus interfaces of the routing communication unit and the control unit; Data beat counter and address mapping table: used to ensure the integrity and timing consistency of cross - protocol transmission.

[0019] Furthermore, the failure migration path of the computing unit is specifically as follows: when the computing unit stops working due to overload or hardware failure, the routing and communication unit marks the unprocessed data as the type of "to be transmitted to the computing unit" and routes it to the control unit for processing through a dedicated channel.

[0020] A redundancy and fault - tolerance method for on - chip interconnection system based on large - scale brain - like computing provided by the present invention can be adjusted according to the requirements of on - chip interconnection systems of different scales; meanwhile, by adopting dynamic channel selection and data caching, it can effectively reduce system failures and communication jams, and significantly improve the stability and efficiency of the on - chip interconnection system. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of the on - chip interconnection system in a redundancy and fault - tolerance method for on - chip interconnection system based on large - scale brain - like computing of the present invention; Figure 2 It is a connection structure diagram of the MIMO_RX module in the MIMO module and its upstream and downstream in a redundancy and fault - tolerance method for on - chip interconnection system based on large - scale brain - like computing of the present invention; Figure 3 It is a connection structure diagram of the MIMO_TX module in the MIMO module and its upstream and downstream in a redundancy and fault - tolerance method for on - chip interconnection system based on large - scale brain - like computing of the present invention; Figure 4 It is a schematic diagram of the communication process of the inter - chip interconnection fault - tolerance - MIMO module in a redundancy and fault - tolerance method for on - chip interconnection system based on large - scale brain - like computing of the present invention; Figure 5 It is an architecture diagram of the on - chip content - fault - tolerance module in a redundancy and fault - tolerance method for on - chip interconnection system based on large - scale brain - like computing of the present invention; Figure 6 It is an interaction schematic diagram of the on - chip content - fault - tolerance module and its upstream and downstream modules in a redundancy and fault - tolerance method for on - chip interconnection system based on large - scale brain - like computing of the present invention. Detailed Embodiments

[0022] The present invention will be further described in detail below with reference to the drawings and embodiments. The described embodiments are only a part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0023] This solution provides a redundancy and fault tolerance method for on-chip interconnection systems based on large-scale brain-inspired computing, aiming to improve the reliability of data transmission and computing processing in on-chip interconnection systems. This method combines the advantages of spatial redundancy, information redundancy, and time redundancy, and through parametric design and fixed-priority management, realizes a highly reliable communication and fault tolerance mechanism for large-scale brain-inspired computing systems to meet the system requirements under different fault scenarios; including inter-chip communication based on a communication redundancy mechanism and intra-chip fault tolerance based on a computing redundancy mechanism, where: The inter-chip communication based on the communication redundancy mechanism realizes multi-channel fault-tolerant communication between chips through the MIMO module. The MIMO module is deployed in the four directions of the east, west, south, and north of the on-chip system and is connected to the on-chip system through the AXI4-Stream protocol; a fixed-priority selection mechanism is adopted to dynamically allocate communication paths. When a channel is detected to be busy or faulty, the arbiter sequentially selects the channel with the sub-optimal priority and is idle for data transmission; flexible configuration of the number of input / output ports, data bit width, and synchronous / asynchronous input mode is supported through parametric design; specifically, when the on-chip interconnection system for brain-inspired computing interacts with the host computer, it needs to transmit routing tables, weight information, neuron states, etc. At the same time, there is also some necessary data interaction and transmission between chips. To ensure the reliability of communication, the present invention realizes multi-channel fault-tolerant communication through a multi-input multi-output (MIMO) module. The MIMO module communicates with all directions of the on-chip system through the AXI4-Stream protocol, is deployed in the four directions of the east, west, south, and north of the on-chip system, and adopts a fixed-priority mechanism to select the output channel to ensure reliable data transmission in the case of a busy channel and a fault in a certain channel; The intra-chip fault tolerance based on the computing redundancy mechanism is achieved by setting up a dual-SRAM cache and a protocol conversion module in the chip. When the computing unit (BPU) is unable to process data, the routing and communication unit (RPU) routes the unprocessed data to the control unit (CPU), realizes the data format conversion between the AXI4-Stream and AHB protocols through the protocol conversion module, and the control unit (CPU) takes over the computing task; using the asynchronous read and write mechanism of the dual-SRAM cache, the buffer area is dynamically switched to match the writing rate of the RPU and the processing rate of the CPU to avoid data congestion. Specifically, as Figure 5 shown, a single computing chip (Tile) consists of a BPU, an RPU, and a CPU. The BPU is responsible for core computing, the RPU is responsible for communication, and the CPU is responsible for control and handling of emergencies. By adding a data transmission protocol conversion module between the CPU and the RPU, the temporary storage and processing of data packets that the BPU fails to process are realized. At the same time, to reduce the congestion problem caused by the mismatch of data transmission rates, two SRAM caches are placed in the intra-chip fault tolerance module.

[0024] As Figure 4 shown, in this embodiment, the MIMO module includes: The MIMO_RX module, when receiving data from the host computer, selects the output channel according to the channel identifier (cid) and priority arbitration, and preferentially uses the high-priority idle channel. The MIMO_TX module, when transmitting on-chip data to the host computer, records the data source channel and dynamically selects the idle output channel through the select signal.

[0025] As an optimization of the inter-chip communication based on the communication redundancy mechanism in this embodiment, the inter-chip communication based on the communication redundancy mechanism supports parametric design, including: The number of input and output ports is dynamically adjusted according to the fault tolerance requirements and hardware resources; The data bit width is adapted to the system bus bit width; The output port adopts a synchronous output mode, and the input port supports synchronous or asynchronous mode selection.

[0026] The inter-chip communication based on the communication redundancy mechanism also includes enhanced fault tolerance, including: Spatial redundancy mechanism: Deploy multiple MIMO modules in different directions, and add redundant paths more than the chip scale in the MIMO module to achieve multi-path transmission; Temporal redundancy mechanism: When all output channels are busy, the data will wait until a channel becomes idle; Information redundancy mechanism: Add an additional CID identifier during data transmission to achieve information distribution and routing.

[0027] Specifically, the temporal redundancy mechanism is specifically: when all output channels are busy, the data is temporarily stored in the input buffer unit until an idle channel is detected and the transmission is restarted.

[0028] The information redundancy mechanism is specifically: attach a CID identifier when transmitting data packets to identify the data source and target path during the distribution and routing process.

[0029] The working process of the dual SRAM cache in this embodiment includes: When writing data, if both SRAM caches are idle, select the one to write according to the SRAM priority; if one SRAM cache is occupied and the other is idle, select the idle SRAM cache to write; if both SRAM caches are occupied, it is in a state of waiting for data; Dynamically indicate the availability of the SRAM cache through the status signal to achieve automatic switching of the buffer area.

[0030] The protocol conversion module in this embodiment includes: AXI4-Stream to AHB protocol conversion bridge: used to adapt the bus interfaces of the routing communication unit (RPU) and the control unit (CPU); Data beat counter and address mapping table: used to ensure the integrity and timing consistency of cross-protocol transmission.

[0031] In this embodiment, the failure migration path of the computing unit (BPU) is specifically as follows: when the computing unit (BPU) stops working due to overload or hardware failure, the routing communication unit (RPU) marks the unprocessed data as the type of "to be transmitted to the computing unit (BPU)", and routes it to the control unit (CPU) for processing through a dedicated channel. Embodiment

[0032] This embodiment introduces the implementation of the communication redundancy mechanism In this embodiment, the communication redundancy mechanism is implemented through a multiple-input multiple-output (MIMO) module. This module aims to ensure the reliability of data transmission between the on-chip interconnection system and the host computer. The following describes the specific implementation details: 1. MIMO communication module design: In a large-scale brain-inspired computing on-chip interconnection system, a structure based on a two-dimensional Mesh topology is used, as Figure 1 shown, to design the MIMO_TX_RX module, which is responsible for multi-directional data communication. This module is deployed in the four directions of the east, west, south, and north of the system to ensure that there are multiple redundant channels in the communication path.

[0033] 2. The working process of the MIMO_RX module, as Figure 2 shown, is as follows: (1) MIMO_RX receives data from the host computer, and its structure is as Figure 2 shown. The input data contains two parts: the data itself (data) and the channel identifier (cid), where cid is determined by the host computer and indicates from which direction the data is output to the on-chip system.

[0034] (2) When MIMO_RX receives the data, it first temporarily stores the data through the input buffer unit, and then the arbiter determines the data output channel according to the busy and idle status of the channels. If the high-priority channel is idle, the data is directly output, otherwise the low-priority channels are detected in sequence until an available channel is found for data output.

[0035] 3. The working process of the MIMO_TX module, as Figure 3 shown, is as follows: (1) MIMO_TX is responsible for transmitting on-chip data to the host computer, and its structure is as Figure 3As shown in the figure. When data within the chip needs to be transmitted, MIMO_TX records the channel from which the data originates and transmits the recorded channel information to the host computer via the select signal.

[0036] (2) When data is output, the system dynamically selects the channel with the highest priority and is idle for transmission according to the busy and idle states of each output channel to ensure the efficient utilization of the communication link.

[0037] 4. Dynamic redundancy design: (1) The MIMO module of the present invention can adjust the number of input and output ports and the data transmission mode according to the on-chip system scale, data bit width, and fault tolerance requirements through flexible parametric design.

[0038] (2) The output port adopts a synchronous output mode, and the input port can select a synchronous or asynchronous input mode according to the system requirements to adapt to the communication requirements in different application scenarios.

[0039] 5. Fault tolerance implementation of the redundancy mechanism: When a fault occurs in a certain transmission channel in the system, the MIMO module can automatically select a backup channel for data transmission to ensure that the communication is not interrupted. In addition, when all channels are busy, the data will be cached until there is an idle channel available for data transmission. Embodiment

[0040] This embodiment introduces the implementation method of the in-chip computing fault tolerance system As Figure 5 and 6 shown, in this embodiment, the CPU takes over the tasks not processed by the BPU to achieve computational redundancy in the fault scenario, specifically including the following core parts: 1. Chip module collaborative architecture The brain-inspired computing chip includes three core modules: BPU (Brain-inspired Computing Unit), which undertakes high-density parallel tasks such as neuron simulation and synaptic calculation and is the core computing power unit of the chip; RPU (Routing Communication Unit), which realizes inter-chip data routing based on the AXI4-Stream protocol and supports multi-channel high-speed data transmission; CPU (Control Unit), which is connected to the local module (LOCAL) of the RPU through the AHB bus and has a built-in CPU_TR data transmission module.

[0041] The CRU_TR data transmission module also includes two sub-modules: (1) CPU_RCV (Receiving Module), which receives the data packets routed by the RPU, caches them in the SRAM, and triggers CPU processing; (2)CPU_TRANS (Transmission Module), reads the data processed by the CPU, converts it into the AXI4-Stream format, and outputs it to the RPU.

[0042] 2. Dual SRAM Caching and Data Interaction Process (1)Data Reception and Caching Trigger: The RPU routes the data that the BPU cannot process to CPU_RCV, converts the AXI4-Stream signal into an AHB protocol signal through the AXI4-Stream2AHB protocol bridge, and adapts to the CPU bus interface; The data is written to the SRAM (SRAM2 / SRAM3) according to the SRAM priority and real-time status, and the write target is dynamically switched through the status signal (for example, when one block is being written, the other block is available for the CPU to read), avoiding read-write conflicts; After the data is written, CPU_RCV generates an interrupt signal to notify the CPU, accompanied by the cache address and data length information, triggering the CPU to read the data through the AHB bus.

[0043] (2)CPU Processing and Data Feedback: The CPU reads the data from the specified SRAM according to the interrupt information and performs the calculation operation; The processed data is written to the target SRAM (SRAM0 / SRAM1) of CPU_TRANS through the AHB, synchronously updating the status signal to confirm the data availability; CPU_TRANS converts the SRAM data into the AXI4-Stream format, and sends it to the rest of the Tiles or the host computer through the RPU, completing the closed-loop of the calculation results.

[0044] 3. Core Design of the Fault Tolerance Mechanism (1)BPU Fault Migration Path When the BPU stops calculating due to overload or hardware failure, the RPU will mark the unprocessed data packets as "data packets to be transmitted to the CPU" according to the information, and route them to the CPU_TR module through a dedicated channel; CPU_RCV caches the data and triggers an interrupt, and the CPU temporarily takes over the calculation task to prevent the system from crashing due to a single-point failure and ensure the continuous processing of critical calculation data.

[0045] (2)Asynchronous Caching and Rate Matching The dual-SRAM architecture supports the asynchronous operation of the RPU and the CPU. When the RPU writes to SRAM0, the CPU can simultaneously read SRAM1, and vice versa; when the RPU write rate is greater than the CPU processing rate, the two SRAMs can alleviate the data congestion caused by the rate mismatch between the RPU and the CPU, reducing the bus bandwidth bottleneck; The status signal dynamically indicates the available status of the SRAM, automatically switches the buffer during data transmission, and realizes the "write - process - send" pipelined operation to improve data throughput.

[0046] (3)Seamless docking of heterogeneous protocols The AXI4 - Stream2AHB bridge is used to solve the protocol differences between the RPU (AXI4 - Stream) and the CPU (AHB), and supports data format conversion and timing adaptation between different buses; The CPU_TR module has a built - in data beat counter and address mapping table to ensure the integrity and timing consistency of data packets during cross - protocol transmission.

[0047] The above is only to illustrate the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A redundancy fault tolerance method for on-chip interconnection system based on large-scale brain-inspired computing, characterized in that It includes inter-chip communication based on a communication redundancy mechanism and intra-chip error correction based on a computing redundancy mechanism, where: The inter-chip communication based on the communication redundancy mechanism realizes multi-channel fault-tolerant communication between chips through the MIMO module. The MIMO module is deployed in the four directions of east, west, south, and north of the system-on-chip and is connected to the system-on-chip through the AXI4-Stream protocol. A fixed-priority selection mechanism is adopted to dynamically allocate communication paths. When a channel is detected to be busy or faulty, the arbiter sequentially selects the channel with the sub-optimal priority and is idle for data transmission; The intra-chip error correction based on the computing redundancy mechanism is achieved by setting up dual SRAM caches and a protocol conversion module in the chip. When the computing unit (BPU) is unable to process data, the routing communication unit (RPU) routes the unprocessed data to the control unit (CPU), and the protocol conversion module realizes the data format conversion between AXI4-Stream and AHB protocols, and the control unit (CPU) takes over the computing task.

2. A redundancy and fault tolerance method for on-chip interconnection system based on large-scale brain-inspired computing according to claim 1, characterized in that The MIMO module includes: The MIMO_RX module. When receiving data from the host computer, the MIMO_RX module selects the output channel according to the channel identifier (cid) and priority arbitration, and preferentially uses the high-priority idle channel; The MIMO_TX module. When transmitting on-chip data to the host computer, the MIMO_TX module records the data source channel and dynamically selects an idle output channel through the select signal.

3. A redundancy and fault tolerance method for on-chip interconnection system based on large-scale brain-inspired computing according to claim 1 or 2, characterized in that, The inter-chip communication based on the communication redundancy mechanism supports parametric design, including: The number of input and output ports is dynamically adjusted according to the fault-tolerant requirements and hardware resources; The data bit width is adapted to the system bus bit width; The output port adopts a synchronous output mode, and the input port supports synchronous or asynchronous mode selection.

4. A redundancy and fault tolerance method for on-chip interconnection system based on large-scale brain-inspired computing according to claim 3, characterized in that It also includes enhanced fault tolerance, including: Spatial redundancy mechanism: Deploy multiple MIMO modules in different directions, and add redundant paths more than the chip scale in the MIMO module to achieve multi-path transmission; Temporal redundancy mechanism: When all output channels are busy, the data will wait until a channel becomes idle; Information redundancy mechanism: Add an additional CID identifier during data transmission to realize the distribution and routing of information.

5. A redundancy and fault tolerance method for on-chip interconnection system based on large-scale brain-inspired computing according to claim 4, characterized in that, The temporal redundancy mechanism is specifically: When all output channels are busy, the data is temporarily stored in the input buffer unit until an idle channel is detected and the transmission is restarted.

6. A redundancy and fault tolerance method for on-chip interconnection system based on large-scale brain-inspired computing according to claim 4, characterized in that The information redundancy mechanism is specifically: Attach a CID identifier when transmitting data packets to identify the data source and target path during the distribution and routing process.

7. A redundancy and fault tolerance method for an on-chip interconnection system based on large-scale brain-like computing according to claim 1, characterized in that The working process of the dual SRAM cache includes: When writing data, if both SRAM caches are idle, select one to write according to the SRAM priority; if one SRAM cache is occupied and the other is idle, select the idle SRAM cache to write; if both SRAM caches are occupied, it is in a state of waiting for data; Dynamically indicate the availability of the SRAM cache through status signals to realize automatic switching of the buffer area.

8. A redundancy fault tolerance method for an on-chip interconnection system based on large-scale brain-inspired computing according to claim 1, characterized in that The protocol conversion module includes: AXI4-Stream to AHB protocol conversion bridge: used to adapt the bus interfaces of the routing communication unit (RPU) and the control unit (CPU); Data beat counter and address mapping table: used to ensure the integrity and timing consistency of cross-protocol transmission.

9. A redundancy fault tolerance method for on-chip interconnection system based on large-scale brain-inspired computing according to claim 1, characterized in that The specific failure migration path of the computing unit (BPU) is as follows: when the computing unit (BPU) stops working due to overload or hardware failure, the routing communication unit (RPU) marks the unprocessed data as the type of "to be transmitted to the computing unit (BPU)", and routes it to the control unit (CPU) through a dedicated channel for processing.

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