Chip verification method and device and electronic equipment
By automatically allocating storage space for each stream and generating a second table entry in chip verification, the high code volume problem caused by complex table entry correlation and constraints is solved, and fast configuration and efficient verification are achieved.
Patent Information
- Application Number
- CN202510574064.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-06
- Publication Date
- 2025-08-01
AI Technical Summary
During the chip verification process, as the number of table entries increases and the complexity of correlation increases, verification personnel need to write a large amount of verification code and debug constraint code, resulting in an increase in time and manpower investment. Especially in the presence of mutually exclusive constraints, the existing methods are inefficient.
By automatically allocating storage space for each stream in the first table entry and generating the second table entry based on the allocation results, the rapid configuration of the common table entry structure is realized, the amount of verification and constraint code is reduced, and the debugging overhead is reduced.
It realizes the rapid configuration of chip verification, reduces the amount of verification code, reduces the debugging overhead caused by unsuccessful constraint codes, and improves verification efficiency.
Smart Images
Figure CN120407308A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip verification technologies, and in particular, to a chip verification method, apparatus, and electronic device. Background Art
[0002] In order to store information inside a chip, various table entries for chip functions are set up, and these table entries cooperate with each other to implement the functions of the chip. Since these table entries need to be used in cooperation, there is a certain correlation and constraint between different table entries. During the verification process of the chip, these table entries need to be configured to verify whether the logic function of the DUT (Design Under Test) is correct, and the verifier needs to consider the correlation and constraint between these table entries when configuring the table entries. As the complexity of chip design continues to increase, the number of table entries also continues to increase, and the correlation and constraint between each table entry become more complex. The time and human effort spent by the verifier in constructing table entries that meet the correlation and constraint gradually become the bottleneck of module verification or system verification.
[0003] If there are mutually exclusive constraints in different table entries, currently, verifiers generally use the constraint syntax provided by UVM (Universal Verification Methodology) in the UVM verification platform to implement each mutually related table entry one by one according to the index. A large amount of verification code needs to be written, and time is spent debugging whether these constraint codes are effective and successfully constrained. Among them, the existence of a mutually exclusive relationship means that when multiple streams share one entry resource, there cannot be an overlapping bit space between them.
[0004] For example, Table Entry 1 is associated with Table Entry 2. Table Entry 2 is a configuration file table entry for Table Entry 1. In Table Entry 2, configuration and subsequent use need to be combined with the configuration information in Table Entry 1. For example, starting information is configured at the corresponding position of Table Entry 2 based on Table Entry 1, and then relevant analysis and judgment are performed based on this starting information, and information is recorded in Table Entry 1 based on Table Entry 2. The recorded position ranges of different streams cannot overlap. If Table Entry 2 is implemented through the constraint syntax, a large amount of verification code needs to be written, and time is spent debugging whether these constraint codes are effective and successfully constrained. Summary of the Invention
[0005] Embodiments of this application provide a chip verification method, apparatus, electronic device, and readable storage medium, which can automatically allocate storage space for each stream in a first table entry for storing message information, and then perform chip verification based on a second table entry obtained after the storage space allocation is completed. In this way, fast configuration of mutual exclusion of common table entry structures can be automatically realized, which not only greatly reduces the amount of verification code, but also greatly reduces the debugging overhead caused by unsuccessful constraint codes.
[0006] Embodiments of the present application can be implemented as follows:
[0007] In a first aspect, an embodiment of the present application provides a chip verification method, and the method includes:
[0008] For each flow, automatically allocate idle storage space as the corresponding flow storage space for the flow in a first entry of a first table according to the current space allocation information, and obtain a second table according to the allocation result, where the current space allocation information is used to indicate the storage space allocation situation of each first entry of the current first table, the idle storage space is the unallocated storage space, the second entry in the second table is used to indicate the flow storage space allocated for each flow, and the flow storage space is used to store the message information of the corresponding flow;
[0009] Record information according to the second table and the corresponding flow storage space of the message to be recorded in the storage space of the first table to perform chip verification, where the chip to be verified performs information recording.
[0010] In a second aspect, an embodiment of the present application provides a chip verification device, and the device includes:
[0011] A configuration module, configured to, for each flow, automatically allocate idle storage space as the corresponding flow storage space for the flow in a first entry of a first table according to the current space allocation information, and obtain a second table according to the allocation result, where the current space allocation information is used to indicate the storage space allocation situation of each first entry of the current first table, the idle storage space is the unallocated storage space, the second entry in the second table is used to indicate the flow storage space allocated for each flow, and the flow storage space is used to store the message information of the corresponding flow;
[0012] A verification module, configured to record information according to the second table and the corresponding flow storage space of the received message in the storage space of the first table to perform chip verification, where the chip to be verified performs information recording.
[0013] In a third aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, where the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the chip verification method described in the foregoing embodiments.
[0014] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the chip verification method described in the foregoing embodiments.
[0015] The chip verification method, device, electronic device, and readable storage medium provided by the embodiments of the present application first automatically allocate free storage space as the corresponding flow storage space for each flow in a first entry of a first table item according to the current space allocation information, and obtain a second table item according to the allocation result; then, information recording is performed according to the second table item and the corresponding flow storage space of the packet to be recorded in the storage space of the first table item to perform chip verification. Among them, the current space allocation information is used to indicate the storage space allocation situation of each first entry of the current first table item, the free storage space is the unallocated storage space, the second entry in the second table item is used to indicate the flow storage space allocated for each flow, and the flow storage space is used to store the packet information of the corresponding flow; the chip to be verified performs information recording. The above method can automatically allocate storage space for each flow in the first table item for storing packet information, and then perform chip verification based on the second table item obtained after the storage space allocation is completed. In this way, the rapid configuration of mutual exclusion of the common table item structure can be automatically realized, which not only greatly reduces the amount of verification code, but also greatly reduces the debugging overhead caused by unsuccessful constraint codes. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.
[0017] Figure 1 Structural schematic diagram of a multi-logic common table item;
[0018] Figure 2 Block diagram of the electronic device provided by the embodiments of the present application;
[0019] Figure 3 Flow chart of the chip verification method provided by the embodiments of the present application;
[0020] Figure 4 For Figure 3 One of the flow charts of the sub-steps included in step S110 in
[0021] Figure 5 For Figure 4 Flow chart of the sub-steps included in sub-step S113 in
[0022] Figure 6 For Figure 4 Flow chart of the sub-steps included in sub-step S114 in
[0023] Figure 7 ForFigure 3 The second schematic flow diagram of the sub-steps included in step S110;
[0024] Figure 8 The schematic structural diagram of the second table entry provided by the embodiment of the present application;
[0025] Figure 9 The schematic process diagram of obtaining the second table entry provided by the embodiment of the present application;
[0026] Figure 10 The schematic block diagram of the chip verification device provided by the embodiment of the present application.
[0027] Icons: 100 - electronic device; 110 - memory; 120 - processor; 130 - communication unit; 200 - chip verification device; 210 - configuration module; 220 - verification module. Detailed implementation manners
[0028] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.
[0029] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0030] It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.
[0031] There are mutually exclusive configuration constraints for multiple logical common table entries. The structure of multiple logical common table entries can be as Figure 1As shown, a multi-logic common table entry may include multiple entries, each entry being 1024 bits, that is, the storage space for each entry is 1024 bits. Figure 1 The narrowest column in Figure 1 represents a data width of 64 bits. The available granularities in the multi-logic common table entry are 64 / 128 / 256 / 512 / 1024 bits, and the content stored in the storage space is determined by actual requirements. Among them, there can be multiple record statuses of flows within the same entry, but there is a mutually exclusive relationship in the storage space ranges used by different flows, that is, when multiple flows share the resources of one entry, there cannot be an overlapping situation in the bit spaces between them.
[0032] For example, each bit corresponds to a record mark indicating whether there is a packet output for the SN (Sequence number) of a packet of a flow. If there is a packet output, it is recorded as 1, otherwise it is recorded as 0. There can be multiple SN record statuses of flows within the same entry, but there is a mutually exclusive relationship in the storage space ranges used by different flows, that is, when multiple flows share the resources of one entry to record the SN status, there cannot be an overlapping situation in the bit spaces between them.
[0033] In the UVM verification platform, if the mutually exclusive configuration of the multi-logic common table entry is implemented through the constraint syntax provided by UVM, a large amount of verification code needs to be written, and time is spent debugging whether these constraint codes are effective and successfully constrained.
[0034] In view of the above situation, the embodiments of the present application provide a chip verification method, device, and electronic device, which automatically allocate storage space for each flow in the first table entry for storing packet information, and then perform chip verification based on the second table entry obtained by completing the flow storage space. In this way, the rapid configuration of the mutually exclusive structure of the common table entry can be automatically realized, which not only greatly reduces the amount of verification code but also greatly reduces the debugging overhead caused by unsuccessful constraint codes.
[0035] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0036] Please refer to Figure 2 , Figure 2The block diagram of the electronic device 100 provided by the embodiment of the present application is shown. The electronic device 100 may be, but is not limited to, a computer, a server, etc. The electronic device 100 may include a memory 110, a processor 120, and a communication unit 130. Each of the memory 110, the processor 120, and the communication unit 130 is directly or indirectly electrically connected to each other to achieve data transmission or interaction. For example, these components may be electrically connected to each other through one or more communication buses or signal lines.
[0037] Among them, the memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.
[0038] The processor 120 is used to read / write the data or programs stored in the memory 110 and perform corresponding functions. For example, a chip verification device 200 is stored in the memory 110, and the chip verification device 200 includes at least one software function module that can be stored in the memory 110 in the form of software or firmware. The processor 120 executes various function applications and data processing by running the software programs and modules stored in the memory 110, such as the chip verification device 200 in the embodiment of the present application, that is, the chip verification method in the embodiment of the present application is implemented.
[0039] The communication unit 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through a network and is used to send and receive data through the network.
[0040] It should be understood that Figure 2 The structure shown is only the schematic diagram of the structure of the electronic device 100, and the electronic device 100 may further include more or fewer components than those shown Figure 2 herein, or have a different configuration from that shown Figure 2 herein. It is worth noting that Figure 2Each of the components shown can be implemented in hardware, software, or a combination thereof. That is, the implementation of the processing flow of the chip verification method in the above embodiments is not limited to the processor reading and running pure computer-readable program code from the memory, but can also be implemented by means of hardware or logic devices.
[0041] It should be understood here that the improvement of a technology can be divided into hardware improvements (for example, improvements to circuit structures such as diodes, transistors, switches, etc.) and software improvements (improvements to method flows). However, with the development of technology, many improvements to method flows today can be regarded as direct improvements to hardware circuit structures. Almost all designers obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement to a method flow cannot be implemented with a hardware entity module. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logical function is determined by the user programming the device. The designer can program by himself to "integrate" a digital system on a PLD, without having to ask a chip manufacturer to design and fabricate a dedicated integrated circuit chip. Moreover, nowadays, instead of manually fabricating integrated circuit chips, this programming is mostly implemented using "logic compiler" software, which is similar to the software compiler used in program development writing, and the original code before compilation also has to be written in a specific programming language, which is called Hardware Description Language (HDL), and there is not only one type of HDL, but many types, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. Among them, the most commonly used currently are VHDL (Very High Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be clear that as long as the method flow is slightly logically programmed with the above-mentioned several hardware description languages and programmed into the integrated circuit, it is easy to obtain the hardware circuit that implements the logical method flow.
[0042] Please refer to Figure 3 , Figure 3Schematic flowchart of the chip verification method provided by the embodiments of the present application. The method can be applied to the above-mentioned electronic device. The specific process of the chip verification method will be elaborated in detail below. In this embodiment, the method may include steps S110 to S120.
[0043] Step S110: For each flow, automatically allocate idle storage space as the corresponding flow storage space for the flow in one of the first entries of the first table according to the current space allocation information, and obtain a second table according to the allocation result.
[0044] In this embodiment, the chip to be verified needs to record the message information corresponding to each of multiple flows for chip verification. The first table is a table for storing the message information corresponding to each of multiple flows. That is, the first table can be understood as a storage resource pool. The first table includes multiple entries. Subsequently, the entries in the first table are referred to as first entries. The first table is the multi-logic shared table mentioned above. The second table is the configuration file table of the first table, and the second table is used to indicate the correspondence between the storage space in the first table and each of the multiple flows. The second table includes multiple entries. Subsequently, the entries in the second table are referred to as second entries.
[0045] Before verification, for one of the multiple flows, automatically allocate a part of the idle storage space from the idle storage space of the first entry in the first table as the flow storage space corresponding to the flow according to the current space allocation information, and update the current space allocation information according to the updated space storage allocation situation this time; then, a flow can be determined from the remaining flows, and the above process can be repeated until the flow storage space is allocated from the first table for each flow. Among them, the idle storage space is the unallocated storage space. The current space allocation information is used to indicate the storage space allocation situation of each first entry in the current first table, that is, it is used to indicate which spaces in the storage space of each first entry have been allocated and which spaces have not been allocated. When the flow storage space allocation for multiple flows is completed, the second table can be obtained based on the allocation result. The second entry in the second table is used to indicate the flow storage space allocated for each flow. That is, based on the second entry, the specific location of the flow storage space of a flow can be determined, that is, it can be determined which bit spaces are the spaces available for the flow i. The flow storage space is used to store the message information corresponding to the flow, and can be specifically determined according to actual requirements.
[0046] Step S120: Record information according to the second table and the corresponding flow storage space of the message to be recorded in the storage space of the first table for chip verification.
[0047] In this embodiment, the chip to be verified may include the above-mentioned first entry and second entry. When performing verification, the chip to be verified may record information in the corresponding flow storage space in the storage space of the first entry according to the second entry and the currently determined packet to be recorded, so as to perform chip verification. For example, the chip to be verified needs to record the relevant information of the currently determined packet to be recorded in order to implement a certain function; then, during verification, the second entry can be obtained through step 110, and then the packet-related information can be recorded in the first entry based on the second entry, so as to perform function verification.
[0048] This embodiment is directed to Figure 1 the multi-logic shared entry shown, automatically allocates storage space for each flow in the multi-logic shared entry (i.e., the first entry) for storing packet information, and then performs chip verification based on the second entry obtained after the storage space allocation is completed. In this way, the fast configuration of the mutual exclusion of the common entry structure can be automatically realized, which not only greatly reduces the amount of verification code, but also greatly reduces the debugging overhead caused by the unsuccessful constraint code.
[0049] In this embodiment, the flow storage space can be allocated for a flow in the manner shown in Figure 4 . Please refer to Figure 4 , Figure 4 which is Figure 3 one of the flow schematic diagrams of the sub-steps included in step S110. In this embodiment, step S110 may include sub-steps S112 to sub-step S115.
[0050] Sub-step S112, determine the flow identifier of a flow as the first target flow identifier.
[0051] In this embodiment, the flow identifiers of multiple flows that need to be allocated flow storage space can be determined. Then, a flow identifier can be randomly selected from the unallocated flow identifiers as the current first target flow identifier. Alternatively, the flow identifiers of multiple flows can also be sorted based on the naming rule of the flow identifier. For example, if the flow identifiers of multiple flows are 0, 1, 2, etc., then the multiple flow identifiers can be sorted in ascending or descending order of numbers, and then a flow identifier can be used as the current first target flow identifier in sequence.
[0052] Sub-step S113, according to the current space allocation information, determine a first target entry identifier with free storage space as the first target entry identifier corresponding to the first target flow identifier.
[0053] Since the current space allocation information indicates the storage space allocation of each first entry of the current first table entry, a first target entry identifier of a first target entry can be determined based on the current space allocation information. There is free storage space in the first target entry, that is, the storage space of the first target entry stores the space that has not been allocated. The first target entry identifier is the entry identifier of the first target entry. At this time, a correspondence between the first target stream identifier and the first target entry identifier can be established. Among them, the entry identifier can be the Index of the entry.
[0054] As a possible implementation manner, the current space allocation information may include the entry identifiers of each first entry and the currently corresponding allocated quantity. The allocated quantity represents the quotient of the allocated storage space in a first entry and the minimum allocation granularity. In this case, the first target entry identifier can be conveniently and quickly determined in the Figure 5 shown manner. Please refer to Figure 5 , Figure 5 which Figure 4 is a schematic flowchart of the sub-steps included in sub-step S113. In this embodiment, sub-step S113 may include sub-steps S1131 to S1133.
[0055] Sub-step S1131, determine an entry identifier from the entry identifiers of the first entries included in the first table entry as the initial target entry identifier.
[0056] Sub-step S1132, determine whether the target allocated quantity is equal to the maximum quantity.
[0057] If the target allocated quantity is equal to the maximum quantity, jump to sub-step S1131.
[0058] If the target allocated quantity is not equal to the maximum quantity, execute sub-step S1133.
[0059] Sub-step S1133, use the initial target entry identifier as the first target entry identifier.
[0060] In this embodiment, the entry identifiers of the first target included in the first table entry can be sorted in a certain order. For example, they can be sorted in descending or ascending order, and then the first sorted entry identifier is used as the initial target entry identifier. Or, an entry identifier can be randomly determined from the entry identifiers of the first entries included in the first table entry as the initial target entry identifier. In this way, the randomness can be increased, which is convenient for ensuring the chip verification effect.
[0061] After determining the initial target entry identifier, obtain the allocated quantity UsedCnt corresponding to the initial target entry identifier from the current space allocation information as the target allocation quantity. Then, compare the target allocated quantity with a preset maximum quantity. The product of the maximum quantity and the minimum allocation granularity is the storage space capacity of one of the first entries, and the storage space capacities of the first entries in the first table entry are the same. Usually, the available granularities are 64 / 128 / 256 / 512 / 1024 bits, and at this time, the minimum allocation granularity is 64 bits.
[0062] If the target allocated quantity is equal to the maximum quantity, it means that the storage space of the first entry corresponding to the initial target entry identifier has been fully allocated, that is, there is no free storage space in the first entry corresponding to the initial target entry identifier. At this time, select another entry identifier of the first entry as the initial target entry identifier, and determine again whether there is free storage space in the selected first entry until an entry identifier of the first entry with free storage space is determined.
[0063] If the target allocated quantity is not equal to the maximum quantity, it means that the storage space of the first entry corresponding to the initial target entry identifier has not been fully allocated, that is, there is free storage space in the first entry corresponding to the initial target entry identifier. At this time, the initial target entry identifier can be directly used as the first target entry identifier.
[0064] Sub-step S114, allocate a stream storage space for the first target stream identifier from the free storage space of the first target entry corresponding to the first target entry identifier.
[0065] When the first target entry identifier is determined, according to the set space allocation method, allocate a part of the space from the free storage space of the first target entry for the first target stream identifier as the stream storage space corresponding to the first target stream identifier, that is, allocate a stream storage space for the stream corresponding to the first target stream identifier. Among them, the set space allocation method can be specifically determined in combination with actual requirements.
[0066] As a possible implementation, it can be achieved through Figure 6 the shown method to allocate the stream storage space. Please refer to Figure 6 , Figure 6 for Figure 4 the flow schematic diagram of the sub-steps included in sub-step S114 in
[0067] Sub-step S1141, determine the starting position of the stream storage space allocated for the first target stream identifier according to the target allocated quantity and the minimum allocation granularity.
[0068] In this embodiment, the starting position of the flow storage space allocated to the first target flow identifier can be set as the product of the allocated quantity (i.e., the target allocated quantity) corresponding to the first target flow identifier in the current space allocation information and the minimum allocation granularity. For example, if the target allocated quantity is UsedCnt and the minimum allocation granularity is 64, then the starting position startOffset of the flow storage space allocated to the first target flow identifier is UsedCnt x 64.
[0069] Sub-step S1142: Determine the current maximum allocation granularity according to the maximum quantity, the minimum allocation granularity, and the target allocated quantity.
[0070] The difference between the maximum quantity and the target allocated quantity can be calculated, and then the product of this difference and the minimum allocation granularity can be calculated as the current maximum allocation granularity.
[0071] Sub-step S1143: Determine the target granularity corresponding to the first target flow identifier according to the current maximum allocation granularity, and update the target allocated quantity corresponding to the first target flow identifier in the current space allocation information according to the target granularity.
[0072] When the current maximum allocation granularity is obtained, a granularity smaller than the current maximum allocation granularity can be determined as the target granularity, and the specific determination method of the size of the target granularity can be determined in combination with actual requirements. The target granularity represents the size of the storage space allocated to the first target flow identifier, and the starting position and target granularity of the flow storage space are used to indicate the position information of the flow storage space.
[0073] Optionally, multiple preset allocation granularities can be preset, such as 64 / 128 / 256 / 512 / 1024 bits. When the current maximum allocation granularity is determined, each preset allocation granularity that is not greater than the current maximum allocation granularity is determined from the multiple preset allocation granularities as the candidate allocation granularities. Then, a candidate allocation granularity is selected from the above candidate allocation granularities as the target granularity, and the specific selection method can be determined in combination with actual requirements.
[0074] As a possible implementation manner, a candidate allocation granularity can be randomly selected from the determined candidate allocation granularities as the target granularity. In this way, it is convenient to increase randomness.
[0075] After determining the target granularity, the target allocated quantity corresponding to the first target stream identifier in the current space allocation information can be updated according to the target granularity and the minimum allocation granularity, so as to make the current space allocation information consistent with the actual situation, thereby facilitating the continued allocation of storage space. After the update, the target allocated quantity corresponding to the first target stream identifier is: UsedCnt = UsedCnt + (step / minimum allocation granularity).
[0076] Sub-step S115: Generate a second entry corresponding to the first target stream identifier and save it in the second entry table.
[0077] After determining the first target entry identifier, start position, and target granularity corresponding to the first target stream identifier, a second entry can be generated based on the above corresponding information and saved in the second entry table. The second entry includes the corresponding stream identifier, the entry identifier of the first entry, and the location information of the allocated stream storage space, and the location information is represented by the start position and the target granularity.
[0078] Execute sub-steps S112 to S115 for each stream in sequence until all streams have been allocated stream storage space, and then the second entry table can be obtained.
[0079] Please refer to Figure 7 , Figure 7 as Figure 3 the second schematic diagram of the flow of the sub-steps included in step S110 in. In this embodiment, before sub-step S112, step S110 may further include sub-step S111, and after sub-step S115, step S110 may further include sub-steps S116 to S117 to allocate stream storage space for each stream under the condition of increasing randomness.
[0080] Sub-step S111: Save the stream identifiers of multiple streams in a random order to the stream identifier queue.
[0081] The first target stream identifier is a stream identifier taken out from the stream identifier queue.
[0082] Sub-step S116: After allocating the stream storage space for the first target stream identifier, determine whether the stream identifier queue is empty.
[0083] When the stream identifier queue is not empty, jump to sub-step S112: Determine the stream identifier of a stream as the first target stream identifier.
[0084] When the stream identifier queue is empty, execute sub-step S117: Determine that the stream storage space has been allocated for all stream identifiers.
[0085] In this embodiment, the flow identifiers of multiple flows that need to allocate storage space can be randomly shuffled and pushed into the FlowId queue (i.e., the flow identifier queue). Then, a flow identifier is popped out from the flow identifier queue as the first target flow identifier, and then a corresponding second entry is generated through sub-steps S113 to S115 and saved into the second entry. Next, it is judged whether the flow identifier queue is empty. If it is empty, it means that the flow storage space has been allocated for all flows, and the space allocation process can end; if it is not empty, a flow identifier is popped out from the flow identifier queue again as the first target flow identifier, and the allocation is performed again until the flow identifier queue is empty.
[0086] When the first entry is used to record the SN status of the packet, the second entry obtained in the above manner can be as Figure 8 shown. Figure 8 Each entry in includes the flow identifier, the entry identifier of the first entry, the start position, and the granularity, where Figure 8 Flow0 and Flowm in represent the flow identifiers, SNRecordIndex0 and SNRecordIndex m represent the entry identifiers of the first entry, startOffset0 and SNRecordIndem represent the start positions, and step0 and stepm represent the granularities.
[0087] In this embodiment, for a mutual exclusion configuration constraint of multiple logical common entries, that is, for the situation where there is a mutual exclusion configuration of common entries in chip verification, a method of selecting and recording in a limited configuration space is adopted; for the situation of the correlation of configuration constraints in chip verification, a method of recording the usage situation of the configuration space is adopted. In this way, the rapid configuration of the mutual exclusion of the common entry structure can be quickly realized, thereby reducing the verification code amount and also reducing the debugging overhead caused by unsuccessful constraint codes.
[0088] After obtaining the second entry, according to the second target flow identifier corresponding to the packet to be recorded and the second entry, the corresponding target flow storage space in the first entry is determined, and the target flow storage space is a part of the storage space in the second target entry corresponding to the second target flow identifier in the second entry. Then, the processed packet information recorded in the target flow storage space can be updated according to the packet to be recorded, that is, the corresponding SN status is updated in the corresponding target flow storage space.
[0089] Next, taking the first entry as the SNRecord entry for storing the SN record status as an example, combined with Figure 9, an example of how to obtain the second table entry FlowRXCfg and use the second table entry FlowRXCfg is given. In the following example, a 1024 - flow pattern is used to illustrate how to quickly configure startOffset and step.
[0090] Since there are 1024 flows and the flows correspond one - to - one with the entries in FlowRXCfg, there are 1024 entries in FlowRXCfg at this time. There are also 1024 entries in SNRecord. The number of entries in SNRecord can also be other values. One entry is 1024 bits. A UsedCnt is defined for each SNRecordIndex. UsedCnt is in units of 64 bits and the initial value is 0, that is, the maximum UsedCnt corresponding to each entry in SNRecord is 16 (64×16 = 1024).
[0091] 1. Randomly shuffle the 1024 FlowIds from 0 to 1023 and push them into the FlowId queue.
[0092] 2. Pop a FlowId from the FlowId queue.
[0093] 3. Randomly obtain an SNRecordIndex from SNRecordIndex0 to SNRecordIndex1023 in SNRecord for this FlowId.
[0094] 4. Determine whether the UsedCnt corresponding to the obtained SNRecordIndex is 16. If UsedCnt is equal to 16, return to step 3. If UsedCnt is not equal to 16, then proceed to step 5.
[0095] 5. Set startOffset for this FlowId to UsedCnt × 64, and the current maximum step to (16 - UsedCnt) × 64. At this time, select step from the range less than the maximum step. This step must be in the set [64, 128, 256, 512, 1024], and update UsedCnt = UsedCnt+(step / 64).
[0096] 5. Determine whether the FlowId queue is empty. If it is not empty, return to step 2. If it is empty, end the processing.
[0097] The FlowRXCfg can be obtained through the above processing.
[0098] The SNRecordIndex, startOffSet, and step of the SNRecord can be found from the FlowRXCfg according to the FlowId. The way to record information in the SNRecord based on this FlowRXCfg is as follows.
[0099] The first step: Use the ID of the flow, that is, FlowId, to find the FlowRxCfg, and obtain the SNRecordIndex, StartOffset, and step of its SN resources.
[0100] The second step: Use the found SNRecordIndex to read the content of the corresponding entry from the SNRecord, obtain the starting position of the SN resources available for this flow according to the found startOffset, and at the same time update the corresponding SN status within the information position range corresponding to the found step.
[0101] The third step: Write the updated entry content back to the SNRecord to complete the status record.
[0102] In this embodiment, for the case where there are mutual exclusion constraints in the common table item structure, a fast and effective verification configuration method is provided, which simplifies the original workload of using UVM constraints for constraints and greatly improves the verification efficiency. In addition, for other table item configuration cases with complex constraints, the idea of this embodiment can be used to quickly construct a set of configuration methods to accelerate the chip verification process.
[0103] To execute the corresponding steps in the above embodiments and various possible ways, an implementation manner of a chip verification device 200 is given below. Optionally, the chip verification device 200 may adopt the device structure of the electronic device 100 shown above. Further, please refer to Figure 2 shown in the device structure of the electronic device 100. Further, please refer to Figure 10 , Figure 10 is a block diagram of the chip verification device 200 provided by the embodiment of the present application. It should be noted that the basic principle and the technical effects generated by the chip verification device 200 provided in this embodiment are the same as those in the above embodiments. For the sake of brief description, for the parts not mentioned in this embodiment, reference may be made to the corresponding content in the above embodiments. In this embodiment, the chip verification device 200 may include: a configuration module 210 and a verification module 220.
[0104] The configuration module 210 is configured to automatically allocate free storage space in a first entry of the first table for each flow as corresponding flow storage space based on current space allocation information, and obtain a second table entry based on the allocation result. The current space allocation information indicates the current storage space allocation status of each first entry of the first table, the free storage space is unallocated storage space, and the second entry in the second table indicates the flow storage space allocated for each flow, where the flow storage space is used to store message information of the corresponding flow.
[0105] The verification module 220 is configured to record information based on the second entry and the received message in the corresponding flow storage space in the storage space of the first entry to perform chip verification.
[0106] Optionally, the above modules can be stored in the form of software or firmware. Figure 2 The memory 110 shown in FIG. 110 or the operating system (OS) of the electronic device 100 may be fixed and may be used by Figure 2 Meanwhile, the data, program codes, etc. required to execute the above modules may be stored in the memory 110.
[0107] An embodiment of the present application further provides a readable storage medium having a computer program stored thereon, and the computer program implements the chip verification method when executed by a processor.
[0108] In summary, the embodiments of the present application provide a chip verification method, device, electronic device and readable storage medium. First, for each flow, according to the current space allocation information, free storage space is automatically allocated to the flow in a first entry of the first table item as the corresponding flow storage space, and a second table item is obtained according to the allocation result; then, information is recorded according to the second table item and the corresponding flow storage space of the message to be recorded in the storage space of the first table item to perform chip verification. Wherein, the current space allocation information is used to indicate the storage space allocation status of each first entry of the current first table item, the free storage space is the unallocated storage space, the second entry in the second table item is used to indicate the flow storage space allocated for each flow, and the flow storage space is used to store the message information of the corresponding flow; the chip to be verified records the information. The above method can automatically allocate storage space for each flow in the first table item for storing message information, and then perform chip verification based on the second table item obtained after the storage space allocation is completed. In this way, the mutual exclusion of the common table item structure can be automatically realized. Rapid configuration, not only greatly reducing the amount of verification code, but also greatly reducing the debugging overhead caused by unsuccessful constraint code.
[0109] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of this application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the part of the module, program segment, or code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.
[0110] In addition, each functional module in various embodiments of this application can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.
[0111] If the above functions are implemented in the form of software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.
[0112] The above are only optional embodiments of this application and are not used to limit this application. For those skilled in the art, this application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included in the protection scope of this application.
Claims
1. A chip verification method, characterized in that The method includes: For each flow, automatically allocate idle storage space as the corresponding flow storage space for the flow in an entry of the first entry of the first table according to the current space allocation information, and obtain a second table according to the allocation result, where the current space allocation information is used to indicate the storage space allocation situation of each entry of the first entry of the first table currently, the idle storage space is the unallocated storage space, the second entry in the second table is used to indicate the flow storage space allocated for each flow, and the flow storage space is used to store the packet information of the corresponding flow; Record information according to the second table and the corresponding flow storage space of the packet to be recorded in the storage space of the first table for chip verification, where the chip to be verified records information.
2. The method according to claim 1, wherein The step of, for each flow, automatically allocate idle storage space as the corresponding flow storage space for the flow in an entry of the first entry of the first table according to the current space allocation information, and obtain a second table according to the allocation result includes: Determine the flow identifier of a flow as the first target flow identifier; According to the current space allocation information, determine the entry identifier of an entry with idle storage space as the first target entry identifier corresponding to the first target flow identifier; Allocate flow storage space for the first target flow identifier from the idle storage space of the first target entry corresponding to the first target entry identifier; Generate a second entry corresponding to the first target flow identifier and save it in the second table, where the second entry includes the corresponding flow identifier, the entry identifier of the first entry, and the location information of the allocated flow storage space.
3. The method according to claim 2, wherein The current space allocation information includes the entry identifiers of each entry of the first entry and the currently corresponding allocated quantity, where the allocated quantity represents the quotient of the allocated storage space in an entry of the first entry and the minimum allocation granularity. The step of, according to the current space allocation information, determine the entry identifier of an entry with idle storage space as the first target entry identifier corresponding to the first target flow identifier includes: Determine an entry identifier as the initial target entry identifier from the entry identifiers of the entries of the first entry included in the first table; Judge whether the target allocated quantity is equal to the maximum quantity, where the target allocated quantity is the allocated quantity corresponding to the initial target entry identifier in the current space allocation information, the product of the maximum quantity and the minimum allocation granularity is the capacity of the storage space of an entry of the first entry, and the storage space capacities of the entries of the first entry in the first table are the same; If the target allocated quantity is equal to the maximum quantity, execute again the step of determining an entry identifier as the initial target entry identifier from the entry identifiers of the entries of the first entry included in the first table; If the target allocated quantity is not equal to the maximum quantity, use the initial target entry identifier as the first target entry identifier.
4. The method according to claim 3, characterized in that, The step of allocating flow storage space for the first target flow identifier from the idle storage space of the first target entry corresponding to the first target entry identifier includes: Determine the starting position of the flow storage space allocated for the first target flow identifier according to the target allocated quantity and the minimum allocation granularity; Determine the current maximum allocation granularity according to the maximum quantity, the minimum allocation granularity, and the target allocated quantity; Determine the target granularity corresponding to the first target flow identifier according to the current maximum allocation granularity, and update the target allocated quantity corresponding to the first target flow identifier in the current space allocation information according to the target granularity, where the target granularity represents the storage space size allocated for the first target flow identifier, the target granularity is not greater than the current maximum allocation granularity, and the starting position and the target granularity of the flow storage space are used to indicate the location information of the flow storage space.
5. The method according to claim 4, wherein The determining the target granularity corresponding to the first target flow identifier according to the current maximum allocation granularity includes: Determine the preset allocation granularity that is not greater than the current maximum allocation granularity from multiple preset allocation granularities as the candidate allocation granularity; Use one of the determined candidate allocation granularities as the target granularity.
6. The method according to claim 5, wherein The determining one of the entry identifiers included in the first entry as the initial target entry identifier includes: randomly determining one of the entry identifiers included in the first entry as the initial target entry identifier; and / or The using one of the determined candidate allocation granularities as the target granularity includes: randomly selecting one of the determined candidate allocation granularities as the target granularity.
7. The method according to claim 2, characterized in that, The automatically allocating, for each flow, an idle storage space in the first entry as the corresponding flow storage space according to the current space allocation information, and obtaining a second entry according to the allocation result further includes: Save the flow identifiers of multiple flows to a flow identifier queue in a random order, where the first target flow identifier is a flow identifier taken out from the flow identifier queue; After allocating the flow storage space for the first target flow identifier, determine whether the flow identifier queue is empty; When the flow identifier queue is not empty, execute the step of determining the flow identifier of a flow as the first target flow identifier again; When the flow identifier queue is empty, determine that the flow storage space has been allocated for all flow identifiers.
8. The method according to any one of claims 1-7, characterized in that, The recording information according to the second entry and the received packet in the corresponding flow storage space in the storage space of the first entry for chip verification includes: Determine the corresponding target flow storage space according to the second target flow identifier corresponding to the packet to be recorded and the second entry, and update the processed packet information recorded in the target flow storage space according to the packet to be recorded.
9. A chip verification device, characterized in that, The device includes: A configuration module, for each flow, automatically allocates free storage space as the corresponding flow storage space for the flow in a first entry of a first table item according to the current space allocation information, and obtains a second table item according to the allocation result, where the current space allocation information is used to indicate the storage space allocation situation of each first entry of the current first table item, the free storage space is the unallocated storage space, the second entry in the second table item is used to indicate the flow storage space allocated for each flow, and the flow storage space is used to store the packet information of the corresponding flow; A verification module, for recording information in the corresponding flow storage space of the storage space of the first table item according to the second table item and the received packet to perform chip verification, where the chip to be verified performs information recording.
10. An electronic device, characterized in that, It includes a processor and a memory, the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the chip verification method according to any one of claims 1-8.