Server state real-time visual energy digital display method and system and server

Abstract

The invention relates to a server state real-time visualization digital display method and system and a server, a CPLD unit is included, according to the method, BIOS, CPLD and BMC are linked through the CPLD unit, digital display of the server state is visually carried out, Debug and monitoring of the server state are facilitated, resources on a server mainboard are fully utilized, and the server state real-time visualization digital display method and system have the excellent compatibility characteristic and are convenient to use. And the development period and the development cost are greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of server status display, and more specifically, to a real-time visualization digital display method, system and server for server status. Background Art

[0002] The server board is huge. Currently, the display of server status is usually achieved by relying on various indicator lights, and the display effect is not intuitive. Moreover, some developed software systems with server status display have high costs, long development cycles, and usually require targeted development for specific server models, with relatively poor applicability. Based on this situation, there is an urgent need for a digital display method, system and server that can intuitively reflect the server status. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a real-time visualization digital display method for server status in view of the above-mentioned defects of the prior art, and also provide a real-time visualization digital display system for server status and a server applying this method.

[0004] The technical solution adopted by the present invention to solve its technical problems is as follows:

[0005] Construct a real-time visualization digital display method for server status, which includes a CPLD unit. The method includes the following steps:

[0006] Power-on stage: The first sub-module of the CPLD unit controls the power-on sequence of the BMC module, PCH module, PSU module, MEM module and CPU module on the server. After the module sequences of the BMC module, PCH module, PSU module, MEM module and CPU module are successfully completed, a corresponding module OK signal is sent to the second sub-module of the CPLD unit, and the second sub-module performs data processing and conversion and then displays it on the digital tube;

[0007] POST stage: The CPLD unit constructs an IIC slave. The IIC master of the BMC module fills the POST code received from the BIOS module into the corresponding register in real time. The CPLD unit reads the POST code in the register through the IIC slave and converts it into the corresponding two-digit hexadecimal number, and displays it through the digital tube;

[0008] Power - on temperature display stage: When the second sub - module receives the CPU temperature display instruction, it enters the temperature display state after a set delay time. The BMC module reads the register of TPM175 in real - time through the IIC host to obtain the CPU temperature, and then communicates with the CPLD unit through the IIC bus, passing the temperature value data to the CPLD unit. The CPLD unit processes and converts the temperature value data into the corresponding display format for display on the digital tube.

[0009] For the method of real - time visual digital display of server status described in the present invention, during the power - on stage, the first sub - module also monitors the SLP_S3_N signal, SYS_PWR OK signal, and PLT_RST_N signal, and displays them correspondingly on the digital tube.

[0010] For the method of real - time visual digital display of server status described in the present invention, when the second sub - module receives the delay signal of PLT_RST_N, it enters the POST stage.

[0011] For the method of real - time visual digital display of server status described in the present invention, the BIOS module passes the POST code to the BMC module, specifically as follows:

[0012] The BIOS module gives the 80 code of the post code to the ESPI interface.

[0013] The BMC module parses the post code hardware - wise. The BMC directly reads the value in the lpc - snoop register to obtain the postcode value.

[0014] For the method of real - time visual digital display of server status described in the present invention, the processing and conversion of the temperature value data are as follows:

[0015] When the temperature is not greater than 100 degrees Celsius, take the remainder of dividing by 10 to get the units digit, divide by 10 to get the tens digit, and add a decimal point to the right of the units digit.

[0016] When the temperature is greater than 100 degrees Celsius, first subtract 100, then take the remainder of dividing by 10 to get the units digit, divide by 10 to get the tens digit, and add decimal points to the right of both the tens digit and the units digit.

[0017] A system for real - time visual digital display of server status, wherein the system includes a CPLD unit, and the CPLD unit is used to execute the method of real - time visual digital display of server status as described above.

[0018] A server, wherein the server is provided with the system for real - time visual digital display of server status as described above.

[0019] The beneficial effects of the present invention are as follows: By applying the methods and means of this application, the CPLD unit is used to link BIOS, CPLD, and BMC together, and the digital display of the server status is carried out intuitively to facilitate Debug and monitor the server status. This not only makes full use of the resources on the server motherboard but also has excellent compatibility characteristics, significantly reducing the development cycle and development cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will further describe the present invention in conjunction with the accompanying drawings and embodiments. The accompanying drawings in the following description are only partial embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts:

[0021] Figure 1 is a flowchart of the method for real-time visualization digital display of server status in a preferred embodiment of the present invention;

[0022] Figure 2 is a block diagram of the principle of the system for real-time visualization digital display of server status in a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are partial embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0024] The method for real-time visualization digital display of server status in a preferred embodiment of the present invention, as Figure 1 shown, includes a CPLD unit, and the method includes:

[0025] The CPLD unit directly drives the seven-segment digital tube. The lde_control sub-module (the second sub-module) defines the truth table of various display numbers of the seven-segment digital tube, and then divides the 50MHz clock by 1KHz clock. The cathodes of the two seven-segment digital tubes are switched back and forth at the high and low levels of the 1KHz clock to complete the display function. A state machine is implemented in the lde_control sub-module;

[0026] Power-on stage: The first sub-module of the CPLD unit (such as the Mstr_Seq sub-module) controls the power-on timing of the BMC module, PCH module, PSU module, MEM module, and CPU module on the server. After the module timing of the BMC module, PCH module, PSU module, MEM module, and CPU module is successfully completed, a signal corresponding to the OK of the module is sent to the second sub-module of the CPLD unit, and the second sub-module performs data processing and conversion and then displays it on the digital tube.

[0027] In the power-on stage, the first sub-module also monitors the SLP_S3_N signal, SYS_PWR OK signal, and PLT_RST_N signal, and displays them on the digital tube correspondingly for convenient Debug. The total signal list is as follows:

[0028] -0: CPLD OK, PCH or BMC is not ready yet

[0029] -1: Standby Power OK (PCH and BMC)

[0030] -2: RSMRST_N High (South Bridge reset)

[0031] -3: SLP_S3_N High

[0032] -4: PSU Power OK

[0033] -5: MEM Power OK

[0034] -6: CPU PowerOK

[0035] -7: System Power OK

[0036] -8: PLT_RST_N High (Global reset)

[0037] POST (Power-on Self-Test) stage: After the second sub-module receives the delayed signal of PLT_RST_N (such as 200mS, this signal is used to stay and display the last state of the power-on stage), it enters the POST stage. The CPLD unit constructs an IIC slave, and the IIC master of the BMC module fills the POST code received from the BIOS module into the corresponding register in real time. The CPLD unit relies on the IIC slave to read the POST code in the register and convert it into the corresponding two-digit hexadecimal number, and displays it through the digital tube.

[0038] The BIOS module passes the POST code to the BMC module, specifically as follows: The BIOS module gives the 80 code of the post code to the ESPI interface; The BMC module parses the post code hardware, and the BMC directly reads the value in the lpc-snoop register to obtain the postcode value;

[0039] Power-on temperature display stage: When the second sub-module receives the CPU temperature display instruction, it delays for the set time and enters the temperature display state. The BMC module reads the register of the TPM175 in real time through the IIC host to obtain the CPU temperature, and then communicates with the CPLD unit through the IIC bus to transmit the temperature value data to the CPLD unit. The CPLD unit processes and converts the temperature value data into the corresponding display format and displays it on the digital tube;

[0040] The processing and conversion of the temperature value data adopt:

[0041] When the temperature is not greater than 100 degrees Celsius, take the remainder of 10 to get the units digit, divide by 10 to get the tens digit, and add a decimal point to the right of the units digit;

[0042] When the temperature is greater than 100 degrees Celsius, first subtract 100, then take the remainder of 10 to get the units digit, divide by 10 to get the tens digit, and add a decimal point to the right of both the tens digit and the units digit;

[0043] Example:

[0044] —— 0 to 99°C: Display as 00.~99., that is, the rightmost decimal point lights up.

[0045] —— Above 100°C: Both decimal points light up, and the highest digit 1 is omitted, that is, 105°C is displayed as 0.5.

[0046] —— If no temperature is obtained, FF is displayed by default.

[0047] Applying the method of the present application, the BIOS, CPLD, and BMC are linked by the CPLD unit to visually display the server status digitally, facilitating Debug and monitoring of the server status. It not only makes full use of the resources on the server motherboard but also has excellent compatibility characteristics, significantly reducing the development cycle and development cost.

[0048] A real-time visual digital display system for server status, as Figure 2 shown, the system includes a CPLD unit, and the CPLD unit is used to execute the real-time visual digital display method for server status as described above;

[0049] Applying the system of the present application, the BIOS, CPLD, and BMC are linked through the CPLD unit to visually display the digital status of the server, facilitating Debug and monitoring of the server status. This not only makes full use of the resources on the server motherboard but also has excellent compatibility characteristics, significantly reducing the development cycle and development cost.

[0050] A server, wherein the server is provided with the digital display system for real-time visualization of the server status as described above.

[0051] It should be understood that those of ordinary skill in the art can make improvements or transformations based on the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A real-time visualization digital display method for server status, characterized in that, It includes a CPLD unit, and the method includes the steps of: Power-on stage: The first sub-module of the CPLD unit controls the power-on timings of the BMC module, PCH module, PSU module, MEM module, and CPU module on the server. After the module timings of the BMC module, PCH module, PSU module, MEM module, and CPU module are successfully completed, a signal corresponding to the OK of the module is sent to the second sub-module of the CPLD unit, and the second sub-module performs data processing and conversion and then displays it on the digital tube. POST stage: The CPLD unit constructs an I2C slave. The I2C master of the BMC module fills the received POST code from the BIOS module into the corresponding register in real time. The CPLD unit reads the POST code in the register through the I2C slave and converts it into the corresponding two-digit hexadecimal number, and displays it through the digital tube. Power-on temperature display stage: When the second sub-module receives the CPU temperature display instruction, it delays for a set time and enters the temperature display state. The BMC module reads the register of TPM175 in real time through the I2C master to obtain the CPU temperature, and then communicates with the CPLD unit through the I2C bus, and transmits the temperature value data to the CPLD unit. The CPLD unit processes and converts the temperature value data into the corresponding display format and displays it on the digital tube.

2. The real-time visual digital display method for server status according to claim 1, wherein In the power-on stage, the first sub-module also monitors the SLP_S3_N signal, SYS_PWR OK signal, and PLT_RST_N signal, and correspondingly displays them on the digital tube.

3. The real-time visualization energy digital display method for server status according to claim 2, characterized in that, After the second sub-module receives the delayed signal of PLT_RST_N, it enters the POST stage.

4. The real-time visual digital display method for server status according to claim 1, wherein The BIOS module transmits the POST code to the BMC module, specifically by: The BIOS module gives the 80 code of the post code to the ESPI interface; The BMC module parses the post code hardware, and the BMC directly reads the value in the lpc-snoop register to obtain the post code value.

5. The real-time visualization digital display method for server status according to claim 1, characterized in that The processing and conversion of the temperature value data adopt: When the temperature is not greater than 100 degrees Celsius, take the remainder of 10 to get the units digit, divide by 10 to get the tens digit, and add a decimal point to the right of the units digit; When the temperature is greater than 100 degrees Celsius, first subtract 100, then take the remainder of 10 to get the units digit, divide by 10 to get the tens digit, and add decimal points to the right of both the tens digit and the units digit.

6. A real-time visual digital display system for server status, characterized in that, The system includes a CPLD unit, and the CPLD unit is used to execute the server status real-time visualization digital display method as described in any one of claims 1-5.

7. A server, characterized in that, The server is provided with the server status real-time visualization digital display system as described in claim 6.

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