Direct cache hit and delivery in sequentially programmed memory subsystems

Abstract

The invention relates to direct cache hit and delivery in a sequentially programmed memory subsystem. A system includes a buffer and a processing device that receives a read request having a logical block address (LBA) value for a memory device, creates a logical delivery unit (LTU) value including the LBA value and mapped to a first physical address of the memory device, and generate a command flag instructing the processing device to retrieve data from the memory device and store the data in a buffer. The command flag includes a first command flag associated with the first physical address and a second command flag associated with a second physical address sequentially following the first physical address. The processor further creates an entry in a read cache table for the buffer. The entry may include a starting LBA value set to a first LBA value and a read offset value corresponding to an amount of data.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application of the invention patent application with the application date of June 28, 2021, the application number of "202110718597.3", and the invention title of "Direct Cache Hit and Transfer in a Sequentially Programmed Memory Subsystem". Technical Field

[0003] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to direct cache hit and transfer in a sequentially programmed memory subsystem. Background Art

[0004] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0005] In one aspect, the present application provides a system, including: a memory device; a volatile memory including a buffer and a read cache table; and a processing device coupled to the memory device and the volatile memory, wherein the processing device will: access a read command having a first command tag, the first command tag including a first logical transfer unit (LTU) value and a first buffer address of a first buffer in the buffer, the first LTU value being mapped from a region of a plurality of sequential logical block address (LBA) values to a first physical address among a plurality of sequential physical addresses of the memory device, wherein first data is stored at the first physical address, and wherein the first LTU value contains a first LBA value among the plurality of sequential LBA values; generate a set of command tags indicating that a command execution processor of the processing device retrieves second data from the memory device and stores the second data in a set of the buffers, wherein the set of command tags includes at least a second command tag associated with a second physical address sequentially after the first physical address; and create an entry in the read cache table for the set of the buffers, wherein the entry includes a starting LBA value set to the first LBA value and a read offset value corresponding to the amounts of the first data and the second data.

[0006] On the other hand, the present application provides a method, which includes: receiving, by a processing device of a memory subsystem controller, a read request for a memory device that includes a first logical block address (LBA) value of an LBA space, where the LBA value belongs to a region of a plurality of sequential LBA values mapped to a plurality of sequential physical addresses; creating, by the processing device, a first logical transfer unit (LTU) value that includes the first LBA value, where the first LTU value is mapped to a first physical address of the memory device; allocating, by the processing device, a set of buffers in volatile memory, where a capacity of the set of buffers matches an amount of data stored at the first physical address and subsequent physical addresses, and the subsequent physical addresses are sequentially numbered within a read offset value starting from the first physical address; generating, by the processing device, a set of command tags that instruct a command execution processor of the processing device to retrieve the data from the memory device and store the data in the set of buffers, where the set of command tags includes a first command tag associated with the first physical address and a second command tag associated with a second physical address sequentially after the first physical address; and creating, by the processing device, an entry in a read cache table for the set of buffers, where the entry includes a starting LBA value set to the first LBA value and the read offset value corresponding to the amount of data.

[0007] On the other hand, the present application provides a non-transitory computer-readable medium storing instructions that, when executed by a processing device of a memory subsystem controller, cause the processing device to perform a plurality of operations, including: receiving a read request for a memory device that includes a first logical block address (LBA) value of an LBA space, where the LBA value belongs to a region of a plurality of sequential LBA values mapped to a plurality of sequential physical addresses; creating a first logical transfer unit (LTU) value that includes the first LBA, where the first LTU value is mapped to a first physical address of the memory device; allocating a set of buffers in volatile memory, where a capacity of the set of buffers matches an amount of data stored at the first physical address and subsequent physical addresses, and the subsequent physical addresses are sequentially numbered within a read offset value starting from the first physical address; generating a set of command tags that instruct a command execution processor of the processing device to retrieve the data from the memory device and store the data in the set of buffers, where the set of command tags includes a first command tag associated with the first physical address and a second command tag associated with a second physical address sequentially after the first physical address; and creating an entry in a read cache table for the set of buffers, where the entry includes a starting LBA value set to the first LBA value and the read offset value corresponding to the amount of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1A An example computing system including a memory subsystem according to an embodiment is shown.

[0010] Figure 1B An example of Figure 1A additional details of the memory subsystem according to an embodiment is shown.

[0011] Figure 2 is a block diagram showing examples of data structures configured to support region-based mapping according to various embodiments.

[0012] Figure 3 An example of Figure 1A - 1B the interrelationship of the command generation processor, the translation processor, and the command execution processor of a memory subsystem controller according to an embodiment is shown.

[0013] Figure 4 is a flowchart of a method for supporting a direct cache hit based on a read command according to an embodiment.

[0014] Figure 5 is a flowchart of a method for supporting a direct cache hit according to an embodiment.

[0015] Figure 6A - 6C is a flowchart of a method for supporting direct cache hit and passing according to related embodiments.

[0016] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Description

[0017] Aspects of the present disclosure relate to direct cache hit and passing in a sequentially programmed memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1A Generally speaking, a host system may utilize a memory subsystem that includes one or more memory components (e.g., memory devices) that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0018] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device. Below in connection with Figure 1ADescribe other examples of non-volatile memory devices. A non-volatile memory device is a package of one or more dies. The dies in the package can be assigned to one or more channels for communication with a memory subsystem controller. Hereinafter, the memory subsystem controller is also referred to as the "controller". Each die can be composed of one or more planes. A plane can be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Hereinafter, a block refers to the unit of the memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or a single memory cell.

[0019] Data operations can be performed by the memory subsystem. A data operation can be a host-initiated operation. For example, a host system can initiate a data operation (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send an access request (e.g., a write command, a read command) to the memory subsystem to store data in the memory device at the memory subsystem and to read data from the memory device of the memory subsystem.

[0020] The data to be read or written specified by the host request is hereinafter referred to as "host data". The host request can include logical address information of the host data (e.g., logical block address (LBA), namespace), which is the location of the host system associated with the host data. The logical address information (e.g., LBA, namespace) can be part of the metadata of the host data. The metadata can also include error handling data (e.g., ECC codeword, parity code), data version (e.g., used to distinguish the age of the written data), valid bitmap (the LBA value or logical transfer unit of which contains valid data), and so on. For simplicity, if "data" is mentioned hereinafter, such data can be understood to refer to at least the host data, but can also refer to other data such as media management data and / or system data.

[0021] When performing data operations (e.g., write, read, erase), the memory subsystem may use a striping scheme to process groups of data as units. A LUN stripe is a series of planes that are processed as a unit when writing, reading, or erasing data. Each plane in a LUN stripe may perform the same operation in parallel with all other planes in the LUN stripe. A block stripe is a series of blocks within each plane of a LUN stripe that are processed as units. The blocks in a block stripe have the same block identifier (e.g., block number) within their respective planes. A block stripe (also referred to hereinafter as a block set) may be a set of blocks arranged across planes of different dies such that the blocks are grouped together for the purpose of data storage. Writing to a block stripe enables more host data to be written and read simultaneously and in parallel across multiple dies. Multiple blocks within one or more block sets may be identified as a data group.

[0022] The host file system may group host data by location and write the host data sequentially to the memory devices of the memory subsystem. Then, the file system may write the host data at different locations as parallel sequential streams to the memory devices, each stream having its own location, e.g., different host applications may write to the locations of their own streams. "Location" may refer to a temporal location or a spatial location. The memory subsystem controller (e.g., a processing device) typically writes to the media randomly in portions of host data (e.g., 4KB) and then uses metadata to map the LBA space to the physical address space of the memory devices. However, when larger host data groups (e.g., 100 megabytes (MB) or larger) are written and grouped by data location, the "data group" may be written sequentially as larger chunks to one or more block sets across multiple dies. To simplify the mapping of such data groups, the LBA values of regions (e.g., the logical address space associated with the data group) may be sorted sequentially within the LBA space and may be mapped to sequentially sorted physical addresses within the physical address space. In other words, a data group may be associated with a region of the LBA space having multiple sequential LBA values that are sequentially mapped to multiple sequential physical addresses. A memory subsystem that can write (e.g., program) data regions and map these regions accordingly operates in a zone namespace (ZNS), e.g., where logical address regions are named / identified as groups. Advantageously, using ZNS for logical-to-physical (LTP) address mapping greatly reduces the amount of metadata for tracking the LTP mapping.

[0023] In a memory subsystem, a read request (or read operation) typically issues one command tag at a time to a translation processor of the memory subsystem controller (e.g., to translate a logical address to a physical address) to perform a random read at the granularity specified by the command tag. The command tag, also referred to as a system tag (e.g., systag), contains a logical transfer unit (LTU) value and a buffer address identifying a buffer (e.g., a slot or entry in volatile memory) in which the content corresponding to the transfer unit is stored as in a cache. In one embodiment, the LTU value corresponding to a 4 kilobyte (KB) data portion is a subset of a plurality of sequential LBA values that can be mapped to a physical address via a set of mapping data structures. Thus, to generate the LTU value, the command generation processor of the controller can combine the LBA value of the read request with additional LBA values that succeed the LBA value (which can also be received in the read request). Depending on the LTU type, each LTU value can be translated to a logical block or a logical page. For example, an LTU can correspond to 8 KB, 16 KB, 32 KB, or more data increasing in 4 KB or 8 KB data increments.

[0024] Because a read request is typically executed for one command tag at a time, each read request generates a command message (e.g., a mailbox message in one instance) to the command generation processor of the controller (regardless of whether the read is sequential) and generates multiple (e.g., four or more) data structure lookups to map the LBA of the read request to a physical location in the memory device, as will be explained in detail. The command message can be used after obtaining a non-volatile memory command, where the command generation processor notifies the translation processor of the command reception. These data structures (e.g., tables) can be stored in volatile memory. This way of processing read requests increases the overhead and reduces the overall performance due to increased latency, especially under conditions where some read requests are issued sequentially to a sequentially written physical address space (e.g., of a ZNS). Thus, the sequential data layout of sequential writes is not used to limit the number of lookups that a controller (e.g., the translation processor of the controller) must perform to determine the physical address from which to retrieve data to fulfill a read request.

[0025] Aspects of the present disclosure address the above and other deficiencies by: A command generation processor (e.g., processing device) of a memory subsystem controller generates a set of command tags indicative of an amount of data (e.g., sequential data) that a command execution processor reads sequentially written to a set of buffers. The amount of sequential data read of the set of buffers can be significantly greater than the amount requested by a particular read request. By performing such a look-ahead of sequential data read, the command generation processor of the controller can access the sequential data as if accessing a cache to fulfill subsequent read requests without having to perform address translation of sequentially numbered LTU values. To do so, the command generation processor can further create and update a read cache table and a read index table to manage the use of the set of buffers as a cache to fulfill these subsequent read requests. Thus, when a read request is received that is known to be within a read offset value of the LBA value of an initial read request, determining an offset within the read offset value of the data can determine the location of the requested data within the set of buffers. The controller can then pass the requested data to the host system in response to a cache "hit" at the set of buffers.

[0026] In various embodiments, the read cache table optionally stores, in each entry, a region identifier of a region of the LBA in the read request, a starting LBA value set to a first LBA value (e.g., received in an initial read request or read command), and a read offset value. The region identifier is optional because the starting LBA value also identifies the region. Each entry in the read cache table can also optionally store an ending LBA value that identifies the end of the read offset value starting from the starting LBA within the physical address space. The read offset value can be the amount of data that is read in a look-ahead manner into the set of buffers and can include data corresponding to the initial read request or command. Thus, the read offset value can be significantly greater than the amount of data mapped to the LTU, e.g., between 128 KB and 2 MB. In one example, if an LTU value maps to 16 KB of data (e.g., which is the buffer allocation unit offset), then 1 MB of data within the read offset value will contain 64 data chunks corresponding to 64 LTU values. Thus, a look-ahead of 1 MB of data can save an additional 63 sets of lookups by the translation processor for determining the physical addresses of an additional 63 read requests. This latency reduction is quite significant, especially when extrapolated over thousands of read requests.

[0027] In various embodiments, a command generation processor may create and manage a buffer index table to track LTU values associated with each command tag in the set of command tags. For example, the buffer index table may map LTU values to buffer addresses associated with the LTU values in each command tag. Thus, when a subsequent read request is received, after determining a new LTU value (e.g., by an offset value relative to an initial or first LTU value), the command generation processor may index into the buffer index table using the new LTU value to determine the corresponding buffer address. The command generation processor may then retrieve the requested data from the identifier buffer and pass the requested data to the host system to fulfill the subsequent read request. This indexing within the relatively small read cache table and buffer index table consumes much less processing power and latency compared to a translation processor translating each LTU value to a separate physical address and individually fulfilling each request or command at the granularity of logical transfer units.

[0028] Advantages of the present disclosure include, but are not limited to, improved read performance and obviating the costly overhead of interrupting write operations to service a very large number of read requests (which occur more frequently than write operations), e.g., by allowing many read requests to hit in the buffer using read look-ahead operations. Additionally, the present disclosure illustrates ways to perform direct cache hits and data transfers to reduce the latency of sequential read requests from the host system (even if those read requests are interleaved with write operations and / or read requests to other regions). These advantages synergistically leverage sequential writes performed by a ZNS-enabled memory device. Other advantages will be apparent to those skilled in the art in the area of memory allocation and error optimization within the memory subsystem discussed below.

[0029] Figure 1A FIG. 1 shows an example computing system 100 that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. The memory subsystem 110 may include media such as volatile memory (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices. Each memory device 130 or 140 may be one or more memory components.

[0030] The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0032] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components or devices, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components or devices), whether wired or wireless, including electrical, optical, magnetic, etc. connections.

[0033] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0034] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface communicable through a system bus. Examples of the physical host interface include but are not limited to Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interface (e.g., DIMM socket interface supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access components (e.g., the memory device 130) when the memory subsystem 110 is coupled to the host system 120 via the PCIe interface. The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. As an example, Figure 1A illustrates the memory subsystem 110. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., the memory device 140) can be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of the non-volatile memory device (e.g., the memory device 130) include "NAND" (Negative-AND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. The non-volatile memory cross-point array can perform bit storage based on the change of the bulk resistance in combination with the stackable cross-gridded data access array. Additionally, compared with many flash-based memories, the cross-point non-volatile memory can perform in-situ write operations, where the non-volatile memory cells can be programmed in the case where they have been previously erased. The NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, as well as an MLC portion, TLC portion, or QLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages, where a page may refer to a logical unit of the memory device for storing data. In some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] Although non-volatile memory components such as NAND-type flash memories (e.g., 2D NAND, 3D NAND) and 3D cross-point non-volatile memory cell arrays have been described, the memory devices 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (or simply referred to as the controller 115) may communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory devices 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-wired) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processor 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operations of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, the local memory 119 may include memory registers that store memory pointers, fetched data, and the like. The local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1A the illustrated memory subsystem 110 is shown as including a memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Generally, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses (e.g., logical block address (LBA), namespace) and physical addresses (e.g., physical block address) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions for accessing the memory device 130 and may convert responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130.

[0044] In some embodiments, the memory device 130 includes a local media controller 135 that, in conjunction with the memory subsystem controller 115, performs operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is an original memory device combined with a local controller (e.g., the local media controller 135) for memory management within the same memory device package or memory die. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] In some embodiments, the controller 115 includes an error correction code (ECC) encoder / decoder 111. The ECC encoder / decoder 111 may perform ECC encoding of data written to the memory device 130 and ECC decoding of data read from the memory device 130, respectively. ECC decoding may be performed to decode an ECC codeword to correct errors in the original read data and, in many cases, also report the number of bit errors in the original read data.

[0046] Figure 1B Shows additional details of the Figure 1A memory subsystem 110 according to an embodiment. In an embodiment, the memory subsystem controller 115 (e.g., a processing device, referred to as the controller 115 for simplicity) includes one or more registers 112, a command generation processor 122 including a buffer manager 113, a translation processor 123, a command execution processor 124, and volatile memory 125. For example, the processor 117 ( Figure 1A ) may include the command generation processor 123, the translation processor 123, and the command execution processor 124.

[0047] In various embodiments, the volatile memory 125 stores a region mapping data structure 101, a read cache table 127, and a buffer index table 129, as well as other ZNS mapping data structures as shown in the example of Figure 2 . In one embodiment, the region mapping data structure 101 includes a plurality of entries such that each entry has a block set entry identifier that is associated with an entry within a block set mapping data structure 107, and the entries within the block set mapping data structure 107 may in turn be associated with entries of a page mapping data structure, and the entries of the page mapping data structure may in turn locate pages in memory, as will be referenced Figure 2Detailed Explanation. In some embodiments, the volatile memory 125 includes one or both of a tightly coupled memory (TCM) and a static random access memory (SRAM) device. Storing the read cache table 127 and the buffer index table 129 in the TCM can make the buffer management discussed below as efficient as possible, but they can also be stored in an SRAM device or a combination thereof.

[0048] The memory subsystem 110 may further include a memory device 140A, which can be a dynamic random access memory (DRAM) device or other such volatile memory device, and is typically used to store larger data structures. Such a data structure can be a block set mapping data structure 107, which can map block set identifiers to individual data blocks in the physical address space. The memory device 140A can also be referred to as shared volatile memory because it is shared by multiple processors to execute instructions and store data.

[0049] In various embodiments, the memory device 140A can further store a block set mapping data structure 107 and buffers 142, which are illustrated by way of example as including a first buffer 142A, a second buffer 142B, a third buffer 142C, and so on up to an Nth buffer 142N. Any group of these buffers 142 can be considered a set of buffers. The controller 115 can allocate buffers 142 (e.g., by buffer address) to store (e.g., cache) data to fulfill read requests. For example, each buffer can be an addressed slot or entry of the volatile memory device 140A. Each buffer can store the data page size or amount of data mapped by the LTU.

[0050] In addition, as discussed previously with reference to one or more memory devices 130, 140, the physical address space of multiple dies (e.g., die A and die B) can be hierarchically organized into planes, blocks, and pages. Thus, for example, each of die A and die B can include plane A and plane B, and each of plane A and plane B can include block A and block B. A block set (or block stripe) can be defined as a group of blocks arranged across the planes of multiple dies of a memory device. As shown, the block set 144 is arranged to include block A of plane A of die A, block A of plane B of die B, and so on, and can also include, for example, block A of plane C of die C and other dies (if present and online).

[0051] In various embodiments, the translation processor 123 (and / or the dynamic data placer of the controller 115 coupled to the translation processor 123) dynamically determines the layout for placing data associated with a logical address in the cells or memory components (also referred to as "IC dies") of the memory devices 130, 140. The layout specifies the mapping between the logical address for a command received in the memory subsystem 110 (e.g., from the host system 120) and the physical memory locations in the IC dies of the memory subsystem 110.

[0052] For example, based on the availability of the IC die for writing, programming, storing, and committing data during input / output scheduling in the memory subsystem 110, the translation processor 123 can determine the layout for placing data at the logical address associated with the physical address of the media of the memory device 130 or 140 for a portion of the logical addresses in the LBA space. When the IC die (including the physical cells within the IC die) is available for committing programming data, a write command is scheduled for execution in the memory subsystem 110; the translation processor 123 generates a portion of the layout for the write command and maps the logical address used for the write command for mapping to a memory location within the IC die. Execution of the write command causes the memory subsystem 110 to commit / program the data associated with the write command into the IC die.

[0053] Depending on the availability of the IC die across the media and / or application of the sequential mapping scheme, the controller 115 can write data groups sequentially (e.g., provided in a sequential stream of data locations) to fill one IC die at a time, or can write to multiple IC dies sequentially and in parallel each time, e.g., to fill the IC dies in parallel (if the memory device). The mapping of writes within a region of the LBA space can also be done sequentially to simplify the calculations for performing the mapping, as will be discussed in more detail with reference to the ZNS mapping data structure. When multiple IC dies are available, the logical addresses (e.g., LBA or LTU values) for commands from multiple write streams can be mapped to the multiple IC dies respectively through the dynamically generated portion of the layout such that there are no access conflicts when executing commands from multiple write streams.

[0054] In various embodiments, the translation processor 123 accesses certain ZNS mapping data structures (e.g., the region mapping data structure 101 and the block set mapping data structure 107) to translate LBA values into physical block addresses (PBAs) of the physical address space. The translation processor 123 may be referred to as a flash translation layer (FTL) in the context of flash media (e.g., NOR or NAND flash memory). The mapping employed by the translation processor 123 may generally be assumed to involve a certain type of block mapping, such as block-level mapping or log-level mapping. In cases where data locations are detected or in the case of a ZNS memory device, the translation processor 123 may map groups of blocks that form a region, such as groups of blocks within the ZNS data structures, which may involve mapping sequentially numbered LBA values to sequentially numbered PAs. Refer to Figure 2 More detailed discussion of using ZNS data structures and their interrelationships to map the LBA space of a region to the physical address space of the media.

[0055] In various embodiments, the command generation processor 122 performs command processing, including processing read or write commands received from the host system 120 or generating read commands and write commands based on read and write requests received from the host system 120 or another request agent, respectively. As part of executing a read request, the buffer manager 113 of the command generation processor 122 may allocate a specific number (e.g., "a set") of buffers having a capacity that matches the amount of data stored at a first physical address (mapped to the LTU value that encloses the LBA value of the created read request) and subsequent physical addresses, the subsequent physical addresses being sequentially numbered after the first physical address, for example, within a read offset value that defines the read window size of the memory device. For purposes of explanation, the data stored at the first physical address may be referred to as first data, and the data stored at the subsequent physical addresses may be referred to as second data. In one embodiment, the read offset value is 128 KB, enabling a read look-ahead of an additional 124 KB of second data beyond the first read request, but the read offset value may range up to 2 MB or greater. Various other offset values or read window sizes are envisioned. For example, each subsequent physical address may increment in page number across the read window of the sequential physical address space defined by the read offset value to determine the subsequent physical address. The allocation and tracking of buffers by the buffer manager 113 facilitates the read look-ahead operation.

[0056] In these embodiments, the command generation processor 122 may further generate a set of command tags for instructing the command execution processor 124 of the processing device to retrieve data from the first address and subsequent addresses of the memory device 130 or 140 and store the data in the set of buffers. The command generation processor 122 may further transmit a command group including the set of command tags to the command execution processor 124. In this way, each command tag in the set of command tags includes an LTU value mapped to one of the corresponding sequential physical addresses. Each command tag further includes a buffer address corresponding to a buffer in the buffer 142 stored in the memory device 140A.

[0057] In related embodiments, the buffer manager 113 may track the usage of the buffer 142 and be responsible for locking or releasing the buffer when host commands hit these buffers using any number of buffer management algorithms, thereby tracking the data cached in each buffer through several potential applications. The buffer management algorithms may include, for example, a 2-3 tree algorithm (also known as a 2-3 tree algorithm) in which the buffer 142 is sorted according to the LTU value (or LBA value), a linked list algorithm, or an N-way cache using a hash algorithm, and other cache management algorithms.

[0058] For purposes of explanation, assume that read commands and write commands are intermixed into more than one region, but three of the read commands include a read command to region zero ("0") with an LBA_0 value, a read command to region 44 with an LBA_44 value, and a read command to region 23 with an LBA_23 value. When performing a read lookahead, the buffer manager 113 may generate a set of command tags to read a 1MB lookahead data (as a read offset value), which includes first data and second data. The command tag may include a buffer address as a way of allocating a buffer 142 to each LTU value in the set of LTU values identified as mapped to the read offset value with the first data and the second data.

[0059] Item number Region identifier Starting LBA value Ending LBA value Read offset value 1 0 0 1024 1,024KB 2 44 4400 5424 1,024KB 3 23 2300 2454 1,024KB

[0060] Table 1

[0061] To track and manage the allocation of buffer 142, buffer manager 113 may further create and update a read cache table 127. For example, buffer manager 113 may create an entry in read cache table 127 for each read look-ahead operation to track the allocation of buffer 142 to the respective LTU values marked by each set of read look-ahead commands. Table 1 shows an example of read cache table 127 based on the presentation of three read commands to the three different regions discussed previously. Each entry may include a region identifier, a starting LBA value (e.g., the initial or first LBA retrieved according to the read request or command), an ending LBA value, and a read offset value (e.g., 1MB in this example). However, the region identifier is optional since the starting LBA value also identifies the region. The read offset value may be a predetermined system amount of fixed read look-ahead data, and the ending LBA value may be the LBA value corresponding to the end of the read offset value starting from the starting LBA value within the physical address space. The starting LBA value and the ending LBA value may define an LBA value range corresponding to the read offset value in the physical address space, e.g., the read window size. As mentioned, the read look-ahead data includes first data corresponding to the first LTU value in different cases, and second data corresponding to 63 additional LTU values of 63 additional data chunks mapped to the corresponding one of the sequential physical addresses of memory devices 130 or 140. The specific numbers presented in this example are for illustrative purposes only and may be different in different embodiments or scenarios.

[0062] In various embodiments, buffer manager 113 may further create and update a buffer index table 129, in which the sequentially read data cached in the buffer is indexed relative to discontinuous buffer numbers, as shown in Table 2. For example, the data index may refer to the LTU value corresponding to the set of LTU values, which is included in the read look-ahead command tag generated for the read command to be sent to the command execution processor. For example, each LTU value may be a "data index" indexed relative to the buffer address corresponding to the LTU value. Thus, in the example buffer index table 129 of Table 2, the buffer address may be the "buffer index".

[0063] Data index (e.g., for 64 - byte data) Buffer index 0 0 1 3 2 4 3 1 … … 63 230

[0064] Table 2

[0065] Metadata available for such buffer management algorithms (e.g., for tracking buffer allocation and usage) includes LTU / LBA values (based on which data is sorted), buffer addresses (or other buffer identifiers for indexing) indicating where the data resides in which buffer slot, and buffer usage counts enabling multiple users (e.g., host applications) in separate read or write paths to be jointly tracked. In this way, buffer manager 113 can manage writes and reads by multiple applications to multiple regions where any set of commands can write to or read from sequentially stored data, but the allocated buffers may not be sequentially numbered, as shown in Table 2. If the data in the buffers is tracked, hardware acceleration can be used to facilitate data tracking and management in the buffers.

[0066] As another example, after buffer manager 113 has created or updated the read cache table 127 according to Table 1 and the buffer index table 129 according to Table 2, assume that host system 120 subsequently issues a read request or command to subsequent sequential LBA values, as shown in Table 3. For example, the sequential LBA values for region zero ("0") can be LBA_0 plus 16KB, followed by LBA_0 plus 32KB, followed by LBA_0 plus 48KB, and so on. The value 16KB can be referred to as the buffer allocation unit offset corresponding to the amount of data in the memory device for the LTU value. Then, buffer manager 113 can perform offset calculations in different cases and determine the LTU value associated with the LBA value retrieved from the subsequent read request. As shown, the read request / command is for sequentially numbered LTU values. The determined LTU values can be, for example, LTU_1, LTU_2, and LTU_3 as shown in Table 3. Once the LTU values are known, buffer manager 113 can index within buffer index table 129 to determine the buffer address corresponding to the LTU value associated with the LBA value in the subsequent read command or request.

[0067]

[0068] Table 3

[0069] As a further illustration, assume that the command generation processor 122 retrieves a second LBA value from a second request received from the host system 120. Then, the buffer manager 113 may determine via access to an entry in the read cache table 127 that the second LBA value (LBA_16) has a single buffer allocation unit offset (16KB) relative to the starting LBA value (LBA_0), and thus corresponds to the second LTU value (LTU_1) in the set of LTU values. The buffer manager 113 may further determine that the second LBA value is within the range of LBA values corresponding to the read offset value (1,024KB = 1MB) and thus is not out of range. The buffer manager 113 may further use the second LTU value to index within the buffer index table 127 to retrieve a second buffer address (buffer index 3 in Table 2). The buffer manager 113 may then return a subset of the second data retrieved from the second buffer corresponding to the second buffer address in the set of buffers to the host system 120.

[0070] In various embodiments, the buffer manager 113 further uses a flag (e.g., a bit flag) or a counter to keep track of whether any given buffer is being used for the read or write path. This may allow the buffer to satisfy in-flight commands (e.g., already processed) with a fast search time and find a particular LBA with a short search time, so that the buffer can be used for cache hits and direct passes to the host system 120 without having to go back to the translation processor 123 for mapping. As long as the region mapping data structure 101 is checked first, consistency due to retrieving data from the cache-like buffer should not be a problem, and the command generation processor 122 will continue to do so in the disclosed sequential read optimization. In some embodiments, the controller 115 includes at least a portion of the buffer manager 113. In other embodiments or in combination, the processing device of the controller and / or the host system 120 includes at least a portion of the buffer manager 113. For example, the processing device of the controller 115 or the host system 120 may be configured to execute instructions stored in a memory to perform the operations of the buffer manager 113 described herein. In some embodiments, the buffer manager 113 is implemented in an integrated circuit chip disposed in the memory subsystem 110. In other embodiments, the buffer manager 113 is part of the operating system, device driver, or application of the host system 120.

[0071] In these embodiments, the command execution processor 124 orders write and read commands within the channels of the data buses to the memory devices 130, 140. Additionally, the command execution processor 124 may retrieve data from a first physical address and from subsequent physical addresses pointed to by the set of command tags of the memory devices 130, 140 in response to the receipt of a read command. It should be borne in mind that each command tag contains an LTU value mapped to a physical address and identifies a buffer address cached in a buffer within the volatile memory device 140A. The command execution processor 124 may further store (e.g., cache) the data implementing the read command into an allocated buffer consistent with the respective buffer address of the set of command tags, the set of command tags being generated by the command generation processor 122 and included within a command group sent to the command execution processor 124. The command execution processor 124 may further perform error handling, for example, in the physical layer corresponding to the physical address space.

[0072] The translation processor 123 translates the LTU value into a physical address of the physical address space to facilitate the command generation processor 122 in generating commands to the command execution processor 124. Thus, the translation processor 123 may act as an intermediary between the command generation processor 124 (which receives a memory request with an LBA value and creates an LTU value containing the LBA value) and the command execution processor 124 that needs to know the physical address of the physical layer to implement the command. In the present disclosure, in the sequential read optimized read-ahead operation, the conventional use of the translation processor 123 indexing into various ZNS mapping data structures may be dispensed with.

[0073] Figure 2 is a block diagram showing an example of a data structure configured to support zone-based mapping according to various embodiments. The controller 115 may store Figure 2 the data structure shown in local memory 119 (e.g., SRAM) or in a memory component (e.g., DRAM) of the memory device 140. The controller 115 may also use Figure 2 the data structure to configure or implement a media layout (e.g., a layout in which groups of data of a zone will be located within the physical address space). In Figure 2 this, the zone mapping data structure 201 is configured to provide media layout information for zones in a namespace (e.g., an LBA space for ZNS operations). The zone mapping data structure 201 may be the same as or similar to Figure 1B the zone mapping data structure 101. The zone mapping data structure 201 may have multiple entries. Each zone mapping entry in the zone mapping data structure 201 identifies information about a zone, such as the starting LBA address 211 of the zone, the block set identifier 213 of the zone, the zone cursor value 215 of the zone, the status 217 of the zone, and so on.

[0074] The host system 120 writes data in a region of LBAs starting at the region start LBA identifier 211. The host system 120 writes data sequentially in a region in the LBA space. After a certain amount of data has been written to the region, the current start LBA address for writing subsequent data is identified by the region cursor value 215. Each write command for the region moves the region cursor value 215 to a new start LBA address for the next write command for the region. The status 217 can have values indicating that the region is empty, full, implicitly open, explicitly open, closed, etc., to track the progress of writing to the region.

[0075] In Figure 2 , the logical-to-physical block mapping data structure 203 is configured to facilitate the translation of LBA addresses to physical addresses in the IC die. The logical-to-physical block mapping 203 can have multiple entries. The LBA value can be used as or converted to an index (e.g., an LTU value) of an entry in the logical-to-physical block mapping 203. The index can be used to look up an entry for the LBA value. Each entry in the logical-to-physical block mapping 203 identifies the physical address of a memory block in the IC die for the LBA value. For example, the physical address of a memory block in the IC die can include a die identifier 233, a block identifier 235, a page map entry identifier 237, etc. The die identifier 233 identifies a specific IC die (e.g., die A or die B) of the memory devices 130, 140 of the memory subsystem 110. The block identifier 235 identifies a specific memory block (e.g., a NAND flash memory) within the IC die identified by the die identifier 233. The page map entry identifier 237 identifies an entry in the page map data structure 205.

[0076] The page map data structure 205 can have multiple entries. Each entry in the page map 205 can include a page identifier 251 that identifies a page of memory cells within a block of memory cells (e.g., NAND memory cells). For example, the page identifier 251 can include the word line number and sub-block number of a page in a NAND memory cell block. In addition, the entry for the page can include the programming mode 253 of the page. For example, the page can be programmed in the SLC mode, MLC mode, TLC mode, or QLC mode. When configured in the SLC mode, each memory cell in the page will store one data bit. When configured in the MLC mode, each memory cell in the page will store two data bits. When configured in the TLC mode, each memory cell in the page will store three data bits. When configured in the QLC mode, each memory cell in the page will store four data bits. Different pages in the integrated circuit die can have different data programming modes.

[0077] In Figure 2In [text], the block set data structure 207 stores data regarding various aspects of the dynamic layout of the control region. The block set data structure 207 can be the same as or similar to the block set mapping data structure 107 of Figure 1B In one embodiment, the block set data structure 207 can be a table, which can have multiple entries. Each block set entry in the block set data structure 207 identifies the number / count 271 of integrated circuit dies (e.g., die A and die B) in which the data of the storage region is stored. For each of the integrated circuit dies used for the region, the block set entry of the block set data structure 207 has a die identifier 273, a block identifier 275, a page map entry identifier 277, a page map offset value, and so on.

[0078] The die identifier 273 identifies a specific integrated circuit die (e.g., die A or die B) in the integrated circuit dies of the memory subsystem 110, on which the subsequent data of the region can be stored. The block identifier 275 identifies a specific memory block (e.g., NAND flash memory or other media) within the integrated circuit die identified by the die identifier 273, in which the subsequent data of the region can be stored. The page map entry identifier 237 identifies a page map entry in the page map data structure 205, which identifies the page that can be used to store the subsequent data of the region.

[0079] For example, the memory subsystem 110 receives multiple streams of write commands. In an embodiment, each corresponding stream of the multiple streams is configured to write data sequentially in the logical address space in one embodiment; and in another embodiment, the streams of the multiple streams are configured to write data pseudo-sequentially or randomly in the logical address space in one embodiment. Each write stream includes a set of commands marked to write a set of data together as a group, trim, or overwrite. In the group, the data can be written sequentially, randomly, or pseudo-sequentially into the logical space. Preferably, the data in the group is written into an erase block set, where the memory cells in the erase block set store the data of the stream but not the data from other streams. The erase block set can be erased to remove the data of the stream without erasing the data of other streams.

[0080] For example, each write stream is permitted to write sequentially at the LBA of the region in the namespace of the integrated circuit dies of the memory devices 130, 140 allocated to the memory subsystem 110, but is prohibited from writing data disorderly in the LBA (or logical address) space. The translation processor 123 of the memory subsystem 110 identifies multiple physical or erase units in the memory subsystem 110 that can be used to write data in parallel.

[0081] The translation processor 123 may select a first command from the plurality of streams for parallel execution in a plurality of physical units available for writing data. In dynamic response to the first command being selected for parallel execution in the plurality of physical units, the translation processor 123 may generate and store a portion of a layout that maps a logical address identified by the first command in a logical address space to a physical address of a memory unit in the plurality of memory units.

[0082] The command execution processor 124 may execute the first command in parallel by storing data in memory cells according to the physical addresses. For example, while the first command is being scheduled for execution, the execution of the second command may be in progress in a subset of memory cells of the IC die of the memory subsystem 110. Therefore, the subset of memory cells used to execute the second command may not be available for the first command. After scheduling the first command and determining the portion of the layout of the logical addresses for the first command, the first command may be executed in parallel in the plurality of physical cells and / or in parallel with the execution of the second command in the remaining physical cells of the memory subsystem 110.

[0083] For example, after identifying a number of memory units (e.g., IC dies) that can be used to execute a subsequent command, the translation processor 123 can identify physical addresses that can be used to store data for the subsequent command from the block set data structure 207. The physical addresses can be used to update corresponding entries in the logical-to-physical block mapping data structure 203 for the LBA addresses for the subsequent command.

[0084] For example, when the IC die is free to write data, the translation processor 123 can determine a command that can be written / programmed to a region of memory cells in the IC die. Based on the block set data structure 207, the translation processor 123 locates the entry for the region, locates the block identifier 275 and the page map entry identifier 277 associated with the integrated circuit die identifier 273, and updates the corresponding fields of the entry in the logical-to-physical block mapping data structure 203 for the LBA for the command for the region using the die identifier 273, the block identifier 275, and the page map entry identifier 277.

[0085] Figure 3 According to the embodiment Figure 1A - 1B FIG. 1 is a block diagram of the relationship between the command generation processor 122, the translation processor 123, and the command execution processor 124 of the memory subsystem controller 115. In various embodiments, the controller 115 includes a shared volatile memory 140B and a command buffer 140C in the shared volatile memory 140B. In one embodiment, the shared volatile memory 140B is a reference Figure 1BPortions of the volatile memory 125 or volatile memory device 140A being discussed. In various embodiments, the command generation processor 122 may receive a first read request from the host system 120 (or other requesting agent). The first read request may include a first LBA value that corresponds to a first physical address of the memory device 130 or 140 that the read operation is directed to. In servicing the first read request, the command generation processor 122 may create a first logical transfer unit (LTU) value that includes the first LBA value, and the first LTU value will map to the first physical address of the memory devices 130, 140.

[0086] In some embodiments, the translation processor 123 may be configured to automatically store (or buffer) the LTU-to-physical address (PA) mapping 301 into the shared volatile memory 140B when its data is programmed into the memory devices 130, 140. For example, the LTU-to-PA mapping 301 may be a portion of the logical-to-physical block mapping data structure 203 and the page mapping data structure 205 that is written when the corresponding physical address is programmed into the memory device 130 or 140. This may provide a data structure that can be accessed quickly, which only provides the LTU-to-PA mapping at the command tag level. In some embodiments, the LTU-to-PA mapping 301 in the shared volatile memory 140B may be regarded as a cache to keep the size of this data structure limited.

[0087] Continuing to refer Figure 3 to, the translation processor 123 may further selectively set a flag 303 (e.g., a bit flag, etc.) in the shared volatile memory 140B. Thus, each entry in the LTU-to-PA mapping 301 may include a physical address that maps to the LTU value and the flag. In an alternative embodiment, the bit value of a bitmap stored in the register 112 ( Figure 1B ) may be set. A bit value in the bitmap may correspond to a specific LTU value and thus be used as the flag 303 in the shared volatile memory 140B. The bitmap may be associated with a physical address space that is known to be written sequentially (e.g., for each ZNS operation). The flag 303 (or the bit value within the bitmap) may indicate whether the LTU-to-PA mapping entry is associated with a region of the LBA address space that maps to data written sequentially in the memory device 130 or 140. The translation processor 123 may further selectively set the die available flag 305 to indicate that the die where the physical address is located is available to service commands. In some embodiments, if there is more than one die for a region, then there may be more than one flag, one flag per region.

[0088] In various embodiments, if the flag 303 is set and the die available flags 305 are all set, then the command generation processor 122 performs the read look-ahead optimization disclosed herein. The read optimization may include, for example, automatically incrementing a first physical address retrieved from the LTU-to-PA mapping 301 for a first read request to determine subsequent physical addresses within an offset value (e.g., read window size) of the first physical address. In one embodiment, the automatic incrementing is performed such that the first physical address is incremented by page number until the end of the read window size is reached from the first physical address.

[0089] Next, the command generation processor 122 may generate (or update) in the command buffer 140C a set of command tags for instructing the command execution processor 124 to retrieve data from the memory device 130 or 140 and store the data in a set of buffers (discussed with reference to Figure 1B ). Then, the command generation processor 122 may further transmit to the command execution processor 124 of the processing device a command group that respectively includes one of the set of command tags. The set of commands may be buffered in the command buffer 140C as Cmd[0], Cmd[1], Cmd[2], etc. up to Cmd[n]. In one embodiment, the command generation processor 122 may concatenate the set of command tags into a command chain (e.g., a series of corresponding commands) and transmit the command chain to the command execution processor 124 in a single command message.

[0090] After the command execution processor 124 stores the data into the corresponding buffer of the read look-ahead allocated for the first (or initial) read command, the command generation processor 122 may return the data stored at the first physical address to the host system 120 or other requesting agent. However, the command generation processor 122 may further service subsequent read requests or commands directly for subsequent physical addresses outside the buffer, as described herein. For example, in response to a second read request, the command generation processor 122 may determine that a second LBA value of the second read request corresponds to a second physical address among the subsequent physical addresses. Next, the command generation processor 122 may retrieve a second subset of data from a second buffer having a buffer address associated with the second command tag among the set of command tags from the set of buffers, and transmit the second subset of data to the host system 120 in response to the first of the subsequent read commands.

[0091] Figure 4is a flowchart of method 400 for supporting direct cache hits based on read commands according to an embodiment. Method 400 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, the hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 400 is executed by Figure 1A - 1B the controller 115 (e.g., the command generation processor 122) of. Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, all processes are not required in every embodiment. Other process flows are possible.

[0092] At operation 410, the processing logic accesses a read command having a first command tag, where the first command tag includes a first logical transfer unit (LTU) value and a first buffer address of a first buffer in buffer 142. For example, the read command may be received from the host system 120 or generated by the processing logic based on the content of a read request received from the host system 120. The first LTU value is mapped from a region of a plurality of sequential logical block address (LBA) values to a first physical address among a plurality of sequential physical addresses of the memory device 130 or 140. In this embodiment, the first data is stored at the first physical address, and the first LTU value contains the first LBA value among the plurality of sequential LBA values.

[0093] At operation 420, the processing logic generates a set of command tags that direct the command execution processor of the processing device to retrieve second data from the memory device and store the second data in a set of buffers. In this embodiment, for example, the set of command tags includes a second command tag associated with a second physical address sequentially after the first physical address, a third command tag associated with a third physical address sequentially after the second physical address, and so on, until the number of command tags is sufficient to fill the commands for reading the second data and the first data. This read-ahead can be performed without other translation work (by the translation processor 123) or read command execution work performed by the command execution processor 124 at the memory device 130 or 140.

[0094] At operation 430, the processing logic creates an entry in the read cache table 127 for the set of buffers. For example, the entry may include a region identifier for the region, a starting LBA value set to a first LBA value, and a read offset value corresponding to the amounts of the first data and the second data. The entry may further include an ending LBA value that corresponds to the end of the read offset value starting from the starting LBA value within the physical address space. An example of the read cache table 127 is shown in Table 1.

[0095] Figure 5 is a flow chart of a method 500 for sequential read optimization according to an embodiment. The method 500 may be executed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 500 is executed by Figure 1A - 1B the controller 115 (e.g., the command generation processor 122). Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, all processes are not required in every embodiment. Other process flows are possible.

[0096] Referring to Figure 5 , at operation 510, the processing logic receives a read request for a memory device that includes a first LBA value of a logical block address (LBA) address space. At operation 515, the processing logic creates a first logical transfer unit (LTU) value that includes the first LBA value, and the first LTU value will map to a first physical address of the memory device. The first LTU value does not need to be sent to the translation processor 123 as long as the translation processor 123 has created an LTU-to-PA entry in the LTU-to-PA mapping 301 of the shared volatile memory 140B ( Figure 3 ). Then, the processing logic may access the first physical address indexed relative to the first LTU value within the shared memory 140B ( Figure 3 ).

[0097] Continuing to refer to Figure 5, at operation 520, the processing logic determines whether a fast look-up flag is set. This fast look-up flag can be flag 303 associated with the first physical address set in the shared volatile memory 140B; or the fast look-up flag can be a bit value in one of the registers 112 storing a bitmap associated with the ZNS-related physical address space of the memory device 130 or 140. In either case, the fast look-up flag can indicate that the first LTU value is associated with a region of multiple sequential LBA values that are sequentially mapped to multiple sequential physical addresses. At operation 540, the processing logic determines whether the die available flag 305 is set, which has been discussed with reference to Figure 3 above.

[0098] At operation 530, if the fast look-up flag or the die available flag is not set, then the processing logic submits a read request via the normal read path, which includes sending the first LTU value to the translation processor 123 to cause the translation processor 123 to perform a lookup in the ZNS data structure to map the first LTU to the first physical address.

[0099] At operation 550, assuming that the fast look-up flag and the die available flag are set with respect to the first LTU value, the processing logic retrieves the first physical address that has been stored (or buffered) there by the translation processor 123 from the volatile memory (e.g., Figure 3 the shared volatile memory 140B in). The first physical address can be indexed within an entry of the LTU-to-PA mapping 301 in the shared volatile memory 140B.

[0100] At operation 560, the processing logic allocates a set of buffers in the volatile memory, where the capacity of the set of buffers matches the amount of data stored at the first physical address and subsequent physical addresses, and the subsequent physical addresses are sequentially numbered within a read window size defined, for example, by a read offset value (Table 1) starting from the first physical address (e.g., the first LTU value is mapped to the first physical address). The volatile memory storing the buffer can be the volatile memory 125, the volatile memory device 140A, and / or the shared volatile memory 140B. In various embodiments, the processing logic determines each subsequent physical address by incrementing the page number of the first physical address until the end of the read window size (e.g., the offset value) is reached.

[0101] At operation 570, the processing logic generates a set of command tags instructing the command execution processor 124 of the processing device to retrieve data from the memory device and store the data in the set of buffers. The set of command tags can include a first command tag associated with the first physical address and additional command tags associated with subsequent physical addresses.

[0102] At operation 580, processing logic creates an entry in a read cache table for the set of buffers, where the entry includes a region identifier for the region, a starting LBA value set to a first LBA value, and a read offset value corresponding to the amount of data. The entry may further include an ending LBA value that corresponds to the end of the read offset value starting from the starting LBA value within the physical address space. Processing logic may then use the read cache table to identify subsequent requests or commands for LBA values corresponding to physical addresses within the read offset value and thus stored within the set of buffers. Processing logic may thus retrieve a subset of the data stored in the buffer as a cache hit and return the subset of data to host system 120 or other request agent.

[0103] Figure 6A - 6C is a flow diagram of a method 600 for supporting direct cache hits and transfers according to an illustrative embodiment. Method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 600 is performed by Figure 1A - 1B controller 115 (e.g., command generation processor 122). Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, all processes are not required in every embodiment. Other process flows are possible.

[0104] Referring Figure 6A , at operation 605, processing logic receives a read request for a memory device that includes a first LBA value of a logical block address (LBA) address space, where the first LBA value belongs to a region of a plurality of sequential LBA values that map to a plurality of sequential physical addresses. At operation 610, processing logic creates a first logical transfer unit (LTU) value that includes the first LBA value, where the first LTU value maps to a first physical address of memory device 130 or 140.

[0105] At operation 615, the processing logic allocates a set of buffers in volatile memory (e.g., in buffer 142), where the capacity of the set of buffers matches the amount of data stored at a first physical address and subsequent physical addresses, the subsequent physical addresses being sequentially numbered within a read offset value starting from the first physical address. The volatile memory storing the buffers can be volatile memory 125, volatile memory device 140A, or other shared volatile memory 140B. In various embodiments, the processing logic determines each subsequent physical address by incrementing the first physical address by page number until the end of the read offset value is reached.

[0106] At operation 620, the processing logic generates a set of command tokens that direct the command execution processor of the processing device to retrieve data from the memory device and store the data in the set of buffers. In this embodiment, the set of command tokens includes at least a first command token associated with the first physical address and a second command token associated with a second physical address that sequentially follows the first physical address among the subsequent physical addresses. The set of command tokens can include additional command tokens, e.g., up to a total of 64 command tokens with sequentially sorted LTU values, where each LTU value corresponds to 16KB of data, and the read offset value for reading look-ahead data is 1MB.

[0107] At operation 625, the processing logic creates an entry in the read cache table for the set of buffers, where the entry includes a region identifier for the region, a starting LBA value set to a first LBA value, and a read offset value corresponding to the amount of data. The entry can further include an ending LBA value that corresponds to the end of the read offset value starting from the starting LBA value within the physical address space. An example of the read cache table 127 is shown in Table 1.

[0108] Reference Figure 6B , method 600 is performed in the context of a set of LTU values in the set of command tokens that includes a subset of multiple sequential physical addresses within the read offset value. Referring to the generation of the set of command tokens and the generation of the buffer index table, Figure 6B parts of method 600 in

[0109] At operation 630, the processing logic assigns an LTU value from the set of LTU values to each command token in the set of command tokens. The LTU values can be assigned sequentially and can correspond to an increment of buffer allocation units starting from the starting LBA value (e.g., 16KB in the above example). At operation 635, the processing logic assigns a buffer address of a buffer within the set of buffers to each command token in the set of command tokens. This assignment can be Figure 6Aportion of the allocation of the set of buffers in the volatile memory discussed at operation 615. In one embodiment, the buffer addresses assigned to the respective sequential LTU values are not necessarily sequential or contiguous, and thus the allocation within the buffer index table can be managed by a buffer management algorithm as previously discussed.

[0110] At operation 640, the processing logic generates a buffer index table in the volatile memory to track the LTU value associated with each command tag of the set of command tags mapped to buffer addresses associated with LTU values. An example of buffer index table 129 is shown in Table 2. The processing logic can also track the entries of the buffer index table according to one of a linked list or a 2-3 tree algorithm in which the set of buffers are sorted according to LTU values. In this way, the processing logic can access the buffer index table 129 after determining the subsequent LTU value associated with the current read request or command, and locate the corresponding buffer in the set of buffers that contains the requested data.

[0111] More specifically, referring to Figure 6C and using Tables 1 and 2, method 600 is executed to implement subsequent read requests or read commands in cache-type access, so as to pull data from the set of buffers, rather than engaging the translation processor 123 or the command execution processor 124 to pull data from the memory devices 130 or 140. At operation 645, the processing logic retrieves a second LBA value from a subsequent read request or command received from the host system 120. For example, for purposes of explanation, the second LBA value is (LBA_16).

[0112] At operation 650, the processing logic determines via access to an entry in the read cache table 127 that the second LBA value has a buffer allocation unit offset (e.g., 16KB) relative to the starting LBA value (LBA_0), and thus corresponds to a second LTU value (e.g., LTU_1) in the set of LTU values, and is within the LBA value range corresponding to the read offset value. At operation 660, the processing logic indexes using the second LTU value within the buffer index table 129 to retrieve a second buffer address, such as buffer index 3 in Table 2. Other index or addressing values related to the location within the volatile memory are envisioned and can be managed by the buffer manager discussed. At operation 665, in response to a cache hit at the set of buffers, the processing logic returns to the host system 120 a subset of the data retrieved from the second buffer corresponding to the second buffer address in the set of buffers. In this way, the processing logic can also improve read performance and avoid the expensive cost of interrupting write operations to service a large number of read requests (which occur more frequently than write operations), for example by allowing many read requests to hit in the buffer using a read look-ahead operation.

[0113] Figure 6C The portion of method 600 depicted in

[0113] can be extended to other or subsequent read requests or read commands. For example, the processing logic can retrieve a third LBA value from a subsequent read request received from the host system. The processing logic can further determine, via access to an entry in the read cache table, that the third LBA value has a buffer allocation unit offset that is twice that of the starting LBA value, and thus corresponds to the third LTU value in the set of LTU values and is within the range of LBA values corresponding to the read offset value. The processing logic can further use the third LTU value to index within the buffer index table to retrieve a third buffer address. The processing logic can further return to the host system a subset of data retrieved from the third buffer corresponding to the third buffer address in the set of buffers.

[0114] Figure 7 An example machine of computer system 700 is shown, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 700 can correspond to a host system (e.g., Figure 1A host system 120 of Figure 1A ), which includes, is coupled to, or utilizes a memory subsystem (e.g.,

[0115] memory subsystem 110 of

[0116] ). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0115] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing, sequentially or otherwise, a set of instructions specifying actions to be taken by the machine. Additionally, although a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0116] Example computer system 700 includes a processing device 702, a main memory 704 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0117] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 702 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute the instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 that communicates via the network 720.

[0118] The data storage system 718 can include a machine-readable storage medium 724 (also referred to as a non-transitory computer-readable medium) on which a set or sets of instructions 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 can also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution by the computer system 700, the main memory 704, and the processing device 702 which also constitute a machine-readable storage medium. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 can correspond to Figure 1A - 1B the memory subsystem 110.

[0119] In one embodiment, the instructions 726 include instructions implementing the functionality of the buffer manager 113 corresponding to Figure 1B . Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "non-transitory machine-readable storage medium" should be considered to include a single medium or multiple media storing a set or sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0120] Some of the foregoing detailed description has been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the data processing art to convey the substance of their work to others skilled in the art. Herein, and in general, an algorithm is conceived of as a self-consistent sequence of operations that produces the desired result. The operations are those that require physical manipulation of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and so forth.

[0121] However, it should be borne in mind that all such and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memory or registers of the computer system or other such information storage systems.

[0122] The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, which are respectively coupled to a computer system bus.

[0123] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. Structures for various of these systems will be presented from the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0124] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform processes according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0125] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications can be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory subsystem, comprising: A memory device; A volatile memory including a buffer; And A processing device coupled to the memory device and the volatile memory, wherein the processing device is configured to perform operations, the operations including: Accessing a read command having a first command tag, the first command tag including a first logical transfer unit value and a first buffer address of a first buffer, the first logical transfer unit value being mapped from a region of a plurality of sequential logical block address values to a first physical address, and first data being stored at the first physical address; Generating a set of command tags for retrieving second data from the memory device and storing the second data in a set of the buffers, wherein the set of command tags includes at least a second command tag associated with a second physical address sequentially after the first physical address.

2. The memory subsystem according to claim 1, wherein the operations further include allocating the set of the buffers in the volatile memory, wherein a capacity of the set of the buffers matches an amount of data stored at the first physical address and subsequent physical addresses, the subsequent physical addresses being sequentially numbered within a read offset value starting from the first physical address.

3. The memory subsystem according to claim 1, wherein the operations further include transmitting a command group including one of the set of command tags to a command execution processor, and in response to receiving the set of command tags, the command execution processor retrieves the second data from the memory device and stores the second data in the set of the buffers according to corresponding buffer addresses of the set of command tags.

4. The memory subsystem according to claim 1, wherein the volatile memory further stores a read cache table, and wherein the operations further include creating an entry in the read cache table for the set of the buffers, wherein the entry includes: A start local block address value set to a first local block address value of the first logical transfer unit; And A read offset value corresponding to amounts of the first data and the second data.

5. The memory subsystem according to claim 4, wherein the processing device further performs the following operations: Receiving a read request including the first local block address value; Generating the first logical transfer unit value including the first local block address value; Reading a flag from the volatile memory to determine that the first logical transfer unit value is associated with the region; And Populating the read command with the first logical transfer unit value and the first buffer address.

6. The memory subsystem according to claim 4, wherein the entry further includes an end local block address value corresponding to an end of the read offset value starting from the start local block address value within a physical address space.

7. The memory subsystem according to claim 4, wherein the set of command tags includes a set of logical transfer unit values corresponding to a subset of a plurality of sequential physical addresses within the read offset value, and wherein each command tag in the set of command tags includes: a logical transfer unit value of the set of logical transfer unit values that maps to a physical address in the subset of the plurality of sequential physical addresses; and a buffer address of a buffer within the set of the buffers; and wherein the operation further includes generating a buffer index table in the volatile memory to track the logical transfer unit values associated with each command tag in the set of command tags, the logical transfer unit values being indexed relative to the buffer address associated with the logical transfer unit values.

8. The memory subsystem according to claim 7, wherein the entries of the buffer index table are tracked according to one of the following: a linked list; a 2-3 tree algorithm in which the buffers are sorted according to logical transfer unit values; or an N-way cache employing a hashing algorithm.

9. The memory subsystem according to claim 7, wherein the operation further includes: retrieving a second local block address value from a second read request received from a host system; determining the second local block address value based on the entry in the read cache table: having a single buffer allocation unit offset relative to the starting local block address value and thus corresponding to a second logical transfer unit value in the set of logical transfer unit values; and within the range of local block address values corresponding to the read offset value; indexing within the buffer index table using the second logical transfer unit value to retrieve a second buffer address; and returning to the host system a subset of the second data retrieved from a second buffer corresponding to the second buffer address in the set of the buffers.

10. A method for supporting direct cache hits and transfers, comprising: accessing a read command having a first command tag, the first command tag including a first logical transfer unit value and a first buffer address of a first buffer of a plurality of buffers, the first logical transfer unit value mapping from a region of a plurality of sequential logical block address values to a first physical address where first data is stored; and generating a set of command tags for retrieving second data from the memory device and storing the second data in a set of the plurality of buffers, wherein the set of command tags includes at least a second command tag associated with a second physical address sequentially after the first physical address.

11. The method according to claim 9, further comprising allocating the set of the plurality of buffers in the volatile memory, wherein the capacity of the set of the plurality of buffers matches the amount of data stored at the first physical address and subsequent physical addresses, the subsequent physical addresses being sequentially numbered within a read offset value starting from the first physical address.

12. The method according to claim 10, further comprising transmitting to a command execution processor command groups respectively including one of the set of command tags, and in response to receiving the set of command tags, the command execution processor retrieving the second data from the memory device and storing the second data in the set of the plurality of buffers according to corresponding buffer addresses of the set of command tags.

13. The method according to claim 10, further comprising creating entries in a read cache table for the set of the plurality of buffers, wherein the entries include: A starting local block address value, which is set to a first local block address value of the first logical transfer unit; And A read offset value corresponding to the amounts of the first data and the second data.

14. The method according to claim 13, further comprising: Receiving a read request including the first local block address value; Generating a first logical transfer unit value including the first local block address value; Reading a flag from volatile memory to determine that the first logical transfer unit value is associated with the region; And Filling the read command with the first logical transfer unit value and the first buffer address.

15. The method according to claim 13, wherein the entry further includes an ending local block address value, the ending local block address value corresponding to the end of the read offset value starting from the starting local block address value within the physical address space.

16. The method according to claim 13, wherein the set of command tags includes a set of logical transfer unit values corresponding to a subset of a plurality of sequential physical addresses within the read offset value, and wherein each command tag in the set of command tags includes: A logical transfer unit value in the set of logical transfer unit values, which is mapped to one physical address in the subset of the plurality of sequential physical addresses; And A buffer address of a buffer within the set of buffers; And The method further includes generating a buffer index table to track the logical transfer unit values associated with each command tag in the set of command tags indexed according to the buffer addresses associated with the logical transfer unit values.

17. The method according to claim 16, wherein the entries of the buffer index table are tracked according to one of the following: A linked list; A 2-3 tree algorithm in which the plurality of buffers are sorted according to logical transfer unit values; or An N-way cache employing a hash algorithm.

18. The method according to claim 16, further comprising: Retrieving a second local block address value from a second read request received from a host system; Determining the second local block address value according to the entry in the read cache table: Having a single buffer allocation unit offset twice that relative to the starting local block address value and thus corresponding to a second logical transfer unit value in the set of logical transfer unit values; and Within the local block address value range corresponding to the read offset value; Index within the buffer index table using the second logical transfer unit value to retrieve a second buffer address; And Return to the host system a subset of the second data retrieved from the second buffer corresponding to the second buffer address from the set of the plurality of buffers.

19. A non-transitory computer-readable medium storing instructions that, when executed by a processing device of a memory subsystem, cause the processing device to perform a plurality of operations, including: Access a read command having a first command tag, the first command tag including a first logical transfer unit value and a first buffer address of a first buffer of a plurality of buffers, the first logical transfer unit value being mapped from a region of a plurality of sequential logical block address values to a first physical address, and first data being stored at the first physical address; And Generate a set of command tags for causing second data to be retrieved from the memory device and stored in a set of the plurality of buffers, wherein the set of command tags includes at least a second command tag associated with a second physical address sequentially after the first physical address.

20. The non-transitory computer-readable medium according to claim 16, wherein the operations further include: Allocate the set of the plurality of buffers in volatile memory, wherein the capacity of the set of the plurality of buffers matches the amount of data stored at the first physical address and subsequent physical addresses, the subsequent physical addresses being sequentially numbered within a read offset value starting from the first physical address; And Create an entry in a read cache table for the set of the plurality of buffers, wherein the entry includes: A starting local block address value that is set to the first local block address value of the first logical transfer unit; And A read offset value corresponding to the amounts of the first data and the second data.

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