Cache management method, electronic equipment and storage medium

Abstract

The invention provides a cache management method, electronic equipment and a storage medium, and the method comprises the steps that a flow management chip determines an up-regulation value of a cache occupancy level threshold in response to the detection of the start of a calibration task of a DDR cache; and the traffic management chip up-regulates the cache occupancy level threshold based on the up-regulation value of the cache occupancy level threshold. According to the method provided by the invention, unnecessary packet loss of the service data can be avoided during the calibration period of the DDR cache.

Description

Technical Field

[0001] This application relates to the field of cache management, and particularly to a cache management method, an electronic device, and a storage medium. Background Art

[0002] A traffic management chip is a chip used for traffic management in an electronic device. Among them, traffic management can be based on factors such as performance, latency, and packet loss rate. The purpose of traffic management is to meet the performance requirements, latency requirements, or packet loss rate requirements of services or users.

[0003] In a scenario where a Double Data Rate (DDR) cache is used as a traffic cache device, the traffic management chip usually sets a write-side cache (wcache), which is used to receive service data and write the service data into the DDR cache. However, due to tasks such as calibration (Retrain) in the DDR cache, during the calibration process of the DDR cache, the DDR cache cannot respond to the read / write access requests of the traffic management chip, which will cause service data to continuously accumulate in the traffic management chip, resulting in unnecessary packet loss. Summary of the Invention

[0004] This application provides a cache management method, an electronic device, and a storage medium, which helps to avoid unnecessary packet loss of service data during the calibration period of the DDR cache.

[0005] In a first aspect, this application provides a cache management method, which is applied to an electronic device. The electronic device includes a traffic management chip and a Double Data Rate (DDR) cache. The method includes: in response to detecting the start of the calibration task of the DDR cache, the traffic management chip determines an upward adjustment value of the cache occupancy level threshold; the traffic management chip adjusts the cache occupancy level threshold upward based on the upward adjustment value of the cache occupancy level threshold.

[0006] In this application, after detecting the start of the calibration task of the DDR cache, the traffic management chip adjusts the cache occupancy level threshold upward, so that the incoming traffic during the calibration period is no longer calculated into the occupancy of the write-side cache, thereby avoiding unnecessary packet loss caused by a sudden increase in the cache occupancy level.

[0007] In one possible implementation, the traffic management chip determines the upward adjustment value of the cache occupancy level threshold by: the traffic management chip determines the upward adjustment value of the cache occupancy level threshold based on the write bandwidth of the DDR cache.

[0008] In this application, configuring the upward adjustment value based on the product specifications of the DDR can improve the adaptability to different products.

[0009] In one possible implementation, after the traffic management chip increases the cache occupancy level threshold based on the increased value of the cache occupancy level threshold, the method further includes: the traffic management chip periodically detects the cache occupancy in the traffic management chip; in any first period, if the cache occupancy in the traffic management chip is close to the threshold of the current cache occupancy level, the traffic management chip increases the threshold of the current cache occupancy level based on a first preset increased value.

[0010] In this application, by detecting the occupancy of the write-side cache in real time during the calibration of the DDR cache and gradually increasing the cache occupancy level threshold according to this situation, unnecessary packet loss caused by a sudden increase in the incoming traffic can be avoided.

[0011] In one possible implementation, the increased value of the cache occupancy level threshold is a second preset increased value, and the cache occupancy level threshold after being increased based on the second preset increased value is the maximum value of the cache occupancy level threshold.

[0012] In this application, by directly increasing the maximum value, the cache occupancy level threshold can be increased, and the overhead caused by multiple increases can be reduced.

[0013] In one possible implementation, the method further includes: in response to detecting the end of the calibration task of the DDR cache, the traffic management chip determines the decreased value of the cache occupancy level threshold; the traffic management chip decreases the current cache occupancy level threshold based on the decreased value of the cache occupancy level threshold.

[0014] In this application, after the traffic management chip detects the end of the calibration task of the DDR cache, it decreases the cache occupancy level threshold to the original value to avoid affecting normal services due to an excessively high cache occupancy level threshold.

[0015] In one possible implementation, the decreased value of the cache occupancy level threshold is a preset decreased value, and the traffic management chip decreasing the increased cache occupancy level threshold based on the decreased value of the cache occupancy level threshold includes: in any second period, the traffic management chip decreases the current cache occupancy level threshold based on the preset decreased value.

[0016] In this application, by gradually decreasing the cache occupancy level threshold to the original value, unnecessary packet loss caused by a sudden decrease in the cache occupancy level threshold can be avoided.

[0017] In a second aspect, this application provides a cache management device, including one or more functional modules, and the one or more functional modules are used to implement the cache management method as described in the first aspect.

[0018] In a third aspect, the present application provides an electronic device, including: a processor and a memory, where the memory is used to store a program; and the processor is used to run the program to implement the cache management method as described in the first aspect.

[0019] In a fourth aspect, the present application provides a readable storage medium, in which a program is stored. When the program runs on an electronic device, the electronic device is caused to implement the cache management method as described in the first aspect.

[0020] In a fifth aspect, the present application provides a program. When the above program runs on a processor of an electronic device, the electronic device is caused to execute the cache management method as described in the first aspect.

[0021] In a possible design, the program in the fifth aspect may be stored in whole or in part on a storage medium packaged together with the processor, or may be stored in whole or in part on a memory not packaged together with the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic structural diagram of the electronic device provided by an embodiment of the present application;

[0023] Figure 2 It is a system architecture diagram provided by an embodiment of the present application;

[0024] Figure 3 It is a schematic flowchart of an embodiment of the cache management method provided by the present application;

[0025] Figure 4 It is a schematic structural diagram of the cache management device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] In the embodiments of the present application, unless otherwise specified, the character " / " indicates that the associated objects before and after are in an "or" relationship. For example, A / B may represent A or B. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, these three situations.

[0027] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features, nor can they be understood as indicating or implying an order.

[0028] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. In addition, "at least one (item)" or its similar expressions refer to any combination of these items, which may include any combination of a single item or plural items. For example, at least one (item) of A, B, or C may represent: A, B, C, A and B, A and C, B and C, or A, B, and C. Each of A, B, and C itself may be an element or a set containing one or more elements.

[0029] In the embodiments of the present application, terms such as "exemplary", "in some embodiments", "in another embodiment", etc. are used to give examples, provide illustrations, or make explanations. Any embodiment or design solution described as "exemplary" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of the term "exemplary" is intended to present concepts in a specific manner.

[0030] In the embodiments of the present application, the words "of", "corresponding", and "corresponding to" can sometimes be used interchangeably. It should be noted that when not emphasizing the differences, the meanings to be expressed are the same. In the embodiments of the present application, communication and transmission can sometimes be used interchangeably. It should be noted that when not emphasizing the differences, the meanings they express are the same. For example, transmission may include sending and / or receiving, and can be a noun or a verb.

[0031] In the embodiments of the present application, the equality involved can be used in combination with greater than, applicable to the technical solutions adopted when greater than, or can also be used in combination with less than, applicable to the technical solutions adopted when less than. It should be noted that when equality is used in combination with greater than, it cannot be used in combination with less than; when equality is used in combination with less than, it is not used in combination with greater than.

[0032] A traffic management chip is a chip used for traffic management in an electronic device. Among them, traffic management can be based on factors such as performance, latency, and packet loss rate. The purpose of traffic management is to meet the performance requirements, latency requirements, or packet loss rate requirements of services or users.

[0033] In a scenario where a double data rate (DDR) cache is used as a traffic cache device, the traffic management chip usually sets a write-side cache (wcache), which is used to receive service data and write the service data into the DDR cache. However, due to tasks such as calibration (Retrain) in the DDR cache, during the calibration process of the DDR cache, the DDR cache cannot respond to the read and write access requests of the traffic management chip, which will cause service data to continuously accumulate in the traffic management chip, resulting in unnecessary packet loss.

[0034] Based on the above problems, an embodiment of the present application proposes a cache management method, which is applied to an electronic device. The electronic device may be a device with a traffic management chip and a DDR cache. The electronic device may be a network device, such as a router, a switch, etc., or the electronic device may be a terminal device. The embodiment of the present application does not make special limitations on this.

[0035] In some alternative embodiments, the traffic management chip may also be replaced by a traffic management module.

[0036] Figure 1 First, a schematic structural diagram of the electronic device 100 is exemplarily shown.

[0037] The above-mentioned electronic device 100 may include: at least one processor; and at least one memory communicatively connected to the above-mentioned processor, wherein: the above-mentioned memory stores program instructions executable by the above-mentioned processor, and the processor can execute the method provided by the embodiments shown in this article by invoking the above-mentioned program instructions.

[0038] Figure 1 A block diagram of an exemplary electronic device 100 suitable for implementing the embodiments of this article is shown. Figure 1 The shown electronic device 100 is only an example and should not bring any limitations to the functions and usage scopes of the embodiments of this article.

[0039] As Figure 1 shown, the components of the electronic device 100 may include but are not limited to: one or more processors 110, a memory 120, a communication bus 140 connecting different system components (including the memory 120 and the processor 110), and a communication interface 130.

[0040] The communication bus 140 represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus structure in a variety of bus structures. For example, these architectures include but are not limited to the Industry Standard Architecture (hereinafter referred to as: ISA) bus, the Micro Channel Architecture (hereinafter referred to as: MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (hereinafter referred to as: VESA) local bus, and the Peripheral Component Interconnection (hereinafter referred to as: PCI) bus.

[0041] The electronic device 100 typically includes various computer system-readable media. These media can be any available media that can be accessed by the device, including volatile and non-volatile media, removable and non-removable media.

[0042] The memory 120 may include computer system-readable media in the form of volatile memory, such as random access memory (Random Access Memory; hereinafter referred to as: RAM) and / or cache memory. The device may further include other removable / non-removable, volatile / non-volatile computer system storage media. Although Figure 1 not shown in the figure, a disk drive for reading and writing to a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (such as: Compact Disc Read Only Memory; hereinafter referred to as: CD-ROM), Digital Video Disc Read Only Memory; hereinafter referred to as: DVD-ROM) or other optical media) may be provided. In these cases, each drive may be connected to the communication bus 140 through one or more data media interfaces. The memory 120 may include at least one program product having a set (such as at least one) of program modules configured to perform the functions of the embodiments herein.

[0043] A program / utility having a set (at least one) of program modules may be stored in the memory 120. Such program modules include - but are not limited to - an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include the implementation of a network environment. The program modules generally perform the functions and / or methods in the embodiments described herein.

[0044] The electronic device 100 can also communicate with one or more external devices (such as a keyboard, a pointing device, a display, etc.), and can also communicate with one or more devices that enable a user to interact with the device, and / or communicate with any device that enables the device to communicate with one or more other devices (such as a network card, a modem, etc.). Such communication can be carried out through the communication interface 130. And, the electronic device 100 can also communicate with one or more networks (such as a Local Area Network; hereinafter referred to as: LAN), a Wide Area Network; hereinafter referred to as: WAN) and / or a public network, such as the Internet) through a network adapter ( Figure 1 not shown in the figure). The above-mentioned network adapter can communicate with other modules of the device through the communication bus 140. It should be understood that althoughFigure 1 is not shown in the figure, and other hardware and / or software modules can be used in combination with the electronic device 100, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, redundant arrays of independent drives (hereinafter referred to as RAID) systems, tape drives, and data backup storage systems, etc.

[0045] The processor 110 executes various functional applications and data processing by running the programs stored in the memory 120, such as implementing the methods provided in the embodiments of the present application.

[0046] It can be understood that the interface connection relationships between the modules illustrated in the embodiments of the present application are only illustrative descriptions and do not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 can also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0047] Next, in combination with Figure 2 an exemplary description of the system architecture of the electronic device 100 will be given.

[0048] Figure 2 is a schematic diagram of an embodiment of the system architecture of the electronic device 100 provided in the present application. Referring to Figure 2 , the electronic device 100 includes a traffic management chip 210 and a DDR cache 220. The traffic management chip 210 includes a write-ahead unit 211, a queue management unit 212, and a read / write control unit 213. The read / write control unit 213 can include a write-side cache 2131 and a cache occupancy level adjustment unit 2132.

[0049] Among them, the write-ahead unit 211 is used to receive service data and can send the service data to the write-side cache 2131.

[0050] The queue management unit 212 is used to receive the adjusted cache occupancy level threshold sent by the cache occupancy level adjustment unit 2132 and manage the service data according to the adjusted cache occupancy level threshold. For example, it can be determined whether to discard the service data in the write-ahead unit 211 according to the adjusted cache occupancy level threshold.

[0051] The write-side cache 2131 is used to receive the service data sent by the write-ahead unit 211 and write the service data into the DDR cache 220.

[0052] The cache occupancy level adjustment unit 2132 is configured to receive the calibration notification sent by the DDR cache 220, and based on the predicted traffic of the cache occupancy of the write-side cache 2131 after receiving the calibration notification, adjust the threshold of the cache occupancy level, and send an adjustment indication including the adjusted threshold of the cache occupancy level to the queue management unit 212.

[0053] In some alternative embodiments, the traffic management chip 210 may also be replaced by a traffic management module.

[0054] Next, Figure 3 the cache management method provided by the embodiments of the present application will be described.

[0055] As Figure 3 shown in the flowchart of an embodiment of the cache management method provided by the present application, it specifically includes the following steps:

[0056] Step 301, in response to the start of the calibration task, the DDR cache sends a calibration notification to the traffic management chip. Correspondingly, the traffic management chip receives the calibration notification.

[0057] Specifically, due to the influence brought by testing or other reasons, the calibration task can be started for the DDR cache. Among them, the testing may include, but is not limited to, the Process Verification Test (PVT), and the purpose of calibration may include, but is not limited to, correcting the timing parameters.

[0058] Since the DDR cache cannot accept read / write access requests during the calibration period of the DDR cache, that is to say, during the calibration period of the DDR cache, the service data in the traffic management chip cannot be written into the DDR cache, which will cause the accumulation of the service data in the DDR cache. Therefore, in response to the start of the calibration task, the DDR cache can send a calibration notification to the traffic management chip.

[0059] Exemplarily, the DDR cache can send a calibration notification to the cache occupancy level adjustment unit in the traffic management chip. This calibration notification is used to notify the traffic management chip that the DDR cache is undergoing calibration, so that the traffic management chip can adjust the threshold of the cache occupancy level, thereby avoiding the discarding of service data due to the accumulation of service data.

[0060] Step 302, in response to the received calibration notification, the cache occupancy level adjustment unit increases the threshold of the cache occupancy level.

[0061] Specifically, in response to the received calibration notification, the cache occupancy level adjustment unit in the traffic management chip can increase the threshold of the cache occupancy level according to the write bandwidth of the DDR cache.

[0062] It can be understood that the value of the write bandwidth of the DDR cache can be understood as the promised value of the DDR cache, or the value of the write bandwidth of the DDR cache can be understood as the theoretical value of the DDR cache, or the value of the write bandwidth of the DDR cache can be understood as the value determined according to the product specifications of the DDR cache.

[0063] Exemplarily, the product specifications of the DDR cache may include, but are not limited to, the number of channels and the operating frequency. The corresponding write bandwidth can be calculated through the number of channels and the operating frequency.

[0064] It can be understood that after obtaining the write bandwidth of the DDR cache, the simulated write amount of the service data of the DDR cache can be calculated based on the write bandwidth.

[0065] In some alternative embodiments, the simulated write amount of the service data can be determined by the write bandwidth of the DDR cache and the calibration duration. Among them, the calibration duration can be the duration for the DDR cache to perform calibration. For example, the calibration duration can be 3 us. It can be understood that the value of the calibration duration is only for exemplary illustration, and the embodiments of the present application do not make special limitations on this.

[0066] Next, the simulated write amount of the above service data can be used as a compensation value to compensate the threshold of the cache occupancy level, that is, the threshold of the cache occupancy level is increased based on the simulated write amount of the service data. Thus, by means of compensation, the traffic of this part of the service data is simulated to have been written into the DDR cache, rather than accumulated in the traffic management chip, which can help avoid the discarding of service data.

[0067] Exemplarily, taking the cache occupancy level including 8 levels as an example, among them, the 8 cache occupancy levels are respectively wos0, wos1, wos2, wos3, wos4, wos5, wos6, wos7 and wos8, and the 8 cache occupancy levels have a level size. Assume that the 8 cache occupancy levels have the following level relationship: wos0 < wos1 < wos2 < wos3 < wos4 < wos5 < wos6 < wos7 < wos8.

[0068] It should be noted that the lower the cache occupancy level, the lower the probability of discarding service data; the higher the cache occupancy level, the higher the probability of discarding service data. Among them, the types of service data can include one or more, and different types of service data have different priorities.

[0069] For the case where one type of service data is included in a cache occupancy level, the probability of discarding this service data increases as the cache occupancy level increases.

[0070] For the case where multiple types of service data are included within a cache occupancy level, within the same cache occupancy level, for different types of service data, the discard probability of service data with a higher priority is lower, and the discard probability of service data with a lower priority is higher. Within different cache occupancy levels, for the same service data, the discard probability of this service data increases as the cache occupancy level increases.

[0071] Table 1 exemplarily shows the correspondence between the occupancy of service data in the write-side cache of the traffic management chip before adjustment and the cache occupancy level.

[0072] Table 1

[0073] Business data occupancy Cache occupancy level wcache_used<th1 wos0 th1 = <wcache_used < th2 wos1 th2 = <wcache_used < th3 wos2 th3 = <wcache_used < th4 wos3 th4 = <wcache_used < th5 wos4 th5 = <wcache_used < th6 wos5 th6 = <wcache_used < th7 wos6 th7 = <wcache_used < th8 wos7 th8 = <wcache_used wos8

[0074] Referring to Table 1, the eight values of th1, th2, th3, th4, th5, th6, th7, and th8 are the thresholds of the cache occupancy level, and wcache_used is the occupancy of service data in the write-side cache (i.e., wcache). When the occupancy of service data in the write-side cache is below th1, that is, wcache_used < th1, the cache occupancy level can be wos0. When the occupancy of service data in the write-side cache is between th1 and th2, that is, th1 <= wcache_used < th2, the cache occupancy level can be wos1. When the occupancy of service data in the write-side cache is between th2 and th3, that is, th2 <= wcache_used < th3, the cache occupancy level can be wos2. When the occupancy of service data in the write-side cache is between th3 and th4, that is, th3 <= wcache_used < th4, the cache occupancy level can be wos3. When the occupancy of service data in the write-side cache is between th4 and th5, that is, th4 <= wcache_used < th5, the cache occupancy level can be wos4. When the occupancy of service data in the write-side cache is between th5 and th6, that is, th5 <= wcache_used < th6, the cache occupancy level can be wos5. When the occupancy of service data in the write-side cache is between th6 and th7, that is, th6 <= wcache_used < th7, the cache occupancy level can be wos6. When the occupancy of service data in the write-side cache is between th7 and th8, that is, th7 <= wcache_used < th8, the cache occupancy level can be wos7. When the occupancy of service data in the write-side cache is above th8, that is, th8 <= wcache_used, the cache occupancy level can be wos8.

[0075] It can be seen that before adjusting the threshold of the cache occupancy level, there is a corresponding relationship between the cache occupancy level and the eight values of th1, th2, th3, th4, th5, th6, th7, and th8. However, after the DDR cache is calibrated, the service data in the write-side cache cannot be written into the DDR cache, which will cause the service data in the write-side cache to accumulate continuously, resulting in the continuous increase of the cache occupancy level, and then causing the queue management unit to continuously discard low-priority service data. Even after discarding all the low-priority service data, it will further discard high-priority service data, seriously affecting the operation of the service.

[0076] Table 2 exemplarily shows the corresponding relationship between the occupancy of service data in the write-side cache of the traffic management chip after adjustment and the cache occupancy level.

[0077] Table 2

[0078] Business data occupancy Cache occupancy level wcache_used<th1+th_adjust wos0 th1 + th_adjust = <wcache_used < th2 + th_adjust wos1 th2 + th_adjust = <wcache_used < th3 + th_adjust wos2 th3 + th_adjust = <wcache_used < th4 + th_adjust wos3 th4 + th_adjust = <wcache_used < th5 + th_adjust wos4 th5 + th_adjust = <wcache_used < th6 + th_adjust wos5 th6 + th_adjust = <wcache_used < th7 + th_adjust wos6 th7 + th_adjust = <wcache_used < th8 + th_adjust wos7 th8+th_adjust=<wcache_used wos8

[0079] Referring to Table 2, th_adjust is a compensation value determined according to the simulated write volume, and the simulated write volume is the traffic of service data predicted to accumulate in the write-side cache during the calibration of the DDR cache. The specific calculation method of the simulated write volume can refer to the relevant description in the above embodiments and will not be elaborated here.

[0080] As can be seen from Table 2, by compensating the threshold of the cache occupancy level, for example, increasing the value of the threshold of the cache occupancy level, it can be ensured that the cache occupancy level will not be increased in the case of the accumulation of service data in the write-side cache, thereby effectively avoiding the loss of service data caused by the increase of the cache occupancy level.

[0081] Taking the cache occupancy level wos0 as an example, before adjusting the threshold of the cache occupancy level, when the occupancy of service data in the write-side cache reaches th1, it will be upgraded from the cache occupancy level wos0 to wos1. Therefore, during the calibration of the DDR cache, due to the accumulation of service data in the write-side cache, it is very easy for the cache occupancy level wos0 to be upgraded to wos1, or even upgraded to wos2 or higher. Through the embodiments of the present application, that is, after adjusting the threshold of the cache occupancy level, th_adjust takes into account the accumulation volume of service data in the write-side cache during the calibration of the DDR cache. Therefore, during the calibration of the DDR cache, the cache occupancy level will not be increased, thereby effectively avoiding the discarding of service data.

[0082] In some alternative embodiments, since the ingress traffic may be greater than the write bandwidth during a certain period of time, in this case, after adjusting the threshold of the cache occupancy level, it will still cause an increase in the cache occupancy level. Therefore, after adjusting the threshold of the cache occupancy level, the occupancy of the service data in the write-side cache can be periodically detected.

[0083] Among them, the period for detecting the occupancy of the service data in the write-side cache can be determined according to the clock cycle. Exemplarily, assuming that a clock cycle is 1 ns, the period for detecting the occupancy of the service data in the write-side cache can be N clock cycles, that is, N ns, where N is a positive integer and N can be configured according to the actual application scenario.

[0084] If in any period, it is detected that the occupancy of the service data in the write-side cache is close to the current threshold of the cache occupancy level, the current threshold of the cache occupancy level can be increased by th_delta_up.

[0085] Table 3 exemplarily shows the correspondence between the adjustment value and the period.

[0086] Table 3

[0087] Period Adjustment value T1 th_delta_up T2 th_delta_up T3 th_delta_up

[0088] Referring to Table 3, taking the 3 periods of T1, T2, and T3 as examples, where T1 is the first period, T2 is the second period, and T3 is the third period. In the T1 period, if it is detected that the occupancy of the service data in the write-side cache is close to the current threshold of the cache occupancy level, the current threshold of the cache occupancy level can be increased by th_delta_up. Assuming the current threshold of the cache occupancy level is P0, and this P0 can be the threshold adjusted based on the simulated write volume, then the adjusted threshold of the cache occupancy level is P1 = P0 + th_delta_up. In the T2 period, if it is detected that the occupancy of the service data in the write-side cache is close to the current threshold of the cache occupancy level, the current threshold of the cache occupancy level can be increased by th_delta_up. Since the current threshold of the cache occupancy level is P1, the adjusted threshold of the cache occupancy level is P2 = P1 + th_delta_up. In the T3 period, if it is detected that the occupancy of the service data in the write-side cache is close to the current threshold of the cache occupancy level, the current threshold of the cache occupancy level can be increased by th_delta_up. Since the current threshold of the cache occupancy level is P2, the adjusted threshold of the cache occupancy level is P3 = P2 + th_delta_up. Among them, the value of th_delta_up can be configured according to the actual application scenario.

[0089] It is understandable that the above examples are only illustrative examples with 3 cycles, but do not constitute a limitation on the embodiments of the present application. In some embodiments, scenarios with more or less than 3 cycles may also be included.

[0090] It is understandable that, in order to avoid the threshold of the cache occupancy level from being infinitely increased, a maximum value of the threshold of the cache occupancy level can also be set, that is, when the adjusted threshold of the cache occupancy level is greater than the maximum value of the threshold of the cache occupancy level, the threshold of the cache occupancy level is maintained at the maximum value of the threshold of the cache occupancy level.

[0091] In some alternative embodiments, in order to avoid the overhead caused by frequent adjustments, the threshold of the cache occupancy level can also be directly adjusted to the maximum value of the threshold of the cache occupancy level.

[0092] Step 303, the cache occupancy level adjustment unit sends a first adjustment instruction to the queue management unit, and the first adjustment instruction includes the adjusted threshold of the cache occupancy level. Correspondingly, the queue management unit receives the first adjustment instruction.

[0093] Specifically, after the cache occupancy level adjustment unit increases the threshold of the cache occupancy level, it can send a first adjustment instruction to the queue management unit, where the first adjustment instruction is used to instruct the queue management unit to manage the service data based on the adjusted threshold of the cache occupancy level, and the first adjustment instruction includes the adjusted threshold of the cache occupancy level.

[0094] Step 304, in response to the received adjustment instruction, the queue management unit manages the service data based on the threshold of the cache occupancy level indicated in the adjustment instruction.

[0095] Specifically, since the threshold of the cache occupancy level indicated in the adjustment instruction is higher than the initial threshold of the cache occupancy level, it is possible to avoid the increase in the cache occupancy level caused by the accumulation of service data, and thus effectively avoid the queue management unit from discarding the service data.

[0096] In some alternative embodiments, after step 304, step 305 may further be included:

[0097] Step 305, in response to the end of the calibration task, the DDR cache sends a calibration end notification to the traffic management chip. Correspondingly, the traffic management chip receives the calibration end notification.

[0098] Specifically, after the calibration task of the DDR cache ends, a calibration end notification can be sent to the traffic management chip, and the calibration end notification is used to notify the traffic management chip that the calibration task of the DDR cache has ended, and the traffic management chip can write service data to the DDR cache.

[0099] Step 306, in response to the received calibration end notification, the cache occupancy level adjustment unit lowers the threshold of the current cache occupancy level.

[0100] Specifically, after receiving the calibration end notification, the threshold of the current cache occupancy level can be lowered so that the threshold of the current cache occupancy level returns to the initial value. Among them, the threshold of the current cache occupancy level can be understood as the threshold of the increased cache occupancy level.

[0101] It can be understood that when the write-side cache resumes writing data to the DDR cache, since the actual write bandwidth provided by the DDR cache is greater than the promised write bandwidth, and the normal ingress traffic is determined according to the promised write bandwidth of the DDR cache, that is, as the write-side cache continuously writes data to the DDR cache, the accumulated service data in the write-side cache will be gradually released. If the threshold of the cache occupancy level is still configured as the adjusted threshold, it will cause an error in the management strategy of the queue management unit for service data.

[0102] In some alternative embodiments, in order to avoid a sudden increase in the cache occupancy level caused by too rapid a decrease in the threshold of the cache occupancy level, resulting in the discarding of service data, the method of lowering the threshold of the cache occupancy level can be to gradually lower the threshold of the cache occupancy level.

[0103] Exemplarily, the threshold of the current cache occupancy level can be lowered periodically. Among them, the period of lowering the threshold of the cache occupancy level can be determined according to the clock cycle. For example, the period of lowering the threshold of the cache occupancy level can be M clock cycles, where M is a positive integer and M can be configured according to the actual application scenario.

[0104] Table 4 exemplarily shows the correspondence between the adjustment value and the period.

[0105] Period Adjustment value t1 th_delta_down t2 th_delta_down t3 th_delta_down

[0106] Referring to Table 4, taking three cycles of t1, t2, and t3 as examples, where t1 is the first cycle, t2 is the second cycle, and t3 is the third cycle. During the t1 cycle, the threshold of the current cache occupancy level can be decreased by th_delta_down. Assuming the threshold of the current cache occupancy level is Q0, the threshold of the cache occupancy level after the decrease is Q1 = Q0 - th_delta_down. During the T2 cycle, the threshold of the current cache occupancy level can be decreased by th_delta_down. Since the threshold of the current cache occupancy level is Q1, the threshold of the cache occupancy level after the decrease is Q2 = Q1 - th_delta_down. During the T3 cycle, the threshold of the current cache occupancy level can be decreased by th_delta_down. Since the threshold of the current cache occupancy level is Q2, the threshold of the cache occupancy level after the decrease is Q3 = Q2 - th_delta_down. If Q3 is the same as the threshold of the cache occupancy level in the initial configuration, that is, through the decrease, the threshold of the cache occupancy level is restored to the initial situation, the decrease of the threshold of the cache occupancy level can be ended. Among them, the value of th_delta_down can be configured according to the actual application scenario. For example, the value of th_delta_down can be determined according to the difference between the promised value and the actual value of the write bandwidth of the DDR cache.

[0107] It can be understood that the above examples are only for illustrative purposes with three cycles as examples, but do not constitute a limitation on the embodiments of the present application. In some embodiments, scenarios with more or fewer than three cycles may also be included.

[0108] Step 307, the cache occupancy level adjustment unit sends a second adjustment instruction to the queue management unit, and the second adjustment instruction includes the threshold of the cache occupancy level after the decrease. Correspondingly, the queue management unit receives the second adjustment instruction.

[0109] Specifically, after the cache occupancy level adjustment unit decreases the threshold of the cache occupancy level, it can send a second adjustment instruction to the queue management unit. Among them, the second adjustment instruction is used to instruct the queue management unit to manage the service data based on the threshold of the cache occupancy level after the decrease, and the second adjustment instruction includes the threshold of the cache occupancy level after the decrease.

[0110] Step 308, in response to the received second adjustment instruction, the queue management unit manages the service data based on the threshold of the cache occupancy level indicated in the second adjustment instruction.

[0111] Figure 4 This is a schematic structural diagram of an embodiment of the cache management device of the present application, as Figure 4As shown, the above cache management device 40 is applied to an electronic device, which includes a traffic management chip and a double data rate DDR cache. The cache management device 40 may include: a determination module 41 and an upward adjustment module 42; wherein,

[0112] The determination module 41 is configured to, in response to detecting the start of the calibration task of the DDR cache, determine an upward adjustment value of the cache occupancy level threshold by the traffic management chip;

[0113] The adjustment module 42 is configured to, based on the upward adjustment value of the cache occupancy level threshold, the traffic management chip upwardly adjusts the cache occupancy level threshold.

[0114] In one possible implementation, the determination module 41 is specifically configured to determine an upward adjustment value of the cache occupancy level threshold by the traffic management chip based on the write bandwidth of the DDR cache.

[0115] In one possible implementation, the adjustment module 42 is further configured to, by the traffic management chip, periodically detect the cache occupancy in the traffic management chip;

[0116] In any first period, if the cache occupancy in the traffic management chip is close to the threshold of the current cache occupancy level, the traffic management chip upwardly adjusts the threshold of the current cache occupancy level based on a first preset upward adjustment value.

[0117] In one possible implementation, the upward adjustment value of the cache occupancy level threshold is a second preset upward adjustment value, and the cache occupancy level threshold after being upwardly adjusted based on the second preset upward adjustment value is the maximum value of the cache occupancy level threshold.

[0118] In one possible implementation, the adjustment module 42 is further configured to, in response to detecting the end of the calibration task of the DDR cache, determine a downward adjustment value of the cache occupancy level threshold by the traffic management chip;

[0119] The traffic management chip downwardly adjusts the current cache occupancy level threshold based on the downward adjustment value of the cache occupancy level threshold.

[0120] In one possible implementation, the downward adjustment value of the cache occupancy level threshold is a preset downward adjustment value, and the downward adjustment module is specifically configured to, in any second period, the traffic management chip downwardly adjusts the current cache occupancy level threshold based on the preset downward adjustment value.

[0121] Figure 4 The cache management device 40 provided in the shown embodiment can be used to execute the technical solution of the method embodiment shown in the present application, and its implementation principle and technical effects can be further referred to the relevant descriptions in the method embodiment.

[0122] It should be understood that the above Figure 4 division of each module of the cache management device 40 shown is only a division of logical functions. In actual implementation, it can be fully or partially integrated into a physical entity, or physically separated. And these modules can all be implemented in the form of software called by processing elements; they can also all be implemented in the form of hardware; or some modules can be implemented in the form of software called by processing elements and some modules can be implemented in the form of hardware. For example, the detection module can be a separately established processing element, or can be integrated in a certain chip of the electronic device. The implementation of other modules is similar. In addition, all or part of these modules can be integrated together or can be independently implemented. In the implementation process, each step of the above method or each of the above modules can be completed by the integrated logic circuit in the processor element or the instructions in the form of software.

[0123] For example, the above-mentioned modules can be one or more integrated circuits configured to implement the above method, such as: one or more application specific integrated circuits (ASIC for short), or, one or more digital signal processors (DSP for short), or, one or more field programmable gate arrays (FPGA for short), etc. Again, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC for short).

[0124] In each of the above embodiments, the processor involved can include, for example, a CPU, a DSP, a microcontroller or a digital signal processor, and can also include a GPU, an embedded neural-network processor (NPU for short), and an image signal processor (ISP for short). The processor can also include necessary hardware accelerators or logic processing hardware circuits, such as an ASIC, or one or more integrated circuits for controlling the execution of the technical solution program of the present application. In addition, the processor can have the function of operating one or more software programs, and the software programs can be stored in a storage medium.

[0125] The embodiment of the present application also provides a readable storage medium, in which a program is stored. When it runs on an electronic device, it causes the electronic device to execute the method provided by the embodiment shown in the present application.

[0126] An embodiment of this application also provides a program product, which includes a program that, when running on an electronic device, enables the electronic device to execute the method provided by the embodiments shown in this application.

[0127] In the embodiments of this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent the cases where A exists alone, A and B exist simultaneously, and B exists alone. Here, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one of the following" and its similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, and c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0128] Those of ordinary skill in the art can realize that the various units and algorithm steps described in the embodiments disclosed herein can be implemented by a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0129] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0130] In several embodiments provided by this application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (hereinafter referred to as ROM), random access memories (hereinafter referred to as RAM), magnetic disks, or optical discs that can store program codes.

[0131] The above are only specific embodiments of the present application. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A cache management method, characterized in that, Applied to an electronic device, the electronic device includes a traffic management chip and a double data rate (DDR) cache, and the method includes: In response to detecting the start of a calibration task for the DDR cache, the traffic management chip determines an upward adjustment value of the cache occupancy level threshold; The traffic management chip adjusts upward the cache occupancy level threshold based on the upward adjustment value of the cache occupancy level threshold.

2. The method according to claim 1, wherein The traffic management chip determining the upward adjustment value of the cache occupancy level threshold includes: The traffic management chip determines the upward adjustment value of the cache occupancy level threshold based on the write bandwidth of the DDR cache.

3. The method according to claim 2, wherein After the traffic management chip adjusts upward the cache occupancy level threshold based on the upward adjustment value of the cache occupancy level threshold, the method further includes: The traffic management chip periodically detects the cache occupancy in the traffic management chip; In any first period, if the cache occupancy in the traffic management chip is close to the threshold of the current cache occupancy level, the traffic management chip adjusts upward the threshold of the current cache occupancy level based on a first preset upward adjustment value.

4. The method according to claim 1, wherein The upward adjustment value of the cache occupancy level threshold is a second preset upward adjustment value, and the cache occupancy level threshold after being adjusted upward based on the second preset upward adjustment value is the maximum value of the cache occupancy level threshold.

5. The method according to any one of claims 1 to 4, characterized in that The method further includes: In response to detecting the end of the calibration task for the DDR cache, the traffic management chip determines a downward adjustment value of the cache occupancy level threshold; The traffic management chip adjusts downward the current cache occupancy level threshold based on the downward adjustment value of the cache occupancy level threshold.

6. The method according to claim 5, wherein The downward adjustment value of the cache occupancy level threshold is a preset downward adjustment value, and the traffic management chip adjusting downward the cache occupancy level threshold that has been adjusted upward based on the downward adjustment value of the cache occupancy level threshold includes: In any second period, the traffic management chip adjusts downward the current cache occupancy level threshold based on the preset downward adjustment value.

7. An electronic device, characterized in that, Includes: A processor and a memory, the memory is used to store a program; the processor is used to run the program to implement the cache management method according to any one of claims 1-6.

8. A readable storage medium, characterized in that, The readable storage medium stores a program, and when the program runs on an electronic device, it implements the cache management method according to any one of claims 1-6.

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