A method, system, device, and medium for multi-level page table walk acceleration

Abstract

The application provides a multi-level page table traversal acceleration method, system, device and medium, and belongs to the technical field of computers. The method comprises the following steps: inputting a virtual address into a path predictor and a dynamic weight hierarchical cache, and collecting an instruction access proportion, a TLB hit rate and a prefetch success rate in real time; performing hash calculation on the virtual address according to a preset bit of the virtual address by the path predictor, querying a history record table to obtain a predicted path and a confidence level, so as to determine a query range; when the cache hits, the score of the hit entry is calculated, the priority of the cache entry is sorted and the elimination decision is made, and a hybrid replacement algorithm is used to manage the cache entry; under a preset condition, a prefetch operation is started by an adaptive prefetch engine, the prefetch step is calculated and dynamically expanded, and memory bandwidth contention is prevented through two-level monitoring; when the instruction access proportion, the TLB hit rate and the prefetch success rate meet the conditions, an instruction priority mode is activated, the score of the hit entry is updated by adjusting the related calculation parameters.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, and more specifically relates to a method, system, device and medium for accelerating multi-level page table traversal. Background Technology

[0002] In modern processor architectures, multi-level page table mechanisms are the core technology for translating virtual addresses to physical addresses. With the improvement of processor performance and the expansion of memory space, the efficiency of page table traversal directly affects the overall system performance. However, traditional multi-level page table traversal schemes have the following significant technical drawbacks:

[0003] First, inefficient caching hinders address translation performance. Existing TLBs (Translation Lookaside Buffers) generally employ fixed replacement strategies (such as the LRU algorithm), failing to consider the actual differences in benefits between page table entries at different levels. For example, in a four-level page table structure, a hit on an L3-level page table entry can directly skip queries at L2 and L1 levels, resulting in a benefit three times greater than a hit on an L1-level entry. However, the traditional LRU algorithm only uses access time as the replacement criterion, failing to quantify the benefit differences between different levels, leading to frequent eviction of high-value page table entries. This "lack of awareness of level-based benefits" makes it difficult for TLB hit rates to overcome bottlenecks, especially in deep page table scenarios where performance degradation is significant.

[0004] Secondly, the locality of failure in the prefetching mechanism leads to a sharp drop in efficiency for cross-level access. Due to the tree-like nature of page table structures, page table entries corresponding to consecutive virtual addresses are sparsely distributed in physical memory, rather than stored linearly and contiguously. Existing linear prefetching mechanisms (such as fixed-step prefetching) cannot adapt to the branching characteristics of the tree structure during cross-level access, resulting in a prefetch hit rate drop of more than 40%. For example, when the page table traversal path jumps from PUD (second-level page table) to PTE (fourth-level page table), the page table entries prefetched linearly are misaligned with the actual access path, causing wasted memory bandwidth and additional latency.

[0005] Furthermore, resource contention between instruction pages and data pages creates a performance degradation cycle. When instruction page entries and data page entries share the STLB (Secondary TLB), high-frequency instruction access continuously consumes the cache space of data page entries. Traditional solutions lack differentiated management for page types, leading to frequent invalidation of data page entries, which in turn triggers page table lookups during data access; the missing data page entries further exacerbate TLB conflicts, forming a vicious cycle of "cache contention - exacerbated invalidation." Especially in instruction-intensive workloads, this problem can increase data access latency by more than 30%.

[0006] The essence of the above problem lies in the fact that existing page table traversal schemes optimize cache management, prefetching strategies, and page type control in a fragmented manner, lacking a cross-level collaborative management mechanism. Each module operates independently and cannot dynamically link based on page table hierarchy characteristics, access patterns, and resource status, thus limiting system-level performance optimization. Summary of the Invention

[0007] To address the above problems, the present invention aims to provide a method, system, device, and medium for accelerating multi-level page table traversal. Through path prediction, dynamic cache hierarchy, adaptive prefetching, and instruction priority parameter tuning, it achieves accelerated page table traversal, improved cache hit rate, and optimized memory bandwidth.

[0008] To achieve the above objectives, the present invention employs the following technical solution:

[0009] In a first aspect, embodiments of this application provide a method for accelerating multi-level page table traversal, including:

[0010] The virtual addresses are input into the path predictor and the dynamic weighted hierarchical cache respectively, and the instruction access ratio, TLB hit rate and prefetch success rate are collected in real time.

[0011] The path predictor performs hash calculations based on preset bits of the virtual address, queries the historical record table to obtain the predicted path and confidence level, and determines the query range based on the confidence level through dynamic weighted hierarchical caching.

[0012] When a cache hit occurs, the score of the hit entry is calculated using a comprehensive scoring formula. Based on the score, the cache entries are prioritized and eviction decisions are made. At the same time, a hybrid replacement algorithm is used to manage the cache entries.

[0013] When the preset trigger conditions are met, the prefetching operation is started through the adaptive prefetching engine. The prefetching step size is dynamically expanded using Q4.12 fixed-point number calculation, and memory bandwidth contention is prevented through two-level monitoring.

[0014] When the instruction access rate, TLB hit rate, and prefetch success rate meet the preset conditions, the instruction priority mode is activated, and the score of the hit item is updated by adjusting the relevant parameters of the comprehensive scoring formula.

[0015] In an optional implementation, the step of inputting virtual addresses into the path predictor and the dynamic weighted hierarchical cache respectively, and collecting instruction access ratio, TLB hit rate and prefetch success rate in real time, includes:

[0016] Input the virtual addresses VA[47:0] into the path predictor and the dynamic weighted hierarchical cache, respectively;

[0017] A 32-bit sliding window counter is used in real time to detect the instruction access ratio. When the CPU executes an instruction, the counter value counter is incremented by 1; when the CPU accesses data, the counter value counter is decremented by 1. The instruction access ratio InstrRatio is calculated in real time using the formula InstrRatio=(counter+32768) / 65536.0.

[0018] The TLB hit rate is calculated by reading the number of TLB hits and misses recorded in the hardware performance counter.

[0019] Read the number of prefetch hits and misses recorded in the hardware performance counters and calculate the prefetch success rate;

[0020] The collected instruction access percentage, TLB hit rate, and prefetch success rate are broadcast every cycle via a 32-bit status bus. In the 32-bit status bus, bit segment [7:0] represents the operating mode code, bit segment [15:8] represents the instruction percentage, bit segment [23:16] represents the prefetch success rate, and bit segment [31:24] represents the TLB hit rate.

[0021] In an optional implementation, the step of using a path predictor to perform hash calculations based on preset bits of the virtual address, querying a historical record table to obtain the predicted path and confidence level, and determining the query range based on the confidence level through a dynamic weighted hierarchical cache includes:

[0022] The path predictor performs hash calculation based on the virtual address VA[47:39] and queries the historical record table to obtain the predicted path and the path prediction confidence Z;

[0023] The confidence level is determined based on the path prediction confidence level Z; when Z ≥ 6, it is high confidence; when 5 < Z < 6, it is medium confidence; and when Z ≤ 5, it is low confidence.

[0024] The page table level for the query is determined based on the confidence level; the page table adopts a four-level page table of PGD, PUD, PMD, and PTE.

[0025] When the confidence level is high, only the prediction level ±1 range is queried; when the confidence level is low, parallel queries are performed across all levels.

[0026] In an optional implementation, when a cache hit occurs, a score is calculated using a comprehensive scoring formula for the hit entry. Based on the score, cache entries are prioritized and evicted. Simultaneously, a hybrid replacement algorithm is used to manage cache entries, including:

[0027] When a cache hit occurs, the score for the hit entry is calculated using the comprehensive scoring formula: Score = α • LevelWeight + β • TypeBoost - γ • Δt. Here, α is the scaling factor for path prediction confidence, LevelWeight is the weight of the page table level where the cache entry resides, β is the type gain coefficient for instruction access ratio, TypeBoost is the type gain of the cache entry, γ is the time decay factor related to prefetch hit rate, and Δt is the access interval of the cache entry. If the cache entry is at the PGD layer, LevelWeight = 4; if it's at the PUD layer, LevelWeight = 3; if it's at the PMD layer, LevelWeight = 2; and if it's at the PTE layer, LevelWeight = 1.

[0028] Based on the score of the hit item, determine the cache priority of the item and cache it.

[0029] When the number of free entries in the current cache is greater than or equal to 10% of the total number of entries, the cache entries are classified into four levels: PGD, PUD, PMD, and PTE. Two candidate entries are randomly selected from each level for replacement.

[0030] When the number of free entries in the current cache is less than 10% of the total number of entries, entries with a score < 2 are evicted.

[0031] For entries that are hit 3 times consecutively, lock them in the cache for 200 cycles.

[0032] In an optional implementation, when a preset trigger condition is met, the prefetching operation is initiated through an adaptive prefetching engine, using Q4.12 fixed-point number calculation and dynamically expanding the prefetching step size, while preventing memory bandwidth contention through two-level monitoring, including:

[0033] If the current PTE level entries have been loaded, the remaining space in the dynamic cache is greater than 20% of the total cache space, and Z≥5, the prefetch operation is started through the adaptive prefetch engine;

[0034] The step size is updated every 100 cycles. The initial step size is ±2 pages. The step size value stride is calculated and updated based on the real-time item hit rate using the step size calculation formula, and the step size is dynamically expanded.

[0035] The L1D-Cache miss rate Q is sampled every 50 cycles. When Q > 15% for a cumulative total of 3 times, the prefetch operation is turned off for 200 cycles.

[0036] In an optional implementation, the step size calculation formula is:

[0037]

[0038] in, This represents the item hit rate.

[0039] In an optional implementation, the step of activating the instruction priority mode when the instruction access ratio, TLB hit rate, and prefetch success rate meet preset conditions, and updating the score of the hit item by adjusting the relevant parameters of the comprehensive scoring formula, includes:

[0040] Real-time monitoring command access ratio (InstrRatio);

[0041] When InstrRatio > 60%, TLB hit rate < 85%, and prefetch success rate > 40%, activate instruction priority mode, increase TypeBoost to 1.2 times the current level, force the β value to 0.1, and update the score of the entry.

[0042] The type gain coefficient β of the instruction access ratio is dynamically adjusted in real time according to the formula β=max(0, min(0.5, 0.2 + 0.5•(InstrRatio - 0.6))), and the score of the entry is updated.

[0043] Secondly, embodiments of this application also provide a multi-level page table traversal acceleration system, including:

[0044] The address input and status monitoring module is used to input virtual addresses into the path predictor and the dynamic weighted hierarchical cache respectively, and to collect the instruction access ratio, TLB hit rate and prefetch success rate in real time.

[0045] The path prediction and query planning module is used to perform hash calculations based on preset bits of the virtual address using a path predictor, query the historical record table to obtain the predicted path and confidence level, and determine the query range based on the confidence level through dynamic weighted hierarchical caching.

[0046] Weighted evaluation and cache management are used to calculate the score of the hit entry using a comprehensive scoring formula when the cache is hit. Based on the score, the cache entries are prioritized and eviction decisions are made. At the same time, a hybrid replacement algorithm is used to manage the cache entries.

[0047] The prefetch strategy adjustment module is used to start the prefetch operation through the adaptive prefetch engine when the preset trigger conditions are met. It uses Q4.12 fixed-point number calculation and dynamically expands the prefetch step size, while preventing memory bandwidth contention through two-level monitoring.

[0048] The mode switching and parameter adjustment module is used to activate the instruction priority mode when the instruction access ratio, TLB hit rate and prefetch success rate meet preset conditions. It updates the score of the hit item by adjusting the relevant parameters of the comprehensive scoring formula.

[0049] Thirdly, embodiments of this application also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the multi-level page table traversal acceleration method as described in any of the above.

[0050] Fourthly, embodiments of this application also provide a storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the multi-level page table traversal acceleration method described in any of the above claims.

[0051] As can be seen from the above technical solutions, the present invention has the following advantages:

[0052] The multi-level page table traversal acceleration method provided in this application achieves efficient optimization of page table traversal through the collaborative work of a path predictor and a dynamic weighted hierarchical cache, combined with real-time collected dynamic indicators such as instruction access ratio, TLB hit rate, and prefetch success rate. The path predictor calculates predicted paths based on virtual address bit hashing and queries hierarchically according to confidence level. At high confidence, the query range is narrowed to reduce time consumption, while at low confidence, parallel queries across all levels ensure accuracy. The dynamic weighted hierarchical cache, through a comprehensive scoring formula (integrating hierarchical weights, type gain, and time decay) and a hybrid replacement algorithm, prioritizes the retention of higher-level page tables and frequently accessed entries, improving cache utilization. The adaptive prefetch engine initiates prefetching based on PTE loading status, remaining cache space, and prediction confidence. It dynamically adjusts the step size using Q4.12 fixed-point numbers to match the hit rate and monitors L1D-Cache miss rate to prevent memory bandwidth contention, thus improving prefetch efficiency. When the instruction access ratio is high and the TLB hit rate is low, an instruction priority mode is activated, adjusting scoring parameters to increase the priority of instruction-related page table entries and reduce instruction access latency. The overall solution effectively improves TLB hit rate, reduces page table traversal latency, optimizes memory bandwidth allocation, and significantly improves system performance in instruction-intensive scenarios.

[0053] This application uses a path predictor to perform hash calculations on virtual addresses, achieving accurate prediction of access paths and dynamically adjusting the query range based on the confidence level. At high confidence, it focuses on the prediction level ±1 range; at low confidence, it performs parallel queries across all levels, significantly reducing invalid traversals and improving query efficiency.

[0054] This application implements intelligent sorting and eviction of cached entries based on a comprehensive scoring formula. By combining multiple factors such as page table hierarchy weight, instruction access ratio, and time decay, high-value entries are prioritized for retention, thereby improving cache hit rate and reducing memory access latency.

[0055] This application uses a prefetch engine to dynamically trigger prefetching based on PTE loading status, cache space, and prediction confidence. It employs the Q4.12 fixed-point algorithm to dynamically expand the prefetch step size and intelligently adjusts the prefetch switch by monitoring the L1D-Cache miss rate, thereby improving the prefetch hit rate while avoiding memory bandwidth contention.

[0056] This application monitors instruction access percentage, TLB hit rate, and prefetch success rate in real time, activating an instruction priority mode when specific conditions are met. By increasing the TypeBoost value of instruction-related entries and adjusting the β parameter, it ensures that page table entries for critical instructions are cached preferentially, significantly reducing instruction execution latency and improving CPU utilization.

[0057] This application implements periodic broadcasting of performance indicators through a 32-bit state bus, and combines it with hardware performance counters to collect key data such as TLB hits and prefetch success rates in real time, forming a deep collaboration between software algorithms and hardware architecture, giving full play to the efficiency of hardware resources, and achieving system-level performance optimization. Attached Figure Description

[0058] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 A flowchart illustrating the method for accelerating multi-level page table traversal provided in this application.

[0060] Figure 2 A flowchart illustrating another method for accelerating multi-level page table traversal provided in this application.

[0061] Figure 3 A flowchart illustrating the multi-level path prediction generation method provided in this application.

[0062] Figure 4 A flowchart illustrating the dynamic weighted hierarchical cache management method provided in this application.

[0063] Figure 5 This is a flowchart illustrating the cross-level adaptive prefetch control method provided in this application.

[0064] Figure 6A flowchart illustrating the system status monitoring and mode switching method provided in this application.

[0065] Figure 7 A schematic diagram of the structure of the multi-level page table traversal acceleration system provided in this application.

[0066] Figure 8 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0067] The various embodiments of this disclosure will be described more fully in the detailed steps of the multi-level page table traversal acceleration method described below. This disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of this disclosure to the specific embodiments disclosed herein, but rather this disclosure should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of this disclosure.

[0068] In the following, the terms “comprising” or “may include”, which may be used in various embodiments of this disclosure, indicate the presence of the disclosed functions, operations, or elements, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in various embodiments of this disclosure, the terms “comprising,” “having,” and their cognates are intended only to indicate a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or the possibility of adding one or more combinations of the foregoing.

[0069] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] Please see Figure 1 The diagram shows a flowchart of a method for accelerating multi-level page table traversal in a specific embodiment. The method includes:

[0071] S1: Input the virtual address into the path predictor and the dynamic weighted hierarchical cache respectively, and collect the instruction access ratio, TLB hit rate and prefetch success rate in real time.

[0072] In a specific implementation, the virtual address VA[47:0] is first input into the path predictor and the dynamic weighted hierarchical cache, respectively.

[0073] Meanwhile, a 32-bit sliding window counter is used in real time to detect the instruction access ratio. When the CPU executes an instruction, the counter value counter is incremented by 1; when the CPU accesses data, the counter value counter is decremented by 1. The instruction access ratio InstrRatio is calculated in real time using the formula InstrRatio=(counter+32768) / 65536.0 to achieve accurate monitoring of the ratio of instruction and data access.

[0074] The TLB hit rate is calculated by reading the number of TLB hits and misses recorded in the hardware performance counter.

[0075] Read the number of prefetch hits and misses recorded in the hardware performance counters and calculate the prefetch success rate;

[0076] The collected instruction access percentage, TLB hit rate, and prefetch success rate are broadcast every cycle via a 32-bit status bus. The status bus broadcasts every cycle via a 32-bit status bus, where [7:0] represents the operating mode code, [15:8] represents the instruction percentage, [23:16] represents the prefetch success rate, and [31:24] represents the TLB hit rate, in order to achieve status information sharing and collaborative work among modules.

[0077] S2: The path predictor performs hash calculations based on preset bits of the virtual address, queries the historical record table to obtain the predicted path and confidence level; and determines the query range based on the confidence level through dynamic weighted hierarchical caching.

[0078] In a specific implementation, firstly, the path predictor performs a hash calculation based on the virtual address VA[47:39], queries the historical record table to obtain the predicted path and the path prediction confidence level Z. For example, the path predictor uses a historical record table with a 4-way grouped association structure. After each page table traversal, the confidence value of the corresponding path is updated, incremented by 3 when a hit occurs and decremented by 5 when a miss occurs. A CRC8 hash calculation is performed on VA[47:39] to obtain the index, and the confidence level is output.

[0079] Then, the confidence level is determined based on the path prediction confidence level Z; when Z≥6, it is high confidence; when 5<Z<6, it is medium confidence; when Z≤5, it is low confidence.

[0080] The page table level for the query is determined based on the confidence level; the page table adopts a four-level page table of PGD, PUD, PMD, and PTE, that is, a four-level page table using the x86 architecture (PGD→PUD→PMD→PTE).

[0081] When the confidence level is high, only the prediction level ±1 range is queried; when the confidence level is low, parallel queries are performed across all levels.

[0082] S3: When a cache hit occurs, the score of the hit entry is calculated using a comprehensive scoring formula. Based on the score, the cache entries are prioritized and eviction decisions are made. At the same time, a hybrid replacement algorithm is used to manage the cache entries.

[0083] In a specific implementation, when a cache hit occurs, the score of the hit entry is calculated using the comprehensive scoring formula: Score = α • LevelWeight + β • TypeBoost - γ • Δt. Here, α is the scaling factor for path prediction confidence, LevelWeight is the weight of the page table level where the cache entry resides, β is the type gain coefficient for instruction access ratio, TypeBoost is the type gain of the cache entry, γ is the time decay factor related to prefetch hit rate, and Δt is the access time interval of the cache entry. If the cache entry is in the PGD layer, LevelWeight = 4; if the cache entry is in the PUD layer, LevelWeight = 3; if the cache entry is in the PMD layer, LevelWeight = 2; and if the cache entry is in the PTE layer, LevelWeight = 1.

[0084] It should be noted that the initial weight of the dynamic weighted hierarchical cache can be flexibly configured according to the actual page table hierarchy and application scenario. At the same time, in the cumulative mode of actual revenue calculation, the weight accumulation rules of each level are applicable to page table systems with different hierarchical structures.

[0085] Therefore, the dynamic weighted hierarchical caching adopts a multi-dimensional scoring model, which includes three dimensions: hierarchical weight, type gain, and time decay. The hierarchical weight is initially set to L4=4, L3=3, L2=2, and L1=1. The actual benefit calculation adopts an cumulative mode. For example, when L3 hits, the total weight = L3+L2+L1=6. The type gain is the type gain coefficient β based on the instruction access ratio. The time decay uses a 48-bit high-precision timer to calculate the access time interval Δt of the cache entry. In the comprehensive scoring formula, α is dynamically scaled by the path prediction confidence, β is calculated in real time by the monitoring module for the instruction ratio, and γ changes dynamically with the prefetch hit rate.

[0086] After the calculation is completed, the cache priority of the entries is determined and cached based on the score of the hit entries;

[0087] When the number of free entries in the current cache is greater than or equal to 10% of the total number of entries, the cache entries are classified into four levels: PGD, PUD, PMD, and PTE. Two candidate entries are randomly selected from each level for replacement.

[0088] When the number of free entries in the current cache is less than 10% of the total number of entries, entries with a score < 2 are evicted.

[0089] For entries that are hit 3 times consecutively, lock them in the cache for 200 cycles.

[0090] S4: When the preset trigger conditions are met, the prefetch operation is started through the adaptive prefetch engine. The prefetch step size is dynamically expanded using Q4.12 fixed-point number calculation, and memory bandwidth contention is prevented through two-level monitoring.

[0091] In a specific implementation, the preset triggering conditions are that the entries at the current PTE level have been loaded, the remaining space in the dynamic cache is greater than 20% of the total cache space, and Z≥5. If these conditions are met, the prefetching operation is initiated through the adaptive prefetching engine.

[0092] After startup, the step size is updated every 100 cycles, with an initial step size of ±2 pages. The step size is calculated based on the real-time item hit rate using the step size calculation formula. Calculate and update the stride value to dynamically expand the stride; at the same time, sample the L1D-Cache miss rate Q every 50 cycles, and when Q>15% for a cumulative 3 times, disable the prefetch operation for 200 cycles.

[0093] It should be noted that the step size calculation formula in the dynamic step size adjustment can be adaptively adjusted according to different hardware architectures and performance requirements, but the dynamic expansion method of the step size needs to be determined based on the logarithmic analysis of recent hit rates to ensure the effectiveness and adaptability of the prefetch operation.

[0094] S5: When the instruction access ratio, TLB hit rate and prefetch success rate meet the preset conditions, the instruction priority mode is activated, and the score of the hit item is updated by adjusting the relevant parameters of the comprehensive scoring formula.

[0095] In a specific implementation, the real-time detection command access ratio is InstrRatio.

[0096] When InstrRatio > 60%, TLB hit rate < 85%, and prefetch success rate > 40%, the instruction priority mode is activated, TypeBoost is increased to 1.2 times the current level, the β value is forcibly set to 0.1, and the score of the entry is updated. At the same time, the type gain coefficient β of the instruction access ratio is dynamically adjusted in real time according to the formula β = max(0, min(0.5, 0.2 + 0.5•(InstrRatio - 0.6))), and the score of the entry is updated.

[0097] In this embodiment, a path predictor performs hash calculations on virtual addresses and combines historical records to predict access paths. A dynamic weighted hierarchical cache adjusts the query range according to the confidence level. A comprehensive scoring formula integrates hierarchical weights, instruction type gains, and time decay factors to optimize cache priority. An adaptive prefetch engine uses the Q4.12 fixed-point algorithm to dynamically expand the prefetch step size and monitor the cache miss rate. An instruction priority mode adjusts the scoring parameters according to real-time performance indicators. This achieves significant optimization of system performance in instruction-intensive scenarios, including reduced page table traversal latency, improved TLB hit rate, efficient memory bandwidth utilization, and improved system performance.

[0098] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process in this embodiment, another method for accelerating multi-level page table traversal is provided. This method takes a four-level page table (PGD→PUD→PMD→PTE) of x86 architecture as an example, and is also applicable to page table systems with other hierarchical structures.

[0099] like Figure 2 As shown, the method works collaboratively in the following steps:

[0100] Address input phase: Virtual address VA[47:0] is simultaneously input to the path predictor and dynamic weighted hierarchical cache. The monitoring module collects the command / data access ratio in real time.

[0101] Parallel prediction phase: The path predictor queries the historical record table based on the VA[47:39] hash value and outputs the predicted path (e.g., PUD→PTE direct path) and confidence level (high / medium / low). Dynamic weighted hierarchical caching selects the query range based on the confidence level: high confidence (≥6), only the prediction level ±1 range is queried (e.g., if predicting PUD, then PUD+PMD is queried); low confidence (≤5), all levels are queried in parallel.

[0102] Weighting phase: When a cache hit occurs, the scoring module calculates the Score value of the hit entry according to the formula:

[0103] Score = α • LevelWeight + β • TypeBoost -γ • Δt

[0104] LevelWeight uses register preset values ​​(extended to PGD=4, PUD=3, PMD=2, PTE=1 in a four-level page table scenario).

[0105] Prefetching adjustment phase: The prefetching engine operates dynamically based on the following conditions:

[0106] Triggering conditions: PTE loading is complete, and the remaining cache space is >20%, and the prediction confidence is ≥5;

[0107] Step size calculation: (Implemented using Q4.12 fixed-point numbers).

[0108] Conflict monitoring phase: When the L1D-Cache miss rate is >15% for 3 consecutive times, the prefetch function is disabled for 200 cycles.

[0109] In one embodiment of the present invention, based on step S2, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0110] refer to Figure 3 As shown in the figure, this embodiment discloses a multi-level path prediction generation method, including: historical table updating and prediction generation.

[0111] The history table updates use a 4-way grouped association structure. After each page table traversal, the confidence value of the corresponding path is updated: +3 if a hit occurs, -5 if a miss occurs. Each entry contains the following:

[0112] struct {

[0113] uint8_tva_tag[5]; / / VA[47:43] hash value

[0114] uint16_t path_bits; / / Success path bitmap (bit0: PGD, bit1: PUD, ...

[0115] uint8_tconfidence; / / Confidence counter (0-15)

[0116] }

[0117] The prediction is generated by performing a CRC8 hash calculation on VA[47:39] to obtain the index and outputting the confidence level. The relevant commands are as follows:

[0118] if(confidence>= 12) return HIGH;

[0119] else if(confidence>= 6) return MEDIUM;

[0120] else return LOW;

[0121] In one embodiment of the present invention, based on step S3, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0122] refer to Figure 4 As shown, this embodiment discloses a dynamic weighted hierarchical cache management method, including: entry replacement decision, high-frequency protection mechanism and instruction priority mode.

[0123] Item replacement decision: When the number of idle items is ≥10%, the items are divided into four buckets (PGD / PUD / PMD / PTE), and two candidate items are randomly sampled from each bucket; when the number of idle items is <10%, the score threshold filter is activated, and items with a score <2.0 are eliminated first.

[0124] High-frequency protection mechanism: For entries that are hit 3 times consecutively, a 200-cycle lock flag is set (lock_bit=1), and the Score value is weighted by 1.5 during the lock period.

[0125] Command Priority Mode: When the monitoring module detects that InstrRatio > 60%, the TypeBoost coefficient on the command page is increased to 1.2 times, and the β value on the data page is forcibly set to 0.1.

[0126] In one embodiment of the present invention, based on step S4, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0127] refer to Figure 5 As shown in the figure, this embodiment discloses a cross-level adaptive prefetch control method, including dynamic step size adjustment and conflict detection.

[0128] Dynamic step size adjustment, updating the step size value every 100 cycles, is implemented in hardware using a shifter to calculate 2. n The specific commands are as follows:

[0129] always_comb begin

[0130] hit_log = (hit_rate>0) ? $clog2(hit_rate*100) : 0;

[0131] stride = 1<<(hit_log[3:0]&4'b0011); / / Limit the maximum stride size to 8

[0132] end

[0133] Conflict detection includes short-term detection and long-term regulation. Short-term detection refers to sampling the L1D-Cache Miss event counter every 50 cycles, while long-term regulation refers to switching the prefetch engine to a low-power mode (maintaining only ±1 page prefetch) after accumulating 3 high misses.

[0134] In one embodiment of the present invention, based on step S5, a possible embodiment will be given below, and its specific implementation will be described in a non-limiting manner.

[0135] refer to Figure 6 As shown, this embodiment discloses a system status monitoring and mode switching method, including instruction percentage detection, mode switching decision and status bus transmission.

[0136] Instruction ratio detection uses a 32-bit sliding window counter: incremented by 1 for each instruction access and decremented by 1 for each data access. The real-time calculation is InstrRatio = (counter + 32768) / 65536.0.

[0137] The mode switching decision refers to activating the instruction priority mode when multiple conditions are met simultaneously: InstrRatio>60%, TLB hit rate<85%, and prefetch success rate>40%.

[0138] The status bus is transmitted and broadcast every cycle via a 32-bit status bus, where [7:0] represents the running mode code, [15:8] represents the instruction percentage, [23:16] represents the prefetch success rate, and [31:24] represents the TLB hit rate.

[0139] like Figure 7 As shown, the following are embodiments of the multi-level page table traversal acceleration system provided in this disclosure. This system and the multi-level page table traversal acceleration methods in the above embodiments belong to the same inventive concept. For details not described in detail in the embodiments of the multi-level page table traversal acceleration system, please refer to the embodiments of the multi-level page table traversal acceleration methods described above.

[0140] A multi-level page table traversal acceleration system includes:

[0141] The address input and status monitoring module is used to input virtual addresses into the path predictor and the dynamic weighted hierarchical cache respectively, and to collect the instruction access ratio, TLB hit rate and prefetch success rate in real time.

[0142] The path prediction and query planning module is used to perform hash calculations based on preset bits of the virtual address using a path predictor, query the historical record table to obtain the predicted path and confidence level, and determine the query range based on the confidence level through dynamic weighted hierarchical caching.

[0143] Weighted evaluation and cache management are used to calculate the score of the hit entry using a comprehensive scoring formula when the cache is hit. Based on the score, the cache entries are prioritized and eviction decisions are made. At the same time, a hybrid replacement algorithm is used to manage the cache entries.

[0144] The prefetch strategy adjustment module is used to start the prefetch operation through the adaptive prefetch engine when the preset trigger conditions are met. It uses Q4.12 fixed-point number calculation and dynamically expands the prefetch step size, while preventing memory bandwidth contention through two-level monitoring.

[0145] The mode switching and parameter adjustment module is used to activate the instruction priority mode when the instruction access ratio, TLB hit rate and prefetch success rate meet preset conditions. It updates the score of the hit item by adjusting the relevant parameters of the comprehensive scoring formula.

[0146] The multi-level page table traversal acceleration system provided in this embodiment uses a path predictor to perform hash calculations on preset bits of virtual addresses and combines historical records to predict access paths. It uses dynamic weighted hierarchical caching to determine the query range according to confidence level. It optimizes cache entry priority by integrating page table hierarchy weights, instruction type gains, and time decay factors through a comprehensive scoring formula. It also uses an adaptive prefetch engine to dynamically expand the prefetch step size with a Q4.12 fixed number and prevents memory bandwidth contention by monitoring cache miss rate. In instruction-intensive scenarios, it activates a priority mode to adjust scoring parameters. This system achieves a significant reduction in page table traversal latency, an improvement in TLB and cache hit rates, efficient allocation of memory bandwidth, and optimization of overall system performance.

[0147] Figure 8 A schematic diagram of the hardware structure of an electronic device for implementing various embodiments of the present invention.

[0148] The multi-level page table traversal acceleration method provided in this application embodiment can be applied to electronic devices. Those skilled in the art will understand that the electronic device structure involved in the embodiments of this invention does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. In the embodiments of this invention, the electronic device includes, but is not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of this application described and / or claimed herein.

[0149] Electronic devices may include processors, external memory interfaces, internal memory, universal serial bus (USB) interfaces, charging management modules, power management modules, batteries, wireless communication modules, audio modules, speakers, microphones, sensor modules, buttons, cameras, displays, and SIM card interfaces, etc.

[0150] A processor may include one or more processing units, such as: a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0151] The processor can serve as the nerve center and command center of an electronic device. The controller can generate operation control signals based on the instruction opcode and timing signals to control the fetching and execution of instructions.

[0152] The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to use the instruction or data again, it can retrieve it directly from this memory. This avoids repeated accesses, reduces processor latency, and thus improves system efficiency.

[0153] An external storage interface (ESI) can be used to connect external memory cards, such as microSD cards, to expand the storage capacity of electronic devices. The external memory card communicates with the processor through the ESI to perform data storage functions, such as saving music and video files on the external memory card.

[0154] Internal memory can be used to store computer executable program code, which includes instructions. The processor executes various functional applications and data processing of electronic devices by running the instructions stored in internal memory. Internal memory can include a program storage area and a data storage area. Internal memory can include high-speed random access memory, and can also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0155] Wireless communication functionality in electronic devices can be achieved through antennas, wireless communication modules, modem processors, and baseband processors.

[0156] Wireless communication modules can provide solutions for wireless communication applications in electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies.

[0157] Electronic devices can implement audio functions through audio modules, speakers, receivers, microphones, headphone jacks, and application processors.

[0158] Electronic devices can achieve shooting functions through ISPs, cameras, video codecs, GPUs, displays, and application processors.

[0159] Electronic devices can achieve display functions through GPUs, displays, and application processors.

[0160] A GPU is a microprocessor for image processing, connected to the display screen and application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering. A processor may include one or more GPUs, which execute program instructions to generate or modify display information.

[0161] A display screen is used to display images, videos, etc. A display screen includes a display panel.

[0162] The aforementioned electronic device implements the multi-level page table traversal acceleration method of this application, which uses a path predictor to perform hash calculations on virtual addresses and combines historical records to predict paths, dynamically weighted hierarchical caching adjusts the query range according to confidence level, integrates hierarchical weights, instruction type gains, and time decay to optimize cache priority in a comprehensive scoring formula, uses the Q4.12 fixed-point algorithm to dynamically expand the prefetch step size and monitor the cache miss rate in an adaptive prefetch engine, and adjusts the scoring parameters according to real-time indicators in an instruction priority mode. This achieves the beneficial effects of reducing page table traversal latency, improving TLB hit rate, optimizing memory bandwidth utilization, and enhancing performance in instruction-intensive scenarios.

[0163] The storage medium provided in this application stores a program product capable of implementing a method to accelerate multi-level page table traversal.

[0164] Methods to accelerate multi-level page table traversal include:

[0165] The virtual addresses are input into the path predictor and the dynamic weighted hierarchical cache respectively, and the instruction access ratio, TLB hit rate and prefetch success rate are collected in real time.

[0166] The path predictor performs hash calculations based on preset bits of the virtual address, queries the historical record table to obtain the predicted path and confidence level, and determines the query range based on the confidence level through dynamic weighted hierarchical caching.

[0167] When a cache hit occurs, the score of the hit entry is calculated using a comprehensive scoring formula. Based on the score, the cache entries are prioritized and eviction decisions are made. At the same time, a hybrid replacement algorithm is used to manage the cache entries.

[0168] When the preset trigger conditions are met, the prefetching operation is started through the adaptive prefetching engine. The prefetching step size is dynamically expanded using Q4.12 fixed-point number calculation, and memory bandwidth contention is prevented through two-level monitoring.

[0169] When the instruction access rate, TLB hit rate, and prefetch success rate meet the preset conditions, the instruction priority mode is activated, and the score of the hit item is updated by adjusting the relevant parameters of the comprehensive scoring formula.

[0170] In some possible implementations, the multi-level page table traversal acceleration method of this disclosure can be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0171] The storage medium disclosed herein may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0172] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for accelerating multi-level page table traversal, characterized in that, include: The virtual addresses are input into the path predictor and the dynamic weighted hierarchical cache respectively, and the instruction access ratio, TLB hit rate and prefetch success rate are collected in real time. The path predictor performs hash calculations based on preset bits of the virtual address, queries the historical record table to obtain the predicted path and confidence level, and determines the query range based on the confidence level through dynamic weighted hierarchical caching. When a cache hit occurs, the score of the hit entry is calculated using a comprehensive scoring formula. Based on the score, the cache entries are prioritized and eviction decisions are made. At the same time, a hybrid replacement algorithm is used to manage the cache entries. When the preset trigger conditions are met, the prefetching operation is started through the adaptive prefetching engine. The prefetching step size is dynamically expanded using Q4.12 fixed-point number calculation, and memory bandwidth contention is prevented through two-level monitoring. When the instruction access ratio, TLB hit rate, and prefetch success rate meet the preset conditions, the instruction priority mode is activated, and the score of the hit item is updated by adjusting the relevant parameters of the comprehensive scoring formula. When a cache hit occurs, a score is calculated using a comprehensive scoring formula for the hit entry. Based on the score, cache entries are prioritized and evicted. A hybrid replacement algorithm is also used to manage cache entries, including: When a cache hit occurs, the score for the hit entry is calculated using the comprehensive scoring formula: Score = α • LevelWeight + β • TypeBoost - γ • Δt. Here, α is the scaling factor for path prediction confidence, LevelWeight is the weight of the page table level where the cache entry resides, β is the type gain coefficient for instruction access ratio, TypeBoost is the type gain of the cache entry, γ is the time decay factor related to prefetch hit rate, and Δt is the access interval of the cache entry. If the cache entry is at the PGD layer, LevelWeight = 4; if it's at the PUD layer, LevelWeight = 3; if it's at the PMD layer, LevelWeight = 2; and if it's at the PTE layer, LevelWeight = 1. Based on the score of the hit item, determine the cache priority of the item and cache it. When the number of free entries in the current cache is greater than or equal to 10% of the total number of entries, two candidate entries are randomly selected from each of the four levels of PGD, PUD, PMD and PTE for caching. When the number of free entries in the current cache is less than 10% of the total number of entries, entries with a score < 2 are evicted. For entries that are hit 3 times consecutively, lock them in the cache for 200 cycles; When preset triggering conditions are met, the prefetching operation is initiated through an adaptive prefetching engine, using Q4.12 fixed-point calculation and dynamically expanding the prefetching step size. Simultaneously, two-level monitoring prevents memory bandwidth contention, including: If the current PTE level entries have been loaded, the remaining space in the dynamic cache is greater than 20% of the total cache space, and Z≥5, the prefetch operation is started through the adaptive prefetch engine; The step size is updated every 100 cycles. The initial step size is ±2 pages. The step size value stride is calculated and updated based on the real-time item hit rate using the step size calculation formula, and the step size is dynamically expanded. The L1D-Cache miss rate Q is sampled every 50 cycles. When Q > 15% for a cumulative total of 3 times, the prefetch operation is turned off for 200 cycles. The formula for calculating the step size is: in, This represents the item hit rate.

2. The method for accelerating multi-level page table traversal according to claim 1, characterized in that, The process of inputting virtual addresses into the path predictor and the dynamic weighted hierarchical cache, and collecting instruction access ratio, TLB hit rate, and prefetch success rate in real time, includes: Input the virtual addresses VA[47:0] into the path predictor and the dynamic weighted hierarchical cache, respectively; A 32-bit sliding window counter is used in real time to detect the instruction access ratio. When the CPU executes an instruction, the counter value counter is incremented by 1; when the CPU accesses data, the counter value counter is decremented by 1. The instruction access ratio InstrRatio is calculated in real time using the formula InstrRatio=(counter+32768) / 65536.

0. The TLB hit rate is calculated by reading the number of TLB hits and misses recorded in the hardware performance counter. Read the number of prefetch hits and misses recorded in the hardware performance counters and calculate the prefetch success rate; The collected instruction access percentage, TLB hit rate, and prefetch success rate are broadcast every cycle via a 32-bit status bus. In the 32-bit status bus, bit segment [7:0] represents the operating mode code, bit segment [15:8] represents the instruction percentage, bit segment [23:16] represents the prefetch success rate, and bit segment [31:24] represents the TLB hit rate.

3. The method for accelerating multi-level page table traversal according to claim 2, characterized in that, The process involves using a path predictor to perform hash calculations based on preset bits of the virtual address, querying a historical record table to obtain the predicted path and confidence level; and using a dynamic weighted hierarchical cache to determine the query range based on the confidence level, including: The path predictor performs hash calculation based on the virtual address VA[47:39] and queries the historical record table to obtain the predicted path and the path prediction confidence Z; The confidence level is determined based on the path prediction confidence level Z; when Z ≥ 6, it is high confidence; when 5 < Z < 6, it is medium confidence; and when Z ≤ 5, it is low confidence. The page table level for the query is determined based on the confidence level; the page table adopts a four-level page table of PGD, PUD, PMD, and PTE. When the confidence level is high, only the prediction level ±1 range is queried; when the confidence level is low, parallel queries are performed across all levels.

4. The method for accelerating multi-level page table traversal according to claim 1, characterized in that, When the instruction access ratio, TLB hit rate, and prefetch success rate meet preset conditions, the instruction priority mode is activated. The score of the hit item is updated by adjusting relevant parameters of the comprehensive scoring formula, including: Real-time monitoring command access ratio (InstrRatio); When InstrRatio > 60%, TLB hit rate < 85%, and prefetch success rate > 40%, activate instruction priority mode, increase TypeBoost to 1.2 times the current level, force the β value to 0.1, and update the score of the entry. The type gain coefficient β of the instruction access ratio is dynamically adjusted in real time according to the formula β=max(0, min(0.5, 0.2 + 0.5•(InstrRatio - 0.6))), and the score of the entry is updated.

5. A multi-level page table traversal acceleration system, characterized in that, The system employs the multi-level page table traversal acceleration method as described in any one of claims 1 to 4; The system includes: The address input and status monitoring module is used to input virtual addresses into the path predictor and the dynamic weighted hierarchical cache respectively, and to collect the instruction access ratio, TLB hit rate and prefetch success rate in real time. The path prediction and query planning module is used to perform hash calculations based on preset bits of the virtual address using a path predictor, query the historical record table to obtain the predicted path and confidence level, and determine the query range based on the confidence level through dynamic weighted hierarchical caching. Weighted evaluation and cache management are used to calculate the score of the hit entry using a comprehensive scoring formula when the cache is hit. Based on the score, the cache entries are prioritized and eviction decisions are made. At the same time, a hybrid replacement algorithm is used to manage the cache entries. The prefetch strategy adjustment module is used to start the prefetch operation through the adaptive prefetch engine when the preset trigger conditions are met. It uses Q4.12 fixed-point number calculation and dynamically expands the prefetch step size, while preventing memory bandwidth contention through two-level monitoring. The mode switching and parameter adjustment module is used to activate the instruction priority mode when the instruction access ratio, TLB hit rate and prefetch success rate meet the preset conditions. The module updates the score of the hit item by adjusting the relevant parameters of the comprehensive scoring formula. The weight evaluation and cache management are specifically used for: When a cache hit occurs, the score for the hit entry is calculated using the comprehensive scoring formula: Score = α • LevelWeight + β • TypeBoost - γ • Δt. Here, α is the scaling factor for path prediction confidence, LevelWeight is the weight of the page table level where the cache entry resides, β is the type gain coefficient for instruction access ratio, TypeBoost is the type gain of the cache entry, γ is the time decay factor related to prefetch hit rate, and Δt is the access interval of the cache entry. If the cache entry is at the PGD layer, LevelWeight = 4; if it's at the PUD layer, LevelWeight = 3; if it's at the PMD layer, LevelWeight = 2; and if it's at the PTE layer, LevelWeight = 1. Based on the score of the hit item, determine the cache priority of the item and cache it. When the number of free entries in the current cache is greater than or equal to 10% of the total number of entries, two candidate entries are randomly selected from each of the four levels of PGD, PUD, PMD and PTE for caching. When the number of free entries in the current cache is less than 10% of the total number of entries, entries with a score < 2 are evicted. For entries that are hit 3 times consecutively, lock them in the cache for 200 cycles; The prefetch strategy adjustment module is specifically used for: If the current PTE level entries have been loaded, the remaining space in the dynamic cache is greater than 20% of the total cache space, and Z≥5, the prefetch operation is started through the adaptive prefetch engine; The step size is updated every 100 cycles. The initial step size is ±2 pages. The step size value stride is calculated and updated based on the real-time item hit rate using the step size calculation formula, and the step size is dynamically expanded. The L1D-Cache miss rate Q is sampled every 50 cycles. When Q > 15% for a cumulative total of 3 times, the prefetch operation is turned off for 200 cycles. The formula for calculating the step size is: in, This represents the item hit rate.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the multi-level page table traversal acceleration method as described in any one of claims 1 to 4.

7. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the multi-level page table traversal acceleration method as described in any one of claims 1 to 4.

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