Register access method and system

Abstract

According to the register access method and system, a CM or a debugging unit is connected with a master node in a register ring, and a register needing to be read and written is connected with a slave node in the register ring. After the CM or the debugging unit initiates a read-write request, the node connected with the CM or the debugging unit sends the read-write request to the next node of the node in the register ring, and the node receiving the read-write request judges whether the target endpoint identifier in the read-write request is matched with the identifier of the endpoint connected with the node or not; whether the read-write request needs to be sent to the endpoint connected with the node can be known. And if the target endpoint identifier in the read-write request is matched with the identifier of the endpoint connected with the node, forwarding the read-write request to the endpoint (register) connected with the node, thereby completing the task of accessing the register by the CM.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly relates to a register access method and system. Background Art

[0002] The Coherence Manager (CM) needs to access many types of registers, such as multiple CPUs and peripherals, the Cluster Power Controller (CPC), Global Configuration Registers (GCR), Global Interrupt Controller (GIC), etc.

[0003] Currently, the tasks of the CM accessing registers are all processed by the Bus Interface Unit (BIU), resulting in a heavy burden on the BIU. Summary of the Invention

[0004] This application provides a register access method and system, which can reduce the burden on the BIU. The technical solutions are as follows.

[0005] In a first aspect, a register access method is provided, which is applied to a register bus system. The register bus system includes a register ring and multiple endpoints. The register ring includes multiple nodes, and the multiple nodes include at least one master node and at least one slave node. The multiple endpoints include at least one master endpoint and at least one slave endpoint. The at least one master node is respectively connected to the corresponding master endpoint among the at least one master endpoints, and the at least one slave node is respectively connected to the corresponding slave endpoint among the at least one slave endpoints. The at least one master endpoint includes a Coherence Manager (CM) and a debugging unit, and the at least one slave endpoint includes a CPU core, a CPC, a GCR, a GIC, and an IO device. The method includes:

[0006] A first node receives a read / write request from a first endpoint connected to the first node. The first node is one of the at least one master nodes, and the first endpoint is one of the at least one master endpoints. The read / write request includes a destination endpoint identifier, and the destination endpoint identifier is used to identify the register that the first endpoint needs to read or write.

[0007] The first node sends the read / write request to a second node. The second node is the next node of the first node in the register ring, and the second node is connected to a second endpoint.

[0008] The second node receives the read / write request. If the destination endpoint identifier does not match the identifier of the second endpoint, the second node sends the read / write request to a third node, where the third node is the next node of the second node in the register ring; or, if the destination endpoint identifier matches the identifier of the second endpoint, the second node sends the read / write request to the second endpoint.

[0009] In some embodiments, after the second node sends the read / write request to the second endpoint, the method further includes:

[0010] The second node receives a read / write response from the second endpoint, where the read / write response includes a result obtained by the second endpoint in processing the read / write request;

[0011] The second node sends the read / write response to a fourth node, where the fourth node is one of the at least one slave node and is connected to the first endpoint;

[0012] The fourth node receives the read / write response and, based on the fact that the destination endpoint identifier in the read / write response matches the identifier of the first endpoint, sends the read / write response to the first endpoint.

[0013] In some embodiments, the register bus system includes a register bus interface that is respectively connected to the first endpoint, the first node, a memory interface, and a network interface. Before the first node receives a read / write request from a first endpoint connected to the first node, the method further includes:

[0014] The register bus interface intercepts the read / write request of the first endpoint;

[0015] If the destination endpoint identifier in the read / write request matches the identifier of any one of the multiple endpoints, the register bus interface sends the read / write request to the first node;

[0016] If the destination endpoint identifier in the read / write request does not match the identifier of each of the multiple endpoints, the register bus interface sends the read / write request to the memory interface or the network interface.

[0017] In some embodiments, the register bus interface sending the read / write request to the first node includes:

[0018] If the width of the read / write request is greater than the width of the register bus interface, the register bus interface slices the read / write request according to the width of the register bus interface to obtain a plurality of micro-pieces;

[0019] The register bus interface sends the plurality of microtiles to the first node.

[0020] In some embodiments, after the second node sends the read / write request to the third node, the method further includes:

[0021] In a case where the destination endpoint identifier does not match the identifier of each of the plurality of endpoints, the first node receives the read / write request sent by the previous node of the first node in the register ring;

[0022] The first node deletes the read / write request and outputs an error signal.

[0023] In some embodiments, the at least one master node is connected in series, the at least one master node is adjacent in position in the register ring, the first master node in the data transmission direction among the at least one master node is configured to delete a read / write request whose destination endpoint identifier does not match the identifier of each of the plurality of endpoints, and the last master node in the data transmission direction among the at least one master node is configured to delete a read / write response whose destination endpoint identifier does not match the identifier of each of the plurality of endpoints.

[0024] In some embodiments, after the second node receives the read / write request, the method further includes:

[0025] If it is detected that the second endpoint is powered off, the second node cancels the step of matching the destination endpoint identifier with the identifier of the second endpoint, sends the read / write request to the third node, and sends a response signal to the first node, the response signal indicating that the second endpoint is unavailable.

[0026] In a second aspect, a register access system is provided. The register bus system includes a register ring and a plurality of endpoints. The register ring includes a plurality of nodes. The plurality of nodes includes at least one master node and at least one slave node. The plurality of endpoints includes at least one master endpoint and at least one slave endpoint. The at least one master node is respectively connected to a corresponding master endpoint among the at least one master endpoints. The at least one slave node is respectively connected to a corresponding slave endpoint among the at least one slave endpoints. The at least one master endpoint includes a coherence manager CM and a debugging unit. The at least one slave endpoint includes a CPU core, a CPC, a GCR, a GIC, and an IO device. The plurality of nodes includes a first node and a second node;

[0027] The first node is configured to receive read / write requests from a first endpoint connected to the first node. The first node is one of the at least one master node, and the first endpoint is one of the at least one master endpoint. The read / write request includes a destination endpoint identifier for identifying the register to be read from or written to by the first endpoint. The first node sends the read / write request to a second node, which is the next node of the first node in the register ring and is connected to a second endpoint.

[0028] The second node is configured to receive the read / write request. If the destination endpoint identifier does not match the identifier of the second endpoint, the second node sends the read / write request to a third node, which is the next node of the second node in the register ring. Or, if the destination endpoint identifier matches the identifier of the second endpoint, the second node sends the read / write request to the second endpoint.

[0029] In a third aspect, a computing device is provided. The computing device includes a processor coupled to a memory. At least one computer program instruction is stored in the memory and is loaded and executed by the processor to enable the computing device to implement the method provided in the first aspect or any optional implementation of the first aspect.

[0030] In a fourth aspect, a computer-readable storage medium is provided. At least one instruction is stored in the storage medium. When the instruction runs on a computer, the computer is caused to execute the method provided in the first aspect or any optional implementation of the first aspect.

[0031] Therefore, the embodiments of the present application have the following beneficial effects:

[0032] An embodiment of the present application designs a register bus architecture including a register ring, connecting a CM or a debug unit to a master node in the register ring, and connecting registers to be read or written to a slave node in the register ring. After the CM or the debug unit initiates a read / write request, the node connected to the CM or the debug unit (the first node) sends the read / write request to the next node of this node in the register ring. During the process of the read / write request flowing along the register ring, the node receiving the read / write request can know whether the read / write request needs to be sent to the endpoint connected to this node based on whether the destination endpoint identifier in the read / write request matches the identifier of the endpoint connected to this node. If the destination endpoint identifier in the read / write request matches the identifier of the endpoint connected to this node, the read / write request is forwarded to the endpoint (register) connected to this node. If the destination endpoint identifier in the read / write request does not match the identifier of the endpoint connected to this node, the read / write request is forwarded to the next node connected to this node in the register ring, and the next node processes the read / write request according to the same logic, so that the read / write request initiated by the CM or the debug unit can reach the register, thus completing the task of the CM accessing the register. This method separates the task of accessing the register from the BIU. On the premise of meeting the requirements of the CM or the debug unit for the access performance of the register, it greatly reduces the burden on the BIU, simplifies the design complexity of the BIU, and improves the stability and reliability of the system. Description of the Drawings

[0033] Figure 1 is a schematic diagram of the architecture of a register bus system provided by an embodiment of the present application;

[0034] Figure 2 is a schematic diagram of the structure of a node in the register ring of the register bus system provided by an embodiment of the present application;

[0035] Figure 3 is a flowchart of a register access method provided by an embodiment of the present application;

[0036] Figure 4 is a schematic diagram of the format of a data packet transmitted in the register ring provided by an embodiment of the present application;

[0037] Figure 5 is a schematic diagram of deadlock occurring in the register ring provided by an embodiment of the present application;

[0038] Figure 6 is a schematic diagram of a typical connection of a single cluster ring topology provided by an embodiment of the present application

[0039] Figure 7 is a schematic diagram of the structure of a computing device provided by an embodiment of the present application. Detailed Embodiments

[0040] To make the objectives, technical solutions, and advantages of this application more clear, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings.

[0041] The following gives an example of the system architecture provided by the embodiments of this application.

[0042] The embodiments of this application provide a register bus system. This register bus system adopts a point-to-point connected ring structure, allowing multiple master endpoints to perform register reads or writes to multiple slave endpoints.

[0043] In order to distinguish between the devices in the register ring and the devices outside the register ring in this embodiment, the devices in the register ring are called register bus nodes (hereinafter referred to as nodes), and the devices connected to the nodes outside the register ring are called endpoints. Specifically, the register bus system includes a register ring and multiple endpoints. The register ring includes multiple nodes.

[0044] The multiple endpoints include at least one master endpoint and at least one slave endpoint. The master endpoint is the initiator of the read / write request, and the slave endpoint is the responder to the read / write request. The master endpoint has a need to read and write data to the slave endpoint, and the data required for reading and writing by the master endpoint is stored in the slave endpoint. For example, the at least one master endpoint includes a CM or a debug unit. The at least one slave endpoint includes the registers required for reading and writing by the master endpoint. For example, the at least one slave endpoint includes a CPU core, a CPC, a GCR, a GIC, and an input / output (Input / Output, IO) device. The IO device is, for example, an Input / Output Memory Management Unit (IOMMU).

[0045] The multiple nodes include at least one register bus master node (hereinafter referred to as the master node) and at least one register bus slave node (hereinafter referred to as the slave node), and the multiple nodes are connected in series in sequence.

[0046] The master node is used to send the read / write requests from the master endpoints to the register ring, so that the read / write requests are forwarded along the register ring to the destination endpoints. At least one master node is respectively connected to the corresponding master endpoint in at least one master endpoint. For example, each master node is connected to one master endpoint.

[0047] The slave node is used to determine whether the destination endpoint identifier carried in the read / write request matches the identifier of the endpoint connected to this node when receiving a read / write request. If the destination endpoint identifier carried in the read / write request matches the identifier of the endpoint connected to this node, the read / write request is forwarded to the endpoint connected to this node, so as to receive the result corresponding to the read / write request from the endpoint connected to this node. If the destination endpoint identifier carried in the read / write request does not match the identifier of the endpoint connected to this node, the read / write request is forwarded to the next node of this node in the register ring, so that the read / write request is further forwarded in the register ring through the next node and finally forwarded to the destination endpoint. At least one slave node is respectively connected to the corresponding slave endpoint in at least one slave endpoint. For example, each slave node is connected to one slave endpoint.

[0048] Exemplarily, please refer to the appendix Figure 1 , the appendix Figure 1 is a schematic architecture diagram of a register bus system provided by an embodiment of the present application. The appendix Figure 1 shows a single cluster register ring of the CM. Figure 1 The M in Figure 1 represents the master node,

[0049] Figure 1 The S in

[0050] represents the slave node. The master node 110 is connected to the register bus interface of the CM, and the master node 111 is connected to the debugging unit. The CPU core, CPC, GCR, GIC, and IO peripherals are respectively connected to the slave nodes of the register ring. For example, the slave node 120 is connected to the CPU core 0, the slave node 121 is connected to the CPU core 1, the slave node 122 is connected to the CPU core 2, the slave node 123 is connected to the CPU core 3, the slave node 124 is connected to the IOMMU0, the slave node 125 is connected to the IOMMU1, the slave node 126 is connected to the CPC, the slave node 127 is connected to the GCR, the slave node 128 is connected to the register bus interface of the CM, and the slave node 129 is connected to the debugging unit.

[0051] In some embodiments, the register bus system includes a register bus interface. The register bus interface is connected to a first endpoint, a first node, a memory interface, and a network interface respectively. The first endpoint is one of at least one master endpoint included in the register bus system. The first node is one of at least one master node included in the register ring. The first node is connected to the first endpoint through the register bus interface. Since the register bus interface is connected to the first endpoint, the register bus interface can receive read and write requests from the first endpoint and send read and write responses to the first endpoint. Since the register bus interface is connected to the first node, the memory interface, and the network interface, the register bus interface can send read and write requests to any one of the first node, the memory interface, and the network interface.

[0052] For example, please refer to Figure 1 , the first endpoint is, for example, Figure 1 the CM in Figure 1 , the first node is, for example,

[0053] In some embodiments, the register bus interface is also connected to a fourth node. The fourth node is one of at least one slave node. The fourth node is used to send read and write responses with the destination being the first endpoint to the first endpoint through the register bus interface. For example, please refer to Figure 1 , the fourth node is, for example, Figure 1 the slave node 128 in Figure 1 , the first endpoint is, for example,

[0054] In some embodiments, the debug unit is connected to a master node and a slave node in the register ring. For example, please refer to Figure 1 , the debug unit is connected to the master node 111 and is connected to the slave node 129.

[0055] Considering that the ring structure will increase the latency of register access, and the GIC and UGCR (User Global Configuration Registers) endpoints are sensitive to latency, therefore, the GIC and UGCR are processed separately from all other endpoints, and the GIC and UGCR are directly connected to the register bus interface of the CM.

[0056] The clock domain of the endpoint is independent of the register bus clock domain. The power domain of the endpoint is powered off independently. The register ring remains powered on. When the endpoint is powered off or in the clock-off state, the register bus node will send a response indicating that the endpoint is unavailable in response to a request.

[0057] The overall architecture of the register bus system is introduced above. Next, the structure of the nodes in the register bus system will be illustrated by examples.

[0058] Please refer to the appendix Figure 2 , the appendix Figure 2 is a schematic diagram of the structure of the node (reg_bus_node) in the register ring of the register bus system provided by the embodiment of the present application.

[0059] The structure of each node is as Figure 2 shown. The node has at least three directions of data flow, including the request data flow in the ring, the response data flow in the ring, and the data flow between the endpoints connected to this node.

[0060] The request data flow in the ring includes the data flow composed of read and write requests received by this node from the previous node in the register ring ( Figure 2 req_data_in in) and the data flow composed of read and write requests sent by this node to the next node in the register ring ( Figure 2 req_data_out in).

[0061] The response data flow in the ring includes the data flow composed of response requests received by this node from the previous node in the register ring ( Figure 2 rsp_data_in in) and the data flow composed of response requests sent by this node to the next node in the register ring ( Figure 2 rsp_data_out in).

[0062] For the master node in the register ring, the data flow between this node and the endpoint includes the request data flow (endp_req(master)) sent by the master endpoint to this node and the response data flow (endp_rsp(master)) sent by this node to the master endpoint. For the slave node in the register ring, the data flow between this node and the endpoint includes the request data flow (endp_req(slave)) sent by this node to the slave endpoint and the response data flow (endp_rsp(slave)) sent by the slave endpoint to this node.

[0063] For the master node in the register ring, the data stream of the master node also includes the request data stream terminated at this node (req_terminator (master only)), the response data stream terminated at this node (rsp_terminator (master only)), and the output error signal (bus_error (master only)).

[0064] The above focuses on describing the system architecture provided by the embodiments of the present application. Next, the method flow of the embodiments of the present application will be illustrated by examples.

[0065] In Figure 1 In the system architecture shown, each master endpoint can send read / write requests to any slave endpoint, and the read / write requests include read register requests or write register requests. When the slave node in the register bus receives a read / write request associated with the slave endpoint connected to this node, the slave node will send the read / write request to the slave endpoint connected to this node. The slave endpoint executes the received read / write request. Then, the slave endpoint will return a read / write response to the slave node of the register bus connected to this node. The read / write response includes a read response and a write response. If the read / write request received by the slave endpoint is a read register request, the read response returned by the slave endpoint contains the data indicated by the read register request. If the read / write request received by the slave endpoint is a write register request, the write response returned by the slave endpoint is just an acknowledgment and does not need to contain data. Then, the slave node forwards the write response to the next node in the register ring.

[0066] Exemplarily, please refer to the appendix Figure 3 , the appendix Figure 3 is a flowchart of a register access method provided by the embodiments of the present application. The method shown in the appendix Figure 3 is applied to the architecture shown in the appendix Figure 1 , and the method shown in the appendix Figure 3 includes the following steps S300 to step S390.

[0067] Step S300, the first endpoint sends a read / write request.

[0068] The first endpoint is one of at least one master endpoint included in the register bus system. In some embodiments, the first endpoint is the CM. For example, please refer to the appendix Figure 1 , when the CM needs to read data from the register or write data to the register, the CM generates and sends a read / write request, and the destination endpoint identifier in the read / write request contains the identifier of the register that the CM needs to access. The CM sends the read / write request to the register bus interface through the CM request (REQ) bus and the CM write data intervention response (WID) bus. In some other embodiments, the first endpoint can also be a debug unit.

[0069] The read / write request includes at least one of a register read request (abbreviated as read request) and a register write request (abbreviated as write request). The read / write request includes a destination endpoint identifier, which is used to identify the register to be read or written by the first endpoint. The register read request is used to indicate reading the data stored in the register. The register write request is used to indicate writing data to the register. The register write request includes not only the destination endpoint identifier but also the data to be written.

[0070] Step S310: The register bus interface intercepts the read / write request from the first endpoint.

[0071] Step S320: If the destination endpoint identifier in the read / write request matches the identifier of any one of multiple endpoints, the register bus interface sends the read / write request to the first node.

[0072] The first node is one of at least one master node. The first node is communicatively connected to the first endpoint through the register bus interface. For example, please refer to the appendix Figure 1 , where the first endpoint is the CM and the first node is the master node 110. Another example is that the first endpoint is the debug unit and the first node is the master node 111.

[0073] The matching of the destination endpoint identifier with the identifier of any endpoint in the register bus system indicates that the destination of the read / write request is an endpoint in the register bus system. Therefore, the register bus interface forwards the read / write request to the register ring through the first node, and then the read / write request is forwarded to the destination endpoint through the register ring.

[0074] In some embodiments, if the width of the read / write request is greater than the width of the register bus interface, before sending the read / write request, the register bus interface slices the read / write request according to the width of the register bus interface to obtain multiple micro-pieces (flits). The register bus interface sends multiple micro-pieces to the first node. Among them, the width of each micro-piece is, for example, the width of the register bus interface. For example, if the width of the read / write request is 256 bits and the width of the register bus interface is 64 bits, the register bus interface slices the read / write request into 4 micro-pieces with a length of 64 bits.

[0075] In some embodiments, before sending the read / write request, the register bus interface performs protocol conversion on the read / write request and converts the read / write request into a data packet supported by the register ring shown in the appendix Figure 4 .

[0076] Exemplarily, the register bus interface supports widths of 16 bits, 32 bits, and 64 bits. Among the multiple sliced micro-flits, the first micro-flit is called the head flit. The intermediate micro-flits are called body flits. The last micro-flit is called the tail flit. If the multiple sliced micro-flits only include two micro-flits, then there is only one head flit and one tail flit after slicing, and no body flits. If the sliced micro-flit only includes one micro-flit, then the sliced micro-flit will be marked as a head flit or a tail flit.

[0077] In addition, if the destination endpoint identifier in the read / write request does not match the identifier of each endpoint among the multiple endpoints, indicating that the destination of the read / write request is not an endpoint in the register bus system, in this case, the read / write request does not need to be forwarded through the register ring, and the register bus interface sends the read / write request to the memory interface or the network interface.

[0078] In addition, if the destination endpoint identifier in the read / write request matches the identifier of the GIC, the register bus interface can send the read / write request to the GIC that communicates directly with the read / write request for low latency.

[0079] In addition, if the destination endpoint identifier in the read / write request matches the identifier of the UGCR, the register bus interface can send the read / write request to the UGCR that communicates directly with the read / write request for low latency.

[0080] Regarding the method of matching the identifier of the endpoint with the destination endpoint identifier in the read / write request, in some embodiments, the identifier of the endpoint is the address of the endpoint, the addresses of all endpoints in the register bus system belong to the same address range, the register bus interface stores this address range, and determines whether the destination endpoint identifier belongs to this address range. If the destination endpoint identifier belongs to this address range, it is confirmed that the destination endpoint identifier matches the identifier of any one of the multiple endpoints.

[0081] Step S330: The first node receives a read / write request from the first endpoint connected to the first node, and the first node sends the read / write request to the second node.

[0082] The second node is the next node of the first node in the register ring. For example, in the case where the register ring traffic flows point-to-point around the ring in a clockwise direction, the second node is the next node of the first node in the clockwise direction in the register ring. The second node can be a master node or a slave node. For example, please refer to the appendix Figure 1 , the first node is the master node 110, and the second node is the master node 111. Another example is that the first node is the master node 111, and the second node is the slave node 129.

[0083] Step S350: The second node receives a read / write request. If the destination endpoint identifier matches the identifier of the second endpoint, the second node sends the read / write request to the second endpoint.

[0084] The second node is connected to the second endpoint. The second node stores the identifier of the second endpoint. For example, please refer to the appendix Figure 1 , the second node is the master node 111 and the second endpoint is the debug unit. Another example is that the second node is the slave node 121 and the second endpoint is the CPU core 1.

[0085] The second node can match the destination endpoint identifier in the read / write request with the identifier of the second endpoint. If the destination endpoint identifier in the read / write request matches the identifier of the second endpoint, for example, the destination endpoint identifier is the same as the identifier of the second endpoint, the second node can determine that the destination of the read / write request is the endpoint connected to this node, and then send the read / write request to the second endpoint.

[0086] Step S360: The second endpoint receives the read / write request, executes the read / write request, and obtains a processing result.

[0087] Step S362: The second endpoint generates and sends a read / write response to the second node based on the processing result. The read / write response includes the result obtained by the second endpoint for processing the read / write request.

[0088] After obtaining the processing result, the second endpoint carries the processing result in the read / write response and sends the read / write response to the second node connected to the second endpoint. The second node sends the read / write response to the node connected to this node in the register ring.

[0089] The result in the register will then be returned to the node connected to the register, and the node will then send it along the ring to the node that sent the request. For example, in the case where the read / write request is a register read request, the second endpoint reads the data indicated by the register read request and carries the data in the read / write response. In the case where the read / write request is a register write request, the second endpoint stores the data indicated by the register write request.

[0090] This embodiment illustrates the register read / write process with the second endpoint connected to the second node as the destination of the read / write request. In some other embodiments, if the destination endpoint identifier does not match the identifier of the second endpoint, the second node sends the read / write request to the third node. The third node is the next node of the second node in the register ring. For example, please refer to the appendix Figure 1, the second node is the master node 111, and the third node is the slave node 129. For another example, the second node is the slave node 121, and the third node is the slave node 122. The process for the third node to handle read / write requests is the same as that for the second node to handle read / write requests. By analogy, after any node in the register ring receives a read / write request, it can determine whether to send the read / write request to the endpoint connected to this node or to the next node of this node in the register ring based on whether the destination endpoint identifier in the read / write request matches the identifier of the endpoint connected to this node.

[0091] Step S370: The second node receives a read / write response from the second endpoint, and the second node sends the read / write response to the fourth node.

[0092] The fourth node is one of at least one slave node, and the fourth node is connected to the first endpoint. For example, please refer to the appendix Figure 1 , the first endpoint is CM, and the fourth node is the slave node 128. Or, the first endpoint is a debug unit, and the fourth node is the slave node 129.

[0093] Step S390: The fourth node receives the read / write response, and based on the matching of the destination endpoint identifier in the read / write response and the identifier of the first endpoint, sends the read / write response to the first endpoint.

[0094] For example, after the slave node 128 receives the read / write response, based on the matching of the destination endpoint identifier in the read / write response and the identifier of CM, it sends the read / write response to the register bus interface. For another example, after the slave node 129 receives the read / write response, based on the matching of the destination endpoint identifier in the read / write response and the identifier of the debug unit, it sends the read / write response to the debug unit.

[0095] In the embodiment of the present application, the task of accessing the register is separated from the BIU. On the premise of meeting the requirements for the access performance of the register by CM or the debug unit, the burden on the BIU is greatly reduced, the design complexity of the BIU is also simplified, and the stability and reliability of the system are improved.

[0096] In some embodiments, if an endpoint is powered off, the node (master node or slave node) connected to the powered-off endpoint enters bypass mode. After receiving a read / write request, the slave node that enters bypass mode does not need to perform the step of determining whether the destination endpoint identifier carried in the read / write request matches the endpoint identifier, but directly transparently transmits the received read / write request to the next node. Optionally, the slave node that enters bypass mode also returns a response signal to the master node that initiated the read / write request, and the response signal indicates that the endpoint is unavailable. For example, after the second node receives the read / write request, if it detects that the second endpoint to which the second node is connected is powered off, the second node cancels the step of matching the destination endpoint identifier with the identifier of the second endpoint, sends a read / write request to the third node, and sends a response signal to the first node, and the response signal indicates that the second endpoint is unavailable.

[0097] The following is an example of the format of the data message transmitted in the register ring in the embodiment of the present application.

[0098] In the embodiment of the present application, the data messages transmitted in the register ring include data messages in four formats: read request (rd_req), write request (wr_req), read response (rd_rsp) and write response (wr_rsp).

[0099] For example, please refer to the attached Figure 4 , attached Figure 4 This is a schematic diagram of the format of a data message transmitted in a register ring provided by an embodiment of the present application. Read and write requests have a 96-bit (12-byte) message header. Read and write responses have a 48-bit (6-byte) message header. Write requests and read responses have variable-length data fields. The data packet protocol supports data field lengths that are powers of 2, ranging from 1B to 64B.

[0100] All four data message formats include a command (cmd) field, a destination identifier (dest_id) field, a destination cluster identifier (dest_cluster_id) field, a shared data buffer identifier (sdb_id) field, a source identifier (src_id) field, and a source cluster identifier (src_cluster_id) field. Read and write requests contain a core identifier (core_id) field, a VPE identifier (VPE_id) field, a guest identifier (gst_id) field, and two additional fields to identify the byte address (addr) and the data field size (in bytes). These fields are used to define the command type and distinguish between the source and destination correlation IDs.

[0101] The following is an example of how to avoid deadlock in the embodiment of the present application.

[0102] Improper connection between the register bus master node and the slave node may lead to deadlock. For example, please refer to the appendix Figure 5 , appendix Figure 5 is a schematic diagram of deadlock occurring in a register ring provided by an embodiment of the present application.

[0103] In the example shown in the appendix Figure 5 , each node contains only 1 microchip. The master node M0 is trying to send a data packet to the slave node S5 on the other side of the master node M1. The master node M1 is trying to send a data packet to the slave node S0 on the other side of the master node M0. If both master nodes try to send data packets of 7 microchips, they may fall into a deadlock state after sending 5 microchips.

[0104] The master node M0 hopes to complete the transmission of its data packet of 7 microchips before arbitrating and handing over the bus to the incoming request issued by the master node M1. The master node M1 hopes to complete the transmission of its data packet of 7 microchips before arbitrating and handing over the bus to the incoming request issued by the master node M0. As a result, the master node M0 will send 5 microchips, such as the red microchips F0 - F4, and then stop at the master node M1. The master node M1 will send 5 microchips, such as the green microchips F0 - F4, and then stop at the master node M0.

[0105] If two master nodes are separated by slave nodes in the register ring and are sending long data packets to the slave nodes on the other side of the other sending master node, a deadlock situation may occur. Each master node arbitrates on a whole - packet basis. If the data packets sent by both master nodes are long enough, the microchips of each data packet may be suspended by the other sending register bus master node. Connecting all register bus master nodes in series and connecting all register bus slave nodes in series can avoid deadlock situations.

[0106] Specifically, putting all master nodes together and letting the first master node receive incorrect read - write requests can solve the problem of deadlock in read - write requests. Similarly, putting all slave nodes together and letting the last master node receive any unmatched read - write responses can avoid the deadlock problem of read - write responses. For example, multiple master nodes in the register ring are connected in series, the multiple master nodes are adjacent in the register ring, the first master node in the data transmission direction among the multiple master nodes is used to delete read - write requests whose destination endpoint identifiers do not match the identifiers of each of the multiple endpoints, and the last master node in the data transmission direction among the multiple master nodes is used to delete read - write responses whose destination endpoint identifiers do not match the identifiers of each of the multiple endpoints.

[0107] Appendix Figure 6Shows a typical connection of a single-cluster ring topology. In addition to performing the normal register bus master node function, the first register bus master node also acts as a request terminator. In addition to performing the normal register mode function, the last register bus master node also acts as a response terminator.

[0108] Each master node in the register ring can create read and write requests. Each master node performs fair round-robin packet arbitration between the read and write requests it creates and the read and write requests received from other master nodes to determine whether to send the read and write requests from other master nodes or the read and write requests created by this node. For example, the master node sends the read and write requests created by this node for the i-th time and the read and write requests from other master nodes for the (i + 1)-th time.

[0109] The read and write requests are forwarded in the ring and processed by the register bus slave nodes. The slave node that receives the read and write request matches the identifier of the endpoint connected to this node with the destination endpoint identifier in the read and write request. When the match is successful, the slave node forwards the read and write request to the endpoint connected to this node and creates a read and write response, and sends the read and write response to the master node that initiated the request. The source identifier (src_id) in the read and write response is the same as the destination endpoint identifier in the read and write request.

[0110] The method for the read and write response to return to the last register bus master node and still not match is that the source identifier in the read and write response does not match the identifier of each master endpoint. In this case, the last master node performs the task of the response terminator by receiving the read and write response, thereby deleting the read and write response from the register ring. At the same time, the last master node outputs an error signal. The error signal can be output to the device connected out-of-band for processor intervention and cleaning.

[0111] One implementation for the read and write request to bypass the ring and return to the first register bus master node is that when there is no slave endpoint identifier that matches the destination endpoint identifier of the read and write request to process the read and write request, the first master node performs the task of the request terminator. The first master node deletes the read and write request and outputs an error signal. Optionally, the first master node also generates a read and write response, uses the destination endpoint identifier in the read and write request as the source identifier in the read and write response, and sends the read and write response to the originating endpoint of the read and write request.

[0112] Figure 7FIG. 0 is a schematic structural diagram of a computing device 800 provided by an embodiment of the present application. The computing device 800 includes a processor 801, and the processor 801 is coupled to a memory 802. At least one computer program instruction is stored in the memory 802, and the at least one computer program instruction is loaded and executed by the processor 801 so that the computing device 800 implements the above method.

[0113] The embodiments in this specification are all described in a progressive manner. Similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.

[0114] A referring to B means that A is the same as B or A is a simple variation of B.

[0115] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of the objects, nor can they be understood as indicating or implying relative importance. For example, the first node and the second node are used to distinguish different nodes, rather than to describe a specific order of the nodes, nor can it be understood that the first node is more important than the second node.

[0116] In the embodiments of the present application, unless otherwise specified, the meaning of "at least one" is one or more, and the meaning of "a plurality" is two or more. For example, a plurality of nodes means two or more nodes.

[0117] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from a website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid-state drive SolidState Disk (SSD)), etc.

[0118] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present application.

Claims

1. A register access method, characterized in that, Applied to a register bus system, the register bus system includes a register ring and multiple endpoints. The register ring includes multiple nodes, and the multiple nodes include at least one master node and at least one slave node. The multiple endpoints include at least one master endpoint and at least one slave endpoint. The at least one master node is respectively connected to the corresponding master endpoint among the at least one master endpoints, and the at least one slave node is respectively connected to the corresponding slave endpoint among the at least one slave endpoints. The at least one master endpoint includes a coherence manager CM and a debug unit, and the at least one slave endpoint includes a CPU core, a CPC, a GCR, a GIC, and an IO device. The method includes: A first node receives a read / write request from a first endpoint connected to the first node. The first node is one of the at least one master nodes, and the first endpoint is one of the at least one master endpoints. The read / write request includes a destination endpoint identifier, and the destination endpoint identifier is used to identify the register that the first endpoint needs to read or write. The first node sends the read / write request to a second node. The second node is the next node of the first node in the register ring, and the second node is connected to a second endpoint. The second node receives the read / write request. If the destination endpoint identifier does not match the identifier of the second endpoint, the second node sends the read / write request to a third node. The third node is the next node of the second node in the register ring. Or, if the destination endpoint identifier matches the identifier of the second endpoint, the second node sends the read / write request to the second endpoint.

2. The method according to claim 1, wherein After the second node sends the read / write request to the second endpoint, the method further includes: The second node receives a read / write response from the second endpoint. The read / write response includes the result obtained by the second endpoint in processing the read / write request. The second node sends the read / write response to a fourth node. The fourth node is one of the at least one slave nodes, and the fourth node is connected to the first endpoint. The fourth node receives the read / write response. Based on the fact that the destination endpoint identifier in the read / write response matches the identifier of the first endpoint, the fourth node sends the read / write response to the first endpoint.

3. The method according to claim 1, characterized in that, The register bus system includes a register bus interface, which is respectively connected to the first endpoint, the first node, a memory interface, and a network interface. Before the first node receives a read / write request from a first endpoint connected to the first node, the method further includes: The register bus interface intercepts the read / write request of the first endpoint. If the destination endpoint identifier in the read / write request matches the identifier of any one of the multiple endpoints, the register bus interface sends the read / write request to the first node. If the destination endpoint identifier in the read / write request does not match the identifier of each of the multiple endpoints, the register bus interface sends the read / write request to the memory interface or the network interface.

4. The method according to claim 1, characterized in that, The register bus interface sends the read / write request to the first node, including: If the width of the read / write request is greater than the width of the register bus interface, the register bus interface slices the read / write request according to the width of the register bus interface to obtain a plurality of micro-pieces; The register bus interface sends the plurality of micro-pieces to the first node.

5. The method according to claim 1, wherein After the second node sends the read / write request to the third node, the method further includes: In the case where the destination endpoint identifier does not match the identifier of each of the plurality of endpoints, the first node receives the read / write request sent by the previous node of the first node in the register ring; The first node deletes the read / write request and outputs an error signal.

6. The method according to claim 1, wherein The at least one master node is connected in series, the at least one master node is adjacent in position in the register ring, the first master node in the data transmission direction among the at least one master node is used to delete the read / write request whose destination endpoint identifier does not match the identifier of each of the plurality of endpoints, and the last master node in the data transmission direction among the at least one master node is used to delete the read / write response whose destination endpoint identifier does not match the identifier of each of the plurality of endpoints.

7. The method according to claim 1, wherein After the second node receives the read / write request, the method further includes: If it is detected that the second endpoint is powered off, the second node cancels the step of matching the destination endpoint identifier with the identifier of the second endpoint, sends the read / write request to the third node, and sends a response signal to the first node, where the response signal indicates that the second endpoint is unavailable.

8. A register access system, characterized in that, The register bus system includes a register ring and a plurality of endpoints. The register ring includes a plurality of nodes, the plurality of nodes include at least one master node and at least one slave node, the plurality of endpoints include at least one master endpoint and at least one slave endpoint, the at least one master node is respectively connected to the corresponding master endpoint among the at least one master endpoints, the at least one slave node is respectively connected to the corresponding slave endpoint among the at least one slave endpoints, the at least one master endpoint includes a coherence manager CM and a debugging unit, the at least one slave endpoint includes a CPU core, a CPC, a GCR, a GIC, and an IO device, and the plurality of nodes include a first node and a second node; The first node is configured to receive a read / write request from a first endpoint connected to the first node. The first node is one of the at least one master nodes, the first endpoint is one of the at least one master endpoints, the read / write request includes a destination endpoint identifier, and the destination endpoint identifier is used to identify the register to be read / written by the first endpoint; Send the read / write request to a second node, where the second node is the next node of the first node in the register ring, and the second node is connected to a second endpoint. The second node is configured to receive the read / write request. If the destination endpoint identifier does not match the identifier of the second endpoint, the second node sends the read / write request to a third node, where the third node is the next node of the second node in the register ring; or, if the destination endpoint identifier matches the identifier of the second endpoint, the second node sends the read / write request to the second endpoint.

9. A computing device, characterized in that, The computing device includes: a processor, the processor is coupled to a memory, and at least one computer program instruction is stored in the memory. The at least one computer program instruction is loaded and executed by the processor to enable the computing device to implement the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, At least one instruction is stored in the storage medium. When the instruction runs on a computer, the computer is caused to execute the method according to any one of claims 1-7.

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