Controller and device
By introducing a reorder module and a cache module into the controller, low-priority devices are allowed to perform memory operations without interrupting data transmission of high-priority devices, solving the problem of low data operation efficiency of external devices in memory and achieving more efficient memory resource utilization.
Patent Information
- Application Number
- CN202510465543.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-11
- Publication Date
- 2025-08-01
AI Technical Summary
In the prior art, external devices have problems such as large memory access delay and low data operation efficiency when performing data operations in memory through low priority channels.
A controller is adopted, which includes multiple channels and transmission control modules. Through the rearrangement module and the cache module, the low-priority device allows data operations in memory without interrupting the data transmission of high-priority device, and uses the cache information of the cache module to determine the maximum duration for which the device can stop memory operations.
The memory data operation efficiency of low-priority devices is improved, data transmission interruption of high-priority devices is avoided, memory data operation efficiency of high-priority devices is guaranteed, resource utilization is rational, and overall memory data operation efficiency is improved.
Smart Images
Figure CN120407463A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technologies, and particularly to controllers and devices. Background Art
[0002] Currently, some controllers, such as DMA (Direct Memory Access) controllers, can independently control data transmission. Through these controllers, external devices can directly perform data operations (such as data reading and writing operations) in memory without the intervention of the CPU (Central Processing Unit). In this way, direct data transmission between external devices and computer memory is achieved, greatly improving the data transmission efficiency and reducing the burden on the CPU.
[0003] Currently, in some technologies, these controllers include multiple channels. Each channel supports independent configuration and operation. Multiple different external devices can perform data operations in memory through different channels. However, during data operations, these external devices need to queue according to channel priorities and perform data operations in memory sequentially. This results in a large memory access latency when external devices perform data operations in memory through low-priority channels, and the data operation efficiency is low. Summary of the Invention
[0004] This application provides a controller and a device to at least solve the problem of low efficiency of memory data operations in related technologies.
[0005] This application provides a controller, and the controller includes:
[0006] Multiple channels, through which external devices perform data operations in the memory of the device where the controller is located, and at least some of the channels have different priorities;
[0007] A transmission control module, including a rearrangement module and a cache module, where the cache module is used to cache data operated by the external devices in the memory, and the rearrangement module is used to perform the following control:
[0008] When a first external device performs data operations in the memory through a first channel, if a second external device sends a data operation request through a second channel, and the priority of the second channel is lower than that of the first channel, then according to the cache information of the cache module, determine a first maximum duration during which the first external device can stop memory operations without interrupting data transmission. If the first maximum duration is not less than a first memory operation duration required by the second external device, then control the second external device to perform data operations in the memory.
[0009] In the technical solutions of some embodiments of the present application, when the maximum first duration for the first external device to stop memory operations is not less than the first memory operation duration required by the second external device, the second external device is controlled to perform data operations in the memory. On the one hand, when the first external device with a high channel priority performs memory data operations, it can ensure that some second external devices with a low channel priority can also perform memory data operations, thus solving the problem of low memory data operation rate in some technologies; on the other hand, it can preferentially ensure the memory data operation efficiency of the first external device with a high channel priority and avoid the problem of data transmission interruption of the first external device. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0011] Figure 1 Schematic diagram of the modules of a controller in some technologies;
[0012] Figure 2 Schematic diagram of the modules of a controller provided in some embodiments of the present application;
[0013] Figure 3 Schematic diagram of the modules of a controller provided in some other embodiments of the present application;
[0014] Figure 4 Schematic diagram of the modules of a device provided in some embodiments of the present application;
[0015] Figure 5 Schematic flowchart of a control method provided in some embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0016] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some, rather than all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the protection scope of the present application.
[0017] It should be noted that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. The terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. The terms "parallel", "perpendicular", and "equal" include the described situations and situations similar to the described situations, and the range of the similar situations is within the acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximate parallel, where the acceptable deviation range of approximate parallel can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicular and approximate perpendicular, where the acceptable deviation range of approximate perpendicular can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range of approximate equality can be, for example, that the difference between the two equal ones is less than or equal to 5% of either one. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.
[0018] Before elaborating on the solution of the present application, the relevant principles of memory are first explained. Currently, in some memory technologies, the memory is divided into multiple banks (i.e., independent storage blocks). Each bank can be divided into a first number of rows and a second number of columns, such as 32768 rows and 1024 columns. The storage area composed of all columns in a row can be called a page. When an external device operates on data in the memory, it can first determine the target bank where the data is located. In the target bank, it can determine the target row and target column where the data is located.
[0019] Taking data reading as an example, the working principle of memory is described as follows. Usually, when an external device reads data from memory through a central processing unit or a relevant controller (such as a DMA controller), the central processing unit or the controller will perform an activation operation on the target row according to the target row where the data to be read by the external device is located. After the target row is activated, the data in the target row will be read into the row buffer. If the length of the data to be read by the external device exceeds the length of one row (i.e., one page), the central processing unit or the controller can read the data row by row (i.e., page by page) in the memory. In the case of not reading data row by row (such as only reading part of the data in one row), if the data continuously read by the external device multiple times is located in the same row, then after the first data reading, in the subsequent data reading processes, there is no need to perform the activation operation on the target row again. In this way, the data reading delay can be greatly reduced. If the data continuously read by the external device multiple times is located in different rows of the same bank, then each time data is read, an activation operation needs to be performed on different target rows. Since row activation is time-consuming, the data reading delay will be greatly increased. If the data continuously read by the external device multiple times is located in different banks, since while reading data in one bank, precharging can be performed on other banks (different rows in the same bank cannot be charged simultaneously), the time-consuming of row activation can be reduced. To sum up, compared with reading data in different rows of the same bank, when reading data in different banks, the data reading delay is relatively low.
[0020] Refer to in combination Figure 1 , which is a schematic diagram of the modules of the controller 11 in some technologies. Figure 1 In, the controller 11 includes a transmission control module 111, an arbitration module 112, an interrupt module 113, a configuration module 114, a main bus interface 115, and multiple slave bus interfaces 116.
[0021] The transmission control module 111 includes a peripheral access control module 1111, a memory access control module 1112, and a cache module 1113. The arbitration module 112, the interrupt module 113, and the configuration module 114 are respectively connected to the peripheral access control module 1111 and the memory access control module 1112. The peripheral access control module 1111 and the memory access control module 1112 are respectively connected to the slave bus interface 116 and the cache module 1113. The slave bus interface 116 is connected to the external device 13 and the memory 14 through a bus. The central processing unit 12 is connected to the main bus interface 115 through a bus, and the main bus interface 115 is connected to the configuration module 114.
[0022] Based on the physical connection between the external device 13, the slave bus interface 116, the peripheral access control module 1111 and the memory access control module 1112, the external device 13 can operate data in the memory 14 through the slave bus interface 116, the peripheral access control module 1111 and the memory access control module 1112. At the same time, the controller 11 may also include multiple logical channels. Different external devices 13 can perform data operations (such as data read and write operations) in the memory 14 through different channels. These channels have priorities. If multiple external devices 13 send data operation requests through channels with different priorities, these external devices 13 need to queue up according to the channel priority and perform data operations in the memory 14 in turn, that is, the external device 13 of the high-priority channel will have priority to obtain the right to use the slave bus interface 116 and perform data operations in the memory 14 through the slave bus interface 116. After the external device 13 of the high-priority channel completes the data operation, the external device 13 of the high-priority channel will obtain the right to use the bus interface 116.
[0023] Based on the above description, the process of the external device 13 performing data operations in the memory 14 through the controller 11 can be as follows:
[0024] 1) The central processing unit 12 configures parameters in the configuration module 114, such as the enable parameters of the controller 11 and the interrupt module 113, the source and destination addresses of each channel, the base address of the data required to be operated on by each external device 13 in the memory 14, the maximum data length that can be read or written in a single time to each external device 13 (i.e., the peripheral burst length), and the data length required to be operated on by each external device 13 in the memory 14. The configuration module 114 may include storage units such as registers. These storage units can store the parameters configured by the central processing unit 12.
[0025] 2) External devices 13 initiate data operation requests to arbitration module 112 through their corresponding channels. Based on the channel priority, arbitration module 112 determines the target external device 13 that can currently operate data in memory 14 and sends the target external device 13's data operation request to either peripheral access control module 1111 or memory access control module 1112. Memory access control module 1112 is used to read and write data in memory 14, while peripheral access control module 1111 is used to read and write data in external devices 13. The following describes how to read and write data in memory 14, respectively.
[0026] When the target external device 13 needs to read data from the memory 14, the arbitration module 112 can send the data read request of the target external device 13 to the memory access control module 1112. The memory access control module 1112 can obtain the first base address and the first target data length of the data in the memory 14 from the configuration module 114, and read the data from the memory 14 based on the first base address. If the first target data length exceeds the data length of one page in the memory 14, the data can be read page by page, and the read data can be saved in the cache module 1113. After completing the reading of one page of data, the memory access control module 1112 can update and record the new data read address, so that when reading data next time, the data reading starts from the new data read address. At the same time, record the length of the data that has been read, so as to judge whether the length of the read data reaches the first target data length. If after continuous multiple data readings, the length of the data read from the memory 14 reaches the first target data length, the memory access control module 1112 can send a message to the interrupt module 113. The interrupt module 113 can return a response to the central processing unit 12 to indicate that the data reading operation of the target external device 13 is completed. At the same time, when the peripheral access control module 1111 detects that there is data in the channel cache of the target external device 13 in the cache module 1113, it can obtain the peripheral burst length of the target external device 13 from the configuration module 114, and write the data into the target external device 13 according to the peripheral burst length. In this way, the operation of reading data from the memory 14 is realized.
[0027] When the target external device 13 needs to write data into the memory 14, the arbitration module 112 may send a data read request of the target external device 13 to the peripheral access control module 1111. The peripheral access control module 1111 may obtain the second base address and the second target data length of the data in the target external device 13 from the configuration module 114, and read the data from the target external device 13 based on the second base address. The read data may be saved in the cache module 1113. After each data read operation from the target external device 13 is completed, the peripheral access control module 1111 may update and record a new data read address, so that when reading data next time, the data reading starts from the new data read address. Meanwhile, the length of the data read from the target external device 13 is recorded. If the length of the data read from the target external device 13 reaches the second target data length, the peripheral access control module 1111 may send a message to the interrupt module 113. The interrupt module 113 may return a response to the central processing unit 12 to indicate that the data write operation of the target external device 13 is completed. Meanwhile, when the memory access control module 1112 detects that there is data in the channel cache of the target external device 13 in the cache module 1113, it may obtain the target address to which the data of the target external device 13 needs to be written from the configuration module 114, and write the data into the memory 14 according to the target address. In this way, the operation of writing data into the memory 14 is realized.
[0028] In Figure 1 In the technology shown, the external device 13 that performs data operations in the memory 14 through the controller 11 is usually a low-speed device, that is, the data write bandwidth and the data read bandwidth of the external device 13 are relatively low. When writing the data in the cache module 1113 into the external device 13 or reading data from the external device 13, it takes a relatively long time. If different external devices 13 queue up according to the channel priority and perform data operations in the memory 14 in turn, and the external device 13 in the low-priority channel cannot perform data operations until the external device 13 in the high-priority channel completes the data operation. On the one hand, there will be a large memory access delay for the external device 13 that performs data operations in the memory 14 through the low-priority channel, and the data operation efficiency is low. On the other hand, the speed of the peripheral access control module 1111 or the memory access control module 1112 for reading and writing data in the memory 14 is relatively fast. Therefore, the peripheral access control module 1111 or the memory access control module 1112 will be idle for a long time, resulting in waste of resources.
[0029] In view of this, the present application provides a controller, which can solve Figure 1 the problem of low memory data operation efficiency in the technology shown, and at the same time, can improve the resource utilization rate of the peripheral access control module and the memory access control module. Referring to Figure 2, is a schematic diagram of the modules of the controller 21 provided for some embodiments of the present application.
[0030] Figure 2 In it, the controller 21 is used to connect at least one external device 23, and includes a transmission control module 211 and multiple channels. As Figure 1 described in the relevant description, the channel can be a logical channel, and the external device 23 performs data operations in the memory of the device where the controller 21 is located through the channel, and at least some of the channels have different priorities. Among them, the device where the controller 21 is located may include, but is not limited to, a server.
[0031] The transmission control module 211 includes a rearrangement module 2114 and a cache module 2113. The cache module 2113 is used to cache the data operated by the external device 23 in the memory 24, such as the data read by the external device 23 from the memory 24, or the data that the external device 23 needs to write into the memory 24. The relevant principle is the same as Figure 1 and will not be elaborated here. The rearrangement module 2114 is used to perform the following control: when the first external device performs data operations in the memory 24 through the first channel, if the second external device sends a data operation request through the second channel, and the priority of the second channel is lower than that of the first channel, then according to the cache information of the cache module 2113, determine the first maximum duration that the first external device can stop the memory operation without interrupting data transmission. If the first maximum duration is not less than the first memory operation duration required by the second external device, then control the second external device to perform data operations in the memory 24.
[0032] Among them, that the first external device does not interrupt data transmission means that the data transmission between the first external device and the cache module 2113 does not interrupt. That the first external device stops the memory operation means that the data of the first external device is no longer transmitted between the cache module 2113 and the memory 24.
[0033] Specifically, when the first external device reads data from the memory 24, that the first external device does not interrupt data transmission means that the operation of writing the data of the first external device cached in the cache module 2113 into the first external device does not interrupt. That the first external device stops the memory operation means that the operation of reading the data of the first external device from the memory 24 into the cache module 2113 stops. Based on Figure 1With reference to the related description, it can be understood that since the data transfer rate between the first external device and the cache module 2113 is relatively slow, and the data transfer rate between the cache module 2113 and the memory 24 is relatively fast, when the first external device reads data from the memory 24, the data to be written to the first external device will be cached in the cache module 2113. In this way, after the first external device stops the memory operation, based on the cached data, data can still be continuously written to the first external device, that is, the first external device does not interrupt the data transfer. If all the cached data is written to the first external device, the first external device will interrupt the data transfer.
[0034] Based on the above description, when the first external device reads data from the memory 24, the above-mentioned first maximum duration can be the duration for all the data of the first external device cached in the cache module 2113 to be written to the first external device. The above-mentioned cache information can include the first data volume read by the first external device from the memory 24 and cached in the cache module 2113. The rearrangement module 2114 can obtain the first data writing bandwidth of the first external device and determine the first maximum duration based on the first data writing bandwidth and the first data volume.
[0035] Furthermore, when the first external device needs to write data to the memory 24, the first external device does not interrupt the data transfer, which means that the operation of reading the data in the first external device into the cache module 2113 is not interrupted. The first external device stops the memory operation, which means that it stops writing the data cached in the cache module 2113 by the first external device to the memory 24. In this way, it is equivalent to the data in the first external device piling up in the cache module 2113. It can be understood that if the cache space of the cache module 2113 is large enough, then after the first external device stops the memory operation, the data transfer of the first external device can be continuously not interrupted until all the data that needs to be written to the memory 24 by the first external device is read into the cache module 2113. Of course, when the cache space of the cache module 2113 is limited, when the cache module 2113 is occupied, the first external device will interrupt the data transfer.
[0036] Based on the above description, when the first external device needs to write data to the memory 25, the above first maximum duration can be the duration required for the cache module 2113 to change from the current state to being fully occupied. The above cache information may include the second remaining cache space in the cache module 2113 that is not occupied. The rearrangement module 2114 can obtain the first maximum duration based on the second data writing bandwidth of the first external device to the cache module 2113 and the second remaining cache space. However, considering that when the second external device reads or writes data in the memory 24, it also needs to write data to the cache module 2113, and this data will also consume a part of the cache space in the cache module 2113. Therefore, the cache space that the first external device can use needs to deduct the cache space consumed by the data of the second external device. In view of this, the rearrangement module 2114 can determine the first maximum duration for the first external device to stop the memory operation based on the following method:
[0037] Obtain the minimum data volume that the second external device needs to read or write in the memory 24;
[0038] Based on the second remaining cache space and the minimum data volume, determine the third remaining cache space that the data in the first external device can occupy;
[0039] Obtain the second data writing bandwidth of the first external device to the cache module 2113;
[0040] Based on the third remaining cache space and the second data writing bandwidth, determine the first maximum duration.
[0041] In this way, the accuracy of the first maximum duration can be ensured.
[0042] The following elaborates on how to determine the first memory operation duration.
[0043] In some embodiments, the rearrangement module 2114 is used to determine the first memory operation duration required by the second external device based on the following method:
[0044] Obtain the first storage address of the data of the first external device in the memory 24, the second storage address of the data of the second external device in the memory 24, and the data reading and writing duration when the second external device reads or writes data in the memory 24;
[0045] Determine the switching duration between the first storage address and the second storage address;
[0046] Based on the data reading and writing duration and the switching duration, determine the first memory operation duration.
[0047] Specifically, based on the first storage address, the first target row in the memory 24 can be determined, and based on the second storage address, the second target row in the memory 24 can be determined. The first target row is the row where the first storage address is located, and the second target row is the row where the second storage address is located. The switching duration can refer to the duration required for switching between the first target row and the second target row. Combining the above descriptions related to the memory, it can be known that if the first target row and the second target row are the same row within the same bank, the switching duration can be shorter; if the first target row and the second target row are different rows within the same bank, the switching duration is relatively long; if the first target row and the second target row are rows in different banks, the switching duration is moderate.
[0048] The data read / write duration of the second external device can be obtained based on the amount of data read / written by the second external device in the memory 24 and the read / write bandwidth. The sum of the data read / write duration and the switching duration can be used as the first memory operation duration.
[0049] In the above embodiments, when determining the first memory operation duration, the switching duration between storage addresses is considered at the same time, and the obtained first memory operation duration is more accurate.
[0050] In this embodiment, if the first maximum duration is not less than the first memory operation duration required by the second external device, the second external device can be controlled to perform data operations in the memory 24. Among them, when the second external device needs to read data from the memory 24, the first memory operation duration refers to the duration of reading the data of the second external device from the memory 24 to the cache module 2113; when the second external device needs to write data to the memory 24, the first memory operation duration refers to the duration of writing the data of the second external device into the memory 24. Since the first memory operation duration is less than the first maximum duration, after the second external device completes the data operation in the memory 24, normal data reading and writing are still carried out between the first external device and the cache module 2113, that is, the operation of reading and writing data by the second external device in the memory 24 does not affect the data operation efficiency of the first external device. After the second external device completes the data operation in the memory 24, the memory operation of the first external device can be triggered, such as continuing to read the data of the first external device from the memory 24 to the cache module 2113, or writing the data of the first external device cached in the cache module 2113 into the memory 24.
[0051] Furthermore, if the first maximum duration is greater than the first memory operation duration required by the second external device, it means that when the second external device operates data in the memory 24, the first external device will have a problem of data transmission interruption. In this case, since the channel priority of the first external device is relatively high, the memory data operation efficiency of the first external device can be preferentially ensured, that is, the second external device is controlled to pause reading or writing data in the memory 24.
[0052] In some embodiments, when the first maximum duration is greater than the first memory operation duration required by the second external device, the data to be operated by the second external device can be divided into multiple data blocks, and within the first maximum duration, only some of the data blocks can be operated. In this way, without affecting the data operation efficiency of the first external device, partial data operations of the second external device are completed, reducing the subsequent data operation duration of the second external device, and also achieving the effect of improving the memory data operation efficiency.
[0053] In some embodiments, before controlling the second external device to operate data in the memory 24, the rearrangement module 2114 can also be used to perform the following control:
[0054] Obtain the second data volume that the second external device needs to read or write in the memory 24 and the first remaining cache space not occupied by the cache module 2113;
[0055] If the second data volume is greater than the first remaining cache space, control the second external device to pause reading or writing data in the memory 24, or control the second external device to read or write data from the memory 24 according to the size of the first remaining cache space.
[0056] In this way, the problem of data operation failure caused by insufficient cache space of the cache module 2113 can be avoided.
[0057] In summary, in the technical solutions of some embodiments of the present application, when the first maximum duration during which the first external device can stop memory operations is not less than the first memory operation duration required by the second external device, control the second external device to perform data operations in the memory 24. On the one hand, when the first external device with a high channel priority performs memory data operations, it can be ensured that some second external devices with a low channel priority can also perform memory data operations, thus solving the problem of low memory data operation rate in some technologies; on the other hand, it can preferentially ensure the memory data operation efficiency of the first external device with a high channel priority and avoid the problem of data transmission interruption of the first external device.
[0058] Refer to Figure 3 for the module schematic diagram of the controller 31 provided in some other embodiments of the present application. Figure 3 In, the controller 31 includes a transmission control module 311, an arbitration module 312, an interrupt module 313, a configuration module 314, a main bus interface 315, and a slave bus interface 316. The transmission control module 311 includes a memory access control module 3112, a peripheral access control module 3111, a cache module 3113, and a rearrangement module 3114. Among them, the functions of the configuration module 314, the main bus interface 315, and the slave bus interface 316 are the same as Figure 1Similarly, details are not described herein.
[0059] Compared with Figure 1 the arbitration module 312 of the present application can, after receiving a data operation request sent by the external device 33, directly forward the data operation request to the rearrangement module 3114 without performing priority judgment. The rearrangement module 3114 can obtain configuration information from the configuration module 314 and, according to the relevant logic in Figure 2 , determine whether it is necessary to trigger the second external device in the low-priority channel to perform a memory data operation when the first external device in the high-priority channel performs a memory data operation. According to the judgment result, the rearrangement module 3114 can control the memory access control module 3112 and the peripheral access control module 3111 to perform data reading and writing.
[0060] Figure 3 In
[0061] if both the first external device and the second external device write data to the memory 34, when the first external device stops executing the data writing operation, obtain the third storage address of the data of the first external device in the memory 34;
[0062] Based on the third storage address, control the data of the second external device and the data of the first external device to be stored in consecutive memory areas.
[0063] For example, assume that storage address A and storage address B are consecutive storage addresses, and storage address B is after storage address A. When the first external device stops executing the data writing operation, its last data is written in storage address A, then the data of the second external device can be written to storage address B. In this way, there is no need to switch the target row in the memory 34, thus greatly improving the writing efficiency of memory data.
[0064] However, considering that the data of the second external device usually has a pre-planned storage address in the memory 34, such as the storage address planned and configured by the central processing unit. After storing the data according to the above method, although the writing efficiency of memory data can be improved, the storage address does not match the planned data storage address of the second external device, which may cause problems such as data loss. In view of this, after the rearrangement module 3114 controls the data of the second external device and the data of the first external device to be stored in consecutive memory areas, the interrupt module 313 is further used to perform the following control:
[0065] Write the fourth storage address of the data of the second external device in the memory 34 to a specified location, so that after the central processing unit in the device where the controller 31 is located obtains the fourth storage address from the specified location, it adjusts the storage address of the data of the second external device in the memory.
[0066] Briefly speaking, after the memory access control module 3112 writes the data of the second external device into the memory 34, the central processing unit adjusts the data of the second external device to the planned storage location. In this way, while improving the writing efficiency of the memory data, it also ensures that the data of the second external device is stored in the planned location, thus avoiding problems such as data loss.
[0067] In some embodiments, if, when the first external device and the second external device have not completed data operations, the third external device sends a data operation request through the third channel, and the priority of the third channel is lower than the priority of the second channel, the rearrangement module 3114 is further configured to perform the following control:
[0068] According to the cache information of the cache module 3113, determine the second maximum duration for which the first external device can stop the memory operation without interrupting data transmission;
[0069] If the second maximum duration is less than the second memory operation duration required by the second external device and greater than or equal to the third memory operation duration required by the third external device, then control the third external device to perform data operations in the memory 34.
[0070] Briefly speaking, when there are multiple external devices 33 sending data operation requests, it is possible to preferentially ensure the memory data operation efficiency of the first external device with the highest channel priority. Then, among the second external device and the third external device on each low-priority channel, if the memory operation duration required by any external device is less than or equal to the second maximum duration of the first external device, then it is possible to control that external device to perform memory data operations. That is, the external devices on each low-priority channel do not need to queue in the order of channel priority. For example, among the above-mentioned second external device and the third external device, although the channel priority of the third external device is lower than that of the second external device, since the third memory operation duration required by the third external device is less than or equal to the second maximum duration, and the second memory operation duration required by the second external device is greater than the second maximum duration, the third external device can perform memory data operations prior to the second external device. In this way, time resources can be reasonably utilized to further improve the memory data operation efficiency.
[0071] In some embodiments, if, when the first external device and the second external device have not completed data operations, the fourth external device sends a data operation request through the fourth channel, and the priority of the fourth channel is higher than the priority of the first channel, the rearrangement module 3114 is further configured to perform the following control:
[0072] Control the fourth external device to perform data operations in the memory 34 through the fourth channel, and determine the third maximum duration for the fourth external device to stop memory operations without interrupting data transmission according to the cache information of the cache module 3113;
[0073] If the third maximum duration is less than the fourth memory operation duration required by the first external device and greater than or equal to the fifth memory operation duration required by the second external device, then control the second external device to perform data operations in the memory 34.
[0074] In this embodiment, since the channel priority of the fourth external device is the highest, it is necessary to give priority to ensuring the memory data operation efficiency of the fourth external device, that is, the priority of the first external device is reduced. If the fourth memory operation duration required by the first external device is greater than the third maximum duration of the fourth external device, then the first external device can be controlled to stop performing memory data operations. In this way, the memory data operation efficiency of the external device with the highest priority channel is ensured.
[0075] It should be noted that if there is no data operation request sent by other external devices 33 when the first external device performs data operations in the memory 34 through the first channel, then the memory data operations of the first external device can be controlled according to the Figure 1 method. If there is a data operation request sent by other external devices 33, then the memory data operations of each external device can be controlled according to the method of this application.
[0076] Referring to Figure 4 , a module schematic diagram of the device 400 provided in some embodiments of this application. Figure 4 In , the device 400 includes a controller 41. The controller 41 can be one of the above-mentioned controller 31 and controller 21.
[0077] In some embodiments, the device 400 of this application may further include components such as a central processor and a memory. Specifically, the device 400 can be a server or the like.
[0078] Since the device 400 of this application includes a controller 41, it has the same beneficial effects as the above-mentioned controller 31 and controller 21, which will not be elaborated here.
[0079] Referring to Figure 5 , a flowchart of the control method provided in some embodiments of this application. The control method can be applied to the Figure 2 or Figure 3 rearrangement module in. Figure 5 In , the control method includes the following steps:
[0080] Step S501, when the first external device performs data operations in the memory through the first channel, if the second external device sends a data operation request through the second channel and the priority of the second channel is lower than that of the first channel, then according to the cache information of the cache module, determine the first maximum duration for which the first external device can stop the memory operation without interrupting data transmission.
[0081] Step S502, if the first maximum duration is not less than the first memory operation duration required by the second external device, then control the second external device to perform data operations in the memory.
[0082] In some embodiments, the data operation includes reading or writing data in the memory. When the first external device reads data from the memory, the cache information includes the first data volume read by the first external device from the memory and cached in the cache module; determining the first maximum duration for which the first external device can stop the memory operation without interrupting data transmission according to the cache information of the cache module includes:
[0083] Obtain the first data writing bandwidth of the first external device;
[0084] Based on the first data writing bandwidth and the first data volume, determine the first maximum duration.
[0085] In some embodiments, the control method further includes:
[0086] Obtain the second data volume that the second external device needs to read or write in the memory and the first remaining cache space in the cache module that is not occupied;
[0087] If the second data volume is greater than the first remaining cache space, then control the second external device to suspend reading or writing data in the memory, or control the second external device to read or write data from the memory according to the size of the first remaining cache space.
[0088] In some embodiments, the data operation includes reading or writing data in the memory. When the first external device writes data in the memory, the cache information includes the second remaining cache space in the cache module that is not occupied; determining the first maximum duration for which the first external device can stop the memory operation without interrupting data transmission according to the cache information of the cache module includes:
[0089] Obtain the minimum data volume that the second external device needs to read or write in the memory;
[0090] According to the second remaining cache space and the minimum data volume, determine the third remaining cache space that the data in the first external device can occupy;
[0091] Obtain the second data writing bandwidth of the first external device for the cache module;
[0092] Determine a first maximum duration based on a third remaining cache space and a second data write bandwidth.
[0093] In some embodiments, determine a first memory operation duration based on the following method:
[0094] Obtain a first storage address of data of a first external device in memory, a second storage address of data of a second external device in memory, and a data read / write duration when the second external device reads or writes data in memory;
[0095] Determine a switching duration between the first storage address and the second storage address;
[0096] Determine a first memory operation duration based on the data read / write duration and the switching duration.
[0097] In some embodiments, the data operation includes reading or writing data in memory; the control method further includes:
[0098] If both the first external device and the second external device write data in memory, when the first external device stops executing the data write operation, obtain a third storage address of the data of the first external device in memory;
[0099] Control the data of the second external device and the data of the first external device to be stored in continuous memory areas according to the third storage address.
[0100] In some embodiments, if, when the first external device and the second external device have not completed the data operation, a third external device sends a data operation request through a third channel, and the priority of the third channel is lower than the priority of the second channel, the control method further includes:
[0101] Determine a second maximum duration during which the first external device can stop the memory operation without interrupting data transmission according to the cache information of the cache module;
[0102] If the second maximum duration is less than the second memory operation duration required by the second external device and greater than or equal to the third memory operation duration required by the third external device, control the third external device to perform a data operation in memory.
[0103] In some embodiments, if, when the first external device and the second external device have not completed the data operation, a fourth external device sends a data operation request through a fourth channel, and the priority of the fourth channel is higher than the priority of the first channel, the control method further includes:
[0104] Control the fourth external device to perform a data operation in memory through the fourth channel, and determine a third maximum duration during which the fourth external device can stop the memory operation without interrupting data transmission according to the cache information of the cache module;
[0105] If the third maximum duration is less than the fourth memory operation duration required by the first external device and greater than or equal to the fifth memory operation duration required by the second external device, control the second external device to perform data operations in the memory.
[0106] The above has introduced in detail a controller and a device provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.
Claims
1. A controller, characterized in that, For connecting at least one external device, including: A plurality of channels through which the external device performs data operations in the memory of the device where the controller is located, and at least some of the channels have different priorities; A transmission control module, including a rearrangement module and a cache module, where the cache module is used to cache the data operated by the external device in the memory, and the rearrangement module is used to perform the following controls: When a first external device performs a data operation in the memory through a first channel, if a second external device sends a data operation request through a second channel and the priority of the second channel is lower than that of the first channel, then according to the cache information of the cache module, determine a first maximum duration during which the first external device can stop the memory operation without interrupting data transmission. If the first maximum duration is not less than a first memory operation duration required by the second external device, then control the second external device to perform a data operation in the memory.
2. The controller according to claim 1, wherein The data operation includes reading or writing data in the memory. When the first external device reads data from the memory, the cache information includes a first data volume read by the first external device from the memory and cached in the cache module; the rearrangement module is used to determine the first maximum duration during which the first external device can stop the memory operation based on the following method: Obtain a first data write bandwidth of the first external device; Based on the first data write bandwidth and the first data volume, determine the first maximum duration.
3. The controller according to claim 2, characterized in that, The rearrangement module is also used to perform the following controls: Obtain a second data volume that the second external device needs to read or write in the memory and a first remaining cache space in the cache module that is not occupied; If the second data volume is greater than the first remaining cache space, then control the second external device to suspend reading or writing data in the memory, or control the second external device to read or write data from the memory according to the size of the first remaining cache space.
4. The controller according to claim 1, wherein The data operation includes reading or writing data in the memory. When the first external device writes data in the memory, the cache information includes a second remaining cache space in the cache module that is not occupied; The rearrangement module is used to determine the first maximum duration during which the first external device can stop the memory operation based on the following method: Obtain a minimum data volume that the second external device needs to read or write in the memory; According to the second remaining cache space and the minimum data volume, determine a third remaining cache space that the data in the first external device can occupy; Obtain a second data write bandwidth of the first external device for the cache module; Based on the third remaining cache space and the second data write bandwidth, determine the first maximum duration.
5. The controller according to any one of claims 2 to 4, characterized in that The rearrangement module is used to determine the first memory operation duration required by the second external device based on the following method: Obtain a first storage address of data of the first external device in the memory, a second storage address of data of the second external device in the memory, and a data read / write duration when the second external device reads or writes data in the memory; Determine a switching duration between the first storage address and the second storage address; Based on the data read / write duration and the switching duration, determine the first memory operation duration.
6. The controller according to claim 1, characterized in that, The data operation includes reading or writing data in the memory; the rearrangement module is further configured to perform the following control: If both the first external device and the second external device write data in the memory, when the first external device stops executing the data writing operation, obtain a third storage address of data of the first external device in the memory; According to the third storage address, control the data of the second external device and the data of the first external device to be stored in consecutive memory areas.
7. The controller according to claim 6, characterized in that, The controller further includes an interrupt module; after the rearrangement module controls the data of the second external device and the data of the first external device to be stored in consecutive memory areas, the interrupt module is further configured to perform the following control: Write a fourth storage address of data of the second external device in the memory to a specified location, so that after the central processing unit in the device where the controller is located obtains the fourth storage address from the specified location, adjust the storage address of data of the second external device in the memory.
8. The controller according to claim 1, wherein If, when the first external device and the second external device have not completed data operations, a third external device sends a data operation request through a third channel, and the priority of the third channel is lower than the priority of the second channel, the rearrangement module is further configured to perform the following control: According to the cache information of the cache module, determine a second maximum duration for which the first external device can stop the memory operation without interrupting data transmission; If the second maximum duration is less than a second memory operation duration required by the second external device and greater than or equal to a third memory operation duration required by the third external device, control the third external device to perform data operations in the memory.
9. The controller according to claim 1, wherein If, when the first external device and the second external device have not completed data operations, a fourth external device sends a data operation request through a fourth channel, and the priority of the fourth channel is higher than the priority of the first channel, the rearrangement module is further configured to perform the following control: Control the fourth external device to perform data operations in the memory through the fourth channel, and according to the cache information of the cache module, determine a third maximum duration for which the fourth external device can stop the memory operation without interrupting data transmission; If the third maximum duration is less than a fourth memory operation duration required by the first external device and greater than or equal to a fifth memory operation duration required by the second external device, control the second external device to perform data operations in the memory.
10. A device, characterized in that, The device includes the controller according to any one of claims 1 to 9.