Direct memory access control device and control method thereof

Abstract

The invention provides a direct memory access control device and a control method thereof, and relates to the technical field of data storage. A control device for direct memory access comprises a temporary memory used for temporarily storing data blocks of data to be transmitted; the counter is used for counting the data volume of the data blocks stored in the temporary memory and outputting a count value when a preset end condition is met; the write controller is used for writing the data blocks stored in the temporary memory into the target storage module according to the initial write address calculated in the previous batch; and the write address updating module is used for obtaining the initial write address calculated in the current batch according to the initial write address calculated in the previous batch and the count value. According to the technical scheme, the temporary storage is used for data interception, the counter is used for counting, the write controller is used for batch transmission according to the calculated write address, the write address updating module is used for calculating the write address, the data size does not need to be determined in advance, efficiency is high, and cost is low.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and particularly to a control device for direct memory access and a control method thereof. Background Art

[0002] Currently, DMA (Direct Memory Access) is a common function of the chip bus architecture. It can directly access memory and peripherals without the intervention of the CPU or with only a small amount of CPU services, which can release the CPU to handle other tasks and significantly improve data throughput and system efficiency. To implement the DMA function, a dedicated DMA controller (DMAC) is generally required, and the Host (the CPU inside the chip or an external control interface such as PCIe) controls the DMAC to transfer data between memory and peripherals.

[0003] For write operations with a known data volume, the DMAC transfers data between memory and peripherals according to the configuration of the Host. However, if the data volume is unknown, the Host cannot correctly configure the Write DMA Master because the Host itself does not know how much data to write out, and then the Write DMA Master cannot generate the correct hardware operations.

[0004] Taking some systems with dynamic compression or decompression capabilities as an example, the results of dynamic compression or decompression may be related to the input real-time data. Even if the input data volume is the same, as long as the data is not exactly the same, the output data volume may be different, which means that the Host cannot obtain the data volume to be output in advance. If the DMA is controlled by the Host configuration command, the Host must first perform the same dynamic compression processing on the input real-time data to determine the output data volume. Obviously, this will bring a great deal of additional pressure to the system. The more data there is, the more time and resources the system has to consume for compression processing, and the purpose is only to obtain a numerical value. Obviously, the input-output ratio is very low, with low efficiency and high cost. Summary of the Invention

[0005] Based on this, the present invention provides a control device for direct memory access and a control method thereof, realizing high-efficiency and low-cost data transmission.

[0006] According to one aspect of the present invention, a direct memory access control device is provided, including: a temporary memory for temporarily storing data blocks to be transmitted; a counter for counting the data volume of the data blocks stored in the temporary memory and outputting a count value when a preset end condition is satisfied; a write controller for writing the data blocks stored in the temporary memory into a target storage module according to the initial write address calculated in the previous batch; and a write address update module for obtaining the initial write address calculated in the current batch according to the initial write address calculated in the previous batch and the count value.

[0007] According to some embodiments, the temporary memory includes a first temporary memory and a second temporary memory, and the counter includes a first counter and a second counter; wherein, the first counter is used for counting the data volume of the data blocks stored in the first temporary memory and outputting the count value of the first counter as a first count value when a preset end condition is satisfied, and the second counter is used for counting the data volume of the data blocks stored in the second temporary memory and outputting the count value of the second counter as a second count value when a preset end condition is satisfied.

[0008] According to some embodiments, the device further includes: a demultiplexer for: switching the data storage path of the data block when the temporary memory is full; and specifying the data storage path of the data block when each temporary memory is empty, where the data storage path is a corresponding data storage path in one of the temporary memories; a multiplexer for: switching the data source path of the data written into the target storage module when the temporary memory is empty; and specifying the data source path of the data block when each temporary memory is full, where the data source path is a corresponding data source path in one of the temporary memories.

[0009] According to some embodiments, the capacity of the temporary memory is the maximum data volume that can be supported by one hardware bus operation.

[0010] According to some embodiments, the preset end condition is that the count value reaches a preset threshold or it is detected that all data transmissions are completed.

[0011] According to one aspect of the present invention, a control method for accessing memory includes: S1: Activate the control device for direct memory access to obtain data to be transmitted; S2: Store the data to be transmitted byte by byte into the current temporary memory, and use the current counter corresponding to the current temporary memory for counting; S3: When the count value of the current counter reaches a preset threshold, output the count value; S4: In the case where the current batch is 1, write the data block stored in the current temporary memory into the target storage module according to the pre-configured initial write address, obtain the initial write address calculated for the current batch based on the pre-configured initial write address and the count value, and determine whether all data has been transmitted. If so, jump to S6; otherwise, proceed to the next step; S5: In the case where the current batch is greater than 1, write the data block stored in the current temporary memory into the target storage module according to the initial write address calculated for the previous batch, and obtain the initial write address calculated for the current batch based on the initial write address calculated for the previous batch and the count value; S6: Repeat steps S2 - S5 until all data has been transmitted.

[0012] According to some embodiments, before step S2, it further includes: using a demultiplexer to determine the current data storage path; using the temporary memory corresponding to the current data storage path as the current temporary memory.

[0013] According to some embodiments, before step S6, it further includes: using a demultiplexer to determine the current data source path; using the temporary memory corresponding to the current data source path as the current temporary memory.

[0014] According to one aspect of the present invention, an electronic device is provided, which includes: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the method as described above.

[0015] According to one aspect of the present invention, a computer-readable medium is provided, on which a computer program is stored, and when the program is executed by a processor, it implements the method as described above.

[0016] Through the above embodiments provided by the present invention, the data block of the data to be transmitted is stored in the temporary memory, the counter is used to count the amount of data transmitted in each batch, and the temporary memory is used to perform data interception while counting the data volume; the write controller completes the write operation based on the initial write address calculated for the previous batch, and the initial write address of the current batch write operation is obtained by calculation in the previous batch, which can achieve continuous batch transmission; the write address update module calculates the initial write address calculated for the current batch according to the initial write address calculated for the previous batch and the count value, and generates address configuration information in real time according to the dynamic temporary storage. The present invention realizes data transmission without the need to explicitly determine the data volume in advance, with high efficiency and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the present invention.

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exceeding the scope of protection required by the present invention.

[0019] Figure 1 One of the block diagrams of the direct memory access control device provided by the embodiment of the present invention;

[0020] Figure 2 The block diagrams of the read operation and write operation of direct memory access in the background technology;

[0021] Figure 3 Another block diagram of the direct memory access control device provided by the embodiment of the present invention;

[0022] Figure 4 The schematic diagram of the data transmission of the first batch provided by the embodiment of the present invention;

[0023] Figure 5 The schematic diagram of the data transmission of the second batch provided by the embodiment of the present invention;

[0024] Figure 6 The schematic diagram of the data transmission of the third batch provided by the embodiment of the present invention;

[0025] Figure 7 The schematic diagram of the distribution of the storage area after the write operation is completed provided by the embodiment of the present invention;

[0026] Figure 8 The flowchart of the direct memory access control method provided by the embodiment of the present invention;

[0027] Figure 9 The schematic diagram of the structure of the electronic device provided by the embodiment of the present invention.

[0028] Reference Signs:

[0029] 110: Temporary memory; 111: First temporary memory; 112: Second temporary memory; 120: Counter; 121: First counter; 122: Second counter; 130: Write controller; 140: Write address update module; 150: Demultiplexer; 160: Multiplexer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to give a thorough understanding of the embodiments of the present invention. However, those skilled in the art will realize that the technical solutions of the present invention may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be used. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring aspects of the present invention.

[0032] The block diagrams shown in the accompanying drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0033] The flowcharts shown in the accompanying drawings are only exemplary illustrations and do not necessarily include all contents and operations / steps, nor do they necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may be changed according to the actual situation.

[0034] It should be understood that although terms such as first, second, and third may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of the concept of the present invention. As used herein, the term "and / or" includes any one and all combinations of one or more of the associated listed items.

[0035] First, the background technology will be described. The DMAC (Direct Memory Access Controller) realizes the reading and writing of data and is generally divided into independent read and write functions. A simple diagram is as Figure 2 shown.

[0036] Figure 2The middle chip contains a CPU (Central Processing Unit), IP (Intellectual Property Core) A, DDR IP (Double DataRate Intellectual Property Core), and an on-chip bus. Path 1 represents the configuration path, and path 2 represents the data path. DDR is a DDR (Double Data Rate SDRAM) peripheral chip. The DMAC in the figure is the DMA Master. Master means having the ability to initiate data communication actively. Usually, the master is responsible for converting software commands into hardware bus operations. Correspondingly, there is a DMA Slave. The slave is at the opposite end of the master. Usually, the slave receives the hardware bus operations sent by the master passively and accesses the data in the DDR or peripherals according to these operations. For example, there is a DMA Slave in the DDR IP in the figure above.

[0037] If IP A wants to read data from the DDR chip, it can first command the DMAC controlled by the Host (CPU in the chip) to transfer data between the memory and peripherals. Configure the DMAC of IP A using path 1. It can also be considered that only the Read DMA Master needs to be configured at this time. Under the control of this configuration, the DMAC uses path 2 to pass through the on-chip bus and DDR IP, and finally retrieves data from the DDR chip. This is the process of a DMA read operation.

[0038] If IP A wants to write data to the DDR chip, it can first command the Host (CPU in the chip) to configure the DMAC of IP A using path 1. It can also be considered that only the Write DMA Master needs to be configured at this time. Under the control of this configuration, the DMAC uses path 2 to pass through the on-chip bus and DDR IP, and finally writes the data to the DDR chip. This is the process of a DMA write operation.

[0039] That is to say, when writing data to DDR or other peripherals, at least two points must be clear. One is the amount of data to be written, and the other is the address of the area to be written, that is, the storage address. During the actual writing process, usually the Host configures the amount of data, the storage address, and other relevant information to the Write DMA Master in the form of software commands. According to these configurations and other relevant information (such as the address change mode, which is determined by the specific hardware bus protocol), the Write DMA Master converts the write command into a hardware bus operation, such as the write operation of the AXI protocol, that is, the Write DMA Master encapsulates the original data in the hardware bus interface and writes it out.

[0040] If the amount of data is unknown, the Host cannot correctly configure the Write DMA Master, and then the Write DMA Master cannot generate the correct hardware operation.

[0041] Based on this, the present invention proposes a direct memory access control device and its control method.

[0042] The specific implementation manner can refer to the following embodiments.

[0043] Figure 1 It is a block diagram of the direct memory access control device provided by the embodiment of the present invention. As Figure 1 shown, the device includes a temporary memory 110, a counter 120, a write controller 130, and a write address update module 140.

[0044] The temporary memory 110 is used to temporarily store data blocks of data to be transmitted.

[0045] The temporary memory 110 can be any memory that is convenient for data to be stored and retrieved. According to the exemplary embodiment, the temporary memory 110 can be a RAM (Random Access Memory).

[0046] Furthermore, the number of temporary memories 110 can be one or more. When one temporary memory 110 is set, all data is sequentially input / output to / from this memory. In order to maintain the continuity of the overall transmission and improve the transmission efficiency, two or more temporary memories 110 can be set.

[0047] The data to be transmitted is the data that needs to be written to DDR or other peripherals, which can be the original data transmitted from the upper-level system, or the original data transmitted from the upper-level system, after passing through the data processing module required by the system (such as dynamic compression or decompression), to obtain new data. The present invention does not limit this.

[0048] The data to be transmitted is transmitted byte by byte to the temporary memory 110. Limited by the capacity of the temporary memory 110, multiple data blocks are formed. Each data block is a part of the data to be transmitted stored in the temporary memory 110 in each transmission batch.

[0049] The counter 120 is used to count the amount of data in the data blocks stored in the temporary memory 110 and output the count value when a preset end condition is met.

[0050] In order to obtain the amount of data in the temporary memory 110, a corresponding counter 120 must be added to the temporary memory 110 to count the input to the temporary memory 110.

[0051] It should be noted that the initial count of the counter 120 is 0. Each time a byte of data enters the temporary memory 110, the counter 120 is incremented by 1 until the preset end condition is met and then it can be reset to zero.

[0052] The write controller 130 is used to write the data blocks stored in the temporary memory 110 to the target storage module according to the initial write address calculated in the previous batch.

[0053] The main configuration for the write controller 130 to perform the hardware write operation comes from the initial write address calculated in the previous batch, and the write data comes from the temporary memory 110.

[0054] If the current batch is 1, since there is no previous batch, the initial write address calculated in the previous batch is fixed as the initial write address configured by the Host. If the current batch is greater than 1, the initial write address calculated in the previous batch is obtained as the address for the current write operation.

[0055] Furthermore, the initial write address calculated in the previous batch is calculated based on the count value of the counter 120 in the previous batch (batch t - 1) and the initial write address calculated in the batch before the previous batch (batch t - 2).

[0056] According to the exemplary embodiment, the write controller 130 is a Write DMA Master.

[0057] The write address update module 140 is used to obtain the initial write address calculated in the current batch based on the initial write address calculated in the previous batch and the count value.

[0058] As the temporary memory 110 outputs the data to be written in turn, the count value is also synchronously output to the write address update module 140. The write address update module 140 updates the storage address of the DMA write operation according to the initial address configured by the Host and the data volume of each time of the temporary memory 110 (that is, the count value). The updated address is used for the next write operation. It should be emphasized that the initial write address of the write operation in this batch of the present invention is calculated in the previous batch, so as to achieve uninterrupted batch transmission.

[0059] According to the exemplary embodiment, the initial write address calculated in the previous batch is X, the counter 120 starts from 0 and ends, and the count value is 4KB - 1, then the initial write address calculated in the current batch is X + 4096.

[0060] The present invention stores the data block to be transmitted in the temporary memory, uses the counter to count the data volume of each batch of transmission, and performs data volume counting while using the temporary memory for data interception; uses the write controller to complete the write operation based on the initial write address calculated in the previous batch. The initial write address of the write operation in this batch is calculated in the previous batch, and uninterrupted batch transmission can be achieved; uses the write address update module to calculate the initial write address of the current batch according to the initial write address calculated in the previous batch and the count value, and generates the address configuration information in real time according to the dynamic temporary storage. The present invention realizes data transmission without explicitly specifying the data volume in advance, with high efficiency and low cost.

[0061] According to some embodiments, the temporary memory 110 includes a first temporary memory 111 and a second temporary memory 112, and the counter 120 includes a first counter 121 and a second counter 122;

[0062] Among them, the first counter 121 is used to count the data volume of the data block stored in the first temporary memory 111, and when the preset end condition is satisfied, outputs the count value of the first counter 121 as the first count value. The second counter 122 is used to count the data volume of the data block stored in the second temporary memory 112, and when the preset end condition is satisfied, outputs the count value of the second counter 122 as the second count value.

[0063] Specifically, when two temporary memories 110 are set, one of the temporary memories is named the first temporary memory 111, and the other temporary memory is named the second temporary memory 112.

[0064] According to the exemplary embodiment, the two temporary memories receive / output new data in turn by ping-pong operation.

[0065] Correspondingly, a corresponding counter is set for each temporary memory to count the amount of data. That is, the first counter 121 is set to count for the first temporary memory 111, and the second counter 122 is set to count for the second temporary memory 112.

[0066] Correspondingly, in the case of setting multiple temporary memories, it can also be set with reference to this embodiment, and the present invention will not elaborate on this.

[0067] The embodiment of the present invention sets multiple temporary memories and corresponding counters to maintain the continuity of the overall transmission and improve the transmission efficiency.

[0068] According to some embodiments, the apparatus further includes:

[0069] A demultiplexer 150, configured to:

[0070] Switch the data storage path of the data block when the temporary memory 110 is full;

[0071] And

[0072] Designate the data storage path of the data block when each temporary memory 110 is empty, where the data storage path is a corresponding data storage path in one of the temporary memories 110.

[0073] When setting two or more temporary memories 110, in order to switch the path for data to be stored in the temporary memory 110, a demultiplexer 150 needs to be added to coordinate which temporary memory 110 the data is stored in.

[0074] According to an example embodiment, for example, when the current batch is 1, each temporary memory 110 is empty. At this time, the demultiplexer 150 designates the data storage path of the data block, for example, the storage path corresponding to the second temporary memory 112.

[0075] According to an example embodiment, for example, when the current batch is a certain intermediate batch, when a certain temporary memory (for example, the second temporary memory 112) is full, the demultiplexer 150 switches the data storage path of the data block to another temporary memory (for example, the first temporary memory 111). That is to say, the demultiplexer 150 controls two temporary memories to receive data alternately in a ping-pong operation. A multiplexer 160, configured to:

[0076] Switch the data source path of the data written to the target storage module when the temporary memory 110 is empty; and

[0077] Designate the data source path of the data block when each temporary memory 110 is full, where the data source path is a corresponding data source path in one of the temporary memories 110.

[0078] When two or more temporary memories 110 are provided, a multiplexer needs to be added on the output side of the temporary memories 110 to coordinate the output of data from which temporary memory 110.

[0079] According to an exemplary embodiment, for example, when the current batch is a certain intermediate batch, in the case that a certain temporary memory (for example, the second temporary memory 112) is empty, the data source path of the target storage module is switched to another temporary memory (for example, the first temporary memory 111). That is to say, the multiplexer 160 is used to control the two temporary memories to output data alternately in a ping-pong operation.

[0080] According to an exemplary embodiment, for example, when the current batch is a certain intermediate batch and each temporary memory 110 is full, at this time, the data source path of the target storage module is specified through the multiplexer 160, for example, the data source path corresponding to the second temporary memory 112.

[0081] In the embodiment of the present invention, a demultiplexer and a multiplexer are provided to coordinate the data storage path and the data output path, so that the write operation is more orderly and the write operation efficiency is improved.

[0082] According to some embodiments, in the temporary memory 110, the capacity of the temporary memory 110 is the maximum data volume that can be supported by one hardware bus operation.

[0083] In order to ensure the maximum utilization of computing resources, regardless of the number of temporary memories 110 provided, the capacity of each temporary memory 110 is equal to the maximum data volume that can be supported by one hardware bus operation.

[0084] According to an exemplary embodiment, taking the common AXI protocol as an example, the maximum data volume that can be supported by one hardware transmission is 4KB, so the capacity of the temporary memory 110 is set to 4KB.

[0085] According to some embodiments, in the counter 120, the preset end condition is that the count value reaches a preset threshold or it is detected that all data transmissions are completed.

[0086] Specifically, the preset threshold is the upper limit of the capacity of the specified temporary memory 110, for example, 4KB specified in the above embodiment.

[0087] It can be understood that in the case of setting multiple temporary memories 110, the preset threshold can be set to the same value or different values.

[0088] In the case that the preset thresholds of the preset end conditions of multiple temporary memories 110 are set to different values, each satisfies the corresponding preset end condition to end the counting and reset to zero.

[0089] When determining whether all data transmissions are detected, it can be understood that during data transmission, the last data will be accompanied by a valid indication signal for ending. By detecting this indication signal, it can be determined whether all data has been transmitted.

[0090] To provide a more detailed description of the present invention, a specific embodiment is given as follows. Figure 3 As shown, this embodiment uses RAM as temporary storage. In the figure, cnt1 represents the first counter 121, cnt2 represents the second counter 122, ram1 represents the first temporary memory 111, and ram2 represents the second temporary memory 112.

[0091] This embodiment uses the INCR burst type of the AXI protocol, which means that the write address naturally increases as data enters. The Host only needs to configure the starting address corresponding to the first data.

[0092] Assume that the original data passes through the data processing module and will output 10KB of new data. The last data of these new data will be accompanied by a valid indication signal for ending, indicating the end of these 10KB of data.

[0093] During the transmission process, after power-on or the end of a complete DMA write operation, set the values of cnt1 and cnt2 to 0, and set the data paths selected by the demultiplexer and multiplexer to ram1 (obviously, at this time, neither ram1 nor ram2 stores any data). That is to say, the first data is defaultly stored in ram1, and the first batch of write operations is defaultly output from ram1. Since the total data volume is 10KB and the capacity of ram1 is 4KB, ram1 stores the first batch of 4KB of data, and at the same time, the count of cnt1 reaches 4KB - 1 (because counting starts from 0).

[0094] The write address update module uses the count value of cnt1 and the initial write address X configured by the Host to obtain the initial write address X + 4096 for the second write operation. The Write DMA Master performs the first hardware write operation. Among them, the main configurations of the first hardware operation of the Write DMA Master include the 4KB data statistics from cnt1 and the initial write address X configured by the Host, and the multiplexer configures the write data to come from ram1.

[0095] At this time, 6KB of the 10KB of new data remains to be transmitted. The demultiplexer is configured to store the remaining data in ram2. Since the total data volume is 6KB at this time and the capacity of ram2 is 4KB, ram2 stores the second batch of 4KB of data, and at the same time, the count of cnt2 reaches 4KB - 1.

[0096] The write address update module uses the count value of cnt2 and the initial write address of the second write operation to obtain the write address of the third write operation, X + 4096 + 4096 = X + 8192. Write DMAMaster performs the second hardware write operation. Among them, the main configurations of the second hardware operation of Write DMAMaster include the 4KB data statistics from cnt2 and the initial write address X + 4096 of the second write operation. The multiplexer configures the write data to come from ram2.

[0097] At this time, there are 2KB of the 10KB new data remaining to be transmitted. The demultiplexer configures to store the remaining data in ram1. Since the total data volume is 2KB at this time and the capacity of ram1 is 4KB, ram1 stores the 2KB data of the third batch. At the same time, the count of cnt1 reaches 2KB - 1. The last data of the third batch of data will be accompanied by a valid indication signal of ending. Therefore, the main configurations of the third hardware operation of Write DMAMaster include the 2KB data statistics from cnt1 and the initial write address X + 8192 of the third write operation. The multiplexer configures the write data to come from ram1.

[0098] It can be seen that from the perspective of Write DMAMaster, the 10KB data is almost transmitted without interruption. Obviously, the present invention can maximize the transmission efficiency.

[0099] More specifically, the data transmission of the first batch is as Figure 4 shown. The first hardware bus write operation of Write DMAMaster writes out 4KB of data from ram1. The data volume is obtained according to cnt1, that is, 4095 + 1 = 4096, and the initial write address is the initial write address X configured by the Host.

[0100] The data transmission of the second batch is as Figure 5 shown. The second hardware bus write operation of Write DMAMaster writes out 4KB of data from ram2. The data volume is obtained according to cnt2, that is, 4095 + 1 = 4096, and the initial write address is the address calculated by the write address update module at the previous moment, that is, X + 4096.

[0101] The data transmission of the third batch is as Figure 6 shown. The third hardware bus write operation of Write DMAMaster writes out 2KB of data from ram1. The data volume is obtained according to cnt1, that is, 2047 + 1 = 2048, and the initial write address is the address calculated by the write address update module at the previous moment, that is, X + 8192.

[0102] After all 10KB of data is written into the DDR or the peripheral, the distribution of the storage area is asFigure 7 as shown

[0103] It can be seen that after the data arrives at the terminal, starting from address X according to the Host configuration, 10KB of storage is completed, although the Host does not know how much data needs to be stored. According to the conventional DMA write design, the Host needs to issue a data volume configuration of 10KB to the DMAC, and the final distribution of the storage area is the same as the above Figure 1 consistent

[0104] The method embodiments of the present invention will be described below, which can control direct memory access by using the device embodiments of the present invention. For details not disclosed in the method embodiments of the present invention, reference may be made to the device embodiments of the present invention

[0105] Figure 8 shows a flowchart of a method for controlling direct memory access provided by an embodiment of the present invention. As Figure 8 shown, the method includes steps S1 - step S8

[0106] In step S1, start the control device for direct memory access and obtain the data to be transmitted

[0107] Before step S1, it further includes: setting the capacity of the temporary memory according to the hardware bus protocol regulations, for example, equal to the maximum data volume supported by one write transfer

[0108] Before step S1, it further includes: the Host configures the initial write address, which is the initial write address used for the first write transfer after starting the control device for direct memory access

[0109] In step S2, store the data to be transmitted byte by byte into the current temporary memory, and use the current counter corresponding to the current temporary memory to count

[0110] In the case where only one temporary memory is set, store the data to be transmitted byte by byte into the current temporary memory, and the counter corresponding to the temporary memory synchronously counts the data volume when storing the data

[0111] In the case where two or more temporary memories are set, the data to be transmitted is stored into each temporary memory through a demultiplexer in a ping - pong operation, and the counter corresponding to the temporary memory synchronously counts the data volume when storing the data

[0112] In step S3, when the count value of the current counter reaches a preset threshold, output the count value, and determine whether all the data has been transmitted. If so, jump to S6; if not, proceed to the next step

[0113] Among them, the preset threshold is the upper limit of the capacity of the specified temporary memory. That is to say, in step S3, it is judged whether the temporary memory is full. If it is full, it is judged whether all data has been transmitted. If so, it jumps to S6 to end the loop. If not, the subsequent steps are executed. The subsequent steps are to output the data in the current temporary memory, provide the data volume of these data, and generate the initial write address for the next write operation.

[0114] In step S4, when the current batch is 1, according to the pre-configured initial write address, the data block stored in the current temporary memory is written into the target storage module, and the initial write address calculated for the current batch is obtained according to the pre-configured initial write address and the count value.

[0115] This step judges whether it is the first time to output from the temporary memory after starting the direct memory access control device. If so, the initial write address calculated for the current batch is obtained by using the pre-configured initial write address and the count value.

[0116] In addition, it is also necessary to perform the first hardware write operation using the pre-configured initial write address, and the source of the written data is the current temporary memory.

[0117] It should be noted that the hardware write operation and the update of the initial write address can be executed simultaneously or in a sequential order, and the present invention does not limit this.

[0118] In step S5, when the current batch is greater than 1, according to the initial write address calculated for the previous batch, the data block stored in the current temporary memory is written into the target storage module, and the initial write address calculated for the current batch is obtained according to the initial write address calculated for the previous batch and the count value.

[0119] If it is not the first time to output from the temporary memory after starting the direct memory access control device, the initial write address calculated for the current batch is obtained by using the initial write address calculated for the previous batch and the count value.

[0120] In addition, it is also necessary to write the data block stored in the current temporary memory into the target storage module according to the initial write address calculated for the previous batch.

[0121] If it is not the first time to output from the temporary memory after starting the direct memory access control device, the hardware write operation is performed using the initial write address calculated for the previous batch, and the source of the written data is the current temporary memory.

[0122] In the case where only one temporary memory is set, the source of the written data is the current temporary memory.

[0123] In the case where two or more temporary memories are provided, a current temporary memory is determined by a multiplexer, so that data is output from each temporary memory in a ping-pong operation.

[0124] It should be noted that the hardware write operation and the update of the initial write address can be executed simultaneously or in a sequential order, and the present invention does not limit this.

[0125] In step S6, steps S2 - S5 are repeated until all data transmission is completed.

[0126] If a valid end indication signal of the data is detected, all data transmission is completed and the process ends.

[0127] According to some embodiments, before step S2, it further includes:

[0128] Determine the current data storage path by using a demultiplexer;

[0129] Take the temporary memory corresponding to the current data storage path as the current temporary memory.

[0130] When setting two or more temporary memories, in order to switch the path for data to be stored in the temporary memory 110, a demultiplexer needs to be added to coordinate which temporary memory the data is stored in.

[0131] According to an example embodiment, for example, when the current batch is 1 and each temporary memory is empty, at this time, the current data storage path of the data block is specified by the demultiplexer, for example, the storage path corresponding to the second temporary memory, then the second temporary memory is used as the current temporary memory.

[0132] According to an example embodiment, for example, when the current batch is an intermediate batch, in the case where a certain temporary memory (for example, the second temporary memory) is full, the data storage path of the data block is switched to another temporary memory (for example, the first temporary memory) by the demultiplexer, and the first temporary memory is used as the current temporary memory, that is, the demultiplexer is used to control two temporary memories to alternately receive data in a ping-pong operation.

[0133] According to some embodiments, before step S6, it further includes:

[0134] Determine the current data source path by using a demultiplexer;

[0135] Take the temporary memory corresponding to the current data source path as the current temporary memory.

[0136] When setting two or more temporary memories, a multiplexer needs to be added on the output side of the temporary memory to coordinate which temporary memory the data is output from.

[0137] According to an exemplary embodiment, for example, when the current batch is a middle batch, in the case that a certain temporary memory (such as the second temporary memory) is empty, switch the data source path of the target storage module to another temporary memory (such as the first temporary memory), and the first temporary memory serves as the current temporary memory. That is, the multiplexer is used to control the two temporary memories to output data in a ping-pong operation alternately.

[0138] According to an exemplary embodiment, for example, when the current batch is a middle batch and each temporary memory is full, at this time, specify the data source path of the target storage module through the multiplexer. For example, it is the data source path corresponding to the second temporary memory, and then the second temporary memory serves as the current temporary memory.

[0139] The method performs a function similar to that of the device provided above. For other steps, reference can be made to the previous description and will not be elaborated here.

[0140] Figure 9 An electronic device according to an exemplary embodiment of the present invention is shown. The following refers to Figure 9 to describe the electronic device 900 according to this embodiment of the present invention. Figure 9 The displayed electronic device 900 is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present invention.

[0141] As Figure 9 shown, the electronic device 900 is presented in the form of a general-purpose computing device. The components of the electronic device 900 may include but are not limited to: at least one processing unit 910, at least one storage unit 920, a bus 930 connecting different system components (including the storage unit 920 and the processing unit 910), a display unit 940, etc.

[0142] Among them, the storage unit stores program codes, and the program codes can be executed by the processing unit 910, so that the processing unit 910 executes the methods according to various exemplary embodiments of the present invention described in this specification. For example, the processing unit 910 can execute the method as described above.

[0143] The storage unit 920 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 9201 and / or a cache storage unit 9202, and may further include a read-only storage unit (ROM) 9203.

[0144] The storage unit 920 may further include a program / utility 9204 having a set (at least one) of program modules 9205. Such program modules 9205 include but are not limited to: an operating system, one or more application programs, other program modules, and program data. The implementation of a network environment may be included in each or some combination of these examples.

[0145] The bus 930 can represent one or more of several types of bus architectures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of the various bus architectures.

[0146] The electronic device 900 can also communicate with one or more external devices 300 (such as a keyboard, a pointing device, a Bluetooth device, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 900, and / or communicate with any device that enables the electronic device 900 to communicate with one or more other computing devices (such as a router, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 950. Moreover, the electronic device 900 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 960. The network adapter 960 can communicate with other modules of the electronic device 900 through the bus 930. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0147] Through the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software, or can be implemented by a combination of software and necessary hardware. The technical solutions according to the embodiments of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, or a network device, etc.) to execute the above method according to the embodiments of the present invention.

[0148] The software product can adopt any combination of one or more readable media. The readable media can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0149] A computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, in which readable program code is carried. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. The readable storage medium may also be any readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted by any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0150] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and also including conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, executed as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., by connecting through the Internet using an Internet service provider).

[0151] The above computer-readable medium carries one or more programs, which, when executed by a device, cause the computer-readable medium to implement the foregoing functions.

[0152] Those skilled in the art can understand that the above-mentioned modules can be distributed in the device according to the description of the embodiments, or can be correspondingly changed and distributed in one or more devices that are uniquely different from the present embodiment. The modules of the above embodiments can be combined into one module, or further split into multiple sub-modules.

[0153] From the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software, or by a combination of software and necessary hardware. Therefore, the technical solution according to the embodiments of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present invention.

[0154] The exemplary embodiments of the present invention have been specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, arrangements or implementation methods described herein; on the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A control device for direct memory access, characterized in that Comprising: A temporary memory for temporarily storing data blocks of data to be transmitted; A counter for counting the amount of data in the data blocks stored in the temporary memory and outputting a count value when a preset end condition is met; A write controller for writing the data blocks stored in the temporary memory to a target storage module according to an initial write address calculated in the previous batch; A write address update module for obtaining an initial write address calculated in the current batch according to the initial write address calculated in the previous batch and the count value.

2. The device according to claim 1, wherein The temporary memory includes a first temporary memory and a second temporary memory, and the counter includes a first counter and a second counter; Wherein, the first counter is used for counting the amount of data in the data blocks stored in the first temporary memory and outputting the count value of the first counter as a first count value when a preset end condition is met, and the second counter is used for counting the amount of data in the data blocks stored in the second temporary memory and outputting the count value of the second counter as a second count value when a preset end condition is met.

3. The device according to claim 1 or 2, characterized in that, The device further includes: A demultiplexer for: Switching the data storage path of the data block in the case where the temporary memory is full; and Designating the data storage path of the data block in the case where each of the temporary memories is empty, wherein the data storage path is a corresponding data storage path in one of the temporary memories; A multiplexer for: Switching the data source path of the data written to the target storage module in the case where the temporary memory is empty; and Designating the data source path of the data block in the case where each of the temporary memories is full, wherein the data source path is a corresponding data source path in one of the temporary memories.

4. The device according to claim 1, characterized in that, The capacity of the temporary memory is the maximum amount of data that can be supported by one hardware bus operation.

5. The device according to claim 1 or 2, characterized in that, The preset end condition is that the count value reaches a preset threshold or it is detected that all data transmission is completed.

6. A method for controlling direct memory access by using the control device for direct memory access according to any one of claims 1-5, characterized in that, Comprising: S1: Start the control device for direct memory access to obtain the data to be transmitted; S2: Store the data to be transmitted byte by byte into the current temporary memory and use the current counter corresponding to the current temporary memory for counting; S3: When the count value of the current counter reaches a preset threshold, output the count value and determine whether all data transmission is completed. If so, jump to S6; if not, proceed to the next step; S4: In the case where the current batch is 1, write the data block stored in the current temporary memory to the target storage module according to a pre-configured initial write address, and obtain an initial write address calculated in the current batch according to the pre-configured initial write address and the count value; S5: In the case where the current batch is greater than 1, write the data block stored in the current temporary memory to the target storage module according to the initial write address calculated in the previous batch, and obtain an initial write address calculated in the current batch according to the initial write address calculated in the previous batch and the count value; S6: Repeat steps S2 - S5 until all data transmission is completed.

7. The method according to claim 6, wherein Before step S2, it further includes: Determine the current data storage path using a demultiplexer; Use the temporary memory corresponding to the current data storage path as the current temporary memory.

8. The method according to claim 6, wherein Before step S4, it further includes: Determine the current data source path using a demultiplexer; Use the temporary memory corresponding to the current data source path as the current temporary memory.

9. An electronic device, characterized in that, It includes: One or more processors; A storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 6-8.

10. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instruction is executed by a processor, the method according to any one of claims 6-8 is implemented.

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