Data transmission method, device and system and storage medium

Abstract

The invention relates to a data transmission method, device and system and a storage medium. The method is used for a device side, is connected with a host side through PCIe, and comprises the steps that a driver of the device side configures a first descriptor, sends the first descriptor to a DMA of the device side, configures a second descriptor and sends the second descriptor to the DMA under the condition that it is determined that a preset condition is met according to the first descriptor; the DMA sends the target data to the PCIe according to the first descriptor; and when the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a data reading request to the PCIe according to the second descriptor, and when data corresponding to the returned data reading request is received, interrupt information is sent to the host side CPU, so that the CPU reads the target data. According to the embodiment of the invention, the integrity and correctness of data transmission can be ensured, and the data sent by the equipment side and the data read by the host side have consistency.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data processing, and particularly to a data transmission method, apparatus, system, and storage medium. Background Art

[0002] In a computer system, data transmission between a device side and a host side is usually performed through direct memory access (DMA). During the data transmission process, data is communicated through a peripheral component interconnect express (PCIe) bus. The use of DMA can significantly improve the data transmission speed and system efficiency. At the same time, as the underlying transmission channel, PCIe provides reliable high-speed data transmission capabilities. However, in the scenario where DMA writes data from the device side to the host side through PCIe, after DMA receives the completion reply for the write data request sent by PCIe, it will consider the data transmission completed and report an interruption to the central processing unit (CPU) on the host side. However, at this time, the data may not have been written into the system memory on the host side, and there is a situation where DMA reports an interruption to the host side in advance, resulting in the CPU on the host side being unable to read the correct data from the system memory. Summary of the Invention

[0003] In view of this, the present disclosure provides a data transmission method, apparatus, system, and storage medium.

[0004] According to an aspect of the present disclosure, a data transmission method is provided. The method is used for the device side, and the device side is connected to the host side through a peripheral component interconnect express (PCIe) bus. The method includes:

[0005] The driver on the device side configures a first descriptor and sends the first descriptor to the direct memory access (DMA) on the device side;

[0006] When it is determined that a preset condition is met according to the first descriptor, the driver configures a second descriptor and sends the second descriptor to the DMA;

[0007] The DMA sends target data to the PCIe according to the first descriptor, and the PCIe is used to send the target data to a first destination address;

[0008] When the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a read data request to the PCIe according to the second descriptor;

[0009] When the DMA receives the data corresponding to the returned read data request, it sends interrupt information to the central processing unit (CPU) on the host side, causing the CPU to read the target data from the first destination address.

[0010] In a possible implementation, the first descriptor includes a first source address and a first destination address, and the target data is the data corresponding to the first source address;

[0011] The preset condition is that the first source address is the address of the device-side memory and the first destination address is the address of the system memory on the host side.

[0012] In a possible implementation, the second descriptor includes a second source address and a second destination address, and the driver configuration of the second descriptor includes:

[0013] The driver determines an arbitrary address in the system memory on the host side as the second source address;

[0014] The driver determines an arbitrary address in the device-side memory as the second destination address.

[0015] In a possible implementation, the read data request sent by the DMA to the PCIe according to the second descriptor is used to read the data corresponding to the second source address and write the read data back to the second destination address.

[0016] In a possible implementation, the method further includes:

[0017] When the target data has been sent to the PCIe and the second descriptor has not been received, the DMA sends interrupt information to the central processing unit (CPU) on the host side, causing the CPU to read the target data from the first destination address.

[0018] According to another aspect of the present disclosure, a data transmission device is provided. The device is used on the device side, and the device side is connected to the host side through a high-speed serial bus PCIe. The device includes:

[0019] A first configuration module, configured to configure the first descriptor by the driver on the device side and send the first descriptor to the direct memory access (DMA) on the device side;

[0020] A second configuration module, configured to configure the second descriptor by the driver and send the second descriptor to the DMA when it is determined that the preset condition is met according to the first descriptor;

[0021] A first sending module, configured to send the target data to the PCIe according to the first descriptor, and the PCIe is configured to send the target data to the first destination address;

[0022] A second sending module, configured to, when the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a read data request to the PCIe according to the second descriptor;

[0023] A third sending module, configured to, when the DMA receives the data corresponding to the returned read data request, send interrupt information to the central processing unit (CPU) on the host side, so that the CPU reads the target data from the first destination address.

[0024] In a possible implementation manner, the first descriptor includes a first source address and a first destination address, and the target data is the data corresponding to the first source address;

[0025] The preset condition is that the first source address is the address of the memory on the device side and the first destination address is the address of the system memory on the host side.

[0026] In a possible implementation manner, the second descriptor includes a second source address and a second destination address, and a second configuration module is configured to:

[0027] The driver determines an arbitrary address in the system memory on the host side as the second source address;

[0028] The driver determines an arbitrary address in the memory on the device side as the second destination address.

[0029] In a possible implementation manner, the read data request sent by the DMA to the PCIe according to the second descriptor is used to read the data corresponding to the second source address and write the read data back to the second destination address.

[0030] In a possible implementation manner, the apparatus further includes:

[0031] A fourth sending module, configured to, when the target data has been sent to the PCIe and the second descriptor has not been received, the DMA sends interrupt information to the central processing unit (CPU) on the host side, so that the CPU reads the target data from the first destination address.

[0032] According to another aspect of the present disclosure, a data transmission system is provided. The system includes a device side and a host side, and the device side and the host side are connected through a high-speed serial bus PCIe.

[0033] The driver on the device side is configured to:

[0034] Configure a first descriptor and send the first descriptor to the direct memory access (DMA) on the device side;

[0035] When it is determined that the preset condition is satisfied according to the first descriptor, configure a second descriptor and send the second descriptor to the DMA;

[0036] The DMA is configured to:

[0037] Send target data to PCIe according to the first descriptor;

[0038] When the target data has been sent to PCIe and the second descriptor is received, send a read data request to PCIe according to the second descriptor;

[0039] When the data corresponding to the returned read data request is received, send interrupt information to the central processing unit (CPU) on the host side;

[0040] The CPU is used for:

[0041] In response to receiving the interrupt information, read the target data from the first destination address;

[0042] PCIe is used for:

[0043] Send the target data to the first destination address.

[0044] In a possible implementation, the first descriptor includes a first source address and a first destination address, and the target data is the data corresponding to the first source address;

[0045] The preset condition is that the first source address is the address of the device-side memory and the first destination address is the address of the host-side system memory.

[0046] In a possible implementation, the second descriptor includes a second source address and a second destination address. Configuring the second descriptor includes:

[0047] The driver determines an arbitrary address in the host-side system memory as the second source address;

[0048] The driver determines an arbitrary address in the device-side memory as the second destination address.

[0049] In a possible implementation, the read data request sent by the DMA to the PCIe according to the second descriptor is used to read the data corresponding to the second source address and write the read data back to the second destination address.

[0050] In a possible implementation, the DMA is further used for:

[0051] When the target data has been sent to PCIe and the second descriptor has not been received, send interrupt information to the central processing unit (CPU) on the host side to cause the CPU to read the target data from the first destination address.

[0052] According to another aspect of the present disclosure, a data transmission device is provided, including: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to implement the above method when executing the instructions stored in the memory.

[0053] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein when the computer program instructions are executed by a processor, the above method is implemented.

[0054] According to another aspect of the present disclosure, a computer program product is provided, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0055] According to an embodiment of the present disclosure, by configuring a first descriptor by a driver on the device side, sending the first descriptor to the DMA on the device side, and configuring a second descriptor to be sent to the DMA when it is determined according to the first descriptor that a preset condition is satisfied, the DMA sends target data to the PCIe according to the first descriptor, and the PCIe is used to send the target data to a first destination address. When the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a read data request to the PCIe according to the second descriptor. It is possible to utilize the characteristics of the PCIe and ensure that the target data has been written to the first destination address when the read data request is completed by the software filling in more descriptors under the condition of satisfying the preset condition. On this basis, when the DMA receives the data corresponding to the returned read data request, it sends an interrupt message to the CPU on the host side, enabling the CPU to read the target data from the first destination address, so that the target data can be correctly and completely read by the CPU on the host side from the first destination address, ensuring the integrity and correctness of data transmission, and making the data sent by the device side and the data read by the CPU on the host side consistent.

[0056] According to the following detailed description of exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings, which are included in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the present disclosure together with the specification and are used to explain the principles of the present disclosure.

[0058] Figure 1 A schematic diagram showing data writing from the device side to the host side in the prior art is shown.

[0059] Figure 2 A structural diagram of a data transmission system according to an embodiment of the present disclosure is shown.

[0060] Figure 3 A flowchart of a data transmission method according to an embodiment of the present disclosure is shown.

[0061] Figure 4Schematic diagram showing a descriptor according to an embodiment of the present disclosure.

[0062] Figure 5 Structural diagram showing a data transmission device according to an embodiment of the present disclosure.

[0063] Figure 6 It is a block diagram of a device 1900 for data transmission shown according to an exemplary embodiment. Detailed implementation manners

[0064] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0065] The special term "exemplary" herein means "serving as an example, embodiment or illustration". Any embodiment described herein as "exemplary" does not have to be construed as superior or better than other embodiments.

[0066] In addition, for better illustration of the present disclosure, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some instances, methods, means, elements and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0067] In a computer system, data transmission between the device side and the host side is usually performed through direct memory access (DMA). During the data transmission process, data is communicated through a peripheral component interconnect express (PCIe) bus. The use of DMA can significantly improve the data transmission speed and system efficiency. At the same time, as the underlying transmission channel, PCIe provides reliable high-speed data transmission capabilities. However, referring to Figure 1, showing a schematic diagram of a device writing data to the host side in the prior art. In the scenario where DMA writes data from the device side (Device side) to the host side (Host side) through PCIe, the DMA on the Device side reads data from the device-side memory Device Memory, and then sends the data to PCIe. After the DMA receives the reply (resp) sent by PCIe indicating that the data has been received, it will consider that the data transmission is completed and report an interrupt (irq) to the central processing unit (central process unit, CPU) on the host side through PCIe. After receiving the interrupt, the CPU on the Host side reads the data transmitted by the DMA through PCIe from the system memory (System Memory). However, at this time, the data may not have been written into the system memory on the host side yet. In this case, there may be a situation where the DMA reports an interrupt to the host side in advance, resulting in the CPU on the host side being unable to read the correct data from the system memory.

[0068] In view of this, the present disclosure provides a data transmission method, device, system, and storage medium. In the method of the embodiments of the present disclosure, the driver on the device side configures a first descriptor, sends the first descriptor to the DMA on the device side, and configures a second descriptor to be sent to the DMA when it is determined that a preset condition is met according to the first descriptor. The DMA sends target data to PCIe according to the first descriptor, and PCIe is used to send the target data to the first destination address. When the target data has been sent to PCIe and the second descriptor is received, the DMA sends a read data request to PCIe according to the second descriptor, which can utilize the characteristics of PCIe to ensure that the target data has been written to the first destination address when the read data request is completed by the software filling in more descriptors under the preset conditions. On this basis, when the DMA receives the data corresponding to the returned read data request, it sends interrupt information to the CPU on the host side, enabling the CPU to read the target data from the first destination address, so that the target data can be correctly and completely read by the CPU on the host side from the first destination address, ensuring the integrity and correctness of data transmission, and making the data sent by the device side and the data read by the CPU on the host side consistent.

[0069] Figure 2 Showing a structural diagram of a data transmission system according to an embodiment of the present disclosure. The data transmission system of the embodiments of the present disclosure may include a device side (Device side) and a host side (Host side). As Figure 2As shown, the device side may include a DMA and device memory, where the device memory is a memory or buffer on the device side; the host side may include a CPU and system memory, and the system memory can be used to store data and programs of the computer system. The host side and the device side can perform data transmission and communication through PCIe.

[0070] Among them, the host side can be a terminal device or a server. The terminal device can be any one or more of a mobile phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), and an in-vehicle device; the server can be a physical device.

[0071] The device side can be an external device or an expansion card connected to the host, such as an image capture card, a network adapter, a graphics card, a storage controller, etc.

[0072] The data transmission method of the embodiments of the present disclosure can be applied to Figure 2 the data transmission system shown to achieve data transmission between the device side and the host side. The following is an introduction to the data transmission method of the embodiments of the present disclosure through Figure 3 ,.

[0073] Figure 3 A flowchart showing the data transmission method according to an embodiment of the present disclosure is shown. This method can be used on the device side, and the device side is connected to the host side through PCIe. As Figure 3 shown, this method may include:

[0074] Step S301, the driver on the device side configures a first descriptor and sends the first descriptor to the DMA on the device side.

[0075] Among them, after an upper layer (such as an application layer or a protocol stack) sends a data transmission request to the driver, the driver configures the first descriptor. That is to say, when an upper layer instruction notifies the device side to start a data transmission, the driver on the device side can configure the first descriptor according to the data transmission parameters sent by the upper layer, and then send the first descriptor to the DMA, thereby starting the data transmission process. This data transmission request can be a write data request (for example, writing data from the device side to the host side).

[0076] Figure 4 A schematic diagram of a descriptor according to an embodiment of the present disclosure is shown. As Figure 4As shown, the descriptor may include a source address (such as src_address in the figure), a destination address (such as dst_address in the figure), and the size of the data to be transmitted (such as trans_size in the figure).

[0077] Based on Figure 4 the shown descriptor, the first descriptor may include a first source address (corresponding to Figure 4 src_address in Figure 4 the figure) and a first destination address (corresponding to Figure 4 dst_address in

[0078] Step S302, when it is determined according to the first descriptor that a preset condition is met, drive to configure a second descriptor and send the second descriptor to the DMA.

[0079] In the embodiments of the present disclosure, by the way that the software (i.e., the driver) configures the descriptor (i.e., the second descriptor) one more time when it is determined according to the first descriptor that the preset condition is met, it can be ensured that the target data corresponding to the first descriptor can be correctly and completely read by the host - side CPU subsequently.

[0080] Among them, the driver can determine whether to configure the second descriptor when configuring the first descriptor. Among them, the preset condition may be that the first source address is the address of the device - side memory and the first destination address is the system memory address of the host - side, indicating that data is to be written from the device - side to the host - side.

[0081] The driver can configure the second descriptor after configuring the first descriptor. When it is determined according to the first descriptor that the preset condition is not met (that is, the first source address is not the address of the device - side memory, or the first destination address is not the system memory address of the host - side), the second descriptor may not be configured. In the embodiments of the present disclosure, by having the driver determine whether to configure the second descriptor, data transmission resources can be further saved.

[0082] The second descriptor can be used for the device - side to read data. The second descriptor may include a second source address (corresponding to Figure 4 src_address in Figure 4 the figure) and a second destination address (corresponding to Figure 4(trans_size in the middle). During the process of driving the configuration of the second descriptor, any address in the system memory on the host side can be determined as the second source address, and any address in the device-side memory can be determined as the second destination address. The size of the read data can also be any size.

[0083] For example, by filling in the second descriptor, the above-mentioned 1G target data can be read from the system memory on the host side and stored in the address in the device-side memory. At this time, the second source address can be the address of the system memory on the host side used to store the target data, the second destination address can be the address of the device-side used to receive and store the target data, and the size of the data is 1G.

[0084] Step S303, the DMA sends the target data to the PCIe according to the first descriptor.

[0085] Among them, the DMA can take out the target data from the first source address according to the first descriptor and send the target data to the PCIe.

[0086] After receiving the target data sent by the DMA, the PCIe can be used to send the target data to the first destination address.

[0087] Among them, after receiving the data sent by the DMA, the PCIe will usually directly send a reply to the DMA indicating that the target data has been received. When the DMA receives the reply sent by the PCIe, it will consider that the target data has been transmitted. However, at this time, the target data may not have been written into the first destination address (such as the system memory). If the DMA believes that the data has been transmitted and reports an interruption to the CPU on the host side, the CPU cannot read the correct data from the first destination address. To prevent the above situation from occurring, in the embodiments of the present disclosure, when the first source address is the address of the device-side memory and the first destination address is the system memory on the host side, the device-side driver is configured with the descriptor one more time, which can ensure that all data has been written into the system memory on the host side by software before the DMA sends the interruption information.

[0088] Step S304, when the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a read data request to the PCIe according to the second descriptor.

[0089] Among them, the read data request sent by the DMA to the PCIe according to the second descriptor can be used to read the data corresponding to the second source address and write the read data back to the second destination address.

[0090] Step S305, when the DMA receives the data corresponding to the returned read data request, it sends an interruption message to the CPU on the host side, causing the CPU to read the target data from the first destination address.

[0091] According to an embodiment of the present disclosure, by configuring a first descriptor by a driver on the device side, sending the first descriptor to the DMA on the device side, and configuring and sending a second descriptor to the DMA when it is determined according to the first descriptor that a preset condition is met, the DMA sends target data to the PCIe according to the first descriptor, and the PCIe is used to send the target data to a first destination address. When the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a read data request to the PCIe according to the second descriptor, which can utilize the characteristics of the PCIe. By the way of the software filling in more descriptors under the condition of meeting the preset condition, it is ensured that the target data has been written to the first destination address when the read data request is completed. On this basis, when the DMA receives the data corresponding to the returned read data request, it sends an interrupt message to the CPU on the host side, so that the CPU reads the target data from the first destination address, which can make the target data be correctly and completely read by the CPU on the host side from the first destination address, ensure the integrity and correctness of data transmission, and make the data sent by the device side and the data read by the CPU on the host side consistent.

[0092] In the present disclosure, the characteristics of the PCIe are utilized, that is, the read data request of the PCIe will not start until all write data requests before the read data request are completed. Therefore, in the present disclosure, by sending a read data request to the PCIe, when the DMA receives the data corresponding to the returned read data request, it means that all write data requests before the read data request have been completed, so that it can be ensured that the target data has been written to the system memory on the host side.

[0093] At this time, the CPU can read the target data from the first destination address after receiving the interrupt message. The interrupt message can be used to request the attention of the CPU and cause the CPU to pause the task currently being executed and instead process the task with the interrupt event occurring. In the present disclosure, the task with the interrupt event occurring can be implemented based on the target data. Responding to the interrupt message can enable the CPU to read the written target data from the system memory and execute the corresponding task. The generation method of the interrupt message can be implemented based on the prior art, and the embodiments of the present disclosure do not limit this.

[0094] The method may further include:

[0095] When the target data has been sent to the PCIe and the second descriptor has not been received, the DMA sends an interrupt message to the CPU on the host side, so that the CPU reads the target data from the first destination address.

[0096] This situation may correspond to a situation where a preset condition is not met as determined according to the first descriptor, that is, a situation where the driver is not configured with a second descriptor. At this time, the first source address is not the address of the device-side memory, or the first destination address is not the address of the system memory on the host side.

[0097] Figure 5 The structural diagram of a data transmission device according to an embodiment of the present disclosure is shown. This device can be used on the device side, and the device side can be connected to the host side through PCIe, such as Figure 5 as shown, this device includes:

[0098] A first configuration module 501, configured to drive on the device side to configure a first descriptor and send the first descriptor to the direct memory access (DMA) on the device side;

[0099] A second configuration module 502, configured to, when it is determined according to the first descriptor that the preset condition is met, drive to configure a second descriptor and send the second descriptor to the DMA;

[0100] A first sending module 503, configured to send target data to PCIe according to the first descriptor, and PCIe is configured to send the target data to a first destination address;

[0101] A second sending module 504, configured to, when the target data has been sent to PCIe and the second descriptor is received, the DMA sends a read data request to PCIe according to the second descriptor;

[0102] A third sending module 505, configured to, when the DMA receives the data corresponding to the returned read data request, send interrupt information to the central processing unit (CPU) on the host side, so that the CPU reads the target data from the first destination address.

[0103] In a possible implementation manner, the first descriptor includes a first source address and a first destination address, and the target data is the data corresponding to the first source address;

[0104] The preset condition is that the first source address is the address of the device-side memory and the first destination address is the address of the system memory on the host side.

[0105] In a possible implementation manner, the second descriptor includes a second source address and a second destination address, and the second configuration module 502 is configured to:

[0106] Drive to determine any address in the system memory on the host side as the second source address;

[0107] Drive to determine any address in the device-side memory as the second destination address.

[0108] In a possible implementation, the read data request sent by the DMA to the PCIe according to the second descriptor is used to read the data corresponding to the second source address and write the read data back to the second destination address.

[0109] In a possible implementation, the apparatus further includes:

[0110] A fourth sending module, configured to, when the target data has been sent to the PCIe and the second descriptor has not been received, the DMA sends interrupt information to the central processing unit (CPU) on the host side, so that the CPU reads the target data from the first destination address. In some embodiments, the functions or modules included in the apparatus provided in the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0111] The embodiments of the present disclosure also propose a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above methods are implemented. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0112] The embodiments of the present disclosure also propose a data transmission apparatus, including: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above methods when executing the instructions stored in the memory.

[0113] The embodiments of the present disclosure also provide a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in the processor of an electronic device, the processor in the electronic device executes the above methods.

[0114] Figure 6 It is a block diagram of an apparatus 1900 for data transmission shown according to an exemplary embodiment. For example, the apparatus 1900 can be provided as a server or a terminal device. Referring to Figure 6 , the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by a memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in the memory 1932 can include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above methods.

[0115] Device 1900 may further include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 may operate based on an operating system stored in memory 1932, such as Windows Server TM , MacOS X TM , Unix TM , Linux TM , FreeBSD TM or the like.

[0116] In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as memory 1932 including computer program instructions, and the computer program instructions can be executed by the processing component 1922 of device 1900 to complete the above method.

[0117] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0118] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device, such as a punched card or raised structures in grooves storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage medium as used herein is not construed as being a transitory signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0119] The computer-readable program instructions described herein can be downloaded to various computing / processing devices from a computer-readable storage medium or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0120] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via an Internet service provider through the Internet). In some embodiments, by using the state information of the computer-readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0121] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0122] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises a manufacture including instructions for implementing various aspects of the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0123] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, such that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0124] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a segment of code, or a portion of an instruction, and the module, segment of code, or portion of an instruction may include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the boxes may occur out of the order noted in the figures. For example, two consecutive boxes may, in fact, be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each box in the block diagrams and / or flowcharts, and combinations of boxes in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system for performing the specified functions or acts, or by a combination of dedicated hardware and computer instructions.

[0125] The embodiments of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A data transmission method, characterized in that, The method is used for the device side, and the device side is connected to the host side through a high-speed serial bus PCIe. The method includes: The driver on the device side configures a first descriptor and sends the first descriptor to the direct memory access (DMA) on the device side; When it is determined that a preset condition is met according to the first descriptor, the driver configures a second descriptor and sends the second descriptor to the DMA; The DMA sends target data to the PCIe according to the first descriptor, and the PCIe is used to send the target data to a first destination address; When the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a read data request to the PCIe according to the second descriptor; When the DMA receives the data corresponding to the read data request that is returned, the DMA sends interrupt information to the central processing unit (CPU) on the host side, causing the CPU to read the target data from the first destination address.

2. The method according to claim 1, characterized in that, The first descriptor includes a first source address and the first destination address, and the target data is the data corresponding to the first source address; The preset condition is that the first source address is an address in the memory on the device side and the first destination address is the system memory address on the host side.

3. The method according to claim 1, characterized in that, The second descriptor includes a second source address and a second destination address. The driver configuring the second descriptor includes: The driver determines an arbitrary address in the system memory on the host side as the second source address; The driver determines an arbitrary address in the memory on the device side as the second destination address.

4. The method according to claim 3, wherein The read data request sent by the DMA to the PCIe according to the second descriptor is used to read the data corresponding to the second source address and write the read data back to the second destination address.

5. The method according to claim 1, wherein The method further includes: When the target data has been sent to the PCIe and the second descriptor has not been received, the DMA sends the interrupt information to the central processing unit (CPU) on the host side, causing the CPU to read the target data from the first destination address.

6. A data transmission device, characterized in that, The apparatus is used for the device side, and the device side is connected to the host side through a high-speed serial bus PCIe. The apparatus includes: A first configuration module, configured to enable the driver on the device side to configure a first descriptor and send the first descriptor to the direct memory access (DMA) on the device side; A second configuration module, configured to enable the driver to configure a second descriptor and send the second descriptor to the DMA when it is determined that a preset condition is met according to the first descriptor; A first sending module, configured to send target data to the PCIe according to the first descriptor, and the PCIe is used to send the target data to a first destination address; A second sending module, configured to enable the DMA to send a read data request to the PCIe according to the second descriptor when the target data has been sent to the PCIe and the second descriptor is received; A third sending module, configured to, when the DMA receives the data corresponding to the returned read data request, send interrupt information to the central processing unit (CPU) on the host side, so that the CPU reads the target data from the first destination address.

7. A data transmission system, characterized in that, The system includes a device side and a host side, and the device side and the host side are connected through a high-speed serial bus, PCIe. The driver on the device side is configured to: Configure a first descriptor and send the first descriptor to the direct memory access (DMA) on the device side; When it is determined that a preset condition is satisfied according to the first descriptor, configure a second descriptor and send the second descriptor to the DMA; The DMA is configured to: Send target data to the PCIe according to the first descriptor; When the target data has been sent to the PCIe and the second descriptor is received, send a read data request to the PCIe according to the second descriptor; When the data corresponding to the returned read data request is received, send interrupt information to the central processing unit (CPU) on the host side; The CPU is configured to: In response to receiving the interrupt information, read the target data from the first destination address; The PCIe is configured to: Send the target data to the first destination address.

8. The system according to claim 7, wherein The first descriptor includes a first source address and the first destination address, and the target data is the data corresponding to the first source address; The preset condition is that the first source address is the address of the device-side memory and the first destination address is the system memory address of the host side.

9. A data transmission device, characterized in that, Comprising: A processor; A memory for storing processor-executable instructions; Wherein, the processor is configured to implement the method according to any one of claims 1 to 5 when executing the instructions stored in the memory.

10. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, the method according to any one of claims 1 to 5 is implemented.

11. A computer program product, comprising a computer program or a non-volatile computer-readable storage medium carrying the computer program, characterized in that, When the computer program is executed by the processor, the method according to any one of claims 1 to 5 is implemented.

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