A cache device, data handling method and chip

Abstract

The application relates to the technical field of data transmission, and discloses a cache device, a data carrying method and a chip. The cache device is configured with a first address space and a second address space; the cache device is configured to return data by the cache device when receiving a read instruction for the first address space; and the cache device is further configured to trigger a target cache miss when receiving a read instruction for the second address space, so as to obtain target data of a second storage area through a bus on the chip and carry the target data of the second storage area to a specified storage space. The above scheme can realize the DMA function without increasing the DMA module, so that the chip cost and power consumption are reduced while realizing the DMA function.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, and particularly relates to a cache device, a data carrying method and a chip. BACKGROUND

[0002] Direct Memory Access (DMA) is a technology in a computer system, which allows certain hardware subsystems to directly access the main memory independently of the Central Processing Unit (CPU). The DMA can perform data transmission without occupying CPU resources, improve system efficiency, reduce CPU burden, improve data transmission speed and optimize system performance. However, the DMA module itself has a large area, and the integration of the DMA module on the MCU (Microcontroller Unit) or SOC (System on Chip) pursuing extreme area and cost will significantly increase the cost and power consumption.

[0003] Therefore, there is an urgent need for a low-cost and low-power DMA solution. SUMMARY

[0004] Therefore, the present application provides a cache device, a data carrying method and a chip, which can realize the DMA function while reducing the cost and power consumption of the chip.

[0005] In a first aspect, the present application provides a cache device, wherein a first address space and a second address space are configured on the cache device; the cache device is configured to return data by the cache device when receiving a read instruction for the first address space;

[0006] The cache device is further configured to trigger a target cache miss when receiving a read instruction for the second address space, so as to obtain target data of a second storage area through a bus on the chip, and carry the target data of the second storage area to the specified storage space.

[0007] In an optional embodiment, the device comprises a first function register; the first function register stores an address of the second storage area, an address of the specified storage space and a data carrying length.

[0008] In an optional embodiment, the device further comprises a space judgment module; the space judgment module is configured to receive a read instruction and judge a memory access address in the read instruction; if the memory access address is located in the first address space and the cache miss, a primary cache miss is triggered; if the memory access address is located in the second address space, the target cache miss is triggered.

[0009] In an alternative embodiment, the device further comprises a replacement control module; the replacement control module is configured to receive a cache line load request sent by the space judging module after triggering a target cache miss;

[0010] The replacement control module is configured to read the data of the data length to be moved from the second storage area according to the second storage area address after receiving the cache line load request, and write the data into the specified storage space address.

[0011] In an alternative embodiment, the replacement control module further comprises a current data read address register, a current data storage address register, and a remaining data length counter.

[0012] In a second aspect, a data moving method is provided, which is applied to the cache device described above, and the method comprises:

[0013] When receiving a read instruction for a second address space, triggering a target cache miss, and obtaining target data of a second storage area through a bus on the chip;

[0014] Moving the target data of the second storage area to a specified storage space.

[0015] In an alternative embodiment, the method further comprises:

[0016] Before the target data of the second storage area starts to be moved, returning a target identifier to a processor in the chip.

[0017] In an alternative embodiment, the method further comprises:

[0018] When the moving of the data of the data length to be moved from the second storage area is completed, sending an interrupt notification to the processor in the chip.

[0019] In an alternative embodiment, the method further comprises: receiving a configuration instruction sent by a processor; the configuration instruction comprises an address of a second storage area, an address in a specified storage space, and a data length to be moved.

[0020] Configuring a first function register in the cache device according to the configuration instruction.

[0021] In a third aspect, a chip is provided, wherein the chip is provided with the cache device described above.

[0022] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium has stored thereon computer instructions for causing the cache device to perform the data transfer method described above.

[0023] The technical solutions provided in the application can have the following beneficial effects.

[0024] In the application, the cache device is configured to return data when a read instruction for the first address space is received, that is, when a read instruction for the first address space is received and a cache miss occurs, a normal cache miss is triggered, at this time, the data in the first storage area is obtained through a bus on the chip and is transferred to the cache device according to the processing flow of the normal cache miss, and then the data is returned to the CPU, and if a cache hit occurs, the data cached in the cache device is directly returned to the CPU; and in addition to the normal cache miss function, the processing function and logic of the cache miss are also reused, that is, the cache device is configured to trigger a target cache miss when a read instruction for the second storage area is received, so as to obtain target data of the second storage area through the bus on the chip and transfer the target data of the second storage area to a specified storage space; after the cache miss mechanism is triggered, the target data of the second storage area can be transferred through the bus on the chip without the intervention of the CPU, at this time, the cache device can directly transfer the obtained data to the specified storage space, thereby realizing the function of DMA. The above scheme can realize the function of DMA without increasing the DMA module, thereby realizing the function of DMA while reducing the cost and power consumption of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 A low-cost and low-power-consumption MCU system architecture diagram is shown.

[0027] Figure 2 A structural schematic diagram of a cache device is shown.

[0028] Figure 3 A Cache function architecture diagram in an embodiment of the present application is shown.

[0029] Figure 4 A Cache function architecture diagram related to the embodiments of the present application is shown.

[0030] Figure 5 A method flow chart of a data carrying method related to the embodiments of the present application is shown.

[0031] Figure 6 A method flow chart of a cache device related to the embodiments of the present application is shown.

[0032] Figure 7 A structure schematic diagram of a chip provided by the optional embodiments of the present application is shown. DETAILED DESCRIPTION

[0033] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0034] In the description of the embodiments of the present application, the term "corresponding" can represent a direct or indirect corresponding relationship between two, can also represent an associated relationship between two, or can be a relationship of indication and being indicated, configuration and being configured, etc.

[0035] Figure 1 A low-cost and low-power MCU system architecture diagram is shown. As shown in Figure 1 In the processing of the CPU, data can be acquired through the Cache. On the other hand, a DMA module is also provided in the MCU. The DMA can perform data transmission without occupying CPU resources, thereby improving system efficiency and reducing the burden of the CPU. However, the area of the general DMA module itself is relatively large. Therefore, in the MCU pursuing the ultimate area and cost, integrating the DMA module will increase the complexity, area and power consumption of the circuit.

[0036] Figure 2 A structure schematic diagram of a cache device is shown. As shown in Figure 2 The cache device is configured with a first address space and a second address space. The first address space and the second address space can be for a space mapping relationship of a virtual space. The cache device is configured to return data by the cache device when receiving a read instruction for the first address space, acquire data in a first storage area on the bus on the chip and carry the data to the cache device, and then return the data to the CPU.

[0037] The cache device is also configured to trigger a target cache miss when receiving a read instruction for the second address space, so as to obtain target data of the second storage area through the bus on the chip and move the target data of the second storage area to the designated storage space.

[0038] Optional, such as Figure 2 As shown, the first storage area and the second storage area are both located in an external storage outside the chip. When a read instruction for the first address space is received, it can be determined whether the cache hits; if the cache hits, the data cached in the cache device is directly returned; if the cache misses, the original cache miss is triggered, and the data in the first storage area in the external storage can be obtained through the external storage controller, and moved to the cache device, and then the data is returned to the CPU for use; and when the chip triggers a target cache miss, the data in the second storage area in the external storage can be obtained through the external storage controller, and moved to a designated storage space outside the cache device, such as an off-chip storage space or Figure 2 The on-chip system SRAM (Static Random-Access Memory) in the .

[0039] Optionally, in an embodiment of the present application, the cache device may be a Cache, which is configured with a designated address space (including a first address space and a second address space). The designated address space may be used to trigger the CacheMiss mechanism of the Cache. Once the cache device receives a read instruction for the designated address space, if the designated address space data has not been cached, the CacheMiss mechanism of the Cache will be triggered.

[0040] A "cache miss" (also known as a cache miss) occurs when the requested data is not in the cache and must be retrieved from the next-level cache or even slower next-level storage, resulting in additional access latency and performance overhead. In a cache miss mechanism, the data retrieval process is completely automated by the cache controller in hardware. The CPU does not need to execute additional instructions or microcode to coordinate this process; it simply waits for the data to be returned. Therefore, the cache miss mechanism can be used to implement DMA functionality, allowing data transfer without consuming CPU resources, improving system efficiency and reducing CPU burden.

[0041] Data transfer requirements mainly include instruction transfer and data transfer. The instruction transfer is loading from external storage to Cache storage space. The data transfer refers to loading from external storage to a specified storage space, such as on-chip system SRAM or off-chip storage space.

[0042] However, in the Cache Miss mechanism, when data is transferred from the next level of cache or slower next level of storage (off-chip storage in the embodiment of the present application), the data is directly stored in the Cache storage space. Therefore, in the embodiment of the present application, the Cache needs to be configured to directly transfer and store data from the second storage area off-chip to the specified storage space (optionally, the specified storage space in the embodiment of the present application can be on-chip system SRAM), thereby realizing a function similar to DMA data transfer (for convenience of description, this function similar to DMA data transfer is referred to as DMA function in the embodiment of the present application, and it should be noted that the cache device in the embodiment of the present application does not have a DMA module).

[0043] Figure 3 A Cache function architecture diagram in the embodiment of the present application is shown. As shown in Figure 3 , the Cache function architecture includes a Cache configuration register, a Cacheable space judgment module, a Cache storage space, and a replacement control module. Optionally, the Cache in the embodiment of the present application can be an instruction cache or a data cache.

[0044] The Cache configuration register is configured to configure the basic functions of the Cache.

[0045] The Cacheable space judgment module is configured to judge whether the address accessed by the current memory access operation is a cacheable space. If it is judged that the current memory access operation accesses a cacheable space, the memory access address is sent to the main Cache address mapping module. If it is judged that the current memory access operation does not access a cacheable space, the memory access operation directly accesses the corresponding non-cacheable space through the bus interface, such as the configuration space of the system peripheral.

[0046] Optionally, the space judgment module further includes a main Cache address mapping conversion module configured to judge whether the cacheable space currently accessed has been cached in the Cache storage space. If yes, a Cache Hit occurs, the data is obtained from the Cache storage space and returned to the CPU. If not, a Cache Miss occurs, and the access address is sent to the replacement control module.

[0047] The replacement control module is configured to retrieve the missing data from the next level cache or the slower next level storage space when a cache miss occurs. Generally, it retrieves the data / instructions of the entire cacheline (cache line, generally 16 bytes, 32 bytes in length, etc.) where the missing data is located, and then writes it to the cache storage space according to the cache replacement strategy, and then returns the data to the CPU.

[0048] Figure 4 Schematic diagram of the Cache function architecture involved in the embodiment of the present application is shown. Figure 4 As shown, further, in order to realize the above-mentioned DMA function based on the original Cache function, it is necessary to set a first function register in the device; the first function register stores the address of the second storage area, the address of the specified storage space and the length of the transferred data.

[0049] That is, in the embodiment of the present application, it is necessary to add relevant configurations of the DMA function in the DMA configuration register of the cache (that is, the first function register), which needs to include the starting address of the data in the external storage (that is, the address in the second storage area), the starting address of the target SRAM storage space (the address in the specified storage space), and the length of the original data to be transferred (that is, the length of the transferred data).

[0050] In an embodiment of the present application, the cache further includes a second space address register for storing a starting address of the second address space and an ending address of the second address space. In an optional implementation of the embodiment of the present application, the first function register may include the second space address register to store the starting address of the second address space and the ending address of the second address space.

[0051] Optionally, the DMA configuration register can also be used to configure the DMA function switch and the DMA interrupt status register. Enabling the DMA function can be independent of the existing cache function and is not affected by the cache enable control. The DMA interrupt status register can be used to indicate whether DMA data transfer is complete.

[0052] Furthermore, in order to stably trigger the Cache Miss function of the Cache, the device also includes a space judgment module; the space judgment module is configured to receive a read instruction and judge the memory access address in the read instruction; if the memory access address is located in the first address space and the cache misses, the original cache miss is triggered; if the memory access address is located in the second address space, the target cache miss is triggered.

[0053] In the embodiment of the present application, when the DMA function configuration is completed and the DMA function is enabled, the space judgment module monitors the access address sent by the CPU, and if the access address is located in the Cacheable space configured by the DMA function, a Cache Miss is generated, a Cacheline loading request is sent to the replacement control module, and Cacheline loading is performed.

[0054] Specifically, in the embodiment of the present application, the replacement control module is specifically configured to receive the Cacheline loading request sent by the space judgment module after triggering the target cache miss;

[0055] The replacement control module is configured to read the data of the carrying data length from the second storage area address and write the data into the specified storage space address after receiving the Cacheline loading request.

[0056] Therefore, the original replacement control module reads the Cacheline data in the off-chip storage missing back and writes the data into the Cache storage space according to the Cache replacement strategy. After the DMA function is added, the replacement control module can load the data of a preset length from a preset address in the external storage space according to the data carrying configuration of the DMA, and sequentially write the data into the target address space in the on-chip SRAM, so as to realize the function of the DMA through the Cache.

[0057] In order to realize the function of the replacement control module, the replacement control module can further include a current data read address register, a current data storage address register and a remaining data length counter in addition to the original Cacheline loading control logic and a Cacheline buffer (a buffer for buffering the Cacheline). Compared with the area of the DMA module, the increase of the logic area of the replacement control module is basically negligible.

[0058] After the DMA function configuration is completed, the CPU executes a Load instruction to read a data from the original data start address in the second storage space, triggers a Cache miss, and starts the DMA data carrying process. Thereafter, the Cache can return the data corresponding to the Load address to the CPU as the execution result of the Load instruction, without blocking the CPU instruction execution. The Load instruction is only used as an operation for starting the DMA function.

[0059] In the embodiment of the present application, the system further includes the Cache interrupt for identifying the completion of the DMA data carrying. After the DMA carrying of all the data is completed, the interrupt is sent to the CPU, the CPU processes the Cache interrupt, and starts the subsequent processing of the carried data in the SRAM.

[0060] In the embodiments of the present application, the above logic can be implemented by the following two ways to realize specific data carrying processing:

[0061] Way one, the Cacheline buffer will be in the replacement control module of the Cache, which can be reused. Each time data is carried, the Cacheline length is processed, for example, the Cacheline length is 16 Byte data. Each time, 16 byte data is read back from the external storage in turn and stored in the Cacheline Buffer, and then the 16 byte data is taken out from the Cacheline buffer and written to the target space of the on-chip target SRAM through the bus Master interface of the Cache.

[0062] Among them, the Cacheline Buffer is a special buffer in the Cache replacement control module for receiving the entire Cacheline data returned from the next level cache or slower next level storage. When a Cache Miss occurs, the buffer first receives the complete Cacheline (for example, 16 Byte or 32 Byte, etc.), and then writes it into the Cache storage space. Therefore, in way one, the buffer can be reused for DMA function. At this time, the replacement control module can read from the external storage by Cacheline size first, the data read back to the Cacheline Buffer, and then write the entire Cacheline data to the target space of the on-chip target SRAM through the bus Master interface of the Cache.

[0063] Way two, the replacement control module retrieves one data at a time, such as 1 Word, 4 Bytes, without going through the Cacheline Buffer, and directly writes to the target space of the SRAM.

[0064] In way two, the replacement control module can bypass the Cacheline Buffer. In the Cache replacement control module, one unit granularity data (for example, 4 Byte) is read from the external storage at a time, and is directly written to the SRAM corresponding address through the bus Master interface of the Cache, without first buffering the entire Cacheline.

[0065] The above two carrying modes can be selected according to the actual data length to be carried, and one of the two modes can be selected or the two modes can be combined for use. Specifically, in an optional embodiment of the present application, only the data carrying mode one or only the data carrying mode two can be directly selected. Generally, carrying data according to mode one can significantly reduce the pressure of writing data into the target space of the on-chip target SRAM. However, in the process of carrying data by mode one, the size of the data to be carried is not an integer multiple of the Cacheline length, for example, after carrying a certain length of Cacheline data, if the remaining data to be carried is 8 bytes, the Cacheline Buffer does not need to be used, and mode two is directly switched to, and the remaining 8 bytes of data is carried into the target space of the on-chip target SRAM according to mode two.

[0066] Through the above configuration, the cache device in the embodiment of the present application can have the following logic:

[0067] Firstly, the cache device has a conventional Cache function, such as Cache Hit and Cache Miss processing, which is performed according to normal logic. When no Cache Miss occurs in the conventional Cache function, the DMA function can be normally performed according to the above logic.

[0068] However, if the conventional Cache Miss is being processed at present, even if the cache device receives a Load instruction for starting DMA at this time, the DMA function is not started.

[0069] However, if a Cache Miss corresponding to the DMA function occurs, that is, data carrying is being performed, and a Cache Miss of the conventional Cache function also occurs at this time, after the DMA completes the carrying of data of the current Cacheline (read and write according to Cacheline) or single data (read and write according to single data), the DMA function is paused, the replacement control module saves the DMA transmission state, and the conventional Cache Miss is preferentially processed to ensure the performance of the CPU.

[0070] This function saves the state of the current DMA transmission through the DMA intermediate state saving register of the replacement control module, then starts processing the conventional Cache Miss, after the processing is completed, the state in the DMA intermediate state saving register is restored to the control register of the replacement control module, the DMA transmission state is restored, and the data carrying of the DMA is continued.

[0071] If the Cacheable space of the DMA function overlaps with the Cacheable space of the original function, when the CPU sends a Load instruction to start the DMA function, the space accessed by the Load instruction should not fall in the Cacheable space of the original function; if the data space read by the DMA is a subset of the Cacheable space of the original function, the normal function of the Cache can be suspended first, that is, the normal Cache function is suspended, then the DMA transfer is started by the Load instruction, and then the Cache is started, so that the DMA transfer is not affected, and the performance of the CPU is also hardly affected.

[0072] After the DMA function is started, once a DMA Cache Miss occurs, the DMA data loading is started, and thereafter, all subsequent access operations to the second address space are processed according to the normal Load instruction until the current DMA transfer is completed, and then the DMA function is reconfigured and enabled.

[0073] After the DMA is started, the DMA is automatically disabled after the data transfer is completed. If the function of the DMA is to be used again, the DMA function is reconfigured and enabled.

[0074] Moreover, the scheme shown in the embodiments of the present application can be applied to both the Von Neumann bus architecture and the Harvard bus architecture.

[0075] In summary, in the present application, the cache device can be configured to return data when a read instruction for the first address space is received, that is, when a read instruction for the first address space is received and a cache miss occurs, a normal cache miss (i.e., a normal cache miss) is triggered, at this time, according to the processing flow of the original cache miss, the data in the first storage area is obtained through the bus on the chip and is carried to the cache device, and then the data is returned to the CPU, and if the cache hits, the data cached in the cache device is directly returned to the CPU; and in addition to retaining the above normal cache miss function, the processing function and logic of the cache miss are also reused, that is, the cache device is configured to trigger a target cache miss when a read instruction for the second storage area is received, so as to obtain target data of the second storage area through the bus on the chip, and carry the target data of the second storage area to a specified storage space; since the cache miss mechanism is triggered, the target data of the second storage area can be carried through the bus on the chip without the intervention of the CPU, at this time the cache device can directly carry the obtained data to the specified storage space, thereby realizing the function of DMA. The above scheme can realize the function of DMA without increasing the DMA module, thereby realizing the function of DMA while reducing the cost and power consumption of the chip.

[0076] Correspondingly, the present application also provides a data carrying method, which can be applied to the cache device as shown in Figure 2 Figure 5 A method flow chart of a data carrying method related to an embodiment of the present application is shown. As shown in Figure 5 The method comprises the following steps:

[0077] Step 501: when a read instruction for the second address space is received, a target cache miss is triggered, and target data of the second storage area is obtained through the bus on the chip.

[0078] Optionally, a configuration instruction sent by a processor is received; the configuration instruction includes a second storage area address, an address in a specified storage space, and a data carrying length; and a first function register in the cache device is configured according to the configuration instruction.

[0079] In the present application, the cache device can be configured by pre-configuring the original function register corresponding to the Cache, for example, the original cache miss function corresponding to the Cache is configured first, so that the Cache is configured to trigger a normal cache miss as soon as a read instruction for the first address space is received and a cache miss occurs; and according to the processing mechanism of the Cache Miss, data is obtained from the lower-level storage as soon as it is triggered.​

[0080] In another aspect, the cache device can also be configured by pre-configuring the first function register corresponding to the Cache, so that the Cache is configured to trigger the cache miss corresponding to the DMA once it receives the read instruction for the second address space, and according to the processing mechanism of the Cache Miss, the data is obtained from the lower-level storage once it is triggered. In the embodiment of the application, the second storage area address read by the target cache miss function, the specified storage space where the data is to be stored (that is, the address in the specified storage space), and the data length carried each time can be configured as needed.

[0081] Further, when receiving the read instruction for the second address space, it is necessary to determine whether the identification of the DMA function in the first function register of the cache device is enabled. If it is enabled, the cache miss is triggered to trigger the DMA function; if it is not enabled, it is processed according to the normal memory access operation, and the data of the access address space is returned.

[0082] Step 502, the target data of the second storage area is carried to the specified storage space.

[0083] In the embodiment of the application, the target cache miss triggered by the second address space is not completely consistent with the conventional cache miss function. When the conventional cache miss function is triggered, the data is obtained from the lower-level storage and filled into the Cache storage space corresponding to the missing Cacheline; and the cache miss triggered by the second address space obtains the data from the second storage area off-chip, and directly carries the data obtained from the second storage area to the specified storage space (this function can be realized by configuring the permutation control module).

[0084] Therefore, in the logic of the target cache miss triggered by the second address space, the read instruction for the second address space can be used as a trigger instruction to trigger the cache miss to realize the DMA data carrying function. Therefore, in the embodiment of the application, after the cache miss corresponding to the DMA function is triggered, the data in the second storage area off-chip is carried to the specified storage space according to the address stored in the first function register of the cache device, and before the data in the second storage area starts to be carried, the cache device can return the target identification to the processor in the chip; the target identification is the return result of the read instruction for the second address space, so as to inform the processor that the DMA function has started to be executed.

[0085] Optionally, in the embodiment of the application, the read instruction used to trigger the DMA function is a single instruction, and at this time, the target identification can be the data corresponding to the single read instruction.

[0086] Alternatively, in the embodiments of the present application, the target identifier can also be pre-configured to inform the CPU that the cache device has triggered the DMA function at this time.

[0087] Further, when the target data transfer of the second storage area is completed, the cache device needs to send an interrupt notification to the processor in the chip.

[0088] In a possible implementation, in the process of transferring the target data of the second storage area to the designated storage space, the target data of the second storage area can be obtained from the external storage according to the size of the Cacheline Buffer in the Cache replacement control module, the obtained data is read back to the Cacheline Buffer, and then the data in the Cacheline Buffer is sequentially written into the designated storage space (for example, SRAM) through the bus interface of the Cache.

[0089] In another possible implementation, in the process of transferring the target data of the second storage area to the designated storage space, each time a unit granularity (such as 1 Word or 4 Bytes) of data is obtained, the unit granularity of data is directly written into the corresponding address in the designated storage space through the bus interface of the Cache, without the need to first cache the data of the entire Cacheline.

[0090] The above two data transfer methods can be found in Figure 2 The first and second methods in the corresponding embodiments will not be described here.

[0091] Please refer to Figure 6 which shows a method flowchart of the cache device related to the embodiments of the present application. As shown in Figure 6 In the embodiments of the present application, before the Cache (i.e., the cache device) works normally, the CPU needs to configure the function registers of the Cache, including registers for realizing the normal functions of the Cache (such as original cache miss) and DMA function registers. After the configuration of the Cache is completed, the CPU can send a read instruction to the Cache, and after the Cache receives the read instruction, it can judge the memory access address in the read instruction to determine whether it belongs to the first address space or the second address space.

[0092] If the memory access address in the read instruction is in the first address space and the cache hit, the data is directly read from the cache device and returned to the CPU.

[0093] If the access address in the read instruction is in the first address space and the cache is not hit, a raw cache miss is triggered, that is, a normal Cache Miss process. At this time, the Cache reads the target Cache line data in the first storage area in turn, and writes the read data into the corresponding storage space of the Cache. The CPU can obtain the data from the storage space of the Cache and process it.

[0094] If the access address in the read instruction is in the second address space, a target cache miss is triggered, that is, a Cache Miss for implementing the DMA function, and the target identifier is returned to the CPU to inform the CPU that the DMA function has been started. Then the Cache reads the target data in the second storage area in turn, but does not write it into the storage space of the Cache, but directly writes the target data from the second storage area into the specified storage space. After executing the process, an interrupt notification can be sent to the CPU.

[0095] Therefore Figure 6 In the method process of the Cache device shown, by multiplexing the Cache Miss function, the Cache can be multiplexed to implement the DMA function only by simple configuration on the premise of implementing the original function, which reduces the cost and power consumption compared with the scheme of adding a DMA module to implement the DMA function.

[0096] Further, in the Cache device as shown in Figure 6 In the Cache device shown, the first address space and the second address space can be two independent address spaces (that is, the first address space and the second address space have no overlapping part), or the first address space and the second address space at least partially overlap.

[0097] First, if the first address space and the second address space are two independent address spaces, for example, the range of the first address space is (1-1000), and the range of the second address space is (1001-2000). If the address of the read instruction falls within the first address space, the normal Cache function is triggered, that is, if the cache is hit, the data is directly returned, and if the cache is not hit, a raw cache miss is triggered. If the address of the read instruction falls within the second address space, a target cache miss is triggered, thereby implementing the DMA function through the above logic.

[0098] Further, if the first address space and the second address space at least partially overlap, for example, the first address space ranges from 1 to 1000, and the second address space ranges from 800 to 1200, in the range from 800 to 1000, the data belongs to both the first address space and the second address space. Therefore, in the overlapping range, the triggering condition of the normal Cache function and the triggering condition of the target cache miss are both satisfied.

[0099] In a possible implementation, the Cache can be set to trigger neither the Cache function nor the target cache miss. In this case, in the embodiment of the present application, if the first address space and the second address space at least partially overlap, the CPU can control one of the original function register and the first function register in the Cache in advance; so that when the CPU issues a read instruction, one of the normal Cache function or the target cache miss function is in a suspended state. In this case, even if the read instruction is located in the overlapping part of the first address space and the second address space, the function that is not suspended can be triggered.

[0100] Optionally, the second address space can also be a subset of the first address space, for example, the first address space ranges from 1 to 1000, and the second address space ranges from 500 to 700. In this case, the address in the read instruction issued by the CPU needs to be located in the second address space, and the normal Cache function needs to be suspended to trigger the DMA function.

[0101] In another possible implementation, the Cache can also be set to trigger both the normal Cache function and the target cache miss. However, because the normal Cache function includes Cache Hit and Cache Miss, the two need to be described separately.

[0102] If the first address space and the second address space partially overlap, and the read instruction issued by the CPU is located in the overlapping part of the first address space and the second address space, and there is data in the overlapping part, that is, Cache Hit can be triggered, in this case, the Cache runs according to the Cache Hit process, that is, the data in the overlapping part is directly returned to the CPU; on the other hand, the DMA function is also triggered to move the target data in the second storage area to the specified storage space (for example, SRAM).

[0103] If the first address space partially overlaps the second address space, and the read instruction issued by the CPU is located in the overlapping part of the first address space and the second address space, and no data exists in the overlapping part at this time, that is, when the cache miss is triggered, in order not to affect the processing performance of the CPU, the cache will preferentially execute the normal cache miss process, obtain the data in the first storage area through the bus on the chip, and carry the data to the cache device, so as to return the data to the CPU; then when the normal cache miss process is completed, the cache executes the target cache miss, that is, triggers the DMA function, and carries the target data of the second storage area to the specified storage space (for example, SRAM).

[0104] In summary, in the present application, the cache device can be configured to return data when receiving a read instruction for the first address space, that is, when receiving a read instruction for the first address space and the cache miss, triggering the original cache miss (that is, the normal cache miss), at this time, according to the processing flow of the original cache miss, the data in the first storage area is obtained through the bus on the chip and carried to the cache device, and then the data is returned to the CPU, and if the cache hit, the cached data in the cache device is directly returned to the CPU; and in addition to retaining the above normal cache miss function, the present application also reuses the processing function and logic of the cache miss, that is, the cache device is configured to trigger the target cache miss when receiving a read instruction for the second storage area, to obtain the target data of the second storage area through the bus on the chip, and carry the target data of the second storage area to the specified storage space. Since the cache miss mechanism is triggered, the target data of the second storage area can be carried through the bus on the chip without the intervention of the CPU, at this time the cache device can directly carry the obtained data to the specified storage space, thereby realizing the function of DMA. The above scheme can realize the DMA function without increasing the DMA module, thereby realizing the DMA function while reducing the cost and power consumption of the chip.

[0105] The present application also provides a chip which can include the cache device shown in the present application to realize the DMA function in the chip. Please refer to Figure 7 , Figure 7 is a structural schematic diagram of a chip provided by an optional embodiment of the present application, as Figure 7As shown, the chip includes a processor 10, a memory 20, and interfaces, including high-speed interfaces and low-speed interfaces, for connecting the various components. The various components communicate with one another using different buses, and can be mounted on a common motherboard or in other manners as appropriate. The processor can process instructions for execution within the chip. In some optional embodiments, multiple processors and / or multiple buses can be employed as appropriate. Also, multiple chips can be connected, with each device providing portions of the necessary operations (e.g., as a server array, a group of blade servers, or a multi-processor system). Figure 7 The processor 10 is taken as an example.

[0106] The processor 10 can be a central processor, a network processor, or a combination thereof. The chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof, such as an MCU or a SOC.

[0107] The memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in the above embodiments.

[0108] The memory 20 can include a program storage area and a data storage area, where the program storage area can store an operating system, application programs required by at least one function, and the data storage area can store data created according to the use of the chip, etc. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some optional embodiments, the memory 20 can optionally include a memory disposed remotely with respect to the processor 10, and these remote memories can be connected to the chip through a network.

[0109] The memory 20 can include a volatile memory, such as a random access memory, and the memory can also include a non-volatile memory, and the memory 20 can also include a combination of the above kinds of memories.

[0110] The chip also includes a communication interface 30 for the chip to communicate with other devices or communication networks.

[0111] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer codes stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded through a network and stored in a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer codes, when the software or computer codes are accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0112] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A cache apparatus, characterized by The cache device is configured with a first address space and a second address space; the cache device is configured to return data by the cache device when receiving a read instruction for the first address space; The cache device is further configured to trigger a target cache miss when receiving a read instruction for the second address space, to obtain target data of the second storage area through a bus on the chip, and to carry the target data of the second storage area to a designated storage space outside the cache device.

2. The apparatus of claim 1, wherein, The device includes a first function register; the first function register stores a second storage area address, a designated storage space address, and a data carrying length.

3. The apparatus of claim 2, wherein, The device further includes a space judgment module; the space judgment module is configured to receive a read instruction and judge a memory access address in the read instruction; if the memory access address is in the first address space and the cache is not hit, a raw cache miss is triggered; if the memory access address is in the second address space, the target cache miss is triggered.

4. The apparatus of claim 3, wherein, The device further includes a replacement control module; the replacement control module is configured to receive a cache line load request sent by the space judgment module after triggering the target cache miss; The replacement control module is configured to read data of the carrying data length according to the second storage area address and write the data into the designated storage space address after receiving the cache line load request.

5. The apparatus of claim 4, wherein, The replacement control module further includes a current data read address register, a current data storage address register, and a remaining data length counter.

6. A data movement method, characterized by, The method is applied to the cache device of any one of claims 1 to 5, and the method comprises: When receiving a read instruction for the second address space, triggering a target cache miss, and obtaining target data of the second storage area through a bus on the chip; Carrying the target data of the second storage area to a designated storage space outside the cache device.

7. The method of claim 6, wherein, The method further comprises: Before the target data of the second storage area starts to be carried, returning a target identifier to a processor in the chip.

8. The method of claim 6, wherein, The method further comprises: When carrying data of the carrying data length from the second storage area is completed, sending an interrupt notification to the processor in the chip.

9. The method according to any one of claims 6 to 8, characterized in that, The method further comprises: Receiving a configuration instruction sent by the processor; the configuration instruction includes an address of the second storage area, an address in the designated storage space, and a carrying data length; Configuring the first function register in the cache device according to the configuration instruction.

10. A chip, characterized by The chip is provided with the cache device of any one of claims 1 to 5.

Images