Server and anti-hanging device for two-wire serial bus of server

Abstract

The invention discloses a server and a hanging-up prevention device for a two-wire serial bus thereof, and relates to the technical field of fault processing, and the device comprises a fault detection module which is used for outputting an abnormal signal when detecting that an I2C has any one of hanging-up of a serial clock line, hanging-up of a serial data line and bus conflict; the isolation module is used for disconnecting each slave device mounted on the I2C from the clock of the I2C after receiving the abnormal signal, and recovering the connection between each slave device and the clock of the I2C after disconnecting; and the oscillation module is used for outputting a specified number of pulses to a serial clock line of the I2C to reset the I2C after the abnormal signal is received and the isolation module restores the connection between each slave device and the I2C clock. By applying the scheme provided by the invention, high real-time performance is achieved, automatic detection and recovery can be realized on the abnormal conditions of hanging of the serial clock line and the data line and bus conflict, and the comprehensiveness of processing the abnormity is improved.

Description

Technical Field

[0001] This application relates to the technical field of fault handling, and particularly to a server and an anti-hang device for a two-wire serial bus thereof. Background Art

[0002] The I2C (Inter-Integrated Circuit) bus is a bidirectional two-wire synchronous serial bus. Only two wires are required to transmit information between devices connected to the bus. That is, only one data line SDA (Serial Data) and one clock line SCL (Serial Clock) are needed. Both SDA and SCL are bidirectional I / O lines, and the interface circuit is an open-drain output, which needs to be connected to the power supply VCC through a pull-up resistor. When the bus is idle, both wires are at a high level.

[0003] Since the I2C bus adopts an open-drain output structure, the SDA / SCL signal lines may be continuously at a low level (i.e., the bus is hung) due to device deadlock, resulting in system-level paralysis. In some solutions, the bus status is polled and monitored by relying on an FPGA (Field Programmable Gate Array) / MCU (Micro Controller Unit). However, the hardware cost of the FPGA / MCU is relatively high, and the real-time performance is insufficient. In practical applications, it occupies processing resources and the response delay exceeds 200 ms, making it difficult to meet the real-time requirements in scenarios such as edge servers.

[0004] In summary, how to effectively solve the I2C bus anomaly, reduce the hardware cost, and ensure real-time performance is an urgent technical problem for those skilled in the art at present. Summary of the Invention

[0005] This application provides a server and an anti-hang device for a two-wire serial bus thereof to effectively solve the I2C bus anomaly, reduce the hardware cost, and ensure real-time performance.

[0006] This application provides an anti-hang device for a two-wire serial bus, including: A fault detection module, configured to output an abnormal signal when detecting any one of a serial clock line hang, a serial data line hang, and a bus conflict occurring in the two-wire serial bus; An isolation module, configured to disconnect the clock connection between each slave device mounted on the two-wire serial bus and the two-wire serial bus after receiving the abnormal signal, and restore the clock connection between each slave device and the two-wire serial bus after the disconnection; An oscillation module, configured to output a specified number of pulses to a serial clock line of the two-wire serial bus after receiving an abnormal signal and after the isolation module restores the clock connections of the respective slave devices to the two-wire serial bus, so as to reset the two-wire serial bus.

[0007] The present application further provides a server, including the anti-hang-up device of the two-wire serial bus as described above.

[0008] In the solution of the present application, when the fault detection module detects any one of the situations of serial clock line hang-up, serial data line hang-up, and bus conflict on the two-wire serial bus, it outputs an abnormal signal, which improves the comprehensiveness of the anti-hang-up device of the present application in dealing with abnormalities. After the fault detection module outputs an abnormal signal, the isolation module disconnects the clock connections of the respective slave devices mounted on the two-wire serial bus from the two-wire serial bus, and restores the clock connections of the respective slave devices to the two-wire serial bus after disconnection, so that pulses can be sent to the serial clock line subsequently. After the oscillation module receives the abnormal signal and the isolation module restores the clock connections of the respective slave devices to the two-wire serial bus, the oscillation module can output a specified number of pulses to the serial clock line of the two-wire serial bus, so that the two-wire serial bus can be reset according to the rules of the two-wire serial bus, thereby solving the abnormality. And it can be seen that the above process can be automatically executed by the anti-hang-up device, so that the solution of the present application can realize the automatic recovery of the I2C bus hang-up without master control intervention. In addition, the solution of the present application realizes the abnormal detection and recovery of the I2C bus through all hardware, and does not need to rely on FPGA / MCU, so that the hardware cost of the anti-hang-up device of the present application is relatively low, and it can have high real-time performance.

[0009] In summary, the anti-hang-up device of the solution of the present application has a relatively low hardware cost and can have high real-time performance. It can realize automatic detection and recovery for abnormal situations such as serial clock line hang-up, serial data line hang-up, and bus conflict, improving the comprehensiveness of dealing with abnormalities. Description of the Drawings

[0010] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 It is a schematic structural diagram of the anti-hang-up device of the two-wire serial bus provided by a specific embodiment of the present invention; Figure 2 It is a schematic structural diagram of the fault detection module in a specific embodiment of the present invention; Figure 3 This is a schematic structural diagram of the oscillation module in a specific embodiment of the present invention. Specific embodiment

[0012] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0013] It should be noted that in the description of the present application, the terms "including", "comprising" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] To enable those skilled in the art of this technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Please refer to Figure 1 , Figure 1 This is a schematic structural diagram of the anti-hang-up device for a two-wire serial bus provided by a specific embodiment of the present invention. The anti-hang-up device for the two-wire serial bus may include: A fault detection module 10, configured to output an abnormal signal when detecting any one of a serial clock line hang-up, a serial data line hang-up, and a bus conflict on the two-wire serial bus; An isolation module 20, configured to disconnect the clock connection between each slave device mounted on the two-wire serial bus and the two-wire serial bus after receiving the abnormal signal, and restore the clock connection between each slave device and the two-wire serial bus after the disconnection; An oscillation module 30, configured to output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving the abnormal signal and after the isolation module 20 restores the clock connection between each slave device and the two-wire serial bus.

[0015] In the solution of this application, the fault detection module 10 can not only effectively detect the deadlock situation of the I2C bus (serial clock line deadlock, serial data line deadlock), but also effectively detect the bus conflict situation of the I2C bus. When any of these situations occurs, an abnormal signal can be output so as to realize the reset of the I2C bus through the isolation module 20 and the oscillation module 30, thereby completing the processing of abnormal situations.

[0016] The specific structure of the fault detection module 10 can be set and adjusted according to actual needs, as long as it can meet the functional requirements of the fault detection module 10 in the solution of this application. For example, in a specific embodiment of the present invention, the fault detection module 10 may include: The first fault detection unit is used to output an abnormal signal when it detects that the serial clock line of the two-wire serial bus is deadlocked; The second fault detection unit is used to output an abnormal signal when it detects that the serial data line of the two-wire serial bus is deadlocked; The third fault detection unit is used to output an abnormal signal when it detects that the two-wire serial bus has a bus conflict; An OR gate circuit respectively connected to the first fault detection unit, the second fault detection unit and the third fault detection unit, which is used to output an abnormal signal to the isolation module 20 and the oscillation module 30 when receiving the abnormal signal output by any one of the first fault detection unit, the second fault detection unit and the third fault detection unit.

[0017] In this embodiment, considering that the fault detection module 10 needs to detect the deadlock of the serial clock line, the deadlock of the serial data line, and the bus conflict on the I2C bus, specifically, 3 fault detection units can be used to implement the detection respectively, and then input to the OR gate circuit, and then the output of the OR gate circuit is used as the output of the fault detection module 10. Such a design is easy to implement and can ensure that the structure of the fault detection module 10 is relatively simple. Refer to Figure 2 , which is a schematic diagram of the structure of the fault detection module 10 in a specific embodiment, Figure 2 In the example of , the fault detection module 10 is specifically composed of the first fault detection unit, the second fault detection unit and the third fault detection unit.

[0018] The first fault detection unit detects the deadlock situation of the serial clock line on the I2C bus, that is, the deadlock situation of the SCL line. The specific structure can be set according to actual needs. For example, in a specific embodiment of the present invention, the first fault detection unit includes: A first counting circuit is configured to count when the serial clock line of the two-wire serial bus is at a low level; whenever a rising edge or a falling edge appears on the serial clock line, it clears its own count value; when its own count value reaches a preset first value, it outputs a high-level signal as the abnormal signal output by the first fault detection unit. In this implementation manner, specifically, 1 counting circuit, that is, the first counting circuit, is used to implement the required first fault detection unit. The first counting circuit needs to be connected to the SCL line. For example, in one case, specifically, the first counting circuit is implemented based on CD4521, then the SCL line of the I2C bus can be connected to the clock input of CD4521. Whenever a rising edge or a falling edge appears on the SCL line, the first counting circuit can be reset, that is, clear its own count value. And if the SCL line is in a low-level stagnant state, that is, when the first counting circuit detects that the SCL line is at a low level, it will count. It can be understood that if the count value reaches the preset first value, it means that the SCL line is in a low-level stagnant state, and during this process, no rising edge or falling edge appears on the SCL line. Therefore, it can be determined that the SCL line is hung up, and the first counting circuit can output a high-level signal as the abnormal signal output by the first fault detection unit.

[0019] The preset first value serves as a threshold, and its specific value can be set according to actual needs. For example, in one specific case, for each increase of 1 in the count value of the first counting circuit, the represented unit time duration is equal to 9 pulse periods of the SCL line, that is, when it is detected that the serial clock line of the two-wire serial bus is at a low level, after a time period of "9 pulse periods", the count value will increase by 1. For example, if the first value is set to 10, that is, it is equivalent to when the SCL line is at a low level for 90 consecutive pulse periods, the count value of the first counting circuit will reach 10. At this time, the first counting circuit will output a high-level signal as the abnormal signal output by the first fault detection unit, indicating that the SCL line is hung up.

[0020] The second fault detection unit detects the situation where the serial data line on the I2C bus is hung up, that is, the situation where the SDA line is hung up. Its specific structure can be set according to actual needs. For example, in one specific implementation manner of the present invention, the second fault detection unit may include: A second counting circuit is configured to monitor the level state of the serial data line whenever a rising edge appears on the serial clock line within each first detection duration, and add 1 to its own count value when the level state of the serial data line is at a low level; when its own count value reaches a preset second value, it outputs a high-level signal as the abnormal signal output by the second fault detection unit; at the end of each round of the first detection duration, it starts the next round of the first detection duration and clears its own count value.

[0021] In this implementation manner, specifically, a second fault detection unit is implemented through one counting circuit, that is, the second counting circuit. The second counting circuit needs to be connected to the SCL line and the SDA line. For example, in one case, one CD4521 is used to implement the first counting circuit, and another CD4521 is used to implement the second counting circuit.

[0022] The clock input of the second counting circuit needs to be jointly controlled by the SCL line and the SDA line of the I2C bus. Specifically, within each first detection duration, whenever a rising edge appears on the SCL line, the level state of the SDA line can be monitored. If at this time, the monitored level state of the SDA line is low level, the second counting circuit needs to increment its own count value by 1. It can be understood that within the first detection duration, whenever a rising edge appears on the SCL line, under normal circumstances, the level state of the SDA line may be high level or low level, but it will not always be low level. That is to say, under normal circumstances, the count value of the second counting circuit will not reach the preset second value. If the count value of the second counting circuit reaches the preset second value, it can be determined that within the first detection duration, the level state of the SDA line is continuously low level, indicating that the SDA line is hung up. Therefore, the second counting circuit will output a high-level signal as the abnormal signal output by the second fault detection unit.

[0023] In addition, it can be understood that at the end of each round of the first detection duration, the next round of the first detection duration needs to be started and its own count value needs to be cleared. That is to say, the count value of the second counting circuit will be periodically and automatically cleared, so that at the beginning of each round of the first detection duration, the count value of the second counting circuit starts to increase from 0.

[0024] The preset second value also serves as a threshold. The size of the first detection duration and the specific value of the second value can both be set according to actual needs.

[0025] The third fault detection unit detects the bus conflict situation on the I2C bus. The specific circuit structure can be set according to actual needs. For example, in a specific implementation manner of the present invention, the third fault detection unit includes: An edge detection circuit, which is used to monitor whether the level state of the serial data line changes whenever a rising edge appears on the serial clock line within each second detection duration. If so, a conflict signal is output to the third counting circuit; A third counting circuit, which is used to increment its own count value by 1 whenever it receives a conflict signal within each second detection duration; when its own count value reaches the preset third value, it outputs a high-level signal as the abnormal signal output by the third fault detection unit; at the end of each round of the second detection duration, the next round of the second detection duration is started and its own count value is cleared.

[0026] In this embodiment, specifically, the required third fault detection unit is implemented by one counting circuit and one edge detection circuit. The third counting circuit can also be implemented based on CD4521, for example, and the edge detection circuit can be implemented based on a D flip-flop, for example.

[0027] When transmitting data signals, according to the I2C specification, SDA can only change when SCL is at a low level. When SCL is at a high level, the level of SDA needs to be maintained, that is, "sampling on the rising edge and changing on the falling edge". Therefore, normally, whenever a rising edge appears on the SCL line, the level of the SDA line should remain unchanged. Correspondingly, if the level of the SDA line changes when a rising edge appears on the SCL line, a conflict signal needs to be output to the third counting circuit. In practical applications, it is usually the conflict of slave devices on the I2C bus that causes such abnormal situations.

[0028] For example, when implementing the edge detection circuit of this embodiment using a D flip-flop, the SCL line can be connected to the clock terminal of the D flip-flop, and the SDA line can be connected to the data input terminal of the D flip-flop. Whenever a rising edge appears on the SCL line, it can be determined whether the level of the data output terminal of the D flip-flop jumps. If so, a conflict signal can be output to the third counting circuit.

[0029] Within each second detection duration, whenever the third counting circuit receives a conflict signal once, it will increment its own count value. When the count value of the third counting circuit reaches a preset third value, it indicates that the conflict situation occurs too frequently. Then, the third counting circuit will output a high-level signal as the abnormal signal output by the third fault detection unit.

[0030] In addition, it can be understood that at the end of each round of the second detection duration, the third counting circuit needs to start the next round of the second detection duration and clear its own count value. That is to say, the count value of the third counting circuit will be periodically cleared automatically, so that at the start of each round of the second detection duration, the count value of the third counting circuit starts to increase from 0.

[0031] Refer to Figure 2 , the outputs of the first fault detection unit, the second fault detection unit, and the third fault detection unit are all connected to an OR gate circuit, so that when any of the first fault detection unit, the second fault detection unit, and the third fault detection unit outputs an abnormal signal, the OR gate circuit can output an abnormal signal to the isolation module 20 and the oscillation module 30.

[0032] In a specific embodiment of the present invention, the fault detection module 10 can also be connected to a fault recording module. When the fault recording module receives an abnormal signal, it can store the level states on the I2C bus at the time of the fault to support subsequent diagnosis. For example, in a specific embodiment, a preset non-volatile storage device, such as an EEPROM, can be used to continuously record the level states of the SCL line and the SDA line on the I2C bus, and a cyclic storage method can be adopted to ensure that the EEPROM will never be full. For example, the abnormal signal output by the fault detection module 10 can be specifically connected to the write protection pin of the EEPROM, so that if the write protection pin of the EEPROM receives a high-level signal, write protection is triggered. Specifically, the level states of the SCL line and the SDA line within a certain period of time before the current moment are fixed as the level states on the I2C bus at the time of the recorded fault, and are not allowed to be overwritten by newly written data, so as to assist the subsequent diagnosis work of the staff. In Figure 2 the example of, the level states on the I2C bus at the time of the fault are stored using the EEPROM.

[0033] After the fault detection module 10 outputs an abnormal signal, the isolation module 20 and the oscillation module 30 can be used to reset the I2C bus. Specifically, according to the I2C regulations, by sending 9 clk signals, the slave device can be prompted to release the I2C bus, that is, the I2C bus is reset. In this regard, the present application scheme considers that if the SDA is hung up, that is, the SDA is continuously pulled low by a certain slave device mounted on the I2C bus, by sending 9 consecutive clk signals, the slave device can be made to release the I2C bus and the I2C bus can be reset. However, if the SCL line is pulled low, sending 9 consecutive clk signals may fail at this time. In this embodiment, the isolation module 20 disconnects the clock connections of each slave device mounted on the I2C bus from the I2C bus, so that each I2C bus can return to a high level, and then the clock connections of each slave device and the I2C bus are restored. In this way, 9 consecutive clk signals can be successfully sent without the situation of 9 clk signals sending failure. That is to say, the setting of the isolation module 20 in the present application scheme is to ensure that the oscillation module 30 successfully resets the I2C bus.

[0034] In addition, it can be understood that the oscillation module 30 should output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving the abnormal signal and the isolation module 20 restores the clock connection between each slave device and the two-wire serial bus. That is to say, after the fault detection module 10 outputs the abnormal signal, the isolation module 20 first completes its work, and then the oscillation module 30 completes its work. There can be various specific ways to achieve this sequence. For example, in one case, since the circuit structure of the isolation module 20 is simple and it executes quickly, the sequence can be achieved without additional operations, that is, the isolation module 20 will originally complete its own work prior to the oscillation module 30. Of course, in some cases, a certain circuit structure can also be specifically set up to ensure the sequence of the isolation module 20 and the oscillation module 30. For example, a delay circuit can be set between the fault detection module 10 and the oscillation module 30, so that the oscillation module 30 receives the abnormal signal slightly later than the isolation module 20, to ensure that after the isolation module 20 completes its work, the oscillation module 30 starts its work. That is, the oscillation module 30 outputs a specified number of pulses to the serial clock line of the two-wire serial bus, which can achieve the synchronous reset of each slave device, that is, the reset of the two-wire serial bus is achieved. The specified number can usually be set to 9. Of course, in some embodiments, a value greater than 9 can be set to achieve a redundancy effect.

[0035] The isolation module 20 acts as an analog switch, which can disconnect the clock connection between each slave device mounted on the I2C bus and the I2C bus, and after disconnection, restore the clock connection between each slave device and the I2C bus. The specific structure of the isolation module 20 can be set according to actual needs. For example, in a specific embodiment of the present invention, the isolation module 20 can specifically include N three-state buffers corresponding to N slave devices respectively, and each three-state buffer is used for: After receiving the abnormal signal, disconnect the clock connection between the corresponding slave device mounted on the two-wire serial bus and the two-wire serial bus, and after disconnection, restore the clock connection between the slave device and the two-wire serial bus.

[0036] In this embodiment, for each slave device mounted on the I2C bus, its clock pin is mounted on the SCL line of the I2C bus through its corresponding three-state buffer. N is a positive integer, representing the number of slave devices mounted on the I2C bus, and is also equal to the number of three-state buffers set in this embodiment of the present application.

[0037] Each tri-state buffer can use, for example, a 74HC126 tri-state buffer. For any 74HC126 tri-state buffer, after receiving the abnormal signal output by the fault detection module 10, it can disconnect the clock connection of the corresponding slave device. After disconnecting the clock connection of the slave device, it can restore the clock connection between the slave device and the I2C bus.

[0038] After the isolation module 20 completes its work, the oscillation module 30 can output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus. The specific structure of the oscillation module 30 can be set according to actual needs. For example, in a specific embodiment of the present invention, the oscillation module 30 includes: A signal conditioning circuit for acquiring the signal of the serial clock line and amplifying and outputting it; A phase-locked loop circuit for receiving the output signal of the signal conditioning circuit and performing phase-locking. After receiving the abnormal signal and the isolation module restores the clock connection between each slave device and the two-wire serial bus, it outputs a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus; Among them, the frequency of the pulses output by the phase-locked loop circuit is equal to the frequency of the output signal of the signal conditioning circuit; the frequency of the output signal of the signal conditioning circuit is equal to the clock frequency of the serial clock line.

[0039] In this embodiment, it is considered that there are multiple optional values for the clock frequency of the SCL line of the I2C bus, that is, in different scenarios, the clock frequency of the SCL line may be different. And the solution of the present application requires the oscillation module 30 to output a specified number of pulses to the SCL line. Therefore, one implementation solution is to set the parameters of the oscillation module 30 based on the current specific scenario, so that the pulse frequency of the pulses output by the oscillation module 30 conforms to the clock frequency of the SCL line in this scenario. For example, in some scenarios, appropriate parameters are selected for the resistors, capacitors and other components of the voltage-controlled oscillator in the phase-locked loop circuit, so that the pulse frequency of the pulses output by the oscillation module 30 can conform to the clock frequency of the SCL line in this scenario. In this embodiment, however, the required clock frequency is extracted based on the signal of the SCL line and then output, which enables this embodiment to be effectively applied in different scenarios without specifically setting the corresponding parameters of the oscillation module 30 based on the current scenario, improving the application flexibility of the solution of the present application.

[0040] Specifically, in this implementation, the signal conditioning circuit acquires the signal of the SCL line, amplifies it, and outputs it. The phase-locked loop circuit can then perform phase locking on it. Subsequently, after receiving an abnormal signal and the isolation module 20 restores the clock connections of each slave device to the two-wire serial bus, a specified number of pulses can be output to the serial clock line of the two-wire serial bus to reset the two-wire serial bus.

[0041] In this implementation, since the phase-locked loop circuit receives the output signal of the signal conditioning circuit and performs phase locking, the pulse frequency output by the phase-locked loop circuit will be equal to the frequency of the output signal of the signal conditioning circuit, that is, equal to the clock frequency of the SCL line.

[0042] In addition, it should be noted that even if the SCL line hangs up, since the signal conditioning circuit can acquire the signal of the SCL line before the SCL line hangs up, the phase-locked loop circuit can still generate pulses with the same frequency and phase based on the residual clock frequency of the SCL line (that is, the clock frequency of the SCL line before it hangs up), and after the isolation module 20 completes its work, output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus.

[0043] In a specific implementation of the present invention, refer to Figure 3 , the signal conditioning circuit 31 may include: An amplification circuit for acquiring the signal of the serial clock line and amplifying it; A filtering circuit for filtering the output of the amplification circuit; A trigger circuit for converting the output of the filtering circuit into a square wave signal and outputting it to the phase-locked loop circuit.

[0044] This implementation takes into account that the signal amplitude of the SCL line is small. To facilitate the operation of the phase-locked loop circuit, it is necessary to use the amplification circuit to acquire the weak and noisy signal on the SCL line and amplify it. For example, the LM358 is specifically used for signal amplification. Then, the output of the amplification circuit can be filtered by the filtering circuit. The filtering circuit is usually a band-pass filtering circuit. For example, the center frequency covers 10 kHz - 400 kHz, which can effectively filter out out-of-band noise. The trigger circuit can perform waveform shaping, that is, convert the output of the filtering circuit into a square wave signal and output it to the phase-locked loop circuit. For example, in a specific case, the trigger circuit is specifically a Schmitt trigger (such as CD40106), which can effectively convert a sine wave or pulse into a square wave to ensure that the output signal meets the requirements of the phase-locked loop circuit for the input signal.

[0045] In a specific implementation of the present invention, refer to Figure 3 , the phase-locked loop circuit 32 may include: A phase comparator for comparing the phase of the output signal of the signal conditioning circuit and the output signal of the voltage-controlled oscillator, and outputting a phase comparison result; A voltage-controlled oscillator for generating an output signal with a corresponding frequency based on the phase comparison result, so that the frequency of the output signal generated by the voltage-controlled oscillator follows the frequency of the output signal of the signal conditioning circuit; A pulse output circuit for obtaining the output signal of the voltage-controlled oscillator and outputting a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving an abnormal signal and the isolation module restores the clock connection between each slave device and the two-wire serial bus; Wherein, the pulse frequency of the pulses output by the pulse output circuit is equal to the frequency of the output signal of the voltage-controlled oscillator.

[0046] In this embodiment, the phase comparator can compare the phase of the output signal of the signal conditioning circuit and the output signal of the voltage-controlled oscillator, and output a phase comparison result. The phase comparison result is a pulse proportional to the phase difference. In practical applications, usually 1 filter can be used, for example Figure 3 In the example, specifically 1 loop filter is used to convert the pulse into a smooth DC voltage to control the frequency of the output signal of the voltage-controlled oscillator.

[0047] The phase comparison result is used as the control voltage of the voltage-controlled oscillator. Based on the phase comparison result, the voltage-controlled oscillator can generate an output signal with a corresponding frequency. That is to say, the frequency of the output signal of the voltage-controlled oscillator will change with the control voltage until the output signal of the voltage-controlled oscillator is in the same frequency and phase as the output signal of the signal conditioning circuit, and the locking is completed. Of course, the solution of this application does not need to pay attention to whether they are in the same phase, and it is only required that the frequency of the output signal generated by the voltage-controlled oscillator can effectively follow the frequency of the output signal of the signal conditioning circuit. In addition, it can be understood that when the clock on the SCL line is normal, the voltage-controlled oscillator has completed the follow-up locking. So that if the clock on the SCL line becomes abnormal later and the pulse output circuit receives an abnormal signal, it can immediately output a specified number of pulses to the SCL line by obtaining the output signal of the voltage-controlled oscillator to reset the I2C bus. In practical applications, using the anti-hang-up device for the two-wire serial bus of this application, from discovering the abnormality to completing the forced reset of the I2C bus, it does not exceed 1 ms, which is about 50 times faster than the traditional MCU solution (average response time 50 ms).

[0048] Based on the above description, the pulse output circuit not only needs to receive an abnormal signal, but also needs to perform a reset of the I2C bus after the isolation module 20 restores the clock connections of each slave device to the two-wire serial bus. Of course, as described above, in normal situations, the isolation module 20 will quickly complete its work. Therefore, in practical applications, when the pulse output circuit receives an abnormal signal, it can be regarded as the isolation module 20 having completed its work, that is, regarded as the isolation module 20 having cut off and restored the clock connections of each slave device to the two-wire serial bus. At this time, the pulse output circuit can automatically obtain the output signal of the voltage-controlled oscillator and output a specified number of pulses to the SCL line according to the frequency of this output signal, which can achieve the synchronous reset of the master and slave devices mounted on the I2C bus, that is, reset the I2C bus. A counting device can be provided in the pulse output circuit to count the number of output pulses so that the number of output pulses meets the requirements.

[0049] In the solution of this application, the fault detection module 10 can output an abnormal signal when detecting any one of the situations of serial clock line hang-up, serial data line hang-up, and bus conflict on the two-wire serial bus, improving the comprehensiveness of the anti-hang-up device in this application for handling abnormalities. After the fault detection module 10 outputs an abnormal signal, the isolation module 20 will disconnect the clock connections of each slave device mounted on the two-wire serial bus from the two-wire serial bus and restore the clock connections of each slave device to the two-wire serial bus after disconnection, enabling subsequent pulses to be sent to the serial clock line. After the oscillation module 30 receives the abnormal signal and the isolation module restores the clock connections of each slave device to the two-wire serial bus, the oscillation module 30 can output a specified number of pulses to the serial clock line of the two-wire serial bus, enabling the two-wire serial bus to be reset according to the rules of the two-wire serial bus, thereby resolving the abnormality. And it can be seen that the above process can be automatically executed by the anti-hang-up device, enabling the solution of this application to achieve the automatic recovery of the I2C bus hang-up without master control intervention. In addition, the solution of this application realizes the abnormal detection and recovery of the I2C bus through all hardware and does not rely on FPGA / MCU, making the hardware cost of the anti-hang-up device in this application relatively low and having high real-time performance.

[0050] In summary, the anti-hang-up device in the solution of this application has a relatively low hardware cost and high real-time performance, and can achieve automatic detection and recovery for abnormal situations such as serial clock line hang-up, serial data line hang-up, and bus conflict, improving the comprehensiveness of handling abnormalities.

[0051] Corresponding to the embodiment of the anti-hang-up device for the two-wire serial bus above, an embodiment of the present invention further provides a server, which can be correspondingly referred to the above, and the server may include the anti-hang-up device for the two-wire serial bus in any of the above embodiments.

[0052] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0053] The above has introduced in detail a server and its anti-hang-up device for the two-wire serial bus provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. An anti-deadlock device for a two-wire serial bus, characterized in that Including: A fault detection module, configured to output an abnormal signal when any one of the situations of serial clock line hang-up, serial data line hang-up, and bus conflict occurs in the two-wire serial bus; An isolation module, configured to disconnect the clock connection between each slave device mounted on the two-wire serial bus and the two-wire serial bus after receiving the abnormal signal, and restore the clock connection between each slave device and the two-wire serial bus after the disconnection; An oscillation module, configured to output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving the abnormal signal and after the isolation module restores the clock connection between each slave device and the two-wire serial bus.

2. The anti-deadlock device for a two-wire serial bus according to claim 1, characterized in that, The fault detection module includes: A first fault detection unit, configured to output an abnormal signal when it detects that the serial clock line of the two-wire serial bus hangs up; A second fault detection unit, configured to output an abnormal signal when it detects that the serial data line of the two-wire serial bus hangs up; A third fault detection unit, configured to output an abnormal signal when it detects that a bus conflict occurs in the two-wire serial bus; An OR gate circuit respectively connected to the first fault detection unit, the second fault detection unit, and the third fault detection unit, configured to output an abnormal signal to the isolation module and the oscillation module when receiving an abnormal signal output by any one of the first fault detection unit, the second fault detection unit, and the third fault detection unit.

3. The deadlock prevention device for the two-wire serial bus according to claim 2, wherein, The first fault detection unit includes: A first counting circuit, configured to count when it detects that the serial clock line of the two-wire serial bus is at a low level; whenever a rising edge or a falling edge appears on the serial clock line, clear its own count value; when its own count value reaches a preset first value, output a high-level signal as the abnormal signal output by the first fault detection unit.

4. The deadlock prevention device for a two-wire serial bus according to claim 2, characterized in that The second fault detection unit includes: A second counting circuit, configured to monitor the level state of the serial data line whenever a rising edge appears on the serial clock line within each first detection duration, and increment its own count value when the level state of the serial data line is at a low level; when its own count value reaches a preset second value, output a high-level signal as the abnormal signal output by the second fault detection unit; start the next first detection duration and clear its own count value at the end of each round of the first detection duration.

5. The deadlock prevention device for a two-wire serial bus according to claim 2, characterized in that, The third fault detection unit includes: An edge detection circuit, configured to monitor whether the level state of the serial data line changes whenever a rising edge appears on the serial clock line within each second detection duration, and if so, output a conflict signal to a third counting circuit; The third counting circuit is configured to increment its count value by 1 each time it receives the collision signal within each second detection duration; when its count value reaches a preset third value, it outputs a high-level signal as the abnormal signal output by the third fault detection unit; and at the end of each round of the second detection duration, it starts the next round of the second detection duration and clears its count value.

6. The anti-hang-up device for a two-wire serial bus according to claim 1, characterized in that, The isolation module includes N tri-state buffers corresponding to N slave devices respectively, and each tri-state buffer is configured to: After receiving the abnormal signal, disconnect the clock connection between the corresponding slave device mounted on the two-wire serial bus and the two-wire serial bus, and restore the clock connection between the slave device and the two-wire serial bus after the disconnection; N is a positive integer.

7. The deadlock prevention device for a two-wire serial bus according to any one of claims 1 to 6, characterized in that The oscillation module includes: A signal conditioning circuit for acquiring the signal of the serial clock line and amplifying and outputting it; A phase-locked circuit for receiving the output signal of the signal conditioning circuit and performing phase locking, and after receiving the abnormal signal and the isolation module restores the clock connection between each slave device and the two-wire serial bus, output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus; Wherein, the frequency of the pulses output by the phase-locked circuit is equal to the frequency of the output signal of the signal conditioning circuit; the frequency of the output signal of the signal conditioning circuit is equal to the clock frequency of the serial clock line.

8. The anti-hang device for the two-wire serial bus according to claim 7, wherein The signal conditioning circuit includes: An amplifying circuit for acquiring the signal of the serial clock line and amplifying it; A filtering circuit for filtering the output of the amplifying circuit; A triggering circuit for converting the output of the filtering circuit into a square wave signal and outputting it to the phase-locked circuit.

9. The anti-hang device for a two-wire serial bus according to claim 7, characterized in that, The phase-locked circuit includes: A phase comparator for comparing the phase of the output signal of the signal conditioning circuit and the output signal of the voltage-controlled oscillator, and outputting a phase comparison result; A voltage-controlled oscillator for generating an output signal with a corresponding frequency based on the phase comparison result, so that the frequency of the output signal generated by the voltage-controlled oscillator follows the frequency of the output signal of the signal conditioning circuit; A pulse output circuit for, after receiving the abnormal signal and the isolation module restores the clock connection between each slave device and the two-wire serial bus, acquiring the output signal of the voltage-controlled oscillator and outputting a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus; Wherein, the pulse frequency of the pulses output by the pulse output circuit is equal to the frequency of the output signal of the voltage-controlled oscillator.

10. A server, characterized in that, It includes a deadlock prevention device for a two-wire serial bus according to any one of claims 1 to 9.

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