Data processing method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a data processing method and device, electronic equipment and a readable storage medium. The method is applied to a control node included in the data processing system, the data processing system further comprises a data storage node and at least one data processing node, and the method comprises the steps that in response to a data processing operation of a request node, the data storage node and / or the data processing node indicated by the data processing operation are transmitted to the request node; determining the node as a target node; the request node is any data processing node; acquiring a load signal of the target node; and when the load signal represents that the current load of the target node is not greater than a preset load threshold value, responding to the data processing operation through the target node. The situation that interaction waiting time is long due to network congestion is avoided, and resource waste when the network is busy is reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and particularly to a data processing method, apparatus, electronic device, and readable storage medium. Background Art

[0002] With the development of computer technologies, current computer systems are usually distributed systems or multi-core processor systems. On this basis, in order to improve system performance, each processor in a multi-core processor system is usually equipped with an independent cache. To ensure cache consistency, a large amount of data interaction is often required between each processor and the memory.

[0003] Currently, when interacting between processors and the memory, there are often situations where network congestion leads to a long interaction waiting time, and continuous retries are required, resulting in waste of ineffective resources. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a data processing method, apparatus, electronic device, and readable storage medium to solve the problem of how to avoid waste of ineffective resources. The specific technical solutions are as follows:

[0005] In the first aspect of the present invention, a data processing method is first provided, which is applied to a control node included in a data processing system. The data processing system further includes a data storage node and at least one data processing node. The method includes:

[0006] In response to a data processing operation of a requesting node, determining the data storage node, and / or, the data processing node indicated by the data processing operation, as a target node; the requesting node is any one of the data processing nodes;

[0007] Obtaining a load signal of the target node;

[0008] When the load signal indicates that the current load of the target node is not greater than a preset load threshold, responding to the data processing operation through the target node.

[0009] In the second aspect of the present invention, a data processing apparatus is further provided, which is applied to a control node included in a data processing system. The data processing system further includes a data storage node and at least one data processing node. The apparatus includes:

[0010] A first determination module, configured to determine the data storage node, and / or, the data processing node indicated by the data processing operation, as a target node in response to a data processing operation of a requesting node; the requesting node is any one of the data processing nodes;

[0011] A first acquisition module, configured to acquire the load signal of the target node;

[0012] A response module, configured to, when the load signal indicates that the current load of the target node is not greater than a preset load threshold, respond to the data processing operation through the target node.

[0013] In a third aspect of the embodiments of the present invention, there is also provided an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus;

[0014] The memory is used to store a computer program;

[0015] The processor is configured to implement the method described in the first aspect above when executing the program stored on the memory.

[0016] In a fourth aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium, in which instructions are stored. When the instructions run on a computer, the computer is caused to execute the method described in the first aspect above.

[0017] In a fifth aspect of the embodiments of the present invention, there is also provided a computer program product containing instructions. When the computer program product runs on a computer, the computer is caused to execute the method described in the first aspect above.

[0018] The data processing method provided by the embodiments of the present invention is applied to a control node included in a data processing system. The data processing system further includes a data storage node and at least one data processing node. By responding to a data processing operation of a requesting node, the data storage node and / or the data processing node indicated by the data processing operation is determined as a target node; the requesting node is any one of the data processing nodes; the load signal of the target node is acquired; when the load signal indicates that the current load of the target node is not greater than a preset load threshold, the target node responds to the data processing operation. In this way, by setting the load signal in the embodiments of the present invention, when there is a data processing operation, the load signal of the target node can be acquired first. When the load signal indicates that the current load of the target node is not greater than the load threshold, the target node responds to the data processing operation. This can reduce the congestion on the target node, avoid the situation where the interaction waiting time is long due to network congestion, reduce the resource waste when the network is busy, and improve the data processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art.

[0020] Figure 1 It is a flowchart of steps of a data processing method in an embodiment of the present invention;

[0021] Figure 2 It is a schematic structural diagram of a data processing system in an embodiment of the present invention;

[0022] Figure 3 It is a flowchart of a data processing method in an embodiment of the present invention;

[0023] Figure 4 It is a flowchart of another data processing method in an embodiment of the present invention;

[0024] Figure 5 It is a flowchart of yet another data processing method in an embodiment of the present invention;

[0025] Figure 6 It is a schematic structural diagram of a data processing device in an embodiment of the present invention;

[0026] Figure 7 It is a schematic diagram of an electronic device in an embodiment of the present invention. Specific Embodiments

[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0028] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The term "a plurality" in the embodiments of the present invention refers to two or more, and other quantifiers are similar.

[0029] Figure 1The flowchart shows the steps of a data processing method according to an embodiment of the present invention. This method can be applied to a control node included in a data processing system, which may further include a data storage node and at least one data processing node. For example, Figure 1 as shown, the method includes:

[0030] Step 101: In response to a data processing operation of a requesting node, determine the data storage node and / or the data processing node indicated by the data processing operation as a target node; the requesting node is any one of the data processing nodes.

[0031] Step 102: Obtain a load signal of the target node.

[0032] Step 103: When the load signal indicates that the current load of the target node is not greater than a preset load threshold, respond to the data processing operation through the target node.

[0033] Regarding the above steps 101 to 103, the embodiments of the present invention can be applied to any data processing system, which may be a multi-core processor system or a distributed cluster. The embodiments of the present invention do not limit this. Correspondingly, the above control node may be a module for executing control logic in the data processing system, the above data storage node may be a memory, and the above data processing node may be a processor core or a processor group composed of multiple processor cores, which can be set according to the actual data processing system. The embodiments of the present invention do not limit this.

[0034] Exemplarily, Figure 2 The structure diagram shows a data processing system according to an embodiment of the present invention. As Figure 2 shown, Figure 2 it shows a 2*2 interconnection network framework, which includes data processing nodes (cores), a control node, and a data storage node (Memory). Each node is connected through a routing module (router), and through the routing module, request transmission and data interaction between nodes can be achieved.

[0035] Furthermore, the above requesting node is any data processing node, and any data processing node in the data processing system can initiate a data processing operation according to actual needs. Correspondingly, after receiving the data processing operation of the requesting node, the embodiments of the present invention can determine the data storage node and / or the data processing node indicated by the data processing operation as the target node.

[0036] Specifically, according to different data processing operations, the determined target nodes are different. Exemplarily, when the data processing operation indicates clearing the cache data of the request node itself, and the cache data of the request node may be updated data after data processing, in order to ensure cache consistency, it is necessary to write the cache data back to the data storage node so that other data processing nodes can obtain the updated data through the data storage node. In this case, the target node can be the data storage node.

[0037] Among them, the above load signal is used to characterize the load status of the node, that is, it is used to characterize whether there is currently a resource to respond to the data processing request at the node. Correspondingly, the above preset load threshold can be set in advance according to the actual resources of each node. On this basis, the load status of each node can be determined according to the signal value of the load signal. For example, the load signal can be set to busy. When busy = 0, it indicates that the node is in an idle state and the current load of the node is not greater than the preset load threshold. Correspondingly, when busy = 1, it indicates that the node is in a busy state and the current load of the node is greater than the above preset load threshold.

[0038] Specifically, the above data processing node and data storage node can generate the load signal by themselves according to the actual load. Of course, the above load signal can also be generated by an external detection device according to the actual load of each data processing node and data storage node. The embodiments of the present invention do not limit this.

[0039] Specifically, the above load signal can be obtained in real time, or can be actively sent by each data processing node and data storage node at a certain period. The embodiments of the present invention do not limit this. Further, after obtaining the load signal of the target node, the current load of the target node can be judged through the signal value of the load signal of the target node. If the load signal characterizes that the current load of the target node is not greater than the preset load threshold, it indicates that the target node has idle resources to respond to the data processing operation. At this time, the data processing operation can be responded to through the target node.

[0040] Optionally, when the load signal characterizes that the current load of the target node is greater than the preset load threshold, it indicates that the target node currently does not have idle resources to respond to the data processing operation. At this time, it can wait until the current load of the target node is not greater than the preset load threshold, and then respond to the data processing operation through the target node.

[0041] In summary, the data processing method provided by the embodiments of the present invention is applied to a control node included in a data processing system. The data processing system further includes a data storage node and at least one data processing node. By responding to a data processing operation of a requesting node, the data storage node and / or the data processing node indicated by the data processing operation is determined as a target node; the requesting node is any one of the data processing nodes; a load signal of the target node is obtained; and when the load signal indicates that the current load of the target node is not greater than a preset load threshold, the target node responds to the data processing operation. In this way, by setting the load signal, when there is a data processing operation, the load signal of the target node can be obtained first, and when the load signal indicates that the current load of the target node is not greater than the load threshold, the target node responds to the data processing operation, which can reduce the congestion on the target node, avoid the situation of long interaction waiting time caused by network congestion, reduce the resource waste when the network is busy, and improve the data processing efficiency.

[0042] Optionally, the above data processing system further includes a last-level cache. The control node includes multiple entries, and one entry corresponds to a cache block in the last-level cache. Each entry includes a first parameter and a second parameter; the first parameter represents the data processing node that contains the cached data of the cache block corresponding to the entry; the second parameter represents the data processing node that last processed the cached data of the cache block corresponding to the entry. The embodiments of the present invention may specifically further include:

[0043] S21. Based on the multiple entries in the control node, determine the data processing node indicated by the data processing operation.

[0044] Among them, the above last-level cache (LLC) refers to the last-level cache in a multi-level cache, and its next-level storage area is the memory. Correspondingly, the next level of the LLC in the embodiments of the present invention is the data storage node, and the previous level is the higher-level cache in the data processing node.

[0045] It should be noted that in the cache system, data access is usually performed according to the cache hierarchy, that is, from the high-level cache to the next-level cache in turn until the required data is accessed. On this basis, when the data processing node accesses the data storage node, it usually needs to pass through the LLC.

[0046] On this basis, embodiments of the present invention can set multiple entries in the control node. Different entries correspond to different cache lines in the last-level cache. An entry includes a first parameter and a second parameter. The first parameter represents the data processing node that contains the cache data of the cache line corresponding to the entry, and the second parameter represents the data processing node that last processed the cache data of the cache line corresponding to the entry.

[0047] Exemplarily, embodiments of the present invention can represent the first parameter in vector form. Further, the first parameter can be represented by cn_vector. For example, if there are three data processing nodes, the first data processing node and the second data processing node contain the cache data of the cache line corresponding to a certain entry, and the third does not, then the first parameter corresponding to this entry can be (cn_vector = 110). Another exemplarily, the third data processing node contains the cache data corresponding to this entry, and the first and second data processing nodes do not, then the first parameter corresponding to this entry can be (cn_vector = 001).

[0048] Among them, the above second parameter can be represented by cn_id, which can be the identifier of the data processing node that last processed the cache data of the cache line corresponding to the entry.

[0049] Specifically, embodiments of the present invention can determine the data processing node indicated by the data processing operation based on multiple entries in the control node. Specifically, the data processing operation can include the cache line corresponding to the data to be processed. Correspondingly, while the request node executes this data processing operation, in order to maintain the cache consistency of the system, embodiments of the present invention also need to perform consistency processing on the data corresponding to this cache line in the data storage node and other data processing nodes. On this basis, embodiments of the present invention can then determine the data processing node indicated by the data processing operation based on multiple entries in the control node. On this basis, through the first parameter and the second parameter in multiple entries, embodiments of the present invention can determine in which data processing nodes the cache data of each cache line exists, and at the same time, can determine in which data processing nodes the latest data of this cache line exists, facilitating subsequent cache consistency processing operations.

[0050] In an embodiment of the present invention, the data processing system further includes a last-level cache. The control node includes multiple table entries, where one table entry corresponds to one cache block in the last-level cache, and each table entry includes a first parameter and a second parameter. The first parameter characterizes the data processing node that contains the cached data of the cache block corresponding to the table entry. The second parameter characterizes the data processing node that last processed the cached data of the cache block corresponding to the table entry. Based on the multiple table entries in the control node, the data processing node indicated by the data processing operation is determined. In this way, the existence status of different cache blocks can be recorded through the table entries in the control node, so that the data processing node indicated by the data processing operation can be directly determined based on multiple table entries, which improves the data processing efficiency to a certain extent and facilitates subsequent cache coherence processing operations.

[0051] Optionally, when the data processing operation instructs to clear the data of the target cache block in the request node, the operation of determining the data storage node and / or the data processing node indicated by the data processing operation as the target node in the embodiments of the present invention may specifically include:

[0052] S31. Determine the data storage node as the target node.

[0053] The operation of the target node responding to the data processing operation in the embodiments of the present invention may specifically include:

[0054] S32. Write the cached data of the target cache block in the last-level cache to the target node.

[0055] Herein, clearing the data of the target cache block means clearing the cached data corresponding to the target cache block in the request node itself. At this time, the request node may have processed the data of the target cache block, and the data of the target cache block in the request node may be inconsistent with the data of the target cache block in the data storage node, that is, there is dirty data (dirty cache line). After the request node itself clears the data of the target cache block, in order to prevent inaccurate data from being obtained by the next time or other data processing nodes, cache coherence processing needs to be performed on the data storage node. Therefore, at this time, the data storage node can be determined as the target node. Correspondingly, responding to the data processing operation means responding to the data processing operation and ensuring cache coherence.

[0056] On this basis, the embodiments of the present invention can write the cached data of the target cache block in the LLC to the data storage node to complete the update of the cached data and ensure cache coherence.

[0057] It should be noted that the above operations can be performed when the request node is consistent with the LLC, that is, the data of the target cache block in the LLC is the same as the data in the request node. Correspondingly, the data processing operation at this time can be an EvictClean transaction to clear the cache completely.

[0058] In an embodiment of the present invention, when the data processing operation indicates to clear the data of the target cache block in the request node, the data storage node is determined as the target node; and the cache data of the target cache block in the last-level cache is written to the target node. In this way, when any data processing node clears its own data, the corresponding data can be written to the target node to ensure the cache consistency of the system.

[0059] Optionally, for the operation of obtaining the load signal of the target node, the embodiment of the present invention may specifically include:

[0060] S41. Obtain the coherence state of the target cache block in the last-level cache.

[0061] S42. When the coherence state indicates inconsistency and the first parameter and the second parameter corresponding to the target entry indicate that other nodes do not contain the data of the target cache block, obtain the load signal of the target node; the target entry is the entry corresponding to the target cache block in the control node, and the other nodes are data processing nodes other than the request node.

[0062] Among them, the above coherence state is used to indicate whether the data of the current level is consistent with that of the next level. Correspondingly, the coherence state of the last-level cache is used to indicate its consistency with the data storage node (memory).

[0063] Specifically, the embodiment of the present invention can set an entry in the last-level cache to record its consistency with the data storage node. For example, the LLC tag can be used to represent the coherence state of different cache blocks in the LLC. If it is 0, it indicates that the cache block is consistent in the LLC and the data storage node; if it is 1, it indicates inconsistency. Of course, other forms can also be used for representation, and the embodiment of the present invention does not limit this.

[0064] Accordingly, when the consistency state indicates inconsistency, it means that the target cache block is inconsistent in the LLC and the data storage node. At the same time, if the first parameter and the second parameter corresponding to the target entry indicate that other nodes do not contain the data of the target cache block, it means that only the requesting node contains the data of the target cache block. After the requesting node clears the data of the target cache block, the latest data of the target cache block can only be obtained through the LLC. In this case, in order to ensure that any data processing node can obtain the latest data of the target cache block through the data storage node in subsequent processing, it is necessary to perform cache coherence processing on the LLC and the data storage node. At this time, the load signal of the target node can be obtained.

[0065] Accordingly, if the consistency state indicates consistency, it means that the target cache block is consistent in the LLC and the data storage node, and any subsequent data processing node can obtain the latest data of the target cache block through the data storage node. Then, there is no need to perform cache coherence processing on the LLC and the data storage node, that is, there is no need to obtain the load signal of the target node. Or, when the first parameter and the second parameter corresponding to the target entry indicate that other nodes contain the data of the target cache block, it means that there is also the data of the target cache block in other data processing nodes. Then, when there is a data acquisition requirement, there is no need to obtain it through the data storage node, and the data of the target cache block can be accessed by other data processing nodes. At this time, there is also no need to perform cache coherence processing on the LLC and the data storage node, that is, there is no need to obtain the load signal of the target node.

[0066] In the embodiment of the present invention, the consistency state of the target cache block in the last-level cache is obtained; when the consistency state indicates inconsistency and the first parameter and the second parameter corresponding to the target entry indicate that other nodes do not contain the data of the target cache block, the load signal of the target node is obtained; the target entry is the entry corresponding to the target cache block in the control node, and the other nodes are data processing nodes other than the requesting node. In this way, the load signal of the target node is obtained only when there is a cache coherence requirement, which can reduce unnecessary data processing operations to a certain extent and further reduce ineffective resource waste.

[0067] Optionally, when the data processing operation indicates obtaining the exclusive permission of the target cache block, the operation of determining the data storage node and / or the data processing node indicated by the data processing operation as the target node in the embodiment of the present invention may specifically include:

[0068] S51. Obtain other nodes that contain the data of the target cache block based on the first parameter corresponding to the target entry, as the data processing nodes indicated by the data processing operation; the target entry is the entry corresponding to the target cache block in the control node, and the other nodes are data processing nodes other than the requesting node.

[0069] S52. Determine the data processing nodes indicated by the data processing operation as the target nodes.

[0070] The operation of the above-mentioned target node responding to the data processing operation includes:

[0071] S53. Clear the data of the target cache block in the target node.

[0072] Among them, the above-mentioned exclusive permission refers to the Unique permission, that is, only the requesting node is allowed to have the permission to modify the target cache block. On this basis, in order to ensure cache consistency, it is necessary to clear (clean) the data corresponding to the target cache block in other data processing nodes.

[0073] Specifically, other nodes that contain the data of the target cache block can be obtained based on the first parameter of the target entry corresponding to the target cache block in the control node, as the target nodes. Specifically, based on the first parameter of the target entry, other nodes where the data of the target cache block currently exists can be obtained, and then they can be used as the target nodes. Correspondingly, the above-mentioned operation of the target node responding to the data processing operation can be to clear the data of the target cache block in the target node.

[0074] Specifically, the control node can send a data clearing instruction to the target node, and this instruction can carry the identifier of the target cache block. Then, after receiving the data clearing instruction, the target node can clear the corresponding data according to the identifier carried in the instruction. Correspondingly, the data processing operation at this time can be a transaction of invalidating other data processing nodes (InvalidOthers).

[0075] In the embodiments of the present invention, when the data processing operation indicates obtaining the exclusive permission of the target cache block, other nodes that contain the data of the target cache block are obtained based on the first parameter corresponding to the target entry, as the data processing nodes indicated by the data processing operation; the target entry is the entry corresponding to the target cache block in the control node, and the other nodes are data processing nodes other than the requesting node; the data processing nodes indicated by the data processing operation are determined as the target nodes; the data of the target cache block in the target node is cleared. In this way, when the requesting node obtains the exclusive permission, invalidation operations can be performed on other nodes that contain the data of the target cache block, avoiding the situation of cache inconsistency.

[0076] Optionally, when the data processing operation indicates clearing the inconsistent state of the target cache block in the data processing system, determining the data storage node and / or the data processing node indicated by the data processing operation as the target node includes:

[0077] S61. Determine the data storage node as the target node.

[0078] The operations of the embodiments of the present invention for the target node to respond to the data processing operation specifically may include:

[0079] S62. Write the cached data of the target cache block in the node to be processed into the target node; the node to be processed is the data processing node containing the data of the target cache block.

[0080] Wherein, when the data processing operation indicates clearing the inconsistent state of the target cache block in the data processing system, it is necessary to clear the inconsistent states of all data processing nodes containing the data of the target cache block. That is, if there is at least one data processing node whose data corresponding to the target cache block is inconsistent with the data storage node, then clear the data corresponding to the target cache block in this data processing node and write the data back to the data storage node. On this basis, the data storage node can be determined as the target node.

[0081] Meanwhile, the cached data of the target cache block in the node to be processed can be written into the data storage node. Correspondingly, the data processing operation at this time can be a transaction for clearing the inconsistent state (CleanOthers) of other data processing nodes.

[0082] In the embodiments of the present invention, when the data processing operation indicates clearing the inconsistent state of the target cache block in the data processing system, determine the data storage node as the target node; write the cached data of the target cache block in the node to be processed into the target node; the node to be processed is the data processing node containing the data of the target cache block. Cache consistency maintenance can be achieved for the data processing system.

[0083] Optionally, the operations of the embodiments of the present invention for obtaining the load signal of the target node specifically may include:

[0084] S71. Obtain the node to be processed based on the first parameter corresponding to the target entry; the target entry is the entry corresponding to the target cache block in the control node.

[0085] S72. Obtain the consistency state of the target cache block in the node to be processed.

[0086] S73. When the consistency state indicates inconsistency, obtain the load signal of the target node.

[0087] Specifically, the to-be-processed node mentioned above refers to the data processing node containing the data of the target cache block. Correspondingly, the to-be-processed node can be obtained by controlling the first parameter of the target entry in the control node. Correspondingly, the consistency state of the target cache block in the to-be-processed node can be further obtained. If it is consistent, it indicates that there is no dirty data in the target cache block and there is no need to write it back to the data storage node. Correspondingly, if it is inconsistent, it needs to be written back to the data storage node. At this time, the load signal of the data storage node can be obtained.

[0088] In the embodiment of the present invention, based on the first parameter corresponding to the target entry, the to-be-processed node is obtained; the target entry is the entry corresponding to the target cache block in the control node; the consistency state of the target cache block in the to-be-processed node is obtained; when the consistency state indicates inconsistency, the load signal of the target node is obtained. In this way, when the consistency state of the to-be-processed node is inconsistent, the load signal of the target node can be obtained in response to the data processing operation, which can avoid invalid data processing operations and reduce the waste of network resources to a certain extent.

[0089] It should be noted that the above control node can be composed of LLC and snoop filter (SF), and correspondingly, the above control node can be called LLCSF. The embodiment of the present invention can be applied to the scenario where the control node adopts the Modified, Owned, Exclusive, Shared, Invalid (MOESI) protocol and the Core node follows the Modified, Exclusive, Shared, Invalid (MESI) protocol. Since the consistency protocol states followed by the Core node and the control node are different, the cacheline in the SharedDirty state must be recorded in the control node. For a cacheline in the LLC node, after entering the Shared state from the Unique state, it will not return to the Unique state unless the data in the cacheline is kicked out (victim) and rewritten.

[0090] At the same time, the embodiment of the present invention can record the consistency state of the cacheline (which can be represented by 00, 01, etc.) in the LLC tag of the control node. At the same time, there is no need to record the consistency state in the SF tag, and only the above first parameter and second parameter need to be recorded.

[0091] Meanwhile, the embodiments of the present invention can allow the Core node to silently delete clean data. At the same time, since the consistency state does not need to be recorded in the SF tag, the control node can update the first parameter and the second parameter in the SF each time all broadcast results are received to ensure the update speed of the entries in the control node, thereby reducing the invalid traffic in the network.

[0092] Exemplarily, Figure 3 is a flowchart of a data processing method in the embodiments of the present invention, Figure 4 is a flowchart of another data processing method in the embodiments of the present invention, Figure 5 is a flowchart of yet another data processing method in the embodiments of the present invention. Figure 3 Corresponding to the EvictClean transaction, that is, the data processing operation instructs to clear the data of the target cache block in the requesting node. Figure 4 Corresponding to the InvalidOthers transaction, Figure 5 Corresponding to the CleanOthers transaction.

[0093] Specifically, as Figure 3 shown, when executing the clean cache transaction, first query the hit result in the control node. Specifically, it is possible to query in the LLC of the control node whether the cache is hit, that is, whether there is data in the LLC for the cache block indicated by the data processing request. If there is, the cache is hit; if not, the cache is not hit. At the same time, it is possible to query in the SF of the control node whether the entry is hit, that is, whether the first parameter and the second parameter exist in the corresponding entry of the SF for the cache block indicated by the data processing request. If they exist, the entry is hit; if not, the entry is not hit.

[0094] Furthermore, in the case where the cache is not hit and the entry is hit, if only the requesting node is recorded in the control node, that is, both the first parameter and the second parameter in the corresponding entry of the SF for the cache block only point to the requesting node of the data processing operation, it indicates that no other data processing nodes contain the data corresponding to the cache block, and at this time the data in the cache block in the requesting node has been written back to the data storage node. Therefore, there is no need to perform cache consistency operations, and only the corresponding data needs to be deleted in the requesting node. After deletion, invalidate the corresponding entry of the cache block in the control node, indicating that all data processing nodes do not contain the data corresponding to the cache block at this time.

[0095] Furthermore, in the case where the cache is not hit and the entry is hit, if the control node records not only the requesting node, it indicates that there is at least one other data processing node that contains the data corresponding to the cache block. At this time, the corresponding data can be deleted in the requesting node, and at the same time, the requesting node can be removed from the corresponding entry in the control node to complete the update of the SF.

[0096] Further, in the case of cache hit and entry hit, if only the requesting node is recorded in the entry, first judge the consistency state of the cache, that is, judge whether the data in the cache block in the LLC is consistent with the data in the data storage node. If they are consistent, the cache is in a clean state; if not, the cache is in a dirty state. In the clean case, after deleting the corresponding data in the requesting node, first invalidate the entry corresponding to the cache block in the control node, indicating that all data processing nodes do not contain the data corresponding to the cache block at this time.

[0097] Correspondingly, in the dirty case, obtain the load signal of the data storage node. If the load signal is 0 (the current load is not greater than the preset load threshold), invalidate the corresponding entry, that is, invalidate the entry corresponding to the cache block in the control node. At the same time, write the data of the corresponding cache block in the LLC back to the data storage node. If the load signal is 1, invalidate the corresponding entry and retain the data of the corresponding cache block in the LLC, and the write-back operation can be performed when the load signal of the data storage node becomes 0.

[0098] Further, in the case of cache hit and entry hit, if the entry records not only the requesting node, indicating that at least one other data processing node contains the data of the cache block, there is no need to perform a write-back operation at this time. After deleting the corresponding data in the requesting node, remove the requesting node from the entry corresponding to the cache block in the control node, that is, remove the requesting node from the first parameter and the second parameter corresponding to the cache block.

[0099] Specifically, as Figure 4 shown, when executing a transaction to invalidate data of other data processing nodes, first query the hit result in the control node. Specifically, it is possible to query whether the cache is hit in the LLC of the control node, that is, whether there is data in the LLC for the cache block indicated by the data processing request. If there is, the cache is hit; if not, the cache is not hit. At the same time, it is possible to query whether the entry is hit in the SF of the control node, that is, whether the first parameter and the second parameter exist in the entry corresponding to the cache block indicated by the data processing request in the SF. If they exist, the entry is hit; if not, the entry is not hit.

[0100] Further, in the case of cache miss, it indicates that the data does not exist in the cache, and there is no need to perform an invalidation operation on the LLC at this time. Correspondingly, in the case of cache hit, invalidate the cache block in the LLC to facilitate the requesting node to obtain the Unique permission for the cache block.

[0101] Meanwhile, when the table entry is hit, if only the requesting node is recorded in the table entry, it indicates that currently only the requesting node contains the data corresponding to the cache block, and none of the other data processing nodes contain this data. Therefore, no additional operations need to be performed on the other data processing nodes at this time. Correspondingly, if not only the requesting node is recorded in the table entry, the target node can be determined according to the first parameter in the table entry. The target node refers to the other data processing nodes included in the first parameter of the cache block. The target node is a data processing node other than the requesting node that contains the data of this cache block. Correspondingly, to facilitate the requesting node to obtain the Unique permission for this cache block, a data clearing request is sent to the target node. After receiving the data clearing request, the target node clears the corresponding cache block data in the target node.

[0102] Further, after the clearing is completed, the table entry corresponding to this cache block can be updated so that it only records the requesting node, indicating that currently only the requesting node contains the data of this cache block.

[0103] Specifically, as Figure 5 shown, when executing a transaction to clear the inconsistent state of other data processing nodes, first query the hit result in the control node. Specifically, it can be queried in the LLC of the control node whether the cache is hit, that is, whether there is data in the LLC for the cache block indicated by the data processing request. If there is, the cache is hit; if not, the cache is not hit. At the same time, it can be queried in the SF of the control node whether the table entry is hit, that is, whether there are the first parameter and the second parameter in the corresponding table entry of the SF for the cache block indicated by the data processing request. If there are, the table entry is hit; if not, the table entry is not hit.

[0104] Further, in the case of cache hit, judge the state of this cache block in the LLC. If it is in the clean state, it indicates that there is no inconsistent state in the current data processing system, and no other operations need to be performed. If it is in the dirty state, it indicates that this cache block is inconsistent with the data storage node in the LLC. Then, the load signal of the data storage node can be obtained. When the load signal is 0, write this data back to the data storage node to achieve the clearing of the dirty state of the LLC.

[0105] Further, in the case of cache miss, if the table entry is hit, the load signal of the data storage node can be obtained. If the load signal is 1, the corresponding cache block data in the node to be processed can be obtained according to the hit table entry and stored in the control node. The node to be processed refers to the data processing node that contains the corresponding cache block data, and the node to be processed can be obtained according to the first parameter and the second parameter of the hit table entry. Further, after waiting for the load signal of the data storage node to be 0, write the corresponding cache block data from the control node to the data storage node.

[0106] Meanwhile, if the load signal is 0, the data in the corresponding cache block in the node to be processed can be directly obtained and written to the data storage node.

[0107] Further, in the case of cache miss, if the entry is also missed, it indicates that the cache block data indicated does not exist in both the data processing node and the LLC, and thus no other operations need to be performed.

[0108] It should be noted that since multiple caches may store copies of the same data, when a processor modifies the data, how to ensure that the copy data in all caches remains consistent becomes a key issue. Existing mainstream cache coherence protocols define various operation types for cache - to - cache communication. With the continuous development of the protocols, in order to adapt to different application scenarios and optimize performance, the types and the number of fields of the coherence transfer instructions are constantly increasing, making the protocol implementation complex and difficult to apply flexibly. At the same time, the complex instruction sets of existing mainstream coherence protocols significantly increase the debugging and verification costs for application parties. In a multi - core system, potential errors are increasingly difficult to discover and fix.

[0109] In the embodiment of the present invention, it is applied to a control node included in a data processing system. The data processing system further includes a data storage node and at least one data processing node. By responding to the data processing operation of a request node, the data storage node, and / or the data processing node indicated by the data processing operation is determined as a target node; the request node is any one of the data processing nodes; the load signal of the target node is obtained; and in the case where the load signal indicates that the current load of the target node is not greater than a preset load threshold, the target node responds to the data processing operation. In this way, in the embodiment of the present invention, by setting the load signal, when there is a data processing operation, the load signal of the target node can be obtained first. When the load signal indicates that the current load of the target node is not greater than the load threshold, the target node responds to the data processing operation, which can reduce the congestion on the target node, avoid the situation where the network congestion leads to a long interaction waiting time, reduce the resource waste when the network is busy, and improve the data processing efficiency.

[0110] Meanwhile, this method requires fewer resources in the early development and debugging, and thus can reduce the development and debugging costs.

[0111] Figure 6 The following is a schematic structural diagram of a data processing device in the embodiment of the present invention. The device is applied to a control node included in a data processing system. The data processing system further includes a data storage node and at least one data processing node. As Figure 6 shown, the device 20 may include:

[0112] The first determination module 201 is configured to, in response to a data processing operation of a requesting node, determine the data storage node and / or the data processing node indicated by the data processing operation as a target node; the requesting node is any one of the data processing nodes;

[0113] The first acquisition module 202 is configured to acquire a load signal of the target node;

[0114] The response module 203 is configured to, when the load signal indicates that the current load of the target node is not greater than a preset load threshold, respond to the data processing operation through the target node.

[0115] Optionally, the data processing system further includes a last-level cache, and the control node includes a plurality of table entries. One table entry corresponds to one cache block in the last-level cache, and each table entry includes a first parameter and a second parameter; the first parameter represents the data processing node of the cache data of the cache block corresponding to the table entry; the second parameter represents the data processing node that last processed the cache data of the cache block corresponding to the table entry;

[0116] The apparatus further includes:

[0117] The second determination module is configured to determine the data processing node indicated by the data processing operation based on the plurality of table entries in the control node.

[0118] Optionally, when the data processing operation indicates clearing the data of a target cache block in the requesting node, the first determination module is specifically configured to: determine the data storage node as the target node;

[0119] The response module is specifically configured to:

[0120] Write the cache data of the target cache block in the last-level cache to the target node.

[0121] Optionally, the first acquisition module includes:

[0122] The second acquisition sub-module is configured to acquire the coherence state of the target cache block in the last-level cache;

[0123] The third acquisition sub-module is configured to acquire the load signal of the target node when the coherence state indicates inconsistency and the first parameter and the second parameter of the target table entry indicate that other nodes do not include the data of the target cache block; the target table entry is the table entry corresponding to the target cache block in the control node, and the other nodes are data processing nodes other than the requesting node.

[0124] Optionally, when the data processing operation indicates obtaining exclusive permission for a target cache block, the first determination module includes:

[0125] A fourth acquisition sub-module, configured to, based on a first parameter corresponding to a target entry, acquire other nodes containing data of the target cache block as data processing nodes indicated by the data processing operation; the target entry is an entry corresponding to the target cache block in the control node, and the other nodes are data processing nodes other than the request node;

[0126] A third determination sub-module, configured to determine the data processing node indicated by the data processing operation as a target node;

[0127] The response module is specifically configured to:

[0128] Clear the data of the target cache block in the target node.

[0129] Optionally, when the data processing operation indicates clearing the inconsistent state of a target cache block in the data processing system, the first determination module is specifically configured to: determine the data storage node as the target node;

[0130] The response module is specifically configured to:

[0131] Write the cached data of the target cache block in the node to be processed into the target node; the node to be processed is a data processing node containing data of the target cache block.

[0132] Optionally, the first acquisition module includes:

[0133] A fifth acquisition sub-module, configured to, based on a first parameter corresponding to a target entry, acquire a node to be processed; the target entry is an entry corresponding to the target cache block in the control node;

[0134] A sixth acquisition sub-module, configured to acquire the consistency state of the target cache block in the node to be processed;

[0135] A seventh acquisition sub-module, configured to, when the consistency state indicates inconsistency, acquire the load signal of the target node.

[0136] In summary, the data processing device provided in the embodiments of the present invention is applied to a control node included in a data processing system. The data processing system further includes a data storage node and at least one data processing node. By responding to a data processing operation of a requesting node, the data storage node and / or the data processing node indicated by the data processing operation is determined as a target node. The requesting node is any one of the data processing nodes. A load signal of the target node is obtained. When the load signal indicates that the current load of the target node is not greater than a preset load threshold, the target node responds to the data processing operation. In this way, by setting the load signal, in the presence of a data processing operation, the load signal of the target node can be obtained first, and when the load signal indicates that the current load of the target node is not greater than the load threshold, the target node responds to the data processing operation. This can reduce the congestion on the target node, avoid the situation where the interaction waiting time is long due to network congestion, reduce the waste of resources when the network is busy, and improve the data processing efficiency.

[0137] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, please refer to the partial description of the method embodiments.

[0138] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0139] Regarding the request processing device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0140] The embodiments of the present invention further provide an electronic device, including: a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the above data processing method.

[0141] Refer to Figure 7 , which is a schematic structural diagram of the electronic device provided in the embodiments of the present invention. As Figure 7 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus. The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the data processing method of the foregoing embodiments.

[0142] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0143] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0144] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, Figure 3 only one line is shown in the figure, but it does not mean that there is only one bus or one type of bus. <{

[0145] The memory may be a ROM (Read Only Memory), or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory), or other types of dynamic storage devices that can store information and instructions. It may also be an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, and optical data storage devices, etc.

[0146] The embodiment of the present invention also provides a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), the processor can execute Figure 1 the data processing method shown.

[0147] The embodiment of the present invention also provides a computer program product containing instructions. When it runs on a computer, the computer is enabled to execute Figure 1 the data processing method shown.

[0148] An embodiment of the present application further provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is configured to run programs or instructions to implement each process of the above data processing method embodiment and can achieve the same technical effects. To avoid repetition, details are not described herein again.

[0149] It should be understood that the chip mentioned in the embodiment of the present application may also be referred to as a system-on-chip, system chip, chip system, or system-on-a-chip, etc.

[0150] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0151] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, apparatus, or computer program product. Therefore, the embodiments of the present invention can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available media can be magnetic media (such as floppy disks, hard disks, magnetic tapes), optical media (such as DVDs), or semiconductor media (such as solid state disk (SSD)), etc.

[0152] Embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate means for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0153] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal device to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including instruction means, and the instruction means implement the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0154] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0155] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0156] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0157] It should be noted that in the embodiments of the present application, the processes of obtaining various data are all carried out on the premise of complying with the corresponding data protection regulations and policies of the country where the location is located and obtaining the authorization given by the owner of the corresponding device.

[0158] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the said element.

[0159] The above has introduced in detail a data processing method, apparatus, electronic device and readable storage medium provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A data processing method, characterized in that, The method is applied to a control node included in a data processing system, which further includes a data storage node and at least one data processing node. The method includes: In response to a data processing operation of a requesting node, determining the data storage node, and / or, the data processing node indicated by the data processing operation, as a target node; the requesting node is any one of the data processing nodes; Obtaining a load signal of the target node; When the load signal indicates that the current load of the target node is not greater than a preset load threshold, responding to the data processing operation through the target node.

2. The method according to claim 1, wherein The data processing system further includes a last-level cache. The control node contains a plurality of table entries, one table entry corresponding to one cache block in the last-level cache. Each table entry includes a first parameter and a second parameter; the first parameter represents the data processing node that contains the cache data of the cache block corresponding to the table entry; The second parameter represents the data processing node that last processed the cache data of the cache block corresponding to the table entry; The method further includes: Based on the plurality of table entries in the control node, determining the data processing node indicated by the data processing operation.

3. The method according to claim 2, wherein When the data processing operation indicates clearing the data of a target cache block in the requesting node, the determining the data storage node, and / or, the data processing node indicated by the data processing operation, as a target node includes: determining the data storage node as the target node; The responding to the data processing operation through the target node includes: Writing the cache data of the target cache block in the last-level cache to the target node.

4. The method according to claim 3, wherein The obtaining a load signal of the target node includes: Obtaining the coherence state of the target cache block in the last-level cache; When the coherence state indicates incoherence, and the first parameter and the second parameter corresponding to the target table entry indicate that other nodes do not contain the data of the target cache block, obtaining the load signal of the target node; the target table entry is the table entry corresponding to the target cache block in the control node, and the other nodes are data processing nodes other than the requesting node.

5. The method according to claim 2, wherein When the data processing operation indicates obtaining exclusive permission for a target cache block, the determining the data storage node, and / or, the data processing node indicated by the data processing operation, as a target node includes: Based on the first parameter corresponding to the target table entry, obtaining other nodes that contain the data of the target cache block, as the data processing node indicated by the data processing operation; the target table entry is the table entry corresponding to the target cache block in the control node, and the other nodes are data processing nodes other than the requesting node; Determining the data processing node indicated by the data processing operation as the target node; The responding to the data processing operation through the target node includes: Clearing the data of the target cache block in the target node.

6. The method according to claim 2, wherein When the data processing operation indicates clearing the inconsistent state of the target cache block in the data processing system, determining the data storage node, and / or the data processing node indicated by the data processing operation, as the target node includes: determining the data storage node as the target node; Responding to the data processing operation through the target node includes: Writing the cached data of the target cache block in the node to be processed into the target node; the node to be processed is the data processing node containing the data of the target cache block.

7. The method according to claim 6, wherein Obtaining the load signal of the target node includes: Based on the first parameter corresponding to the target entry, obtaining the node to be processed; the target entry is the entry corresponding to the target cache block in the control node; Obtaining the consistency state of the target cache block in the node to be processed; When the consistency state indicates inconsistency, obtaining the load signal of the target node.

8. A data processing device, characterized in that, The device is applied to a control node included in a data processing system, the data processing system further includes a data storage node and at least one data processing node, and the device includes: A first determination module, configured to, in response to a data processing operation of a requesting node, determine the data storage node, and / or the data processing node indicated by the data processing operation, as the target node; the requesting node is any one of the data processing nodes; A first acquisition module, configured to acquire the load signal of the target node; A response module, configured to, when the load signal indicates that the current load of the target node is not greater than a preset load threshold, respond to the data processing operation through the target node.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used to store a computer program; When the processor is configured to execute the program stored on the memory, it implements the method according to any one of claims 1-7.

10. A computer-readable storage medium, on which a computer program is stored, characterized in that, When the program is executed by the processor, it implements the method according to any one of claims 1-7.

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