Connection configuration method of computing device, computing device, system and apparatus

Abstract

The present application discloses a method for configuring a connection of a computing device, a computing device, a system, and an apparatus, and relates to the field of device management technology. After a user changes the line connection mode of a computing device, the line connection mode of the computing device is automatically identified by a switching processor, and the firmware adapted to the line connection mode is automatically switched to, thereby reducing the difficulty of configuring the connection of the computing device and improving the versatility of the computing device.

Description

Technical Field

[0001] The present application relates to the field of device management technology, and in particular to a connection configuration method for a computing device, a computing device, a system, and an apparatus. Background Art

[0002] With the rapid development of compute-intensive applications, users are placing higher demands on the hardware devices that perform computations. Accelerators can improve computing efficiency. Interconnecting multiple accelerators to achieve collaborative operation further improves computing efficiency.

[0003] In related technologies, multiple accelerators are connected using a fixed connection method that adapts to the corresponding application scenario. When the application scenario changes, the original connection method is no longer suitable and needs to be adjusted. However, adjusting the connection method is complex, resulting in low versatility of the device. Summary of the Invention

[0004] The present application provides a connection configuration method for a computing device, a computing device, a system and an apparatus to at least solve the problem of low versatility of computing devices in related technologies.

[0005] The present application provides a connection configuration method for a computing device, which is applied to the computing device, wherein the computing device includes at least one switching processor, a first controller, and at least one connection port. For any connection port, the method includes: obtaining a first level state of an identification pin of the connection port through the first controller, and sending the first level state to the switching processor; determining a line connection mode corresponding to the connection port through the switching processor based on the first level state; and matching firmware corresponding to the line connection mode through the switching processor, so that the connection port performs data transmission according to the line connection mode.

[0006] The present application also provides a computing device, comprising: at least one switching board, at least one switching processor, a first controller, and at least one connection port, wherein the switching processor, the first controller, and multiple connection ports are installed on the switching board; the first controller is connected to the multiple connection ports and the switching processor through the internal circuit of the switching board, and the first controller is used to obtain a first level state of an identification pin of the connection port and send the first level state to the switching processor; the switching processor is used to determine a line connection mode corresponding to the connection port based on the first level state; the switching processor is also used to match firmware corresponding to the line connection mode, so that the connection port transmits data according to the line connection mode.

[0007] The present application also provides a computing system, including: a host, a power supply, and a computing device, wherein the host is connected to a second connector of the computing device, and the host is used to manage the computing system; the power supply is connected to a power supply connector of the computing device and the host, and the power supply is used to power the computing system.

[0008] The present application also provides a connection configuration device for a computing device, which is applied to the computing device, wherein the computing device includes at least one switching processor, a first controller, and at least one connection port; for any connection port, the device includes: an acquisition module, which is used to obtain a first level state of an identification pin of the connection port through the first controller and send the first level state to the switching processor; a determination module, which is used to determine a line connection mode corresponding to the connection port through the switching processor according to the first level state; and a matching module, which is used to match firmware corresponding to the line connection mode through the switching processor, so that the connection port transmits data according to the line connection mode.

[0009] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned connection configuration methods for computing devices when executing the computer program.

[0010] The present application also provides a non-volatile computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned connection configuration methods for computing devices are implemented.

[0011] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned connection configuration methods for computing devices when executed by a processor.

[0012] Through this application, after the user changes the line connection mode of the computing device, the switching processor automatically identifies the line connection mode of the computing device and automatically switches to firmware adapted to the line connection mode, thereby reducing the difficulty of connection configuration of the computing device and improving the versatility of the computing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 A schematic diagram of an application scenario of a computing device provided in an embodiment of the present application;

[0015] Figure 2A flowchart of a method for configuring a connection of a computing device provided in an embodiment of the present application;

[0016] Figure 3 A flowchart of a method for configuring a connection of a computing device provided in an embodiment of the present application;

[0017] Figure 4 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0018] Figure 5 A schematic structural diagram of a first connector provided in an embodiment of the present application;

[0019] Figure 6 A schematic diagram of the structure of a circuit board provided in an embodiment of the present application;

[0020] Figure 7 A schematic diagram of the structure of the inter-board connection provided in the embodiment of the present application;

[0021] Figure 8a A schematic diagram of a fully interconnected connection provided in an embodiment of the present application;

[0022] Figure 8b A schematic diagram of a non-fully interconnected connection provided in an embodiment of the present application;

[0023] Figure 9 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0024] Figure 10 A schematic diagram of the structure of the power supply board provided in an embodiment of the present application;

[0025] Figure 11 A schematic diagram of the structure of a computing system provided in an embodiment of the present application;

[0026] Figure 12 A schematic diagram of the structure of a connection configuration device for a computing device provided in an embodiment of the present application;

[0027] Figure 13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0030] It should be noted that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely for ease of description and simplification of the present application. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "mounted," "connected," and "connected" should be interpreted broadly, and may include, for example, fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. The terms "parallel," "perpendicular," and "equal" encompass the described conditions and conditions similar to the described conditions, provided that the range of the similar conditions is within an acceptable range of deviation, as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes both absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes both absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes both absolute equality and approximate equality, where the acceptable deviation range for approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0031] For example, a computing device manages multiple devices to perform data computations. For server applications, the computing device may include a switching processor and at least one accelerator. The computing device can be used to manage multiple accelerators through the switching processor to perform data computations. The accelerator performs computations and features a massively parallel architecture with a deeply optimized data throughput design. It contains numerous computing cores, each dedicated to executing specific instructions, effectively implementing parallel computing. The accelerator uses hardware-level thread scheduling to host dozens of task threads on each computing core. When a thread stalls due to unavailable data, the hardware seamlessly switches to the next thread, avoiding long waits and improving computing efficiency. The accelerator utilizes onboard high-bandwidth video memory, directly connected to the computing core via chip stacking technology, extending memory bandwidth to several times that of the processor's main memory, thereby improving computing efficiency. The accelerator eliminates common processor logic, such as complex branch prediction and out-of-order execution, allowing it to focus on computation, thereby improving efficiency. The switching processor manages multiple accelerators to ensure the correct transmission of computational data, enabling the accelerator to operate normally.

[0032] Combined with scenario examples, in computing-intensive application scenarios such as deep learning, scientific computing, big data processing, or graphics rendering, multiple accelerators are interconnected to improve computing efficiency. The switching processor of the computing device can effectively manage multiple accelerators to achieve effective collaboration between multiple accelerators.

[0033] In related technologies, computing devices use a fixed connection between the switching processor and multiple accelerators. This fixed connection corresponds to a specific application scenario. When the application scenario changes, the original scenario becomes unsuitable, and the connection between the switching processor and the multiple accelerators needs to be adjusted. However, adjusting the connection is complex, resulting in poor versatility of the computing device.

[0034] Different application scenarios have different requirements, as illustrated by example scenarios. For example, some scenarios require high computing efficiency, so the computing device may require a large number of accelerators. Other scenarios require high communication bandwidth, so the computing device may need fewer accelerators and more network controllers. Fixed connection methods make adjustments difficult.

[0035] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0036] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the connection configuration method of the computing device depends, the specific application environment architecture or specific hardware architecture is described herein. Figure 1 , Figure 1 This is a diagram of a computing device application scenario. A user generates data to be calculated and sends it to the computing device. The computing device processes the data to obtain a result, which it then sends to the user.

[0037] Figure 2 A flow chart of a method for configuring a connection of a computing device provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, an embodiment of the present application provides a connection configuration method for a computing device, and the method is described in detail as follows:

[0038] S201: Acquire a first level state of an identification pin of a connection port through a first controller, and send the first level state to a switching processor.

[0039] The connection configuration method of a computing device is applied to the computing device, which includes at least one switching processor, a first controller, and at least one connection port; and is directed to any one of the connection ports.

[0040] Exemplarily, a switching processor is configured to manage devices installed on a computing device. A connection port is configured to connect to an accelerator and / or a network controller to enable the accelerator and / or the network controller to access the computing device. An identification pin of the connection port is configured to display a corresponding first electrical level status based on a line connection mode between the connection port and the connected device. A first controller is configured to monitor the first electrical level status of the identification pin in real time. The first controller transmits the first electrical level status to the switching processor, so that the switching processor determines the real-time line connection mode of the connection port based on the first electrical level status.

[0041] Optionally, the connection port connects to different types of devices, corresponding to different line connection methods. For the same type of device, a connection port can be connected to one or more.

[0042] S202: Determine, by a switching processor, a line connection mode corresponding to the connection port according to the first level state.

[0043] Optionally, for different application scenarios, the line connection modes of the connection ports are different, and a correspondence between the line connection modes and the first level states is preset to associate the line connection modes with the first level states.

[0044] In this scenario example, when a user switches the line connection mode, the identification pin switches to the corresponding first level state according to the preset correspondence. Therefore, the real-time first level state can reflect the real-time line connection mode, allowing the switching processor to determine the real-time line connection mode.

[0045] S203: Match the firmware corresponding to the line connection mode through the switching processor, so that the connection port performs data transmission according to the line connection mode.

[0046] For example, the line connection mode is a hardware-level structure. After the user switches the line connection mode, software-level firmware is required to implement data transmission. The switching processor loads the corresponding firmware based on the identified line connection mode to implement data transmission using the corresponding firmware.

[0047] Combined with the scenario example, after the line connection mode is switched according to the application scenario, the switching processor automatically identifies the line connection mode and loads the corresponding firmware so that the line connection mode can operate normally to realize data transmission, so that the computing device can adapt to the switched application scenario.

[0048] The connection configuration method for a computing device provided in an embodiment of the present application comprises obtaining a first level state of an identification pin of a connection port through a first controller and sending the first level state to a switching processor; determining a line connection mode corresponding to the connection port through the switching processor based on the first level state; and matching firmware corresponding to the line connection mode through the switching processor so that the connection port transmits data according to the line connection mode. With the above scheme, after a user changes the line connection mode of a computing device, the switching processor automatically identifies the line connection mode of the computing device and automatically switches to firmware adapted for the line connection mode, thereby reducing the difficulty of connection configuration of the computing device and improving the versatility of the computing device.

[0049] Based on any of the above embodiments, Figure 3 , describes the detailed process of connection configuration of computing devices.

[0050] Figure 3 This is a flow chart of a method for configuring a connection of a computing device provided in an embodiment of the present application. Figure 3 As shown, the method includes:

[0051] S301: Determine a plurality of identification pins connected to a plurality of first connectors.

[0052] Wherein, the connection port includes a plurality of first connectors.

[0053] Exemplarily, the plurality of first connectors are used to split the data transmission channel of the connection port to expand the number or type of devices connected to the connection port.

[0054] To illustrate this scenario, consider a 16-channel (X16) port. The port can include two first connectors, each with 8 channels (X8). Together, these two connectors form the port's 16 channels. The two first connectors can be connected to a single device, enabling 16-channel data transmission. Alternatively, each first connector can be connected to a single device, enabling two 8-channel data transmissions. Different firmware is required for data transmission in different line connection modes.

[0055] Exemplarily, each first connector is connected to at least one identification pin, so that the identification pin can identify each first connector.

[0056] S302: Obtain first level states corresponding to multiple identification pins.

[0057] Exemplarily, each first connector is connected to at least one identification pin, so the line connection mode of each first connector can be represented by the first level state of at least one identification pin.

[0058] Using a scenario example, for the same type of device, when multiple first connectors of a connection port are connected to the same device, the first level states of the identification pins of each first connector are different. When multiple first connectors of a connection port are connected to different devices, the first level states of the identification pins of each first connector are the same. This first level state can thus be used to distinguish different line connection methods.

[0059] S303: If the connection port is a dual-function port, determine the line connection mode corresponding to the connection port through the switching processor according to the first level state, and the line connection mode is a full interconnection connection or a non-full interconnection connection. The dual-function port is used to connect to a network controller or to connect to other switching processors through other dual-function ports.

[0060] For example, a dual-function port is a port that supports connecting two types of devices. Users can switch the device connected to the dual-function port according to the actual needs of the application scenario.

[0061] Exemplarily, an interconnection connection is a connection between multiple computing devices to enable collaborative operation of the multiple computing devices, thereby improving computing efficiency. Taking the interconnection connection between two computing devices as an example, any switch processor of one computing device is connected to each switch processor of the other switch processor as a fully interconnected connection, while any switch processor of one computing device is connected to one switch processor of the other switch processor as a partially interconnected connection. The switch processors of the two computing devices are connected via the dual-function ports of each of the two computing devices.

[0062] For example, a fully interconnected connection requires more lines than a non-fully interconnected connection, and accordingly, more dual-function ports are involved. In a non-fully interconnected connection, fewer dual-function ports are involved, and some of these dual-function ports can be connected to a network controller to increase the network bandwidth of the computing device.

[0063] Exemplarily, whether the dual-function port is used for interconnecting computing devices or is not used for interconnecting computing devices corresponds to different first level states.

[0064] Based on the above implementations, the first level state can automatically identify the line connection mode of the dual-function port, thereby performing corresponding configuration to improve the versatility of the computing device.

[0065] S304. If the connection port is a single-function port, determine the line connection mode corresponding to the connection port through the switching processor according to the first level state. The line connection mode is that the connection port is connected to one device, or the connection port is connected to multiple devices. The single-function port is used to connect to an accelerator or a network controller.

[0066] Exemplarily, a single-function port is used to connect to an accelerator or a network controller. The difference between a single-function port and a dual-function port is that a single-function port is not used to establish an interconnection connection.

[0067] Exemplarily, a single-function port is connected to different devices, or is connected to devices through different line connection modes, which respectively correspond to different first level states.

[0068] It should be noted that this application does not limit the execution order of S303 and S304.

[0069] S305 , matching the firmware corresponding to the line connection mode through the switching processor, so that the connection port performs data transmission according to the line connection mode.

[0070] It should be noted that the execution process of S305 refers to S203 and will not be repeated here.

[0071] Figure 4 A schematic diagram of the structure of a computing device provided in an embodiment of the present application is shown in FIG. Figure 4As shown, an embodiment of the present application provides a computing device, and the structure of the computing device is described in detail. The computing device includes: at least one switching board, at least one switching processor, a first controller, and at least one connection port, wherein the switching processor, the first controller, and multiple connection ports are installed on the switching board; the first controller is connected to the multiple connection ports and the switching processor through the internal circuit of the switching board, and the first controller is used to obtain the first level state of the identification pin of the connection port and send the first level state to the switching processor; the switching processor is used to determine the line connection mode corresponding to the connection port according to the first level state; the switching processor is also used to match the firmware corresponding to the line connection mode through the switching processor, so that the connection port transmits data according to the line connection mode.

[0072] Exemplarily, a switch board integrates internal circuits, connection ports, and a processor slot. The processor slot is connected to the internal circuits, and a switch processor is installed in the processor slot to connect the switch processor to the internal circuits. The internal circuits are connected to the connection ports. The switch processor manages devices on the switch board and devices connected to the switch board.

[0073] Exemplarily, the switching processor is directly connected to the connection port via an internal circuit of the switching board to control the connection port. In addition, the switching processor is further connected to a first controller, which is connected to the connection port, so that the switching processor obtains a first level state of the connection port through the first controller.

[0074] In combination with the scenario example, through real-time monitoring of the first controller, the latest line connection mode can be obtained in real time after the user switches the line connection mode of the computing device, so that the switching processor can perform corresponding configuration according to the latest line connection mode.

[0075] Optionally, the first controller may be a complex programmable logic device (CPLD).

[0076] A feasible implementation method is Figure 5 A schematic diagram of the structure of the first connector provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the connection port includes multiple first connectors; wherein, the multiple first connectors are connected to multiple identification pins, and the identification pins are used to indicate the first level state of the first connector; the first controller is connected to the multiple identification pins, and the first controller is used to obtain the first level state corresponding to the multiple identification pins.

[0077] Exemplarily, the plurality of first connectors are used to split the data transmission channel of the connection port to expand the number or type of devices connected to the connection port.

[0078] For example, multiple first connectors of the same connection port can be connected to devices respectively, or multiple first connectors of the same connection port can be connected to one device together. The above solutions correspond to different line connection methods, and each line connection method corresponds to a different channel.

[0079] Exemplarily, by providing an identification pin on each first connector and monitoring each identification pin separately, multiple line connection modes can be identified.

[0080] In this feasible implementation, by providing a plurality of first connectors at the connection port, the types of line connection modes that can be identified can be expanded, thereby accurately identifying various application scenarios.

[0081] In a feasible implementation, the switching processor is used to perform firmware matching to switch the line connection mode for data transmission. The line connection mode includes at least one of the following: a fully interconnected connection between the switching processors, a non-fully interconnected connection between the switching processors, one connection port connected to one device, or one connection port connected to multiple devices, where the device is an accelerator or a network controller.

[0082] Optionally, connection ports can be divided into uplink ports, interconnection ports, and downlink ports based on their functions. Uplink ports connect to hosts to facilitate data transmission between the switch device and the host. Interconnection ports are dual-function ports used to connect switch processors to enable collaborative operation. Downlink ports connect to accelerators or network controllers.

[0083] Combined with the scenario example, for application scenarios with high requirements for communication bandwidth, some dual-function ports are used to connect to the network controller to improve the network bandwidth of the computing device.

[0084] Optionally, the connection mode of the connection port is set to an easy-plug structure. When the application scenario of the switching device changes and the device connected to the connection port needs to be adjusted, the easy-plug structure can be used to achieve rapid adjustment.

[0085] For example, interconnect ports are configured as fabric mode ports. Fabric mode ports are ports with dynamically reconfigurable functions. Fabric mode ports are protocol-independent signal channels that do not parse upper-layer data content, focusing on direct device connectivity and signal relay. Therefore, fabric mode ports are compatible with different types of devices and can be switched to connect to different devices based on application scenarios, thereby enhancing the versatility of switching equipment. Fabric mode enables dual-function modes for interconnect ports.

[0086] For example, by adjusting the devices connected to the connection ports, it is possible to adapt to different application scenarios, thereby improving the versatility of the switching device.

[0087] Exemplarily, the accelerator is used to perform data calculations. The switching processor sends the data to be calculated to the accelerator, which performs calculations to obtain calculation results and sends the calculation results to the switching processor.

[0088] Optionally, the accelerator may be a graphics processing unit (GPU).

[0089] Exemplarily, the network controller is used to implement network connection of the switching device.

[0090] Combined with the scenario example, for the application scenario of large model training, network controllers are used to form a network to enable multiple computing devices to work together. If the application scenario requires higher communication bandwidth, this can be achieved by increasing the number of network controllers.

[0091] For computationally intensive and parallelizable application scenarios, such as large model training expansion and multi-task concurrent processing, connecting more accelerators can increase parallelism and thus improve computing efficiency.

[0092] In this feasible implementation, corresponding firmware is matched to various line connection methods, so that the computing device can be flexibly configured in multiple application scenarios, thereby improving the versatility of the computing device.

[0093] A feasible implementation method is Figure 6 A schematic diagram of the structure of the circuit board provided in the embodiment of the present application is shown in FIG. Figure 6 As shown, the computing device also includes at least one circuit board, wherein the switching processor is connected to a circuit board through multiple first connectors of a connection port, and one circuit board is connected to one device to realize that one connection port is connected to one device; the switching processor is connected to multiple circuit boards through multiple first connectors of a connection port, and one circuit board is connected to one device to realize that one connection port is connected to multiple devices.

[0094] For example, the circuit board can be connected to one first connector or multiple first connectors. The circuit board uses pre-designed and manufactured precision conductive lines to accurately, reliably, and permanently connect components such as resistors, capacitors, and interfaces to ensure a correct electrical path.

[0095] Optionally, the circuit board may be a printed circuit board (PCB).

[0096] For example, each connector includes a fixed number of channels. The more channels, the greater the data transmission bandwidth. When a switching processor connects to multiple accelerators via multiple first connectors on a single connection port, the number of connected accelerators can be effectively expanded, thereby increasing the accelerator's parallel processing capability. When a switching processor connects to a single accelerator via multiple first connectors on a single connection port, the accelerator's transmission bandwidth can be effectively increased due to the larger number of channels connected to the accelerator.

[0097] In conjunction with the scenario example, take the example of a connection port connecting two first connectors, each of which corresponds to 8 channels. When both first connectors are connected to one accelerator, one accelerator is connected to the switching processor via 16 channels. Compared to 8 channels, 16 channels can provide a larger bandwidth, thereby reducing communication latency. For data-mobile intensive application scenarios, for example, the frequent synchronization of gradients in distributed training, the transmission of to-be-calculated data to the accelerator's video memory in high-resolution data processing, and the output of the calculation results to the switching processor require high bandwidth. Providing a larger bandwidth can effectively improve computing efficiency.

[0098] For computationally intensive and parallelizable application scenarios, such as large model training expansion and multi-task concurrent processing, connecting more accelerators can increase parallelism and thus improve computing efficiency.

[0099] In this feasible implementation, by providing a first connector that can be flexibly switched, adaptive switching can be performed according to the application scenario of the switching device, thereby improving the versatility of the switching device.

[0100] A feasible implementation method is Figure 7 The schematic diagram of the structure of the board connection provided in the embodiment of the present application is as follows: Figure 7 As shown, there are multiple switch boards, wherein the multiple switch boards are connected through connection ports to connect the first connectors corresponding to the multiple switch boards to each other, wherein the number of connection ports for inter-board connection of any switch board is at least one.

[0101] For example, the computing device may include multiple switch boards. The inter-board connection is an interconnection between the multiple switch boards to enable the multiple switch boards to work in coordination and to establish connections between devices connected to the multiple switch boards.

[0102] Exemplarily, the connection port for realizing the connection between boards is a dual-function port, that is, the dual-function port is used to connect the switch board.

[0103] For example, inter-board connections via connection ports can enable direct connections between multiple switch boards. Data and / or signals transmitted between the multiple switch boards are transmitted via the inter-board connection lines. This eliminates the need for data and / or signals to be forwarded through other devices (e.g., a host or backplane) and eliminates the need for protocol conversion, thereby improving transmission efficiency.

[0104] In this feasible implementation, by accurately identifying the inter-board connections between the multiple switch boards, accurate configuration can be performed, thereby improving the transmission efficiency between the multiple switch boards.

[0105] A feasible implementation method is that any first connector of any one of the multiple switch boards is connected to multiple first connectors of other switch boards to achieve full interconnection connection; any first connector of any one of the multiple switch boards is connected to one first connector of other switch boards to achieve non-full interconnection connection.

[0106] Next, combine Figure 8a Describe the full interconnection.

[0107] Figure 8a This is a schematic diagram of the fully interconnected connection provided by the embodiment of this application. Figure 8a As shown, in a fully interconnected connection, any switch processor of any switch board is connected to multiple switch processors of another switch board.

[0108] Next, combine Figure 8b A description of non-fully interconnected connections is provided.

[0109] Figure 8b This is a schematic diagram of a non-full interconnection connection provided by an embodiment of the present application. Figure 8b As shown, in a non-fully interconnected connection, any switch processor of any switch board is only connected to one switch processor of another switch board.

[0110] For example, compared with a non-fully interconnected connection, a fully interconnected connection has more lines between boards, and therefore requires more dual-function ports.

[0111] Optionally, the connection between the switch processors also includes an intra-board connection, in which two first connectors corresponding to one of the connection ports on the switch board are interconnected to interconnect two switch processors on a switch board. In the switch board, any switch processor manages some devices. Through the intra-board connection, multiple devices in the switch board can be interconnected to achieve direct transmission, thereby improving the computing efficiency of the computing device.

[0112] In conjunction with the scenario examples, a specific scenario identified based on the first level state is illustrated. For example, a switch board includes two switch processors, each connection port includes two first connectors, and the connection port has 16 channels. A first level state of 10 for a single-function port indicates that the single-function port is connected to one device via 16 channels. A first level state of 00 for a single-function port indicates that the single-function port is connected to two devices via two 8-channels. A first level state of 11 for a dual-function port indicates that the dual-function ports are fully interconnected. A first level state of 10 for a dual-function port indicates that the dual-function ports are fully interconnected.

[0113] In this feasible implementation, various interconnection connection modes are adapted to corresponding application scenarios, the interconnection connection modes are automatically identified, and corresponding configurations can be performed to improve the versatility of the switch board.

[0114] A feasible implementation method is Figure 9 A schematic diagram of the structure of a computing device provided in an embodiment of the present application is shown in FIG. Figure 9 As shown, the computing device also includes a second controller, a configuration connector, and a jumper pin, wherein the jumper pin is connected to the configuration connector, and the jumper pin is used to control the second level state of the configuration connector; the first controller is connected to the configuration connector and the second controller, and the first controller is used to obtain the second level state and send the second level state to the second controller; the second controller is used to determine whether to manage the computing device based on the second level state.

[0115] Exemplarily, the second controller may be a baseboard management controller (BMC), which is used to manage devices inside the computing device so that the computing device can operate normally.

[0116] Optionally, the management tasks of the second controller include but are not limited to power supply, heat dissipation, and the like.

[0117] For example, different management methods are adapted in different application scenarios, and the computing device can be managed by a second controller inside the computing device or an external controller.

[0118] Using a scenario example, a whole-rack solution includes multiple independent computing devices. A second controller within each device manages the devices. In this solution, a single device failure does not affect overall management (for example, a short circuit in a device does not trigger a power outage for the entire rack). When hot-swapping a switch board in a computing device, the second controller maintains local logs and configuration persistence. This solution also allows for firmware upgrades without relying on a host external to the computing device.

[0119] In a rack server solution, the server includes multiple computing devices, all of which are centrally managed by the server host. This unified host management can standardize power sequencing, including power-on, initialization, and fan startup. It also manages the topology mapping tables for multiple computing devices. This unified host management can also accurately control the server's cooling system based on internal server temperatures.

[0120] In combination with the scenario example, after the user switches to the whole cabinet solution or the rack server solution, the user manually adjusts the jumper pins so that the computing device automatically identifies the solution of the current application scenario, thereby automatically determining the control solution of the computing device.

[0121] In this feasible implementation method, by setting jumper pins and configuring connectors, the first controller can obtain the second level state in real time, so that the second controller can determine whether to manage the computing device according to the application scenario of the computing device, thereby making the management of the computing device adaptable to different business scenarios, thereby improving the versatility of the computing device.

[0122] In a feasible implementation, the computing device further includes a power supply board, wherein the power supply board is connected to the switch board, the accelerator, and the network controller, and is used to supply power to the switch board, the accelerator, and the network controller.

[0123] Exemplarily, a computing device may include multiple switch boards, which are arranged in multiple layers to form the computing device. A power supply board is connected to each layer of switch boards of the computing device, and the power supply board is used to power the multiple switch boards to realize power supply to the devices on the multiple switch boards.

[0124] Next, combine Figure 10 The power supply board will be described.

[0125] Figure 10 This is a schematic diagram of the structure of the power supply board provided in the embodiment of the present application. Figure 10 As shown, the computing device includes a multi-layer switching board, and the power supply board includes multiple connectors, which are arranged in multiple rows. The positions of the multiple connectors of the power supply board correspond to the positions of the connection ports of the multiple switching boards of the computing device, so as to supply power to the computing device through the connectors.

[0126] Combined with the scenario example, the multiple connectors of the power supply board can achieve a detachable connection between the power supply board and the computing device. Compared with an integrated power supply board, in the event of a single point failure, only the faulty part can be removed and replaced, thereby reducing maintenance costs.

[0127] Optionally, multiple connectors of the power supply board can be used for power supply or data transmission. The connector for power supply can transmit current, and the connector for data transmission can transmit data, so that the host can perform data transmission with multiple switch boards in a unified manner.

[0128] Exemplarily, by supplying power through a power supply board including multiple connectors, unified power supply for multiple devices in a computing device can be achieved.

[0129] In this feasible implementation, multiple devices in the computing device are uniformly powered by a power supply board to reduce the complexity of power supply.

[0130] In a feasible implementation, the power supply board further includes a power supply connector, wherein the power supply connector is connected to the power supply board and a power source outside the computing device, and the power supply connector is used to introduce a power source to power the computing device.

[0131] For example, the power supply board is connected to a power source outside the computing device through a power supply, thereby introducing external power. The power supply board is connected to a multi-layer switching board of the computing device through multiple connectors, thereby simultaneously powering devices on multiple switching boards.

[0132] In this scenario, the power supply connector and multiple connectors on the power board are used to establish a power supply line between the power supply and the computing device, thereby providing unified power to multiple switch boards in the computing device. This eliminates the need to reserve independent power supply space for each switch board within the computing device.

[0133] In this feasible implementation, current is uniformly introduced through the power supply connector of the power supply board to uniformly power multiple switch boards of the computing device, which can effectively save space of the computing device and thus improve the computing power density of the computing device.

[0134] Figure 11 A schematic diagram of the structure of the computing system provided in the embodiment of the present application is shown in FIG. Figure 11 As shown, an embodiment of the present application provides a computing system, and the structure of the computing system is described in detail. The computing system includes a host, a power supply, and multiple computing devices, wherein the host is connected to the second connector of the computing device, and the host is used to manage the computing system; the power supply is connected to the power supply connector of the computing device and the host, and the power supply is used to power the computing system.

[0135] For example, a computing system includes multiple computing devices, which together achieve a high overall computing power. A power supply is used to power the devices in the computing system. A host computer is used to centrally manage the computing system, including managing the power supply and multiple computing devices.

[0136] Exemplarily, the second connector of the computing device is used to connect the computing device to the host, and the second connector is used for data transmission between the computing device and the host.

[0137] For example, by setting up a host, multiple computing devices of a computing system can be effectively managed, thereby improving the reliability of collaborative work of multiple computing devices.

[0138] In one feasible implementation, the computing system further includes a backplane, wherein the backplane is connected to the second connector and the power supply connector of the computing device; the host is connected to the backplane to connect the host to the computing device; and the power supply is connected to the backplane to connect the power supply to the computing device and the host.

[0139] For example, a backplane connects multiple computing devices, improving the integration of the host computer. The backplane replaces discrete wiring, allowing direct data flow between the host computer and computing devices. Power is connected to the backplane and distributed intelligently to multiple computing devices.

[0140] For example, a high-current connector is installed on the backplane to achieve board-to-board connection, transmitting 54V DC power from the backplane to the power supply board of the computing device. The 54V DC power passes through the DC-DC step-down module, outputting 12V, which is then passed through the computing device power supply board to the switch board. The 12V DC power entering the switch board powers the devices on the switch board.

[0141] Optionally, the backplane is wired in layers according to function to separate data lines and power supply lines to avoid interference between the lines.

[0142] In this feasible implementation, the backplane is used to improve the integration level of the computing system, thereby effectively improving the computing power density of the computing system.

[0143] In a feasible implementation, the backplane includes a plurality of high-density connectors, wherein the high-density connectors are connected through lines of the backplane; and the high-density connectors are connected to a second connector of the computing device and a host.

[0144] For example, high-density connectors are used to implement interconnection channels: channels between a host and a computing device, and channels between computing devices. The channels between the host and the computing device enable data transmission between the host and the computing device, while the channels between computing devices enable collaborative work between computing devices.

[0145] For example, a high-density connector uses a micro-pitch pin structure to improve the bandwidth and stability of data transmission.

[0146] For example, the backplane in the computing system serves as the core interconnection carrier, and multiple high-density connectors are integrated and deployed on its surface. These high-density connectors are electrically interconnected through the multi-layer precision lines pre-laid inside the backplane, building a criss-crossing signal and power transmission network. Specifically, each high-density connector adopts a micro-pitch pin structure to achieve dense arrangement of contacts in a compact space in a staggered layout, and ground isolation strips are embedded between the contacts to block electromagnetic crosstalk. High-speed signal lines can be laid in the backplane to ensure that the impedance of the signal path is maintained within the target threshold range throughout. The high-density connector achieves bidirectional connection function through a physical docking mechanism. The interconnection channels between each high-density connector are formed through the cascade wiring embedded in the backplane, allowing any two computing devices to establish a direct path without passing through the host, forming a distributed device interconnection architecture.

[0147] In this feasible implementation, unified connection through high-density connectors can effectively save circuit space, thereby improving the computing power density of the computing system.

[0148] In one feasible implementation, the computing device further includes a heat sink, wherein the heat sink is connected to the host computer and is used to dissipate heat from the computing system. The backplate includes a plurality of holes, the opening direction of the plurality of holes being parallel to the heat dissipation channels of the heat sink; the heat dissipation channels of the heat sink at least partially overlap with the heat dissipation channels of the computing device.

[0149] Exemplarily, the heat dissipation device establishes a direct electrical connection with the host system as an active heat dissipation core unit, and receives the heat dissipation strategy instructions issued in real time by the host temperature monitoring processor. At the same time, the main air duct or liquid cooling pipeline of the heat dissipation device and the backplane opening matrix form a physical coupling path. The multiple groups of openings precisely arranged on the backplane surface strictly follow the aerodynamic section optimization principle. The axial extension direction of all openings at least partially overlaps with the axis of the main heat dissipation channel of the heat dissipation device, forming a vector-guided flow field running through the system. After the high-speed airflow or coolant flow of the heat dissipation device passes through the backplane opening, its flow trajectory partially overlaps with the guide structure of the built-in radiator of the computing device. Specifically, the jet at the outlet of the backplane channel directly impacts the air inlet edge area of ​​the computing device radiator, so that the external forced cooling airflow and the device's autonomous heat dissipation airflow form a cooperative vortex on the surface of the computing module.

[0150] Optionally, the heat dissipation device may be a heat dissipation fan or a liquid cooling heat dissipation device.

[0151] In this feasible implementation, a heat dissipation device is provided and the heat dissipation channel of the heat dissipation device at least partially overlaps with the heat dissipation channel of the computing device, so that the computing system can effectively and uniformly dissipate heat, avoiding conflicts between the heat dissipation channels of multiple computing devices and reducing the heat dissipation effect.

[0152] In a feasible implementation, the host includes a third controller, wherein the third controller is connected to the first controller of the computing device, and the third controller is used to determine whether to manage the computing device according to a second level state sent by the first controller.

[0153] Exemplarily, both the second controller and the third controller are used to manage computing devices, with the second controller being used to individually manage one computing device, and the third controller being used to uniformly manage multiple computing devices. The second controller and the third controller are adapted to different application scenarios. The current application scenario of the computing device is automatically determined based on the second level state, thereby automatically determining an adapted controller to manage the computing device based on the current application scenario of the computing device.

[0154] In this feasible implementation method, by setting jumper pins and configuring connectors, the first controller can obtain the second level state in real time, so that the third controller can determine whether to manage the computing device according to the application scenario of the computing device, so that the management of the computing device can adapt to different business scenarios, thereby improving the versatility of the computing device.

[0155] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0156] Figure 12 This is a schematic diagram of the structure of the connection configuration device of the computing device provided in the embodiment of the present application. Figure 12 As shown, an embodiment of the present application further provides a connection configuration device for a computing device. The connection configuration device 120 for the computing device may include: an acquisition module 121, a determination module 122, a matching module 123, and a connection module 124, wherein:

[0157] The connection configuration device of a computing device is applied to the computing device, which includes at least one switching processor, a first controller, and at least one connection port; and is directed to any one of the connection ports.

[0158] The acquisition module 121 is configured to acquire a first level state of an identification pin of a connection port through a first controller, and send the first level state to a switching processor.

[0159] The determining module 122 is configured to determine, through a switching processor, a line connection mode corresponding to the connection port according to the first level state.

[0160] The matching module 123 is configured to match the firmware corresponding to the line connection mode through the switching processor, so that the connection port performs data transmission according to the line connection mode.

[0161] Optionally, the acquisition module 121 may execute Figure 2 S201 in the embodiment.

[0162] Optionally, the determination module 122 may execute Figure 2 S202 in the embodiment.

[0163] Optionally, the matching module 123 may execute Figure 2 S203 in the embodiment.

[0164] It should be noted that the connection configuration device of the computing device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0165] In a possible implementation, the connection port includes a plurality of first connectors; and the acquisition module 121 is specifically configured to:

[0166] determining a plurality of identification pins connected to the plurality of first connectors;

[0167] Acquire first level states corresponding to multiple identification pins.

[0168] The connection module 124 is used to:

[0169] If the connection port is a dual-function port, the switching processor determines a line connection mode corresponding to the connection port according to the first level state, where the line connection mode is a full interconnection connection or a non-full interconnection connection, and the dual-function port is used to connect to a network controller or to connect to other switching processors through other dual-function ports;

[0170] If the connection port is a single-function port, the switching processor determines the line connection mode corresponding to the connection port according to the first level state. The line connection mode is that the connection port is connected to one device, or the connection port is connected to multiple devices. The single-function port is used to connect to an accelerator or a network controller.

[0171] For the description of the features in the embodiment corresponding to the connection configuration apparatus of the computing device, please refer to the relevant description of the embodiment corresponding to the connection configuration method of the computing device, which will not be repeated here.

[0172] Figure 13 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 13 As shown, the electronic device 130 provided in this embodiment includes: at least one processor 1301 and a memory 1302. Optionally, the electronic device 130 further includes a communication component 1303. The processor 1301, the memory 1302 and the communication component 1303 are connected via a bus.

[0173] During the specific implementation process, at least one processor 1301 executes the computer-executable instructions stored in the memory 1302, so that the at least one processor 1301 executes the above-mentioned embodiment of the connection configuration method of the computing device.

[0174] The specific implementation process of the processor 1301 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0175] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0176] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0177] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0178] An embodiment of the present application further provides a non-volatile computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned connection configuration method embodiments of the computing device when running.

[0179] In an exemplary embodiment, the non-volatile computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0180] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned connection configuration method embodiments of the computing device are implemented.

[0181] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps in any of the above-mentioned connection configuration method embodiments of the computing device.

[0182] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0183] The above is a detailed introduction to the connection configuration method, computing device, system and apparatus of a computing device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for configuring a connection of a computing device, characterized in that: Applied to a computing device, the computing device comprising at least one switching processor, a first controller, and at least one connection port; For any connection port, the method includes: acquiring, by the first controller, a first level state of the identification pin of the connection port, and sending the first level state to the switching processor; determining, by the switching processor, a line connection mode corresponding to the connection port according to the first level state; Matching the firmware corresponding to the line connection mode by the switching processor so that the connection port performs data transmission according to the line connection mode; The determining, by the switching processor, a line connection mode corresponding to the connection port based on the first level state includes: if the connection port is a dual-function port, determining, by the switching processor, a line connection mode corresponding to the connection port based on the first level state, the line connection mode being a fully interconnected connection or a non-fully interconnected connection, and the dual-function port being used to connect to a network controller or to connect to other switching processors through other dual-function ports; If the connection port is a single-function port, the line connection mode corresponding to the connection port is determined by the switching processor according to the first level state, and the line connection mode is that the connection port is connected to one device, or the connection port is connected to multiple devices, and the single-function port is used to connect an accelerator or a network controller.

2. The method according to claim 1, characterized in that The connection port includes a plurality of first connectors; Acquiring a first level state of an identification pin of the connection port includes: determining a plurality of identification pins connected to the plurality of first connectors; Acquire the first level states corresponding to the multiple identification pins.

3. A computer device, characterized in that: The method as claimed in claim 1 or 2; comprising: at least one switch board, at least one switch processor, a first controller, and at least one connection port, wherein: The switch processor, the first controller, and the plurality of connection ports are mounted on a switch board; The first controller is connected to the plurality of connection ports and the switch processor via an internal circuit of the switch board, and the first controller is configured to obtain a first level state of an identification pin of the connection port and send the first level state to the switch processor; The switching processor is configured to determine a line connection mode corresponding to the connection port according to the first level state; The switching processor is further configured to match firmware corresponding to the line connection mode, so that the connection port performs data transmission according to the line connection mode.

4. The computer device according to claim 3, wherein: The connection port includes a plurality of first connectors; wherein, The plurality of first connectors are connected to a plurality of identification pins, and the identification pins are used to indicate a first level state of the first connector; The first controller is connected to the plurality of identification pins, and is configured to obtain first level states corresponding to the plurality of identification pins.

5. The computer device according to claim 4, wherein: The switching processor is used to match the firmware to switch the line connection mode for data transmission, and the line connection mode includes at least one of the following: a full interconnection connection between the switching processors, a non-full interconnection connection between the switching processors, one connection port connected to one device, or one connection port connected to multiple devices, and the device is an accelerator or a network controller.

6. The computer device according to claim 5, wherein: The computing device further comprises at least one circuit board, wherein The switching processor is connected to a circuit board through a plurality of first connectors of a connection port, and the circuit board is connected to a device to achieve connection of one connection port to one device; The switching processor is connected to a plurality of circuit boards through a plurality of first connectors of a connection port. The circuit board is connected to a device to achieve connection of a plurality of devices to a connection port.

7. The computer device according to claim 5, wherein: There are multiple exchange boards, wherein: The plurality of switch boards are connected via connection ports so as to connect the first connectors respectively corresponding to the plurality of switch boards to each other, wherein the number of connection ports used for inter-board connection on any switch board is at least one.

8. The computer device according to claim 7, wherein: Any first connector of any one of the multiple switch boards is connected to multiple first connectors of other switch boards to achieve the full interconnection connection; Any first connector of any one of the multiple switch boards is connected to a first connector of another switch board to achieve the non-full interconnection connection.

9. The computer device according to claim 3, wherein: The computing device further includes a second controller, a configuration connector, and jumper pins, wherein: The jumper pin is connected to the configuration connector, and the jumper pin is used to control the second level state of the configuration connector; The first controller is connected to the configuration connector and the second controller, and the first controller is used to obtain the second level state and send the second level state to the second controller; The second controller is configured to determine whether to manage the computing device according to the second level state.

10. The computer device according to claim 3, wherein: The computing device further includes a power supply board, wherein The power supply board is connected to the switch board, the accelerator, and the network controller, and is used to supply power to the switch board, the accelerator, and the network controller.

11. The computer device according to claim 10, wherein: The power supply board also includes a power supply connector, wherein: The power supply connector is connected to the power supply board and a power source outside the computing device, and the power supply connector is used to introduce a power source to supply power to the computing device.

12. A computer system, characterized in that: A computer device comprising a host, a power supply, and any one of claims 3 to 11, wherein: The host is connected to the second connector of the computing device, and the host is used to manage the computing system; The power supply is connected to the power supply connector of the computing device and the host, and is used to supply power to the computing system.

13. The computer system according to claim 12, wherein: The computing system further includes a backplane, wherein The backplane is connected to the second connector and the power supply connector of the computing device; The host is connected to the backplane to connect the host to the computing device; The power supply is connected to the backplane to connect the power supply to the computing device and the host.

14. The computer system according to claim 13, wherein: The backplane includes a plurality of high-density connectors, wherein: The high-density connector is connected via the circuit of the backplane; The high-density connector is connected to the second connector of the computing device and the host.

15. The computer system according to claim 14, wherein: The computing device further includes a heat dissipation device, wherein: The heat dissipation device is connected to the host, and is used to dissipate heat from the computing system; The back plate includes a plurality of holes, and the opening directions of the plurality of holes are parallel to the heat dissipation channels of the heat dissipation device; The heat dissipation channel of the heat dissipation device at least partially overlaps with the heat dissipation channel of the computing device.

16. The computer system according to claim 12, wherein: The host includes a third controller, wherein The third controller is connected to the first controller of the computing device, and the third controller is used to determine whether to manage the computing device according to the second level status sent by the first controller.

17. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the connection configuration method for a computing device as claimed in claim 1 or 2 when executing the computer program.

18. A non-volatile computer-readable storage medium, characterized in that: The non-volatile computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the connection configuration method of the computing device according to claim 1 or 2.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the connection configuration method of the computing device according to claim 1 or 2 are implemented.

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