Cross-scale thermal simulation method of GaN device under HTGB condition

Abstract

The invention provides a cross-scale thermal simulation method of a GaN device under an HTGB condition, which is technically characterized in that a comprehensive simulation analysis method from microcosmic to macroscopic under the HTGB condition by using COMSOL simulation software comprises the following steps of: firstly, performing simulation of thermal distribution and stress distribution on a single cellular structure under a high-temperature gate offset condition to obtain detailed information of a microcosmic level; and secondly, extrapolating an analysis result of a single cell, and loading a plurality of cells as an integral heat source into device-level simulation, thereby realizing comprehensive temperature and stress distribution analysis of the integral device under a high-temperature gate offset condition.

Description

Technical Field

[0001] This application relates to the technical field of power semiconductor devices, and particularly to a cross-scale thermal simulation method of GaN devices under HTGB conditions. Background Art

[0002] With the rapid development of power electronic devices, high-efficiency and reliable wide-bandgap semiconductor devices (such as P-GaN) are increasingly widely used in high-power, high-frequency, and high-temperature environments. Due to their unique structure and electrical properties, wide-bandgap semiconductor materials are prone to severe thermo-mechanical stress coupling effects under high-temperature and gate voltage-biased conditions, thus affecting the performance and reliability of devices. In practical applications, P-GaN devices often operate in high-temperature and powered-on environments. Especially when a constant voltage is applied between the gate and the source, the performance of the device is significantly affected by the environmental temperature and voltage conditions. Particularly when a constant voltage is applied between the gate and the source, the performance of the device will change significantly over time, which poses higher requirements for the reliability and stability of the device. As one of the essential reliability tests for power devices, the HTGB test can effectively evaluate the performance degradation and reliability of devices under harsh working environments.

[0003] In a high-temperature environment, the electrical characteristics of P-GaN devices may be affected by various factors, including carrier mobility, threshold voltage drift, and increased switching losses. These changes not only affect the transient response of the device but may also lead to long-term performance degradation and even device failure. Traditional research methods mainly rely on TCAD software to evaluate the performance of devices under different working conditions through electrical simulation. These simulations can usually provide the current and voltage characteristics of the device and their trends over time. However, TCAD simulations have significant limitations in dealing with the microscopic thermal distribution and stress distribution inside the device. Specifically, TCAD software mainly focuses on electrical characteristics and cannot intuitively reflect the mechanical stress state induced by high temperature and high voltage in the device. In fact, device failure is often closely related to stress. Especially in weak areas of the material, excessive stress may cause structural rupture or performance degradation.

[0004] However, in the existing technology, current research mainly relies on experiments and TCAD simulation software to evaluate the changes in the electrical characteristics of P-GaN devices under a constant voltage and high-temperature environment. The experimental method and TCAD simulation mainly focus on electrical characteristics and cannot effectively reflect the internal stress state of the device. This makes it difficult for researchers to comprehensively understand the true working environment of the device under high-temperature bias conditions. Under high-temperature bias conditions, the performance of P-GaN devices changes over time, and traditional electrical simulation methods are difficult to capture this dynamic evolution, resulting in insufficient evaluation of device reliability. This deficiency may prevent designers from predicting the performance and reliability issues of the device during long-term operation. Summary of the Invention

[0005] Each exemplary embodiment of the present application provides a cross-scale thermal-mechanical simulation method for GaN devices under HTGB conditions, so as to at least effectively solve the limitations of traditional methods in micro-thermal distribution and stress analysis, and provide a more accurate and comprehensive technical effect of performance evaluation.

[0006] According to one aspect of the present application, each exemplary embodiment of the present application provides a cross-scale thermal-mechanical simulation method for GaN devices under HTGB conditions, and the method includes the following steps:

[0007] A cross-scale thermal-mechanical simulation method for GaN devices under HTGB conditions, the method includes the following steps:

[0008] S1, under high-temperature gate bias conditions, simulate and obtain data on the change of cell thermal power density over time through a first simulation software, and use it as the input load of a second simulation software. Process the data using a Gaussian heat source to obtain Gaussian heat source data that conforms to the results obtained by the first simulation software;

[0009] S2, through finite element modeling, construct a three-dimensional equivalent model of the cell according to the two-dimensional model of the cell, use the Gaussian heat source data as the heat source load of the three-dimensional equivalent model of the cell, add the materials required for the model, and perform mesh division to reflect the mechanical behavior of the solder layer and the GaN layer;

[0010] S3, solve the three-dimensional equivalent model of the cell to obtain the temperature distribution and stress distribution of each layer in the cell, and calculate the change data of the overall power of the three-dimensional equivalent model of the cell over time;

[0011] S4, observe and obtain the size of the device microstructure, construct a device simulation model, and use the change data obtained from the three-dimensional equivalent model of the cell as a function to obtain the thermal power of the overall chip;

[0012] S5. Use the thermal power as the heat source load of the device model, solve the device model, obtain the solution results at the device level, and conduct evaluation and analysis.

[0013] According to another aspect of the present application, there is also disclosed a cross-scale thermal-mechanical simulation device for a GaN device under HTGB conditions, including:

[0014] A heat source data acquisition module, configured to, under high-temperature gate bias conditions, simulate through a first simulation software to obtain data on the variation of the cell thermal power density over time, and use it as the input load of a second simulation software. Process the data using a Gaussian heat source to obtain Gaussian heat source data that is consistent with the results obtained by the first simulation software;

[0015] A cell three-dimensional equivalent model construction module, configured to construct a cell three-dimensional equivalent model based on the two-dimensional model of the cell through finite element modeling, use the Gaussian heat source data as the heat source load of the cell three-dimensional equivalent model, add the materials required for the model, and perform mesh division to reflect the mechanical behaviors of the solder layer and the GaN layer;

[0016] A power calculation module, configured to solve the cell three-dimensional equivalent model, obtain the temperature distribution and stress distribution of each layer in the cell, and calculate the data on the variation of the overall power of the cell three-dimensional equivalent model over time;

[0017] A device simulation model construction module, configured to observe and obtain the dimensions of the device microstructure, construct a device simulation model, and use the variation data obtained from the cell three-dimensional equivalent model as a function to obtain the thermal power of the entire chip;

[0018] A device performance analysis module, configured to use the thermal power as the heat source load of the device model, solve the device model, obtain the solution results at the device level, and conduct evaluation and analysis.

[0019] The present application has the following beneficial effects:

[0020] This method conducts detailed simulations on a single cell under high-temperature conditions and extrapolates the results to thousands of cells to form an overall heat source, which is loaded into the device-level simulation. This innovative method can comprehensively evaluate the temperature and stress distributions of P-GaN devices under high-temperature bias conditions, providing important theoretical basis and practical support for understanding the performance of devices in extreme working environments, thereby promoting the progress and application expansion of wide-bandgap semiconductor technologies.

[0021] By using the COMSOL simulation software to simulate the thermal distribution of the cell structure and the device structure, the present invention can intuitively display the temperature distribution and stress distribution of the cell and the device in a high-temperature gate bias environment. This improvement in thermal management ability helps to optimize the heat dissipation design of the device and reduce the risk of performance degradation caused by overheating.

[0022] Traditional TCAD simulation methods have limitations in the evaluation of stress distribution. However, through the loading of cells and overall heat sources, the present invention can more comprehensively analyze the stress changes of the device under high-temperature gate bias conditions. This stress analysis helps to predict the reliability and lifespan of the device and reduce the failure probability caused by stress concentration. At the same time, by obtaining temperature and stress distribution information during the simulation stage, the need for physical experiments is reduced, thereby lowering the R & D cost and time. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments and descriptions thereof are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0024] Figure 1 is a schematic diagram of the overall process involved in the method of the present invention;

[0025] Figure 2 is a flowchart of the implementation involved in the method of the present invention;

[0026] Figure 3 is a finite element simulation heat source load diagram involved in the method of the present invention;

[0027] Figure 4 is a schematic diagram of the cell structure of the P-GaN device involved in the method of the present invention;

[0028] Figure 5 is a contour map of the temperature and stress distribution of the cell structure involved in the method of the present invention;

[0029] Figure 6 is a temperature and stress distribution curve of the P-GaN unit cell involved in the method of the present invention;

[0030] Figure 7 is a device simulation structure diagram involved in the method of the present invention;

[0031] Figure 8 is a contour map of the temperature and stress of the overall structure of the P-GaN device involved in the method of the present invention;

[0032] Figure 9 is a temperature and stress distribution curve of the P-GaN device over time involved in the method of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] Next, in combination with the accompanying drawings in the preferred embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments.

[0034] All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0035] The present application explores the performance changes of power semiconductor devices over time in a high-temperature environment under the condition of applying a constant voltage between the gate and the source. Using the comprehensive simulation analysis method from micro to macro under the HTGB condition by COMSOL simulation software, the thermal distribution and stress distribution of P-GaN devices under high-temperature gate bias conditions are deeply analyzed.

[0036] Specifically, as Figures 1 to 2 shown, the present invention provides a cross-scale thermal-mechanical simulation method for GaN devices under HTGB conditions, and the method includes the following steps:

[0037] S1. Under high-temperature gate bias conditions, simulate and obtain the data of the cell thermal power density changing with time through a first simulation software, and use it as the input load of a second simulation software. Process the data using a Gaussian heat source to obtain Gaussian heat source data that conforms to the results obtained by the first simulation software;

[0038] S2. Through finite element modeling, construct a three-dimensional equivalent model of the cell according to the two-dimensional model of the cell. Use the Gaussian heat source data as the heat source load of the three-dimensional equivalent model of the cell, add the materials required for the model, and perform mesh division to reflect the mechanical behaviors of the solder layer and the GaN layer;

[0039] S3. Solve the three-dimensional equivalent model of the cell to obtain the temperature distribution and stress distribution of each layer in the cell, and calculate the data of the overall power of the three-dimensional equivalent model of the cell changing with time;

[0040] S4. Observe and obtain the dimensions of the device microstructure, construct a device simulation model, and use the changing data obtained from the three-dimensional equivalent model of the cell as a function to obtain the thermal power of the overall chip;

[0041] S5. Use the thermal power as the heat source load of the device model, solve the device model, obtain the solution results at the device level, and perform evaluation and analysis.

[0042] It should be noted that the steps of processing the data using a Gaussian heat source in S1 specifically include: at the center position of the heat source, the power density reaches the maximum value, and as the distance increases, the intensity of the heat source decays in the form of a Gaussian function. In S2, the materials required for the model include physical quantities such as density, coefficient of thermal expansion, and Young's modulus. In S4, the data of the power of the unit cell changing with time is used as a function, and the power is multiplied by the number of unit cells to obtain the thermal power of the overall chip. The specific size of the microscopic structure of the device observed in S4 is: using a super-depth-of-field microscope to observe the microscopic structure of the device in a top-down state to obtain its detailed size. The solution results at the device level in S5 include: the temperature and stress distributions of each part of the device.

[0043] It should be noted that in S4, for key regions such as the chip and solder layer regions, finer meshes should be set to improve the solution accuracy and ensure that the model can accurately reflect the mechanical behaviors of the solder layer and GaN layer during the analysis process. For other relatively simple regions such as the substrate and housing, coarser meshes can be used to reduce the calculation time.

[0044] In this embodiment, the first simulation software uses a TCAD design tool, and the second simulation software uses a COMSOL simulation software. Among them, TCAD (Technology Computer-Aided Design) is a computer-aided design tool for semiconductor process and device design, widely used in integrated circuit design, process development, and device optimization. It helps engineers predict the physical characteristics of devices, optimize the design process, reduce R & D costs, and shorten the product time to market through numerical simulation technology. COMSOL Multiphysics is a powerful multi-physics field simulation software, widely used in the fields of engineering and scientific research. It can simulate various physical phenomena and their interactions, helping users understand and optimize the design and performance of complex systems.

[0045] It should be noted that for obtaining the device-level solution results and conducting evaluation and analysis in S5, from the obtained curves, we can see that due to the high-temperature environment under HTGB conditions and the high electric field in the metal P-GaN Schottky junction region, electrons in the 2DEG will be accelerated to the metal / P-GaN interface under the acceleration of this electric field, resulting in heat accumulation at this interface. Once heat accumulates, the stress in this region will increase. Therefore, under HTGB conditions, the stress in the P-GaN layer is greater than that in the GaN layer. Specifically, the maximum stress value in the key region (such as the GaN layer) is extracted and compared with the stress threshold when cracks appear in the material. If it exceeds the threshold, it is determined that there is a potential failure mechanism. After 105 hours of the HTGB test, the simulation results show that the stress value of the GaN layer is 0.4 GPa, which is lower than the crack threshold of 2 GPa. Therefore, from the perspective of stress, at the 105-hour time point, the GaN layer has not exceeded the stress threshold that causes cracks.

[0046] The present method will be further described below in conjunction with specific drawings and exemplary embodiments.

[0047] Step (1), under high-temperature gate bias conditions, the gate voltage is 4.8 V and the temperature is 150 °C. Data on the cell thermal power density varying with time are obtained through TCAD simulation. Since heat accumulation is the largest on the P-GaN side when a voltage is applied to the gate, the thermal power density in this region can be obtained, and the thermal power density is up to 3×106 W / cm 3 , as Figure 3 shown in the thermal power density diagram of the (a) P-GaN region in

[0048] Step (2), the thermal power density data in Figure 3 (a) are processed using a Gaussian heat source. Since the position of the thermal power peak is fixed at each moment, it is necessary to fix the position of the heat source in the three-dimensional heat source model, that is, the heat source position is fixed at the 1-μm position. This means that at the center position of the heat source, the power density reaches the maximum value, and as the distance increases, the intensity of the heat source rapidly decays in the form of a Gaussian function, and the thermal power decays from 2.5×106 W / cm 3 to 1.6×106 W / cm 3 , as Figure 3 shown in the (b) Gaussian heat source diagram in

[0049] Step (3), based on step (2), finite element modeling is carried out. First, a three-dimensional equivalent model is established according to the two-dimensional model of the cell. Figure 4 is a schematic diagram of the cell structure and a simulation structure diagram.

[0050] Step (4): Add the Gaussian heat source data obtained in step (2) as a heat source load to the thermal simulation model, confirm that the position of the heat source data corresponds to the two-dimensional output result, and ensure that the data accurately reflects the actual heat input position on the P-GaN device.

[0051] Step (5): On the basis of step (4), add the materials required by the model, including physical properties such as density, coefficient of thermal expansion, and Young's modulus. At the same time, perform reasonable mesh division. For key areas, such as around the heat source and stress concentration areas, denser meshes should be set to improve the solution accuracy and ensure that the model can accurately reflect the mechanical behavior of the solder layer and GaN layer during the analysis process. In other relatively simple areas, sparser meshes can be used to reduce the calculation time.

[0052] Step (6): Based on the above steps, solve the unit cell model to obtain the temperature distribution and stress distribution of each layer in the unit cell. Figure 5 In (a) is the temperature contour map of the unit cell structure, Figure 5 In (b) is the stress contour map of the unit cell structure. Figure 6 In (a) is the curve of the temperature and stress of P-GaN changing with time, Figure 6 In (b) is the curve of the temperature and stress of GaN changing with time. It can be seen from Figure 6 that the stress of P-GaN is much greater than that of GaN. This is because under the HTGB condition, under the action of the high-temperature environment and the high electric field in the metal / P-GaN Schottky junction region, the electrons in the 2DEG will be accelerated to the metal / P-GaN interface under the acceleration of this electric field, resulting in heat accumulation at this interface. Once heat accumulates, the stress in this region will increase. Therefore, under the HTGB condition, the stress of the P-GaN layer is greater than that of the GaN layer.

[0053] Step (7): According to the data of the overall power of the unit cell model changing with time calculated in step (6), export the results.

[0054] Step (8): Use a super-depth-of-field microscope to observe the microstructure of the device, obtain its detailed dimensions, and establish a simulation model of the device. Figure 7 What is shown is the simulation structure diagram of the overall structure of the device. It can be known from the figure that the gate pin is connected to the gate metal pad through a bonding wire, the source pin is directly connected to the substrate, the substrate is connected to the metal pad of the source through a bonding wire, and the source and drain pads are staggered.

[0055] Step (9): Take the data of the single-cell power changing with time in step (7) as a function. After determining the functional form of the single-cell power, next, the calculation of the thermal power of the overall chip needs to be considered. The thermal power of the overall chip can be achieved by multiplying the power function of the single cell by the total number of unit cells.

[0056] Step (10), add the thermal power of the overall chip obtained in step (9) as a load to the simulation model and perform reasonable mesh division on it. For key regions, such as the chip and solder layer regions, finer meshes should be set to improve the solution accuracy and ensure that the model can accurately reflect the mechanical behaviors of the solder layer and GaN layer during the analysis process. For other relatively simple regions such as the substrate and the housing, coarser meshes can be used to reduce the calculation time.

[0057] Step (11), based on the above steps, solve the device model to obtain device-level solution results, such as the temperature and stress distributions of the solder, bond wires, chips, etc. Figure 8 (a) in shows the temperature contour of the overall device structure, Figure 8 and (b) in shows the stress contour of the overall device structure. Figure 9 (a) in is the curve of the temperature and stress of the chip varying with time, Figure 9 and (b) in is the curve of the temperature and stress of the chip varying with time. By extrapolating the simulation of the unit cell to the device simulation, the stress curves of other parts of the chip can be obtained, thereby avoiding the stress accumulation phenomenon. It is known that Figure 9 after 105 hours of the HTGB test in (a), the simulation results show that the stress value of the GaN layer is 0.4 GPa, and this stress value is lower than the crack threshold of 2 GPa. Therefore, from the perspective of stress, at the 105-hour time point, the GaN layer has not exceeded the stress threshold that causes cracks. Figure 9 after 105 hours of the HTGB test in (b), the simulation results show that the stress value of the solder layer is 0.2 GPa. It is known that the yield strength of PbSn5Ag2.5 exceeds 152 MPa and the tensile strength exceeds 259 MPa. Therefore, from the perspective of stress, at the 105-hour time point, the solder layer has undergone plastic deformation, but no cracks have appeared, thus further affecting its long-term reliability.

[0058] According to another aspect of the embodiments of the present application, a cross-scale thermal-mechanical simulation device for a GaN device under HTGB conditions, characterized by comprising:

[0059] A heat source data acquisition module, configured to, under high-temperature gate bias conditions, obtain data on the variation of the unit cell thermal power density with time through simulation using a first simulation software, and use it as the input load of a second simulation software. The data is processed using a Gaussian heat source to obtain Gaussian heat source data that is consistent with the results obtained by the first simulation software;

[0060] A three-dimensional equivalent model construction module for cells, configured to construct a three-dimensional equivalent model of cells based on a two-dimensional model of cells through finite element modeling, use the Gaussian heat source data as the heat source load of the three-dimensional equivalent model of cells, add the materials required for the model, and perform mesh division to reflect the mechanical behaviors of the solder layer and the GaN layer;

[0061] A power calculation module, configured to solve the three-dimensional equivalent model of cells, obtain the temperature distribution and stress distribution of each layer in the cells, and calculate the variation data of the overall power of the three-dimensional equivalent model of cells over time;

[0062] A device simulation model construction module, configured to observe and obtain the dimensions of the microstructure of the device, construct a device simulation model, and use the variation data obtained from the three-dimensional equivalent model of cells as a function to obtain the thermal power of the overall chip;

[0063] A device performance analysis module, configured to use the thermal power as the heat source load of the device model, solve the device model, obtain the solution results at the device level, and conduct evaluation and analysis.

[0064] The above is only the preferred embodiment of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

[0065] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

1. A cross-scale thermal simulation method for GaN devices under HTGB conditions, characterized in that The method includes the following steps: S1. Under high-temperature gate bias conditions, obtain data on the change of cell thermal power density over time through simulation using a first simulation software, and use it as the input load for a second simulation software. Process the data using a Gaussian heat source to obtain Gaussian heat source data that conforms to the results obtained by the first simulation software; S2. Through finite element modeling, construct a three-dimensional equivalent model of the cell based on the two-dimensional model of the cell. Use the Gaussian heat source data as the heat source load for the three-dimensional equivalent model of the cell, add the materials required for the model, and perform mesh division to reflect the mechanical behaviors of the solder layer and the GaN layer; S3. Solve the three-dimensional equivalent model of the cell to obtain the temperature distribution and stress distribution of each layer in the cell, and calculate the change data of the overall power of the three-dimensional equivalent model of the cell over time; S4. Observe the size of the device microstructure, construct a device simulation model, and use the change data obtained from the three-dimensional equivalent model of the cell as a function to obtain the thermal power of the entire chip; S5. Use the thermal power as the heat source load for the device model, solve the device model, and obtain the solution results at the device level and conduct evaluation and analysis.

2. The thermal simulation method of a GaN device across scales under HTGB conditions according to claim 1, wherein The step of processing the data using a Gaussian heat source in S1 specifically includes: at the center position of the heat source, the power density reaches the maximum value, and as the distance increases, the intensity of the heat source decays in the form of a Gaussian function.

3. A thermal simulation method for a GaN device across scales under HTGB conditions according to claim 1, characterized in that, In S1, the first simulation software uses a TCAD design tool, and the second simulation software uses a COMSOL simulation software.

4. A method for cross-scale thermal simulation of a GaN device under HTGB conditions according to claim 1, characterized in that In S2, the materials required for the model include density, thermal expansion coefficient, and Young's modulus.

5. A thermal simulation method for a GaN device across scales under HTGB conditions according to claim 1, characterized in that S4 specifically includes: using the data on the change of single-cell power over time as a function, and multiplying the power by the number of cells to obtain the thermal power of the entire chip.

6. A method for cross-scale thermal simulation of a GaN device under HTGB conditions according to claim 1, characterized in that The step of observing the size of the device microstructure in S4 specifically is: use a super-depth-of-field microscope to observe the microstructure of the device in the top-down state to obtain its detailed size.

7. A thermal simulation method for a GaN device across scales under HTGB conditions according to claim 1, characterized in that, The solution results at the device level in S5 include: the temperature and stress distributions of each part of the device.

8. A thermal simulation device for a GaN device across scales under HTGB conditions, characterized in that, Include: A heat source data acquisition module configured to, under high-temperature gate bias conditions, obtain data on the change of cell thermal power density over time through simulation using a first simulation software, and use it as the input load for a second simulation software. Process the data using a Gaussian heat source to obtain Gaussian heat source data that conforms to the results obtained by the first simulation software; A three-dimensional equivalent model construction module of the cell configured to, through finite element modeling, construct a three-dimensional equivalent model of the cell based on the two-dimensional model of the cell. Use the Gaussian heat source data as the heat source load for the three-dimensional equivalent model of the cell, add the materials required for the model, and perform mesh division to reflect the mechanical behaviors of the solder layer and the GaN layer; A power calculation module configured to solve the three-dimensional equivalent model of the cell to obtain the temperature distribution and stress distribution of each layer in the cell, and calculate the change data of the overall power of the three-dimensional equivalent model of the cell over time; The device simulation model construction module is configured to observe and obtain the dimensions of the microscopic structure of the device, construct a device simulation model, and use the change data obtained from the three-dimensional equivalent model of the unit cell as a function to obtain the thermal power of the entire chip; The device performance analysis module is configured to use the thermal power as the heat source load of the device model, solve the device model, and obtain and evaluate the solution results at the device level.

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