Convolutional neural network implementation method based on memristor array

Abstract

The invention discloses a convolutional neural network implementation method based on a memristor array, and relates to the field of semiconductor integrated circuits and neural morphology calculation. According to the method, the weight of the convolutional neural network is directly mapped to the conductance value of the memristor array, and hardware acceleration of the neural network is realized by using the nonvolatile storage and analog computing capability of the memristor. The 8 * 8 memristor array is used as a core calculation unit, the 97.2% high recognition accuracy of 26 letters can be achieved in the efficient learning process only needing 6 training periods, and the structure is remarkably superior to a 3 * 3 array structure and a 4 * 4 array structure of the same type. The 8 * 8 array not only can process recognition tasks with higher complexity, but also has better calculation efficiency, provides an innovative hardware implementation scheme for high-energy-efficiency neuromorphic calculation, and has the remarkable advantages of being short in training period, high in recognition precision, low in power consumption, high in expandability and the like.

Description

Technical Field

[0001] The present invention relates to the fields of semiconductor integrated circuits and neuromorphic computing, and particularly relates to a method for implementing a convolutional neural network based on a memristor array. By directly mapping the weights of the convolutional neural network into the conductance values of the memristor array, the present invention realizes the hardware-accelerated calculation of the neural network, solves the energy efficiency bottleneck problem caused by the separation of storage and calculation in the traditional computing architecture, and provides a new hardware implementation path for high-energy efficiency neuromorphic computing. The present invention is applicable to multiple application scenarios such as artificial intelligence chips, edge computing devices, intelligent sensing systems, pattern recognition, and complex information processing, and is of great significance for promoting the development of low-power and high-performance artificial intelligence technologies. Background Art

[0002] With the rapid development of artificial intelligence technology, convolutional neural networks (CNNs) have been widely applied in the fields of computer vision, natural language processing, and intelligent sensing due to their excellent feature extraction capabilities and classification accuracies. However, traditional convolutional neural networks are mainly implemented by software on general computing architectures (such as CPUs and GPUs). The computing mode using the "von Neumann" architecture causes data to move frequently between storage units and computing units, which not only brings significant energy consumption overhead and latency problems but also severely restricts the real-time performance of neural networks in edge computing environments. In recent years, with the diversification and complexity of artificial intelligence application scenarios, the academic and industrial communities have begun to explore new computing paradigms such as brain-inspired computing, in-memory computing, and compute-in-memory integration to break through the bottlenecks of traditional computing architectures.

[0003] As the fourth basic circuit element, since the first physical demonstration by HP Labs in 2008, the memristor has become an important technical route for the implementation of neuromorphic computing hardware due to its advantages such as nanoscale size, low power consumption, non-volatile storage, and analog computing capabilities. The conductance value of the memristor can be precisely regulated continuously by voltage pulses to achieve continuous multi-value storage. This characteristic is highly similar to the plasticity of synaptic weights in the biological nervous system, providing a new approach for the hardware implementation of neural networks. By directly mapping the weights of the neural network into the conductance values of the memristor crossbar array, parallel hardware acceleration of matrix multiplication can be achieved, significantly improving the computing efficiency and reducing the energy consumption. However, the existing implementation schemes of neural networks based on memristors still face many technical challenges. The sneak current problem in traditional memristor crossbar arrays limits the array scale. The current bypass paths formed by non-target cells cause serious crosstalk and signal distortion, significantly reducing the network accuracy. The weight resolution of conventional memristors is insufficient, and the conductance states show obvious randomness, affecting the network training accuracy and convergence. At the same time, the systematic research on the relationship between the memristor array scale, training efficiency, and task complexity is insufficient. Most works only focus on the performance optimization of arrays with specific scales, lacking comparative analysis of arrays with different scales on the same task, and unable to provide systematic guidance for the selection of array scales in practical applications.

[0004] To address the above problems, there is an urgent need to develop a method for implementing neural networks based on high-performance memristor arrays. In view of the deficiencies of the existing technology, the present invention proposes a method for implementing a convolutional neural network using Ag / AgI / PbI2 / ITO structure memristors with self-rectifying characteristics. Through the PN-junction-like rectification mechanism formed at the AgI / PbI2 interface, the sneak current problem in the crossbar array is effectively solved, ensuring the accuracy of signal reading while maintaining high integration density. A precisely controlled voltage pulse sequence is used to achieve continuous and precise regulation of weights, significantly improving the weight mapping accuracy. By systematically comparing the performance differences of arrays with different scales, the quantitative relationship between the array scale, task complexity, and training efficiency is revealed, providing theoretical guidance for array design. The present invention provides an innovative technical solution for constructing a high-efficiency and high-accuracy hardware neuromorphic computing system, which is of great significance for promoting the development of the next-generation artificial intelligence computing architecture. Summary of the Invention

[0005] Technical problems to be solved by the present invention: A method for implementing a convolutional neural network based on a memristor array disclosed by the present invention aims to solve technical problems such as sneak current interference, insufficient weight mapping accuracy, low training efficiency, and limited array scale in the prior art, and to achieve high-efficiency and high-precision hardware neuromorphic computing. The method for implementing a convolutional neural network based on a memristor array provided by the present invention realizes the integration of neural network computing and storage, eliminating the bottleneck of frequent data movement between storage units and computing units in the traditional architecture. Matrix multiplication operations are directly completed in the physical array, and compared with the software implementation under the traditional von Neumann architecture, the computing efficiency is significantly improved, the energy consumption is reduced, and the real-time processing ability of the neural network is significantly enhanced.

[0006] To solve the technical problems of the present invention, the technical solution proposed is: A method for implementing a convolutional neural network based on a memristor array, characterized by comprising the following steps:

[0007] (1) Construct an m×n memristor crossbar array, where each cross point forms a memristor unit; the memristor is an Ag / AgI / PbI2 / ITO structure memristor with self-rectifying characteristics, with a strip-shaped Ag electrode, an AgI thin film layer, a PbI2 thin film layer, and a strip-shaped ITO electrode from top to bottom. The upper and lower layer electrodes are vertically crossed to form a crossbar crossbar array, and each node is a functional unit;

[0008] (2) Regulate the conductance value of each memristor unit by applying a specific voltage pulse sequence, and map the weights of the neural network to the corresponding conductance states;

[0009] The weight mapping process includes the following steps: s1 Measure the initial conductance value of each memristor unit; s2 Calculate the required conductance adjustment amount according to the target value of the neural network weight; s3 Apply a voltage pulse sequence with the corresponding quantity and amplitude until the conductance value reaches the target value; s4 Perform conductance value normalization processing to map the conductance to a weight value within the range of 0-1.

[0010] (3) Use the array structure to perform convolution operations, where the input voltage is used as the input of the neural network and the output current is used as the output of the neural network; Based on Kirchhoff's law and Ohm's law, the array structure naturally realizes matrix multiply-accumulate operations: The input voltage signal is applied to the row lines through analog-to-digital conversion, the memristor conductance value stores the weight information, and the current signal collected by the column lines is read through a current-voltage conversion circuit to achieve parallel matrix multiplication;

[0011] (4) Calculate the weight gradient through the backpropagation algorithm according to the error between the output current and the target value, and apply corresponding voltage pulses to adjust the conductance value of the memristor; including: calculating the mean square error and its gradient between the output layer and the target value; calculating the gradient values of the weights of each layer layer by layer in reverse propagation; converting the gradient values into the amplitude and quantity of the voltage pulse sequence; applying the pulse sequence in turn to update the weight values of each unit;

[0012] (5) Repeat the above training process until the preset accuracy requirement is met or the training termination condition is satisfied, including: evaluating the network performance after each training cycle; when the change in the recognition accuracy rate for three consecutive cycles is less than the preset threshold of 0.5%, it is considered that the training converges and the training process ends; or forcefully end the training when the maximum number of training cycles is reached.

[0013] Preferably, a method for implementing a convolutional neural network based on a memristor array includes the following steps:

[0014] (1) Construct an m×n memristor crossbar array, where each cross point forms a memristor unit, and use a memristor with an Ag / AgI / PbI2 / ITO structure with self-rectifying characteristics. The p-n junction formed by AgI and PbI2 provides a rectifying function, effectively suppressing the sneak current problem in the array;

[0015] (2) Regulate the conductance value of each memristor unit by applying a specific voltage pulse sequence, and map the weights of the neural network to the corresponding conductance states, specifically including: applying a positive pulse (0.3V, 50ms) to increase the conductance value, and a negative pulse (-0.3V, 50ms) to decrease the conductance value; adaptively adjust the number of pulses according to the difference between the target weight and the current conductance value to achieve precise weight setting; establish a linear weight mapping relationship within the range of 0-1 through conductance value normalization processing;

[0016] (3) Perform convolutional operations using the array structure, where the input voltage serves as the input of the neural network and the output current serves as the output of the neural network; based on Kirchhoff's law and Ohm's law, the array structure naturally realizes matrix multiply-accumulate operations: the input voltage signal is applied to the row lines through analog-to-digital conversion, the memristor conductance value stores the weight information, and the current signal collected by the column lines is read through a current-voltage conversion circuit to achieve parallel matrix multiplication;

[0017] (4) Calculate the weight gradient through the backpropagation algorithm according to the error between the output current and the target value, and apply corresponding voltage pulses to adjust the conductance value of the memristor, including: calculating the mean square error and its gradient between the output layer and the target value; calculating the gradient values of the weights of each layer layer by layer in reverse propagation; converting the gradient values into the amplitude and quantity of the voltage pulse sequence; applying the pulse sequence in turn to update the weight values of each unit;

[0018] (5) Repeat the above training process until the preset accuracy requirement is met or the training termination condition is satisfied, including: evaluating the network performance after each training cycle; when the change in recognition accuracy for three consecutive cycles is less than the preset threshold (e.g., 0.5%), it is considered that the training has converged and the training process is terminated; or the training is forced to end when the maximum number of training cycles is reached.

[0019] Preferably, in the m×n memristor crossbar array, m = n = 8, forming an 8×8 array structure for realizing the recognition function of 26 letters.

[0020] Preferably, the conductance value regulation is achieved through a weight mapping process, including the following steps:

[0021] (1) Measure the initial conductance value of each memristor unit;

[0022] (2) Calculate the required conductance adjustment amount according to the target value of the neural network weight;

[0023] (3) Apply a voltage pulse sequence with the corresponding quantity and amplitude until the conductance value reaches the target value;

[0024] (4) Perform conductance value normalization to map the conductance to a weight value within the range of 0 - 1.

[0025] Preferably, the convolutional neural network includes an 8×8 input layer, 26 8×8 hidden layers, and 26 outputs for realizing the recognition of 26 letters. Each letter corresponds to a dedicated 8×8 convolutional kernel to achieve high-precision feature extraction and classification.

[0026] Preferably, the backpropagation algorithm determines the weight adjustment direction and amplitude by calculating the mean square error between the output current and the target value.

[0027] Preferably, the network performance is evaluated after each training cycle, and when the change in recognition accuracy for three consecutive cycles is less than the preset threshold, the training process is terminated.

[0028] Preferably, it further includes the step of visually displaying the recognition result of the memristor array. A corresponding grayscale image is generated through the current intensity to achieve an intuitive presentation of the recognition result. <(

[0029] Preferably, the read operation of the memristor array is performed with a bias voltage lower than the turn-on voltage to avoid interfering with the stored weight values.

[0030] Preferably, the scale of the m×n memristor crossbar array can be flexibly adjusted according to the task complexity, and a larger-scale neural network can be constructed through array interconnection.

[0031] Beneficial effects

[0032] The present invention discloses a method for implementing a convolutional neural network based on a memristor array, which relates to the fields of semiconductor integrated circuits and neuromorphic computing. This method directly maps the weights of the convolutional neural network into the conductance values of the memristor array, and utilizes the non-volatile storage and analog computing capabilities of the memristor to achieve hardware acceleration of the neural network. Specifically, the present invention uses an 8×8 memristor array as the core computing unit, and adjusts the conductance value of each memristor unit by applying a precisely controlled voltage pulse sequence, realizing continuous and precise adjustability of the network weights; fully utilizing the parallel computing characteristics of the array structure, it can achieve a high recognition accuracy of 97.2% for 26 letters in only 6 training cycles, significantly superior to the 3×3 array and 4×4 array structures of the same type. Comparative experiments show that the 8×8 array of the present invention can not only handle higher complexity recognition tasks, but also has better computing efficiency, providing an innovative hardware implementation scheme for energy-efficient neuromorphic computing, with significant advantages such as short training cycles, high recognition accuracy, low power consumption, and strong scalability, providing a new solution for artificial intelligence edge computing and energy-efficient information processing.

[0033] The method for implementing a convolutional neural network based on a memristor array provided by the present invention utilizes the parallel computing characteristics and non-volatile storage capabilities of the memristor array to achieve the integration of computing and storage of the neural network, eliminating the bottleneck of frequent data movement between the storage unit and the computing unit in the traditional architecture. The matrix multiplication operation is directly completed in the physical array, and compared with the software implementation under the traditional von Neumann architecture, the computing efficiency is significantly improved, the energy consumption is reduced, and the real-time processing ability of the neural network is significantly enhanced.

[0034] The present invention uses an Ag / AgI / PbI2 / ITO memristor with self-rectifying characteristics, and adjusts the conductance value of the memristor by a precisely controlled voltage pulse sequence, realizing a continuously adjustable conductance state to map the neural network weights. The weight resolution is significantly superior to that of traditional memristors. This high-precision weight mapping mechanism lays the foundation for the high-precision convergence of neural network training, enabling the system to accurately express complex weight distributions.

[0035] As described in Embodiment 1, the 8×8 array structure of the present invention can achieve a high recognition accuracy of 97.2% for 26 letters in only 6 training cycles, with an efficiency improvement of 5-8 times compared to the traditional software training method (usually requiring 30-50 cycles), and the energy consumption during the training process is significantly reduced. The efficient training mechanism stems from the direct in-situ adjustment of the conductance value of the memristor, avoiding the frequent reading and writing of weight data in the traditional method, and greatly reducing the system latency and energy consumption.

[0036] As described in Comparative Example 1 and Comparative Example 2, the present invention reveals the quantitative relationship between the array scale, task complexity, and training efficiency by systematically comparing the performance differences of 3×3 arrays, 4×4 arrays, and 8×8 arrays: the 3×3 array requires 7 training cycles to recognize 4 letters (accuracy 99.7%), the 4×4 array requires 6 cycles to recognize 6 letters (accuracy 96.4%), while the 8×8 array only requires 6 cycles to recognize 26 letters (accuracy 97.2%). This result confirms that larger-scale arrays can handle more complex recognition tasks while maintaining or improving training efficiency, providing a technical basis and theoretical guidance for constructing larger-scale neural networks.

[0037] The present invention gives full play to the parallel computing advantages of the crossbar array structure of memristors, providing an innovative hardware implementation scheme for energy-efficient neuromorphic computing, with broad application prospects in the fields of artificial intelligence edge computing, intelligent sensing, pattern recognition, etc., and providing important technical support for the development of the next-generation neuromorphic computing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 : Schematic diagram of the implementation process of a convolutional neural network; <......> (The ellipsis here indicates that the content of the tags

[0039] to Figure 2 is not provided in the original text for translation, but the tags are preserved as required) Figure 2 : Schematic diagram of the structure of the convolutional neural network implemented by the hardware of the present invention;

[0040] Figure 3 : A series of conductance states obtained by the rectifying memristor Ag / AgI / PbI2 / ITO of the present invention;

[0041] Figure 4 : Schematic layout diagram of 3×3 and 4×4 arrays on the 8×8 array prepared by the present invention;

[0042] Figure 5 : Schematic diagram of the network structure for the convolutional neural network of the memristor array (8×8) in Example 1 of the present invention to realize letter recognition;

[0043] Figure 6 : Curve graph of the relationship between the accuracy and training cycles for the 8×8 memristor array in Example 1 of the present invention to realize the recognition of 26 letters;

[0044] Figure 7 : Confusion matrix graph for the 8×8 memristor array in Example 1 of the present invention to realize the recognition of 26 letters;

[0045] Figure 8 : Schematic diagram of the result of the 8×8 memristor array in Example 1 of the present invention to recognize the letter N;

[0046] Figure 9 It should be noted that for the tags

[0039] - Figure 2 and Figure 3 - Figure 4 in the original text, since no specific content is provided for translation, the tags are simply preserved as they are in the translation. If there is any additional information in the future for these tags, the translation can be adjusted accordingly.: Relationship curve between the accuracy and training cycle of the memristor array (4×4) in Comparative Example 1 of the present invention for recognizing letters C, D, F, J, L, P;

[0047] Figure 10 : Relationship curve between the accuracy and training cycle of the memristor array (3×3) in Comparative Example 2 of the present invention for recognizing letters H, U, S, T; Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the embodiments of the invention. Among them, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0049] Embodiment 1

[0050] This embodiment proposes a method for implementing a convolutional neural network based on a memristor array, which can effectively solve the problem of separation between computing and storage in the hardware implementation of traditional neural networks and improve the computing efficiency and energy efficiency of neural networks.

[0051] As Figure 1 shown, the hardware implementation process of the convolutional neural network of the present invention includes setting the working state of the memristor array unit as the weight of the CNN neural network, obtaining an image from the processed image and inputting the pixel point features of the image in the form of voltage, and obtaining the output current after the array transmission operation as the result of the convolutional operation. The basic working principle of the memristor array is shown in Figure 2 . Each intersection point in the matrix represents a memristor unit, and its conductance value corresponds to the weight of the neural network. The input voltage is applied through the row line, and the output current is read through the column line, which conforms to the formula I = ∑G ij V j , realizing matrix multiplication operation.

[0052] The specific implementation steps of this embodiment are as follows:

[0053] Step 1: Construct an 8×8 memristor cross array. An Ag / AgI / PbI2 / ITO self-rectifying memristor is used to construct the cross array structure, where Ag is the top electrode, ITO is the bottom electrode, and AgI / PbI2 forms the functional layer. Through the thermal evaporation process, first deposit a 100-nm-thick PbI2 functional layer on the ITO conductive glass, and the evaporation parameters are a working pressure of 10 -5 Pa and a rate of 0.1 Å / s; then deposit a 2-nm-thick AgI layer on the PbI2 layer, and the evaporation parameters are the same as those of PbI2; finally, deposit an 80-nm-thick Ag electrode on the AgI layer through a mask, and the evaporation parameters are a working pressure of 10 -5Pa, at a rate of 0.5 Å / s, forms an electrode structure with a perpendicular cross arrangement. The width of the Ag electrode is 100 μm, the electrode spacing is 1000 μm, the thickness of the ITO electrode is 185 nm, the width of the ITO electrode is 100 μm, and the electrode spacing is 1000 μm. Finally, an 8×8 cross array structure is obtained.

[0054] Step 2: Conductance state regulation of the memristor. A specific voltage pulse sequence is applied to the memristor units in the array through a source meter (2612B) to achieve precise regulation of the conductance value. As Figure 3 shown, by continuously applying voltage pulses, a series of continuously varying conductance states can be obtained for mapping the weight values of the neural network. The specific operation is as follows: Apply 80 positive pulses (0.3 V, 50 ms) to increase the conductance value, and apply 80 negative pulses (-0.3 V, 50 ms) to decrease the conductance value; after modulation, normalize the conductance value and map it to the weight value in the range of 0-1 as the weight value of the convolutional kernel of the convolutional neural network.

[0055] Step 3: Design and mapping of the convolutional neural network. As Figure 5 shown, in this embodiment, a convolutional neural network structure for letter recognition is designed, including an 8×8 input layer (corresponding to an 8×8 pixel letter image), 26 hidden convolutional layers (each letter corresponds to a dedicated 8×8 convolutional kernel and a specific convolutional weight distribution), and 26 output nodes. The weight values of the 26 hidden layers are obtained through a combination of pre-training and online training. The initial weight distribution is determined using numerical simulation in the pre-training stage. The convolutional kernel weights are directly mapped to the conductance values of the memristor array. Matrix multiplication and addition convolutional operations are implemented through Kirchhoff's law and Ohm's law (in the cross array, the current output by the bit line is the sum of the products of the voltages applied to each unit and the unit element conductance, that is, one convolutional operation is completed). In this way, we can truly implement an on-chip neural network on hardware. As Figure 4 shown, on an 8×8 array, sub-array layouts of various scales can be implemented, including 3×3 and 4×4 arrays. Different scales of network nesting and reuse can be achieved by selecting different row and column combinations.

[0056] Step 4: Training process. Convert the letter image into an 8×8 pixel matrix, input the pixel value of each pixel point into the row line of the array through a voltage signal (input pixel value of 1 corresponds to 0.3 V voltage, and 0 corresponds to 0 V voltage); measure the output current of the column line, compare it with the target value to calculate the error; calculate the weight gradient through the backpropagation algorithm; according to the direction and magnitude of the gradient, apply corresponding voltage pulses to adjust the conductance value of the memristor to correct the weight; repeat the above training process until the recognition accuracy reaches the preset requirement or the accuracy improvement is less than the preset threshold (0.5%) for three consecutive cycles.

[0057] Step Five: Performance Evaluation. As Figure 6 shown, the accuracy of the 8×8 array increased significantly with the number of epochs during training and reached a high recognition accuracy of 97.2% after the 6th training epoch. As Figure 7 shown, by analyzing the recognition results of 26 letters through the confusion matrix, it was confirmed that the main misidentifications occurred between letters with similar shapes (such as "E" and "F"), which conforms to the principle of visual similarity. As Figure 8 shown, the recognition result of the letter "N" presented as an 8×8 grayscale image, and its current distribution highly coincided with the pixel distribution of the target letter, verifying the feature extraction ability of the system.

[0058] In this embodiment, the read operation of the memristor array is performed with a bias voltage lower than the turn-on voltage to avoid disturbing the stored weight values.

[0059] The convolutional neural network based on the 8×8 memristor array implemented in this embodiment achieved a high accuracy of 97.2% in the 26-letter recognition task, only requiring 6 training epochs. Compared with the traditional implementation through backend computer software (usually requiring 30 - 50 epochs), the efficiency was increased by 5 - 8 times. And the energy consumption during the training process was significantly reduced. The efficient training mechanism stems from the direct in-situ regulation of the memristor conductance value, avoiding the frequent reading and writing of weight data in the traditional method, and greatly reducing the system latency and energy consumption.

[0060] The computing and storage integrated architecture implemented by the memristor array in this embodiment effectively solves the energy efficiency bottleneck problem in the traditional von Neumann architecture and provides a hardware foundation for efficient neuromorphic computing.

[0061] Comparative Example 1

[0062] The device preparation process of this comparative example is the same as that of Example 1. The only difference is that when constructing the memristor array, only the 4×4 part of the 8×8 array is used, and a sub-array in the blue box area as Figure 4 shown is formed by selecting specific row lines and column lines.

[0063] The network structure and training method of this comparative example are the same as those of Example 1, but the input image resolution is reduced to 4×4, the convolutional kernel size is correspondingly adjusted to 4×4, and the number of hidden layers is reduced to 6 (corresponding to recognizing six letters "CDFJLP").

[0064] The test results of this comparative example are as Figure 9As shown, for the 4×4 array in the task of recognizing the six letters "CDFJLP", 6 training cycles are required to achieve a recognition accuracy of 96.4%. Although the number of training cycles is the same as that in Example 1, the task complexity is significantly reduced (only 6 letters vs 26 letters), the number of computing units is reduced to 25% of that in Example 1, and the number of weight parameters (4×4×6 = 96) is only about 5.8% of that in Example 1 (8×8×26 = 1664). Considering the significant reduction in task complexity, the comprehensive resource efficiency is lower than that in Example 1.

[0065] In this comparative example, although the 4×4 array can achieve a high recognition accuracy, the complexity of the task it processes is significantly limited, verifying the key influence of the array scale on the processing ability of the neural network.

[0066] Comparative Example 2

[0067] The device preparation process of this comparative example is the same as that in Example 1. The only difference is that when constructing the memristor array, only the 3×3 part of the 8×8 array is used, and by selecting specific row lines and column lines, a sub-array in the purple box area as shown in Figure 4 is formed.

[0068] The network structure and training method of this comparative example are the same as those in Example 1, but the input image resolution is reduced to 3×3, the convolution kernel size is correspondingly adjusted to 3×3, and the number of hidden layers is reduced to 4 (corresponding to recognizing the four letters "HUST").

[0069] The test results of this comparative example are as shown in Figure 10 For the 3×3 array in the task of recognizing the four letters "HUST", 7 training cycles are required to achieve a recognition accuracy of 99.7%. Although the final accuracy is slightly higher than that in Example 1, the task is extremely simplified (only 4 letters vs 26 letters), and the number of training cycles increases instead, indicating that there are obvious limitations in the training efficiency of small-scale arrays. The number of computing units is reduced to about 14% of that in Example 1, and the number of weight parameters (3×3×4 = 36) is only about 2.2% of that in Example 1. Considering the significant reduction in task complexity and the increase in the number of training cycles, the comprehensive resource efficiency is significantly lower than that in Example 1.

[0070] In this comparative example, although the extremely small-scale 3×3 array achieves a high accuracy in an extremely simple task, the training efficiency decreases and the application scenario is extremely limited, further demonstrating the importance of appropriately increasing the array scale to improve the processing ability of the neural network.

[0071] Through the comparison of the above three different-scale arrays, it is confirmed that larger-scale arrays can handle more complex recognition tasks while maintaining or even improving the training efficiency, verifying the scalability advantage of the neural network constructed based on the memristor array in the present invention. When the task complexity of the 8×8 array is about 4.3 times higher than that of the 4×4 array and about 6.5 times higher than that of the 3×3 array, the number of training cycles decreases instead of increasing, demonstrating excellent computational efficiency and resource utilization rate, providing a technical basis for constructing large-scale neuromorphic computing systems.

Claims

1. A method for implementing a convolutional neural network based on a memristor array, characterized in that It includes the following steps: (1) Construct an m×n memristor crossbar array, where each cross point forms a memristor cell; the memristor is an Ag / AgI / PbI2 / ITO structure memristor with self-rectifying characteristics, including a strip-shaped Ag electrode, an AgI thin film layer, a PbI2 thin film layer, and a strip-shaped ITO electrode from top to bottom. The upper and lower layer electrodes are vertically and cross-arranged to form a crossbar crossbar array, and each node is a functional unit; (2) Regulate the conductance value of each memristor cell by applying a specific voltage pulse sequence, and map the weights of the neural network to the corresponding conductance states; The weight mapping process includes the following steps: s1 Measure the initial conductance value of each memristor cell; s2 Calculate the required conductance adjustment amount according to the target value of the neural network weight; s3 Apply a voltage pulse sequence with the corresponding quantity and amplitude until the conductance value reaches the target value; s4 Perform conductance value normalization processing to map the conductance to a weight value within the range of 0-1; (3) Use the array structure to perform convolution operations, where the input voltage serves as the input of the neural network and the output current serves as the output of the neural network; Based on Kirchhoff's law and Ohm's law, the array structure naturally realizes matrix multiply-accumulate operations: the input voltage signal is applied to the row lines through analog-to-digital conversion, the memristor conductance value stores the weight information, and the current signal collected by the column lines is read through a current-voltage conversion circuit to achieve parallel matrix multiplication; (4) According to the error between the output current and the target value, calculate the weight gradient through the backpropagation algorithm and apply the corresponding voltage pulse to adjust the memristor conductance value; It includes: calculating the mean square error between the output layer and the target value and its gradient; calculating the gradient values of the weights of each layer layer by layer in the reverse direction; converting the gradient values into the amplitude and quantity of the voltage pulse sequence; applying the pulse sequence in turn to update the weight values of each unit; (5) Repeat the above training process until the preset accuracy requirement is met or the training termination condition is satisfied, including: evaluating the network performance after each training cycle; when the change in the recognition accuracy rate for three consecutive cycles is less than the preset threshold of 0.5%, it is considered that the training converges and the training process ends; or forcefully end the training when the maximum number of training cycles is reached.

2. The implementation method of the convolutional neural network based on the memristor array according to claim 1, wherein In the m×n memristor crossbar array, m = n = 8, forming an 8×8 array structure.

3. The implementation method of the convolutional neural network based on the memristor array according to claim 1, characterized in that, The specific voltage pulse sequence includes positive pulses and negative pulses, which are used to enhance or weaken the conductance value of the memristor. By continuously applying voltage pulses, a series of continuously changing conductance states can be obtained, which are used to map the weight values of the neural network. The specific operation is as follows: apply 80 positive pulses (0.3V, 50ms) to enhance the conductance value, and apply 80 negative pulses (-0.3V, 50ms) to reduce the conductance value; After modulation, perform normalization processing on the conductance value and map it to a weight value within the range of 0-1, which is used as the weight value of the convolution kernel of the convolutional neural network.

4. The method for implementing a convolutional neural network based on a memristor array according to claim 1, wherein The convolutional neural network includes an 8×8 input layer, 26 8×8 hidden layers, and 26 outputs, which are used to recognize 26 letters. The weight values of the 26 hidden layers are obtained by combining pre-training and online training. In the pre-training stage, numerical simulation is used to determine the initial weight distribution.

5. The implementation method of the convolutional neural network based on the memristor array according to claim 1, characterized in that, The backpropagation algorithm determines the direction and amplitude of weight adjustment by calculating the mean square error between the output current and the target value.

6. The method for implementing a convolutional neural network based on a memristor array according to claim 1, characterized in that, The network performance is evaluated after each training cycle. When the change in recognition accuracy for three consecutive cycles is less than the preset threshold, the training process ends.

7. The implementation method of the convolutional neural network based on the memristor array according to claim 1, wherein It also includes the step of visually displaying the recognition results of the memristor array. By generating a corresponding grayscale image based on the current intensity, the intuitive presentation of the recognition results is realized.

8. The method for implementing a convolutional neural network based on a memristor array according to claim 1, wherein The read operation of the memristor array is performed using a bias voltage lower than the turn-on voltage to avoid disturbing the stored weight values.

9. The method for implementing a convolutional neural network based on a memristor array according to claim 1, wherein The scale of the m×n memristor crossbar array can be flexibly adjusted according to the task complexity, and a larger-scale neural network can be constructed through array interconnection.

10. The method for implementing a convolutional neural network based on a memristor array according to claim 1, wherein It includes the following steps: Step 1: Construct an 8×8 memristor crossbar array. Use an Ag / AgI / PbI2 / ITO self-rectifying memristor to construct the crossbar array structure, where Ag is the top electrode, ITO is the bottom electrode, and AgI / PbI2 forms the functional layer. Through the thermal evaporation process, first deposit a 100-nm-thick PbI2 functional layer on the ITO conductive glass, and the evaporation parameters are a working pressure of 10 -5 Pa and a rate of 0.1 Å / s. Then deposit a 2-nm-thick AgI layer on the PbI2 layer, and the evaporation parameters are the same as those of PbI2. Finally, deposit an 80-nm-thick Ag electrode on the AgI layer through a mask, and the evaporation parameters are a working pressure of 10 -5 Pa and a rate of 0.5 Å / s to form a vertically cross-arranged electrode structure. The width of the Ag electrode is 100 μm, the electrode spacing is 1000 μm, the thickness of the ITO electrode is 185 nm, the width of the ITO electrode is 100 μm, and the electrode spacing is 1000 μm, finally obtaining an 8×8 crossbar array structure; Step 2: Memristor conductance state regulation: A specific voltage pulse sequence is applied to the memristor units in the array through a source meter (2612B) to achieve precise regulation of the conductance value. By continuously applying voltage pulses, a series of continuously changing conductance states can be obtained, which are used to map the weight values of the neural network. The specific operation is as follows: Apply 80 positive pulses (0.3V, 50ms) to increase the conductance value, and apply 80 negative pulses (-0.3V, 50ms) to decrease the conductance value. After the modulation is completed, the conductance value is normalized and mapped to the weight value in the range of 0-1 as the weight value of the convolutional kernel of the convolutional neural network. Step 3: Convolutional neural network design and mapping: The convolutional neural network structure for letter recognition includes an 8×8 input layer corresponding to an 8×8 pixel letter image, 26 hidden convolutional layers, each letter corresponding to a dedicated 8×8 convolutional kernel and a specific convolutional weight distribution, and 26 output nodes. The weight values of the 26 hidden layers are obtained by combining pre-training and online training. In the pre-training stage, numerical simulation is used to determine the initial weight distribution. The convolutional kernel weights are directly mapped to the conductance values of the memristor array. Through Kirchhoff's law and Ohm's law, the matrix multiply-accumulate convolution operation is realized. In the crossbar array, the current output by the bit line is the sum of the products of the voltages applied to each unit and the unit element conductance, that is, one convolution operation is completed, and the on-chip neural network can be truly realized on the hardware: various scales of sub-array layouts can be realized on the 8×8 array. Step 4: Training process: Convert the letter images into 8×8 pixel matrices, input the pixel values of each pixel point as voltage signals, where a pixel value of 1 corresponds to a voltage of 0.3V and a pixel value of 0 corresponds to 0V, and input them to the row lines of the array; measure the output current of the column lines, compare it with the target value to calculate the error; calculate the weight gradient through the backpropagation algorithm; according to the direction and magnitude of the gradient, apply corresponding voltage pulses to adjust the conductance value of the memristor to correct the weight; repeat the above training process until the recognition accuracy reaches the preset requirement or the accuracy improvement is less than the preset threshold of 0.5% for three consecutive cycles; Step 5: Performance evaluation: The accuracy of the 8×8 array increases significantly with the increase of the number of cycles during the training process and reaches a high recognition accuracy of 97.2% after the 6th training cycle. Analyze the recognition results of 26 letters through the confusion matrix, confirm that the main misidentifications occur between letters with similar shapes, which conforms to the principle of visual similarity. The recognition result of the letter "N" is presented as an 8×8 grayscale image, and its current distribution highly coincides with the pixel distribution of the target letter, verifying the feature extraction ability of the system.

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