Quantum processor for screening target lattice vectors and method for solving shortest vector

Abstract

The invention discloses a quantum processor for screening a target lattice vector and a method for solving a shortest vector, and relates to the technical field of quantum computing, the quantum processor comprises an amplitude preparation circuit and an amplitude amplification circuit; the amplitude preparation circuit is used for obtaining a first amplitude of a target lattice vector quantum state and a second amplitude of a non-target lattice vector quantum state, the two-norm of the target lattice vector is smaller than a preset parameter, and the two-norm of the non-target lattice vector is larger than or equal to the preset parameter; the initial state of the amplitude preparation circuit comprises a superposition state of to-be-screened lattice vectors; and the amplitude amplification circuit is used for amplifying the first amplitude of the quantum state of the target lattice vector to be close to 1, so that the target lattice vector can be screened by using a quantum computer.

Description

Technical Field

[0001] This application belongs to the field of quantum computing technology, and particularly relates to a quantum processor for screening target lattice vectors and a method for solving the shortest vector. Background Art

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores, and processes quantum information in accordance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Because a quantum computer has the ability to process mathematical problems more efficiently than an ordinary computer. For example, it can accelerate the time to crack the RSA key from hundreds of years to a few hours, so it has become a key technology under research.

[0003] The shortest vector problem (SVP) is one of the fundamental difficult problems on lattices and is the basis for the security of lattice cryptosystems. The SVP solving algorithm is a key technology for evaluating the specific security of lattice cryptography algorithms. First, the definition of a lattice (Lattice) is given. Suppose there are d linearly independent vectors b1, b2,..., b d ∈R m , then the lattice L generated by b1, b2,..., b d is all integer-coefficient linear combinations of these vectors:

[0004] L = {c1b1 + c2b2 +... + c n b d : c1, c2..., c d ∈Z}

[0005] Correspondingly, such a set of vectors is called a basis of the lattice L.

[0006] The SVP problem is defined as follows: Given a lattice find the shortest non-zero target lattice vector in it, that is, output v ∈ L such that ||v|| = λ1(L), where λ1(L) refers to the length of the shortest vector in the lattice L.

[0007] Therefore, for a given lattice, the sieve method can be used to screen the lattice vectors in the lattice, and determine whether each lattice vector satisfies certain restrictive conditions, search for the target lattice vector, and find the shortest lattice vector. When performing such a search on a lattice of size N, the time complexity of the classical algorithm is O(N), while the Grover quantum search algorithm is only How to implement screening target lattice vectors using a quantum computer is crucial. Summary of the Invention

[0008] The objective of this application is to provide a quantum processor for screening target lattice vectors and a method for solving the shortest vector, aiming to realize screening target lattice vectors using a quantum computer.

[0009] To achieve the above objective, in the first aspect of the embodiments of this application, a quantum processor for screening target lattice vectors is provided. The quantum processor includes an amplitude preparation circuit and an amplitude amplification circuit.

[0010] The amplitude preparation circuit is used to obtain the first amplitude of the quantum state of the target lattice vector and the second amplitude of the quantum state of the non-target lattice vector. Among them, the two-norm of the target lattice vector is less than a preset parameter, and the two-norm of the non-target lattice vector is greater than or equal to the preset parameter. The initial state of the amplitude preparation circuit includes the superposition state of the lattice vectors to be screened.

[0011] The amplitude amplification circuit is used to amplify the first amplitude of the quantum state of the target lattice vector to approach 1.

[0012] In a possible implementation manner, the amplitude preparation circuit includes a two-norm calculator and a data size comparison calculator.

[0013] The two-norm calculator is used to calculate the two-norm of each lattice vector to be screened and store the calculated two-norm in a second register.

[0014] The data size comparison calculator is used to determine the first amplitude of the quantum state of the target lattice vector and the second amplitude of the quantum state of the non-target lattice vector according to the size relationship between the preset parameter and each two-norm.

[0015] In a possible implementation manner, the data size comparator is used to determine the first amplitude of the quantum state of the target lattice vector and the second amplitude of the quantum state of each non-target vector based on the quantum state of the auxiliary bit to determine the first amplitude of the quantum state of the target lattice vector and the second amplitude of the quantum state of each non-target vector;

[0016] When the quantum state of the auxiliary bit is |1>, it indicates that the two-norm of the target lattice vector is less than the preset parameter, and it is determined as the quantum state of the target lattice vector, as the target lattice vector, and sinθ is the first amplitude of the quantum state of the target lattice vector;

[0017] When the quantum state of the auxiliary bit is |0>, it indicates that the two-norm of the non-target lattice vector is greater than or equal to the preset parameter, and it is determined as the quantum state of the non-target lattice vector, as the non-target lattice vector, and cosθ is the second amplitude of the quantum state of the non-target lattice vector.

[0018] In a possible implementation, the amplitude amplification circuit includes a first flipping sub-circuit acting on an auxiliary qubit, which is used to flip the second amplitude of the non-target lattice vector quantum state, so that the quantum state of the auxiliary qubit changes from to

[0019] In a possible implementation, the amplitude amplification circuit further includes a second flipping sub-circuit, which is used to flip the first amplitude of the target lattice vector quantum state, so that the quantum state of the auxiliary qubit changes from to

[0020] In a possible implementation, the amplitude amplification circuit acts on the auxiliary qubit k times, and the quantum state of the auxiliary qubit evolves into where (2k + 1)θ approaches the target quantum state and the first amplitude sin(2k + 1)θ approaches 1.

[0021] In a second aspect of the embodiments of the present application, a method for solving the shortest vector is provided, including:

[0022] Constructing a quantum processor as described in any one of the first aspects; wherein, the initial state of the quantum processor includes a superposition state of lattice vectors to be screened;

[0023] Running the quantum processor and measuring the auxiliary qubit to obtain the quantum state corresponding to the target lattice vector; wherein, the target lattice vector includes vectors in the lattice vectors to be screened whose second norm is less than a preset parameter;

[0024] Updating the obtained quantum state corresponding to the target lattice vector to the initial state of the quantum processor, executing the adjustment rule of the preset parameter, and returning to execute the step of running the quantum processor and measuring the auxiliary qubit to obtain the quantum state corresponding to the target lattice vector, until the shortest vector in the lattice vectors to be screened is obtained when the preset parameter is adjusted to a preset value by using the adjustment rule of the preset parameter.

[0025] In a third aspect of the embodiments of the present application, a device for solving the shortest vector is provided, and the device includes:

[0026] A construction module, configured to construct a quantum processor as described in any one of the first aspects; wherein, the initial state of the quantum processor includes a superposition state of lattice vectors to be screened;

[0027] A running module, configured to run the quantum processor and measure the auxiliary qubit to obtain the quantum state corresponding to the target lattice vector; wherein, the target lattice vector includes vectors in the lattice vectors to be screened whose second norm is less than a preset parameter;

[0028] An update module, configured to update the quantum state corresponding to the obtained target lattice vector to the initial state of the quantum processor, execute the adjustment rule of the preset parameter, and return to execute the step of running the quantum processor and measuring the auxiliary qubit to obtain the quantum state corresponding to the target lattice vector, until the preset parameter is adjusted to a preset value by using the adjustment rule of the preset parameter, and the shortest vector in the lattice vectors to be screened is obtained.

[0029] In a fourth aspect of the embodiments of the present application, a storage medium is provided, in which a computer program is stored, and the computer program is configured to execute the steps of the method described in any one of the above first aspects when running.

[0030] In a fifth aspect of the embodiments of the present application, an electronic device is provided, including a memory and a processor, a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps of the method described in any one of the above first aspects.

[0031] Based on the above technical solutions, the quantum processor provided in the present application includes an amplitude preparation circuit and an amplitude amplification circuit. The amplitude preparation circuit is configured to obtain a first amplitude of the quantum state of the target lattice vector and a second amplitude of the quantum state of the non-target lattice vector, where the two-norm of the target lattice vector is less than a preset parameter, and the two-norm of the non-target lattice vector is greater than or equal to the preset parameter. The initial state of the amplitude preparation circuit includes a superposition state of the lattice vectors to be screened; the amplitude amplification circuit is configured to amplify the first amplitude of the quantum state of the target lattice vector to approach 1. In the embodiments of the present application, the amplitude preparation circuit obtains the first amplitude of the quantum state of the target lattice vector and the second amplitude of the quantum state of the non-target lattice vector, and then the amplitude amplification circuit can amplify the first amplitude of the target lattice vector with a two-norm less than the preset parameter, which can also amplify the measurement probability of the target lattice vector, so that the target lattice vector can be measured, and thus the target lattice vector with a two-norm less than the preset parameter can be screened by using the quantum computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a network block diagram of a system for solving the shortest lattice vector shown according to an exemplary embodiment.

[0033] Figure 2 is a schematic quantum circuit diagram of a two-norm calculator shown according to an exemplary embodiment.

[0034] Figure 3 is a schematic quantum circuit diagram of a data size comparison calculator shown according to an exemplary embodiment.

[0035] Figure 4It is a schematic diagram of an amplitude preparation circuit shown according to an exemplary embodiment.

[0036] Figure 5 It is a schematic diagram of a first flipping sub-circuit shown according to an exemplary embodiment.

[0037] Figure 6 It is a schematic diagram of a second flipping sub-circuit shown according to an exemplary embodiment.

[0038] Figure 7 It is a schematic diagram of a quantum circuit of a quantum processor for screening target lattice vectors shown according to an exemplary embodiment.

[0039] Figure 8 It is a flowchart of a method for solving the shortest lattice vector shown according to an exemplary embodiment.

[0040] Figure 9 It is a block diagram of a device for solving the shortest lattice vector shown according to an exemplary embodiment.

[0041] Figure 10 It is a block diagram of a computer device shown according to an exemplary embodiment. Detailed implementation manners

[0042] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0043] Figure 1 It is a network block diagram of a system for solving the shortest lattice vector provided by an embodiment of the present application. The system for solving the shortest lattice vector may include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0044] The network 110 is a medium for providing communication links between various devices and computers connected together within the system for solving the shortest lattice vector, including but not limited to the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof. The connection method may adopt wired, wireless communication links, or fiber optic cables, etc.

[0045] The server 120, the wireless device 130, and the client 140 are conventional data processing systems, which may contain data and have application programs or software tools for performing conventional computing processes. The client 140 can be a personal computer or a network computer, so the data can also be provided by the server 120. The wireless device 130 can be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0046] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) can be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) can be used to implement a quantum algorithm compiled according to the method for solving the shortest lattice vector provided in the embodiments of the present application.

[0047] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner. Similarly, any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0048] It should be noted that a real quantum computer has a hybrid structure, which at least includes Figure 1 two major parts: the classical computing unit 160, which is responsible for performing classical computing and control; and the quantum computing unit 170, which is responsible for running quantum programs to implement quantum computing.

[0049] The above-mentioned classical computing unit 160 and quantum computing unit 170 can be integrated in one device or distributed in two different devices. For example, the first device including the classical computing unit 160 runs a classical computer operating system, which provides quantum application development tools and services, as well as storage and network services required for quantum applications. The user develops a quantum program through the quantum application development tools and services on it, and sends the quantum program to the second device including the quantum computing unit 170 through the network service on it. The second device runs a quantum computer operating system, which parses and compiles the code of the quantum program into instructions that can be recognized and executed by the quantum processor 170, and the quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0050] The computing unit of the classical processor 161 in the classical computing unit 160 is based on CMOS transistors on a silicon chip. This computing unit is not restricted by time and coherence, that is, this computing unit is not restricted by the usage duration and is available at any time. In addition, in a silicon chip, the number of such computing units is also sufficient. Currently, the number of computing units in a classical processor 161 is in the thousands. The sufficiency of the number of computing units and the fixed computing logic available for selection by CMOS transistors, such as AND logic. When operating with CMOS transistors, a large number of CMOS transistors are combined with limited logic functions to achieve the operation effect.

[0051] The basic computing unit of the quantum processor 171 in the quantum computing unit 170 is a qubit. The input of a qubit is restricted by coherence and also by the coherence time, that is, a qubit is restricted by the usage duration and is not available at any time. Making full use of qubits within their available usage duration is a key problem in quantum computing. In addition, the number of qubits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each qubit realizes its computing function through logic functions configured on demand. Given the limited number of qubits, while the logic functions in the field of quantum computing are diverse, such as Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. When performing quantum computing, it is necessary to combine a limited number of qubits with diverse combinations of logic functions to achieve the operation effect.

[0052] Based on these differences, the design of classical logic functions acting on CMOS transistors and the design of quantum logic functions acting on qubits are significantly and essentially different; the design of classical logic functions acting on CMOS transistors does not need to consider the individuality of CMOS transistors, such as the individual identification of which CMOS transistor it is in the silicon chip, its position, and the available usage duration of each CMOS transistor. Therefore, the classical algorithms composed of classical logic functions only express the operation relationship of the algorithm and do not express the dependence of the algorithm on the individuality of CMOS transistors.

[0053] However, when quantum logic functions act on qubits, it is necessary to consider the individuality of qubits, such as the individual identification of which qubit it is in the quantum chip, its position, the relationship with surrounding qubits, and the available usage duration of each qubit. Therefore, the quantum algorithms composed of quantum logic functions not only express the operation relationship of the algorithm but also express the dependence of the algorithm on the individuality of qubits.

[0054] Exemplary:

[0055] Quantum algorithm one: H1, H2, CNOT(1,3), H3, CNOT(2,3);

[0056] Quantum Algorithm 2: H1, H2, CNOT(1,2), H3, CNOT(2,3);

[0057] Quantum Algorithm 1 and Quantum Algorithm 2 use the method of adding Arabic numerals to quantum logic gates to represent the qubits on which the quantum logic gates act. The Arabic numerals 1, 2, and 3 among them can represent three sequentially connected qubits Q1, Q2, Q3 or interconnected qubits Q1, Q2, Q3;

[0058] An exemplary explanation of how quantum algorithms are affected by the coherence time of qubits is as follows:

[0059] Define the execution duration of a single-qubit logic gate as t, and the execution time of 1 two-qubit logic gate acting on adjacent qubits as 2t; then:

[0060] When Q1, Q2, and Q3 are interconnected with each other, the calculation of Quantum Algorithm 1 requires 6t, which is carried out in 4 time periods. The duration required for each time period is t, 2t, t, 2t respectively. The operations executed within each time period are: H1, H2; CNOT(1,3); H3; CNOT(2,3);

[0061] The calculation of Quantum Algorithm 1 requires 5t, which is carried out in 3 time periods. The duration required for each time period is t, 2t, 2t respectively. The operations executed within each time period are: H1, H2, H3; CNOT(1,2); CNOT(2,3);

[0062] When Q1, Q2, and Q3 are sequentially connected, Quantum Algorithm 1 needs to be equivalent to: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3); The calculation of the equivalent Quantum Algorithm 1 requires 10t, which is divided into 4 time periods. The duration required for each time period is t, 6t, t, 2t respectively. The operations executed within each time period are: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3).

[0063] Therefore, the quantum logic function acting on the design of qubits (including the design of whether to use qubits and the design of the usage efficiency of each qubit) is the key to improving the computing performance of quantum computers and requires special design. This is also the uniqueness of quantum algorithms based on quantum logic functions, which is essentially and significantly different from classical algorithms based on classical logic functions. The above-mentioned design for qubits is a technical problem that ordinary computing devices do not need to consider and do not need to face. This application proposes a quantum processor for screening target lattice vectors and a method for solving the shortest vector to realize screening target lattice vectors using a quantum computer.

[0064] An embodiment of this application provides a quantum processor for screening target lattice vectors. The quantum processor includes an amplitude preparation circuit and an amplitude amplification circuit.

[0065] The amplitude preparation circuit is used to obtain the first amplitude of the quantum state of the target lattice vector and the second amplitude of the quantum state of the non-target lattice vector. Among them, the two-norm of the target lattice vector is less than a preset parameter, and the two-norm of the non-target lattice vector is greater than or equal to the preset parameter. The initial state of the amplitude preparation circuit includes the superposition state of the lattice vectors to be screened.

[0066] The amplitude amplification circuit is used to amplify the first amplitude of the quantum state of the target lattice vector to approach 1.

[0067] In an embodiment of this application, the preparation of the superposition state of the lattice vectors to be screened requires pre-obtaining the lattice basis B = {b1,..., b d}, where b i ∈Z p , the lattice vector dimension d, and pre-setting the upper bound of the lattice points as p, and outputting the superposition state of lattice vectors in the lattice with a sub-exponential O(2 0.2075*d ) number

[0068] Among them, α i is the amplitude corresponding to the i-th lattice vector quantum state, and the sum of the squares of the amplitudes of each lattice vector quantum state is 1, that is, it satisfies S is the number of samples.

[0069] For example, when preparing the superposition state of lattice vectors with a dimension of 2 and an upper bound of 3, the output is {'1001': 0.7071067811865476, '0110': 0.6324555320336759, '0000': 0.31622776601683794}, which respectively represent that the quantum state of the lattice vector (2, 1) is |1001>, the amplitude is 0.7071067811865476, the quantum state of the lattice vector (1, 2) is |0110>, the amplitude is 0.6324555320336759, and the sum of the squares of the amplitudes of the two lattice vector quantum states is 1.

[0070] The preset parameters in the embodiments of the present application can be preset by technicians. To obtain the target lattice vector from the prepared superposition state of lattice vectors, it is necessary to distinguish between the target lattice vector and the non-target lattice vector. The amplitude preparation circuit obtains the first amplitude of the target lattice vector quantum state and the second amplitude of the non-target lattice vector quantum state from the superposition state of the lattice vectors and since the sum of the squares of the first amplitude and the second amplitude is 1.

[0071] Then, the amplitude amplification circuit amplifies the first amplitude of the target lattice vector quantum state to approach 1. When the first amplitude of the target lattice vector quantum state is amplified to approach 1, the second amplitude of the non-target lattice vector quantum state will approach 0. Finally, when performing quantum state measurement, the target lattice vector quantum state can be accurately measured, thus realizing the screening of the target lattice vector from the lattice vectors to be screened.

[0072] In another embodiment of the present application, the amplitude preparation circuit includes a two-norm operator and a data size comparison operator.

[0073] The two-norm operator is used to calculate the two-norm of each lattice vector to be screened.

[0074] Specifically, the two-norm operator includes a square operator and an adder. The square operator is used to square each component of the lattice vector to be screened, and then the adder is used to superimpose the squared operation results of each component.

[0075] In the embodiments of the present application, for a d-dimensional lattice vector U, U can be expressed as U=(u1, u2,..., u d ), and its two-norm calculation can be expressed as:

[0076]

[0077] The first register can be used to store the quantum states corresponding to the respective components u1, u2,..., u of the lattice vector d of the lattice vector.

[0078] In one implementation, each component of the lattice vector U can be converted into a binary number and encoded onto the qubits of the first register.

[0079] For example, if the lattice vector is (3, 2), then in the first register, the lattice vector can be stored as the quantum state |11, 10>, where the component 3 of the lattice vector corresponds to the quantum state |11>, and the component 2 corresponds to the quantum state |10>.

[0080] The second register can be a quantum register for storing the two-norm of the lattice vector, and the initial quantum state of the qubits in the second register is |0>.

[0081] The squaring operator and the division operator act on the second register alternately. The squaring operator is used to perform a squaring operation on the quantum state corresponding to each component of the lattice vector stored in the first register and superimpose the result of the squaring operation on the second register. After each superposition of the result of the squaring operation in the second register and before the next superposition of the result of the squaring operation, the division operator cyclically exchanges the qubits in the second register in the order from the highest bit to the lowest bit times of quantum states, which is used to perform times of division-by-2 operations on the result of the squaring operation already superimposed in the second register.

[0082] For example, for the lattice vector (3, 2), the maximum value of each component of the lattice vector (3, 2) is p = 3.

[0083] The squaring operator acts on the first register and performs a squaring operation on the quantum state |11> corresponding to the component 3, obtaining the result of the squaring operation |01001>. The result of the squaring operation is superimposed on the second register, and the quantum state of the second register is |01001>. Before superimposing the result of the squaring operation of the quantum state |10> corresponding to the component 2 on the second register, the division operator cyclically exchanges the qubits in the second register in the order from the highest bit to the lowest bit times of quantum states, that is, the quantum state |01001> is shifted from left to right in turn, and the last bit on the right is moved to the first bit on the left during the movement, evolving into the quantum state |10100>.

[0084] As Figure 2 shown, Figure 2 is a schematic diagram of a quantum circuit of a two-norm operator provided by an embodiment of the present application. Figure 2 The first register, the second register, and the auxiliary register are shown therein. Among them, the first register is used to store the respective components u0, u1,..., u d , Figure 2 The Sqr shown represents the squaring operator. The squaring operator sequentially performs squaring operations on the respective components u0, u1,..., u d of the lattice vector by means of the auxiliary register and superimposes the results of the squaring operations on the second register, so that the second register stores the operation result of the two-norm of the lattice vector. Figure 2 is a simplified quantum circuit diagram.

[0085] For a more detailed specific structure of the two-norm operator, reference can be made to the Chinese patent document with the application number "202410079345.4".

[0086] The data size comparison operator is used to determine the first amplitude of the target lattice vector quantum state and the second amplitude of the non-target lattice vector quantum state according to the magnitude relationship between the preset parameter and the magnitude of each two-norm.

[0087] Specifically, the data size comparator is used to determine the first amplitude of the target lattice vector quantum state and the second amplitude of the non-target lattice vector quantum state based on the quantum state of the auxiliary qubit When the quantum state of the auxiliary qubit is |1>, it indicates that the two-norm of the target lattice vector is less than the preset parameter, and it is determined that

[0088] is the target lattice vector quantum state, is the target lattice vector, and sinθ is the first amplitude of the target lattice vector quantum state; When the quantum state of the auxiliary qubit is |0>, it indicates that the two-norm of the non-target lattice vector is greater than or equal to the preset parameter, and it is determined that

[0089] is the non-target lattice vector quantum state, is the non-target lattice vector, and cosθ is the second amplitude of the non-target lattice vector quantum state. In the embodiment of the present application, the data size comparison operator is implemented based on the Quantum Fourier Transform (QFT). The data size comparison operator is used to implement the marking and distinction of the target lattice vector quantum state and the non-target lattice vector quantum state in the lattice vector superposition state, so that the amplitude amplification circuit can accurately amplify the amplitude of the target lattice vector quantum state.

[0090] As

[0091] shown, Figure 3 is a schematic quantum circuit diagram of a data size comparison operator provided by an embodiment of the present application. Figure 3 It shows the quantum state |X> corresponding to the two-norm of the lattice vector to be compared and 1 auxiliary qubit with an initial quantum state of |0>. First, a quantum Fourier transform (QFT Figure 3 ) is performed on the register storing the quantum state |X> corresponding to the two-norm and the auxiliary qubit, and then the phase of the quantum Fourier transform result is rotated based on the opposite number (-R) of the preset parameter. Then, an inverse quantum Fourier transform is performed on the quantum states of the register storing the quantum state |X> corresponding to the two-norm and the auxiliary qubit. n+1 At this time, the quantum state of the auxiliary qubit is evolved into |1> +|0> X＜R X≥R ​, which can be used to indicate the magnitude relationship between the two-norm X and the preset parameter R. When the quantum state of the auxiliary bit is |1>, it indicates that the two-norm X is less than the preset parameter R. When the quantum state of the auxiliary bit is |0>, it indicates that the two-norm X is greater than or equal to the preset parameter R.

[0092] Figure 3 The data size comparator shown can also perform a quantum Fourier transform (QFT n ) on the register corresponding to the quantum state |X> of the lattice vector two-norm, then perform a phase rotation on the result of the quantum Fourier transform based on the preset parameter (R), and finally perform an inverse quantum Fourier transform to restore the quantum state of the register corresponding to the quantum state |X> of the lattice vector two-norm.

[0093] The specific implementation manner of the data size comparison operator in the embodiments of the present application can refer to the Chinese patent application document with the application number: "202310623090.9".

[0094] As Figure 4 shown, Figure 4 is a schematic diagram of an amplitude preparation circuit provided by an embodiment of the present application, including a two-norm operator (Norm) that acts on a quantum register storing the lattice vector U to be screened with two auxiliary qubits in the initial state |0>. The operation result of the two-norm operator is It also includes a data size comparison operator (Compare) for comparing with the preset parameter. The initial quantum state of the auxiliary bit aux0 is |0>, and the final state is used to indicate the magnitude relationship with the preset parameter.

[0095] The quantum processor provided by the present application includes an amplitude preparation circuit and an amplitude amplification circuit. The amplitude preparation circuit is used to obtain the first amplitude of the target lattice vector quantum state and the second amplitude of the non-target lattice vector quantum state. Among them, the two-norm of the target lattice vector is less than the preset parameter, and the two-norm of the non-target lattice vector is greater than or equal to the preset parameter. The initial state of the amplitude preparation circuit includes the superposition state of the lattice vector to be screened; the amplitude amplification circuit is used to amplify the first amplitude of the target lattice vector quantum state to approach 1. Through the amplitude preparation circuit, the embodiments of the present application obtain the first amplitude of the target lattice vector quantum state and the second amplitude of the non-target lattice vector quantum state, and then the amplitude amplification circuit can amplify the first amplitude of the target lattice vector with a two-norm less than the preset parameter, which can also amplify the measurement probability of the target lattice vector, so that the target lattice vector can be measured, and thus the target lattice vector with a two-norm less than the preset parameter can be screened by using a quantum computer.

[0096] In another embodiment of the present application, the above amplitude amplification circuit includes a first flipping sub-circuit acting on the auxiliary qubit, which is used to flip the second amplitude of the non-target lattice vector quantum state, so that the quantum state of the auxiliary qubit changes from to

[0097] In the embodiment of the present application, the first flipping sub-circuit can be expressed as:

[0098]

[0099] The first flipping sub-circuit acts on the quantum state of the auxiliary qubit and can be expressed by the following calculation formula:

[0100]

[0101] That is, the quantum state of the auxiliary qubit evolves into the quantum state

[0102] realizing the flipping of the amplitude cosθ of the non-target lattice vector quantum state to -cosθ.

[0103] which is equivalent to the unitary matrix The above first flipping sub-circuit can be decomposed into:

[0104]

[0105] That is, the first flipping sub-circuit includes a Z gate and an RX gate acting on the auxiliary qubit, where the rotation angle of the RX gate is 2π.

[0106] As Figure 5 shown, Figure 5 FIG. is a schematic diagram of the first flipping sub-circuit provided by the embodiment of the present application, where the quantum logic gate Z gate and the rotation logic gate RX gate act on the auxiliary qubit in sequence, and the rotation angle of the RX gate is 2π.

[0107] Furthermore, the above amplitude amplification circuit further includes a second flipping sub-circuit, which is used to flip the first amplitude of the target lattice vector quantum state, so that the quantum state of the auxiliary qubit changes from to

[0108] In the embodiment of the present application, the amplitude amplification circuit includes a second flipping sub-circuit The second flipping sub-circuit S is used to implement the mirror flipping with respect to and the implementation effect is shown by the following calculation formula:

[0109] Among them

[0110]

[0111] S0 represents zero flipping, which is equivalent to the quantum circuit as Figure 6 shown, Figure 6 showing a second flipping sub - circuit including a zero - controlled Z gate and a zero - controlled RX gate, where the rotation parameter of the RX gate is 2π.

[0112] Thus, the amplitude amplification circuit in the embodiments of the present application Among them, is Figure 4 the amplitude preparation circuit as shown.

[0113] The amplitude amplification circuit in the embodiments of the present application needs to act repeatedly for multiple times. According to the quantum calculation formula, the above - mentioned amplitude amplification circuit acts on the auxiliary qubit k times, and the quantum state of the auxiliary qubit evolves into where (2k + 1)θ approaches the target quantum state and the first amplitude sin(2k + 1)θ approaches 1.

[0114] In quantum mechanics, a quantum state is described as a vector, called a quantum state vector or wave function. The magnitude of the quantum state vector represents the probability that the system is in different states, while the measurement probability represents the probability that the system is in different states when a measurement is made.

[0115] The magnitude of the quantum state vector can be represented as a complex number. For a discrete quantum state, such as the spin state of a particle, the quantum state vector can be written as a column vector, where each element corresponds to the amplitude of the system being in a certain specific state. For a continuous quantum state, such as the position state of a particle, the quantum state vector can be written as a function, describing the magnitude of the system being in different positions.

[0116] The measurement probability is calculated from the amplitude of the quantum state vector. According to the rules of quantum mechanics, the measurement probability is equal to the square of the modulus of the amplitude of the quantum state vector. For a discrete quantum state, the measurement probability can be expressed as P = |ψ| 2 , where P is the measurement probability and ψ is the amplitude of the quantum state vector.

[0117] It can be understood that when (2k + 1)θ approaches the first amplitude sin(2k + 1)θ approaches 1, the second amplitude cos(2k + 1)θ approaches 0, and at this time for the quantum superposition state Perform a measurement, and the measurement probability of the target lattice vector quantum state is amplified to 1.

[0118] Among them, the number of iterations k of the amplitude amplification circuit can be obtained by and can be calculated, where N is the solution space, that is, the number of samplings, and M is the number of target lattice vectors.

[0119] In the embodiments of the present application, the amplitude amplification circuit acts k times. Each time it acts, the first amplitude of the target lattice vector quantum state is amplified once. After k times of acting, the first amplitude is amplified to approach 1, so that the measurement probability of the target lattice vector is amplified to approach 1, so that the target lattice vector quantum state can be accurately measured.

[0120] As Figure 7 shown, Figure 7 is a schematic diagram of the quantum circuit of the quantum processor provided by the embodiments of the application. The figure includes an amplitude preparation circuit The circuit in the dashed box represents the amplitude amplification circuit The target lattice vector and the non-target lattice vector can be distinguished through the quantum state of the last auxiliary qubit through amplitude preparation, and the amplitude amplification circuit can amplify the first amplitude of the target lattice vector quantum state to approach 1.

[0121] In another embodiment of the present application, a method for solving the shortest vector is further provided. As Figure 8 shown, the method includes:

[0122] S801. Construct a quantum processor as described in any of the above embodiments; wherein, the initial state of the quantum processor includes a superposition state of the lattice vectors to be screened.

[0123] S802. Run the quantum processor and measure the auxiliary qubits to obtain the quantum state corresponding to the target lattice vector.

[0124] Among them, the target lattice vector includes the vectors among the lattice vectors to be screened whose two-norm is less than a preset parameter.

[0125] In the embodiments of the present application, there are multiple vectors whose two-norm is less than the preset parameter. Running the quantum processor to measure the auxiliary qubits can obtain multiple target lattice vector quantum states.

[0126] S803. Update the quantum state corresponding to the obtained target lattice vector to the initial state of the quantum processor, execute the adjustment rule of the preset parameter, and return to the step of running the quantum processor and measuring the auxiliary bit to obtain the quantum state corresponding to the target lattice vector, until the shortest vector in the lattice vectors to be screened is obtained when the preset parameter is adjusted to the preset value by using the adjustment rule of the preset parameter.

[0127] In the above embodiments, a preset coefficient with a value range of (0, 1) can be used to adjust the magnitude of the preset parameter.

[0128] For example, the preset parameter is R, the preset coefficient is γ, γ ∈ (0, 1). After running the quantum processor once, multiple quantum states of target lattice vectors are obtained. Use γR as the new preset parameter, update the quantum state corresponding to the target lattice vector to the initial state of the quantum processor, run the quantum processor again, screen the lattice vectors with a two-norm less than the preset parameter γR among the multiple target lattice vectors, adjust the preset parameter multiple times. For the i-th run of the quantum processor, use the initial state of the quantum state of the lattice vector with a two-norm less than the preset parameter obtained from the previous measurement, and the preset parameter is γ i+1 R, to obtain the shortest vector in the lattice vectors.

[0129] The iteration number i can be set so that when the preset parameter γ i+1 R is less than or equal to the preset value, stop screening, and determine that the lattice vector with a two-norm less than the preset parameter γ i+1 R at this time is the shortest vector.

[0130] Based on the same inventive concept, an embodiment of the present application also provides a device for solving the shortest vector, as Figure 9 shown. The device includes:

[0131] A construction module 901, configured to construct a quantum processor as described in any of the above embodiments; wherein, the initial state of the quantum processor includes the superposition state of the lattice vectors to be screened;

[0132] A running module 902, configured to run the quantum processor and measure the auxiliary bit to obtain the quantum state corresponding to the target lattice vector; wherein, the target lattice vector includes the vectors with a two-norm less than the preset parameter among the lattice vectors to be screened;

[0133] An update module 903, configured to update the quantum state corresponding to the obtained target lattice vector to the initial state of the quantum processor, execute the adjustment rule of the preset parameter, and return to the step of running the quantum processor and measuring the auxiliary bit to obtain the quantum state corresponding to the target lattice vector, until the shortest vector in the lattice vectors to be screened is obtained when the preset parameter is adjusted to the preset value by using the adjustment rule of the preset parameter.

[0134] Regarding the specific functions and effects of the device implementation for solving the shortest vector, reference may be made to other embodiments of this specification for comparison and explanation, which will not be elaborated here. Each module in the device for solving the shortest vector can be implemented in whole or in part by software, hardware, and their combination. Each of the modules can be embedded in the processor in the computer device in hardware form or be independent of it, or can be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above respective modules.

[0135] Please refer to Figure 10 This embodiment of the specification also provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the method for solving the shortest vector in any of the above embodiments. Please refer to Figure 10 , the computer device can be a classical computer. The computer device can also be a quantum computer.

[0136] This embodiment of the specification also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by the computer, the computer executes the method for solving the shortest vector in any of the above embodiments.

[0137] This embodiment of the specification also provides a computer program product including instructions. When the instructions are executed by the computer, the computer executes the method for solving the shortest vector in any of the above embodiments.

[0138] It can be understood that the specific examples in this specification are only to help those skilled in the art better understand the embodiments of this specification, rather than limiting the scope of this application.

[0139] It can be understood that in various embodiments of this specification, the magnitudes of the serial numbers of the processes do not mean the sequence of execution. The execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this specification.

[0140] It can be understood that the various embodiments described in this specification can be implemented alone or in combination, and this specification does not limit this.

[0141] Unless otherwise specified, all technical and scientific terms used in the embodiments of this specification have the same meanings as those commonly understood by those skilled in the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items. The singular forms "a", "above", and "the" used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise.

[0142] It can be understood that the processor in the embodiments of this specification can be an integrated circuit chip with the ability to process signals. In the implementation process, each step of the above method embodiments can be completed by the integrated logic circuit in the hardware of the processor or instructions in the form of software. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of this specification can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0143] It can be understood that the memory in the embodiments of this specification can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include but not be limited to these and any other suitable types of memory.

[0144] Those of ordinary skill in the art will realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this specification.

[0145] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0146] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be electrical, mechanical, or other forms.

[0147] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, the functional units in each embodiment of this specification can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0149] When the above-described function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this specification. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0150] As described above, the foregoing are only specific embodiments of this specification, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this specification can easily think of changes or substitutions, which should all be covered by the protection scope of this specification. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. A quantum processor for screening target lattice vectors, characterized in that The quantum processor includes an amplitude preparation circuit and an amplitude amplification circuit; The amplitude preparation circuit is used to obtain the first amplitude of the target lattice vector quantum state and the second amplitude of the non-target lattice vector quantum state, where the two-norm of the target lattice vector is less than a preset parameter, the two-norm of the non-target lattice vector is greater than or equal to the preset parameter, and the initial state of the amplitude preparation circuit includes a superposition state of the lattice vectors to be screened; The amplitude amplification circuit is used to amplify the first amplitude of the target lattice vector quantum state to approach 1.

2. The quantum processor according to claim 1, characterized in that, The amplitude preparation circuit includes a two-norm calculator and a data size comparison calculator; The two-norm calculator is used to calculate the two-norm of each lattice vector to be screened and store the calculated two-norm in a second register; The data size comparison calculator is used to determine the first amplitude of the target lattice vector quantum state and the second amplitude of the non-target lattice vector quantum state according to the size relationship between the preset parameter and each two-norm.

3. The quantum processor according to claim 2, characterized in that, The data size comparator is used to determine a first amplitude of the target lattice vector quantum state and a second amplitude of non-target item vector quantum states based on the quantum state of the auxiliary bit and determine a first amplitude of the target lattice vector quantum state and a second amplitude of non-target item vector quantum states When the quantum state of the auxiliary bit is |1>, it indicates that the two-norm of the target lattice vector is less than the preset parameter, and it is determined that is the quantum state of the target lattice vector, is the target lattice vector, and sinθ is the first amplitude of the quantum state of the target lattice vector; When the quantum state of the auxiliary bit is |0>, it indicates that the two-norm of the non-target lattice vector is greater than or equal to the preset parameter, and it is determined that is the quantum state of the non-target lattice vector, is the non-target lattice vector, and cosθ is the second amplitude of the quantum state of the non-target lattice vector.

4. The quantum processor according to claim 3, characterized in that The amplitude amplification circuit includes a first flipping sub-circuit acting on an auxiliary qubit, which is used to flip the second amplitude of the non-target lattice vector quantum state, so that the quantum state of the auxiliary qubit evolves from to 5. The quantum processor according to claim 4, wherein, The amplitude amplification circuit further includes a second flipping sub-circuit for flipping the first amplitude of the target lattice vector quantum state, such that the quantum state of the auxiliary qubit evolves from to 6. The quantum processor according to claim 5, characterized in that, The amplitude amplification circuit acts on the auxiliary bit k times, and the quantum state of the auxiliary bit evolves into where (2k + 1)θ approaches the target quantum state and the first amplitude sin(2k + 1)θ approaches 1.

7. A method for solving the shortest vector, characterized in that, It includes: Construct a quantum processor as described in any one of claims 1-6; wherein, the initial state of the quantum processor includes a superposition state of the lattice vectors to be screened; Run the quantum processor and measure the auxiliary qubits to obtain the quantum state corresponding to the target lattice vector; wherein, the target lattice vector includes the vectors among the lattice vectors to be screened whose two-norm is less than the preset parameter; Update the quantum state corresponding to the obtained target lattice vector to the initial state of the quantum processor, execute the adjustment rule of the preset parameter, and return to execute the step of running the quantum processor and measuring the auxiliary qubits to obtain the quantum state corresponding to the target lattice vector until the shortest vector in the lattice vectors to be screened is obtained when the preset parameter is adjusted to the preset value by using the adjustment rule of the preset parameter.

8. An apparatus for solving the shortest vector, characterized in that, The device includes: A construction module, configured to construct a quantum processor as described in any one of claims 1-6; wherein, the initial state of the quantum processor includes a superposition state of the lattice vectors to be screened; A running module, configured to run the quantum processor and measure the auxiliary qubits to obtain the quantum state corresponding to the target lattice vector; wherein, the target lattice vector includes the vectors among the lattice vectors to be screened whose two-norm is less than the preset parameter; An update module, configured to update the quantum state corresponding to the obtained target lattice vector to the initial state of the quantum processor, execute the adjustment rule of the preset parameter, and return to execute the step of running the quantum processor and measuring the auxiliary qubits to obtain the quantum state corresponding to the target lattice vector until the shortest vector in the lattice vectors to be screened is obtained when the preset parameter is adjusted to the preset value by using the adjustment rule of the preset parameter.

9. A storage medium, characterized in that, A computer program is stored in the storage medium, wherein the computer program is set to execute the method described in claim 7 when running.

10. An electronic device, comprising a memory and a processor, characterized in that, A computer program is stored in the memory, and the processor is set to run the computer program to execute the method described in claim 7.

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