Trigger signal generation method, central control board card and storage medium

Abstract

The embodiment of the invention provides a trigger signal generation method, a central control board card and a storage medium. According to the scheme, when a processing module receives a ready instruction packet which is sent by a first routing board card and carries a thread identifier and a case mask, the processing module sends the case mask to a target thread module matched with the thread identifier; when receiving the case mask, the target thread module updates a target numerical value corresponding to the first routing board card in a ready state value stored in the target thread module, and the ready state value is used for indicating the ready state corresponding to the same quantum computing task of all routing board cards at the current moment; the target thread module generates a first trigger signal when the ready state value of the current moment meets a preset trigger condition, and the preset trigger condition is determined based on the case mask. Through the technical scheme provided by the embodiment of the invention, the trigger signal is accurately and effectively generated in the central control board card, so that a guarantee is provided for parallel execution of a later quantum computing task.

Description

Technical Field

[0001] The present application relates to the field of quantum computing technology, and particularly to a method for generating a trigger signal, a central control board card, and a storage medium. Background Art

[0002] Quantum computing is a computing mode that uses the basic characteristics of quantum mechanics to solve problems. By constructing a quantum physical hardware system that can be precisely operated and running quantum computing software to implement quantum algorithms, computing problems are solved, and the application of quantum computing in specific problems or fields is realized.

[0003] As an important part of a quantum computer, a quantum computing measurement and control system needs to provide corresponding pulse signals for qubits participating in quantum computing during the quantum computing process. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a method for generating a trigger signal, a central control board card, and a storage medium, so as to accurately and effectively generate a trigger signal in the central control board card, thereby providing guarantee for the parallel execution of subsequent quantum computing tasks. The specific technical solutions are as follows:

[0005] The embodiments of the present application provide a method for generating a trigger signal, which is applied to a central control board card in a quantum computing measurement and control system. The central control board card includes a processing module and multiple thread modules. The quantum computing measurement and control system further includes multiple routing board cards, and each routing board card is respectively communicatively connected to the processing module through different transmission paths. The method includes:

[0006] When the processing module receives a ready instruction packet carrying a thread identifier and a chassis mask sent by a first routing board card, it sends the chassis mask to a target thread module that matches the thread identifier.

[0007] When the target thread module receives the chassis mask, it updates a target value corresponding to the first routing board card in a ready state value stored in itself. The ready state value is used to indicate the ready state of all routing board cards for the same quantum computing task at the current moment.

[0008] When the ready state value of the target thread module at the current moment meets a preset trigger condition, a first trigger signal is generated. The preset trigger condition is determined based on the chassis mask.

[0009] The embodiments of the present application further provide a central control board card. The central control board card includes a processing module and multiple thread modules. The central control board card and multiple routing board cards form a quantum computing measurement and control system. Each routing board card is respectively communicatively connected to the processing module through different transmission paths;

[0010] The processing module is configured to send the chassis mask to a target thread module that matches the thread identifier when receiving a ready instruction packet carrying a thread identifier and a chassis mask sent by a first routing board.

[0011] The target thread module is configured to update a target value corresponding to the first routing board in a ready state value stored therein when receiving the chassis mask, where the ready state value is used to indicate the ready state of all routing boards for the same quantum computing task at the current moment; and generate a first trigger signal when the ready state value at the current moment meets a preset trigger condition, where the preset trigger condition is determined based on the chassis mask.

[0012] An embodiment of the present application further provides a central control board, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus;

[0013] The memory is used to store a computer program;

[0014] The processor is configured to implement the steps of the trigger signal generation method described in any one of the above when executing the program stored on the memory.

[0015] An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program implements the steps of the trigger signal generation method described in any one of the above when executed by a processor.

[0016] An embodiment of the present application further provides a computer program product containing instructions, which when running on a computer, causes the computer to execute the trigger signal generation method described in any one of the above.

[0017] An embodiment of the present application further provides a quantum computing measurement and control system, where the quantum computing measurement and control system includes a central control board, and the central control board implements the trigger signal generation method described in any one of the above.

[0018] An embodiment of the present application further provides a quantum computer, where the quantum computer includes a quantum computing measurement and control system, and the quantum computing measurement and control system implements the trigger signal generation method described in any one of the above.

[0019] Advantageous effects of the embodiments of the present application:

[0020] In the technical solution provided by the embodiment of the present application, for each ready instruction packet sent by a routing board, after receiving the ready instruction packet, the processing module in the central control board can send the chassis mask in the ready instruction packet to the target thread module according to the thread identifier in the ready instruction packet, so that after the target thread module updates the ready state value stored in itself, it determines whether the updated ready state value meets the preset trigger condition determined based on the chassis mask, and thus generates a first trigger signal when the preset trigger condition is met.

[0021] Compared with the way that the central control board directly generates a trigger signal when receiving a trigger instruction packet during the execution of a single quantum computing task, considering the situation that in the process of parallel execution of multiple quantum computing tasks, a quantum computing task needs to call multiple routing boards and the lower-level boards connected by the routing boards in communication, each thread module in the above central control board can generate a first trigger signal only when the ready state value at the current moment meets the preset trigger condition determined according to the received chassis mask. This enables the central control board to generate a trigger signal only when the ready states of the routing boards required for the execution of each quantum computing task meet the preset trigger condition, realizing the application of multi-thread technology in the quantum computing measurement and control system, which effectively ensures the effectiveness and accuracy of the generation of the first trigger signal corresponding to each quantum computing task, and thus provides a guarantee for the parallel execution of subsequent quantum computing tasks.

[0022] Of course, it is not necessary for any product or method implementing the present application to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a schematic structural diagram of an existing quantum computing measurement and control system;

[0025] Figure 2 It is the first flowchart of the trigger signal generation method provided by the embodiment of the present application;

[0026] Figure 3 It is a schematic structural diagram of a quantum computing measurement and control system provided by the embodiment of the present application;

[0027] Figure 4 It is a schematic diagram of a ready instruction packet provided by the embodiment of the present application;

[0028] Figure 5 The second schematic flow chart of the trigger signal generation method provided by the embodiment of the present application;

[0029] Figure 6 The third schematic flow chart of the trigger signal generation method provided by the embodiment of the present application;

[0030] Figure 7 The fourth schematic flow chart of the trigger signal generation method provided by the embodiment of the present application;

[0031] Figure 8 The fifth schematic flow chart of the trigger signal generation method provided by the embodiment of the present application;

[0032] Figure 9 A schematic diagram of a second trigger signal provided by the embodiment of the present application;

[0033] Figure 10 The sixth schematic flow chart of the trigger signal generation method provided by the embodiment of the present application;

[0034] Figure 11 The first schematic structural diagram of the central control board card provided by the embodiment of the present application;

[0035] Figure 12 The second schematic structural diagram of the central control board card provided by the embodiment of the present application. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0037] As Figure 1 shown, Figure 1 is a schematic structural diagram of an existing quantum computing measurement and control system. In the Figure 1 shown quantum computing measurement and control system, it includes: a central control board card, a routing board card, and a lower-layer board card. When performing quantum computing using qubits, the quantum computing measurement and control system needs to provide corresponding pulse signals for the qubits participating in quantum computing. For example, the quantum computing measurement and control system can provide a pulse modulation signal, a flux modulation signal, etc. corresponding to the qubits.

[0038] In the above process of generating the pulse signal, the routing board and the lower-layer board successively load the relevant task data required for quantum computing. After completing the loading of the task data, the lower-layer board sends a ready signal to the routing board. After receiving this ready signal, the routing board sends a ready instruction to the central control board. Once the central control board receives the ready instruction sent by the routing board, the central control board generates a trigger signal.

[0039] The central control board sends the generated trigger signal to the routing board. After receiving this trigger signal, the routing board also generates a trigger signal and sends this trigger signal to the lower-layer board. When the lower-layer board receives the trigger signal sent by the routing board, it generates the pulse signal required for the execution of the quantum computing task, realizes the generation of the pulse signal, and ensures the normal progress of the quantum computing task.

[0040] In the above central control board, the generation of the trigger signal is based on whether it receives the ready instruction sent by the routing board. That is, as long as the central control board receives the ready instruction, it will generate a trigger signal. This process is only applicable to the execution process of a single quantum computing task. With the application of multi-threading technology in the process of quantum computing, the above method for generating the trigger signal in the central control board will no longer be applicable.

[0041] To solve the problems in the related technology, an embodiment of the present application provides a method for generating a trigger signal. As Figure 2 shown, Figure 2 is the first schematic flowchart of the method for generating a trigger signal provided by an embodiment of the present application. This method is applied to the central control board in a quantum computing measurement and control system. The central control board includes a processing module and multiple thread modules. The quantum computing measurement and control system further includes multiple routing boards, and each routing board is respectively communicatively connected to the processing module through different transmission paths. In the Figure 2 shown method, the following steps are included.

[0042] Step S201, when the processing module receives a ready instruction packet carrying a thread identifier and a chassis mask sent by the first routing board, it sends the chassis mask to the target thread module that matches the thread identifier.

[0043] Step S202, when the target thread module receives the chassis mask, it updates the target value corresponding to the first routing board in the ready state value stored in itself. The ready state value is used to indicate the ready state of all routing boards for the same quantum computing task at the current moment.

[0044] Step S203, when the ready state value of the target thread module at the current moment meets a preset trigger condition, the target thread module generates a first trigger signal, and the preset trigger condition is determined based on the chassis mask.

[0045] As Figure 3 shown,Figure 3 This is a schematic structural diagram of the quantum computing measurement and control system provided by the embodiments of the present application. In Figure 3 the shown quantum computing measurement and control system, it includes a central control board, a routing board, and a lower-layer board. Among them, the central control board may include a processing module and multiple thread modules, such as Figure 3 the thread module 1 - thread module 5 shown. In addition, the number of routing boards and lower-layer boards in the quantum computing measurement and control system may be multiple, such as Figure 3 the routing board 1 - routing board 3, and the lower-layer board 1 - lower-layer board 3 shown.

[0046] In the embodiments of the present application, the number of the routing boards, lower-layer boards, and the thread modules in the central control board included in the above Figure 3 shown quantum computing measurement and control system can be set according to the number of qubits in the quantum chip or user requirements, etc. For example, in the quantum computing measurement and control system corresponding to a 72-qubit quantum computer, the number of the above routing boards and lower-layer boards can be 3, and the number of thread modules in the central control board can be 5. Here, the number of the routing boards, lower-layer boards, and the thread modules in the central control board included in the above quantum computing measurement and control system is not specifically limited. For ease of understanding, the following only takes the Figure 3 shown quantum computing measurement and control system as an example for illustration, without any limiting effect.

[0047] Other modules may also be included in the above central control board. For example, a parsing module that connects the processing module to each routing board. In addition, multiple thread modules may also be included in each of the above routing boards. The thread modules in the routing board and the thread modules in the central control board are both matched with the threads required for the lower-layer board to execute quantum tasks. For example, they have the same identification information, etc. Here, the various modules included in the above central control board and routing board are not specifically limited.

[0048] In the above quantum computing measurement and control system, each routing board is respectively communicatively connected to the processing module in the central control board through different transmission paths. For example, Figure 3 the routing board 1 - routing board 3 shown are respectively communicatively connected to the processing module through different transmission paths. In addition, the routing board is communicatively connected to the lower-layer board and is in one-to-one correspondence. For example, Figure 3 the routing board 1 is communicatively connected to the lower-layer board 1, the routing board 2 is communicatively connected to the lower-layer board 2, and the routing board 3 is communicatively connected to the lower-layer board 3.

[0049] In the embodiment of the present application, the physical device of the above quantum computing measurement and control system may be a cabinet, and the above central control board, each routing board, and each lower-level board may be represented as each chassis included in the cabinet. The processing module and the thread module in the above central control board may be deployed on the same physical device.

[0050] In the chassis corresponding to each of the above lower-level boards, different types and different numbers of boards may be included. For example, the lower-level boards may include: Arbitrary Waveform Generator (AWG) boards, Analog Digital Digital Analog (ADDA) boards, Digital-to-Analog Converter (DAC) boards, etc. Different types of boards may be used to generate different types of pulse signals. Here, the data and types of the boards included in the lower-level boards are not specifically limited.

[0051] Through the above Figure 2 method shown, for each ready instruction packet sent by the routing board, after receiving the ready instruction packet, the processing module in the central control board may send the chassis mask in the ready instruction packet to the target thread module according to the thread identifier in the ready instruction packet, so that after the target thread module updates its stored ready state value, it determines whether the updated ready state value meets the preset trigger condition determined based on the chassis mask, and thus generates a first trigger signal when the preset trigger condition is met.

[0052] Compared with the method of directly generating a trigger signal by the central control board when receiving a trigger instruction packet during the execution of a single quantum computing task, considering the situation that in the process of parallel execution of multiple quantum computing tasks, a quantum computing task needs to call multiple routing boards and the lower-level boards connected by the routing boards in communication, each thread module in the above central control board can generate a first trigger signal only when the ready state value at the current moment meets the preset trigger condition determined according to the received chassis mask. This enables the central control board to generate a trigger signal only when the ready states of the routing boards required for the execution of each quantum computing task meet the preset trigger condition, realizing the application of multi-thread technology in the quantum computing measurement and control system, which effectively ensures the effectiveness and accuracy of the generation of the first trigger signal corresponding to each quantum computing task, thus providing a guarantee for the parallel execution of subsequent quantum computing tasks.

[0053] The embodiments of the present application will be described below through specific examples.

[0054] Regarding the above step S201, that is, when the processing module receives the ready instruction packet carrying the thread identifier and the chassis mask sent by the first routing board, it sends the chassis mask to the target thread module matching the thread identifier.

[0055] For each routing board in the above quantum computing measurement and control system, when the routing board receives the ready instruction sent by the lower-layer board to which it is communicatively connected, it can send a ready instruction packet to the processing module in the central control board. The ready instruction packet carries a thread identifier and a chassis mask. Among them, the thread identifier is used to indicate the thread required for the lower-layer board to execute the quantum computing task, and the chassis mask is the mask information corresponding to the routing board required to trigger the execution of the quantum computing task. The processing module in the central control board can receive the ready instruction packets sent by each routing board.

[0056] In the embodiment of the present application, the thread identifier in the above ready instruction packet is only the identification information corresponding to one thread.

[0057] In addition, since the above lower-layer boards include different types and different numbers of boards, during the execution of a certain quantum computing task, it may not be necessary to call all the boards in the lower-layer board. That is, some of the boards in the lower-layer board can already support the execution of a quantum computing task, while the remaining boards can be used for the execution of other quantum computing tasks. When applying the multi-thread technology to the quantum computing measurement and control system, all the boards in a certain lower-layer board can be applied to the execution of one or more quantum computing tasks, improving the effective utilization rate of the lower-layer board while ensuring the parallel execution of multiple quantum computing tasks. Correspondingly, the routing board communicatively connected to the lower-layer board can be used to trigger the execution of one or more quantum computing tasks. At this time, the chassis mask in the above ready instruction packet can include the effective mask information of the chassis corresponding to one or more routing boards. For the sake of understanding, the following only takes the case where the chassis mask includes the effective mask information of the chassis corresponding to multiple routing boards as an example for illustration, without any limiting effect.

[0058] In an alternative embodiment, the above central control board may further include a parsing module (the above Figure 3(not shown in the figure), the parsing module is used to connect the processing module and each routing board. For each routing board, the routing board can send the above-mentioned ready instruction packet to the parsing module in the form of a serial data stream, and one or more ready instruction packets can be included in the serial data stream. After receiving the serial data stream sent by the routing board, the parsing module can parse the serial data stream to obtain each ready instruction packet in the serial data stream, and forward the parsed ready instruction packet to the processing module. Therefore, the processing module in the above-mentioned central control board can receive one or more ready instruction packets sent by the routing board at the same time. The parsing process of the ready instruction packet in the serial data stream by the parsing module will not be specifically described here.

[0059] When the processing module in the central control board receives the ready instruction packet sent by any routing board (denoted as the first routing board), it can obtain the thread identifier and chassis mask carried in the ready instruction packet from the ready instruction packet. The processing module can look up the thread module that matches the thread identifier according to the thread identifier as the target thread module. The processing module can send the chassis mask in the ready instruction packet to the target thread module.

[0060] The above-mentioned first routing board can be any one of the above-mentioned multiple routing boards. The processing module can receive one or more ready instruction packets sent by the routing board at the same time. For the sake of understanding, the following only takes the case where the processing module receives the ready instruction packet sent by one routing board as an example for illustration.

[0061] In the embodiment of the present application, the above-mentioned ready instruction packet can be as Figure 4 shown Figure 4 which is a schematic diagram of the ready instruction packet provided by the embodiment of the present application. In Figure 4 the shown ready instruction packet, it includes a frame header, a thread identifier, a chassis mask, and a frame tail. The data amounts corresponding to the thread identifier and the chassis mask in the ready instruction packet are both fixed data amounts.

[0062] For example, when the number of thread modules in the above-mentioned central control board is 5, if the thread identifier in the above-mentioned ready instruction packet is represented by a binary number, the data amount of the thread identifier can be 4 bits (bit). When the number of routing boards in the above-mentioned quantum computing measurement and control system is 3, if the chassis mask in the above-mentioned ready instruction packet is represented by a binary number, the data amount of the chassis mask can be any value greater than or equal to 3 bits, such as 3 bit, 4 bit, 8 bit, etc.

[0063] In an optional embodiment, after receiving the ready instruction packet, the above-mentioned processing module may obtain the thread identifier and the chassis mask from the ready instruction packet respectively according to the fixed data volume corresponding to the above-mentioned thread identifier and the chassis mask. The process of obtaining the thread identifier and the chassis mask in the ready instruction packet will not be specifically described here.

[0064] In the embodiments of the present application, the data volumes of the thread identifier and the chassis mask in the above-mentioned ready instruction may be set according to the number of all threads required for the lower-layer board to execute the quantum computing task, the number of routing boards, the representation form of the thread identifier / routing board, and user requirements, etc. Here, the data volumes corresponding to the thread identifier and the chassis mask in the above-mentioned ready instruction packet are not specifically limited.

[0065] Regarding the above-mentioned step S202, that is, when the target thread module receives the chassis mask, it updates the target value corresponding to the first routing board in the ready state value stored by itself. The ready state value is used to indicate the ready state of all routing boards for the same quantum computing task at the current moment.

[0066] In the embodiments of the present application, during the execution of the quantum computing task, each thread is only used for the execution of one quantum computing task at a time. Since each thread module included in the above-mentioned central control board and each thread module in the routing board match the threads required for the lower-layer board to execute the quantum computing task, therefore, when a certain thread is applied to the execution process of a certain quantum computing task, correspondingly, the thread module in the routing board that matches it and the thread module in the central control board that matches it will both be applied to the execution process of this quantum computing task. In each thread module included in the central control board, a ready state value indicating the ready state of all routing boards for the same quantum computing task at the current moment may be pre-stored.

[0067] In an optional embodiment, the above-mentioned ready state value includes a target value corresponding to each routing board, and the initial value of the target value is the first value.

[0068] Each target value in the above-mentioned ready state value is used to indicate the ready state of the routing board corresponding to a certain quantum computing task. Among them, the ready state includes a first state and a second state. Among them, the first state indicates that the routing board is not ready, and the second state is used to indicate that the routing board is already ready. The value indicating the first state in the ready state value is the above-mentioned valid mask information.

[0069] The above-mentioned first state may be represented as the above-mentioned first value, such as the value 0; the above-mentioned second state may be represented as the second value, such as the value 1.

[0070] For ease of understanding, in combination with the above Figure 3Taking the quantum computing measurement and control system shown as an example for illustration. Since there are three routing boards in the quantum computing measurement and control system, therefore, the ready state values stored in each of the above thread modules can be represented by 3-bit binary numbers. Now assume that the above first value is 0, then the initial ready state value can be represented as 000. That is Figure 3 None of the routing boards 1 - 3 shown are ready.

[0071] In the embodiments of the present application, the amount of data included in the ready state value stored in the above thread module can be set according to the number of routing boards in the above quantum computing measurement and control system, or the amount of data included in the chassis mask in the above ready instruction packet. Here, no specific limitation is made on the amount of data included in the above ready state value.

[0072] After the above target thread module receives the chassis mask sent by the processing module, it can determine the target value corresponding to the above first routing board in the ready state value stored by itself, and update the target data. The specific update method can be seen in the following description and will not be elaborated here.

[0073] In an alternative embodiment, when the target thread module receives a chassis mask for the first time, it can cache the received chassis mask.

[0074] Regarding the above step S203, that is, when the ready state value of the target thread module at the current moment meets the preset trigger condition, a first trigger signal is generated, and the preset trigger condition is determined based on the chassis mask.

[0075] In the embodiments of the present application, when the target thread module receives the above chassis mask for the first time, it can determine the preset trigger condition according to the chassis mask. After the target thread module updates the ready state value stored by itself, it can determine whether the ready state value at the current moment meets the preset trigger condition. The description of the preset trigger condition can be seen in the following description and will not be specifically described here.

[0076] If the ready state value at the current moment meets the above preset trigger condition, the target thread module can generate a first trigger signal. This first trigger signal is used to trigger the routing board to start the execution process of the quantum computing task, that is, it is used to trigger the routing board to generate a trigger signal sent to the lower-level board of the communication connection.

[0077] In an alternative embodiment, if the ready state at the current moment does not meet the above preset trigger condition, the target thread module can determine that all the routing boards for starting the execution of a certain quantum computing task are not completely in the above second state. At this time, the target thread module can do nothing, that is, the target thread module will not generate the above first trigger signal.

[0078] In an alternative embodiment, according to the above Figure 2 method shown, the embodiment of the present application further provides a method for generating a trigger signal. As Figure 5 shown, Figure 5 FIG. is the second process schematic diagram of the trigger signal generation method provided by the embodiment of the present application. In Figure 5 the method shown, the above step S201 can be refined into the following steps, namely step S2011-step S2013.

[0079] Step S2011, the processing module receives a ready instruction packet sent by the first routing board, and the ready instruction packet carries a thread identifier and a chassis mask.

[0080] Step S2012, the processing module selects, according to the module identifier corresponding to each thread module, a thread module whose module identifier matches the thread identifier as the target thread module.

[0081] In the embodiment of the present application, each thread module in the above central control board has a corresponding module identifier. For each thread module in the above central control board, there is a thread that matches the thread module among all the threads for which the lower-layer board executes the quantum computing task, which can be specifically expressed as: the thread identifier corresponding to the thread matches the module identifier corresponding to the thread module.

[0082] The above processing module may record the module identifier corresponding to each thread module. When the processing module receives the ready instruction packet sent by the first routing board, it can obtain the thread identifier and the chassis mask in the ready instruction packet. The processing module may match the thread identifier in the ready instruction packet with the module identifiers corresponding to the respective thread modules it records, and determine the thread module whose module identifier matches the thread identifier as the target thread module.

[0083] In an alternative embodiment, when the representation method of the module identifier corresponding to the above thread module is the same as the representation method of the above thread identifier, the matching of the module identifier and the thread identifier can be expressed as: the module identifier is the same as the thread identifier.

[0084] For ease of understanding, the above thread identifier 0010 is taken as an example for illustration. When determining the above target thread module, the processing module may select the thread module with the module identifier 0010 as the target thread module.

[0085] In another alternative embodiment, when the representation method of the module identifier corresponding to the above thread module is different from the representation method of the above thread identifier, the matching of the module identifier and the thread identifier can be expressed as: the meaning or value represented by the module identifier is the same as that represented by the thread identifier.

[0086] For ease of understanding, the module identifiers corresponding to the above thread modules are represented as decimal numbers 1, 2, 3... and the thread identifiers in the above ready instruction packet are represented as hexadecimal numbers as an example for illustration. Now assume that the thread identifier in the above ready instruction packet is still the above 0010. When the processing module obtains the thread identifier 0010, it can determine that the decimal number corresponding to the thread identifier 0010 is 2. At this time, the processing module can determine the thread module with the module identifier 2 as the target thread module.

[0087] In the embodiments of the present application, there is no specific limitation on the representation method of the matching situation between the above thread identifier and the module identifier.

[0088] Step S2013, the processing module sends the chassis mask to the target thread module.

[0089] Through the above steps S2011 - step S2013, when the processing module receives the ready instruction packet sent by the routing board, by matching the thread identifier in the ready instruction packet with the corresponding module identifiers of each thread module, the target thread module can be accurately determined, so as to ensure that the chassis mask in each ready instruction packet can be accurately sent to the thread module matching the thread identifier, improving the accuracy of the determined target thread module, and further providing guarantee for the generation of the trigger signal in the later stage.

[0090] In an alternative embodiment, according to the above Figure 2 shown method, the embodiments of the present application also provide a method for generating a trigger signal. As Figure 6 shown, Figure 6 This is the third process schematic diagram of the method for generating a trigger signal provided by the embodiments of the present application. In the Figure 6 shown method, the above step S202 can be refined into the following steps, namely step S2021 - step S2022.

[0091] Step S2021, when the target thread module receives the chassis mask, it determines the first routing board that sends the ready instruction packet according to the path identifier of the corresponding transmission path of the ready instruction packet.

[0092] In the embodiments of the present application, when the processing module receives the ready instruction packet sent by the first routing board, since the transmission paths between the processing module and each routing board are different, the processing module can accurately identify from which transmission path the ready instruction packet it receives comes. That is, the processing module can accurately identify the transmission path corresponding to each ready instruction packet. Correspondingly, each thread module in the central control board can learn from the processing module the transmission path corresponding to the ready instruction packet, so as to determine the routing board that sends the ready instruction packet.

[0093] In an alternative embodiment, for each transmission path between a routing board and a thread module, there is a corresponding path identifier for this transmission path. When the target thread module receives the chassis mask sent by the processing module, it can obtain the path identifier of the transmission path corresponding to the ready instruction packet carrying the chassis mask from the thread module. The target thread module can determine the routing board (i.e., the first routing board mentioned above) that sent the ready instruction packet according to this path identifier.

[0094] In an alternative embodiment, the association relationship between the path identifier and the routing board can be pre-stored in the processing module. After the target thread module learns the path identifier of the transmission path corresponding to the ready instruction packet, it can determine the routing board associated with this path identifier as the first routing board according to the association relationship stored in the processing module.

[0095] Step S2022: The target thread module updates the target value corresponding to the first routing board in the ready state value stored by itself.

[0096] In an alternative embodiment, the above step S2022, that is, the target thread module updates the target value corresponding to the first routing board in the ready state value stored by itself, can be specifically expressed as:

[0097] The target thread module updates the target value corresponding to the first routing board in the ready state value stored by itself from the first value to the second value.

[0098] For ease of understanding, the above is illustrated with the first value being 0, the second value being 1, and the initial ready state value being 000.

[0099] Now assume that in the value 000, from the high bit to the low bit are the target data corresponding to the above Figure 3 routing board 3, routing board 2, and routing board 1. When the target thread module receives the chassis mask sent by the processing module, if the target thread module determines that the first routing board is the Figure 3 shown routing board 1, then the target thread module can update the 0 at the lowest bit in the ready state value it stores to 1, that is, update the ready state value from 000 to 001.

[0100] Through the above steps S2021 - S2022, the target thread module can accurately determine the routing board card that sends the ready instruction packet according to the path identifier of the corresponding transmission path of the ready instruction packet, thereby updating the target value corresponding to this routing board card in the ready state value, realizing the update of the ready state value stored in the target thread module with the chassis mask it receives, enabling the ready state value to be updated as the ready state of the routing board card changes, ensuring the accuracy and timeliness of the update of the ready state value, and thus ensuring the accuracy of the trigger signal generated based on the ready state value at the current moment.

[0101] In the above Figure 6 In the illustrated embodiment, only the update of the ready state value by the target thread module according to the transmission path of the ready instruction packet is taken as an example for illustration. In addition to this, after the above processing module identifies the transmission path of the ready instruction packet, it can also directly determine the first routing board card corresponding to this transmission path, that is, determine the routing board card that sends the ready instruction packet. The target thread module can directly update the target value corresponding to this routing board card in the ready state value according to the routing board card that sends the ready instruction packet. Here, the update method of the above ready state value is not specifically limited.

[0102] In an optional embodiment, according to the above Figure 2 method shown, the embodiments of the present application also provide a method for generating a trigger signal. As Figure 7 shown, Figure 7 This is the fourth flowchart of the method for generating a trigger signal provided by the embodiments of the present application. This method includes the following steps.

[0103] Step S701, when the processing module receives a ready instruction packet carrying a thread identifier and a chassis mask sent by the first routing board card, it sends the chassis mask to the target thread module that matches the thread identifier.

[0104] Step S702, when the target thread module receives the chassis mask, it updates the target value corresponding to the first routing board card in the ready state value stored by itself. The ready state value is used to indicate the ready state of all routing board cards for the same quantum computing task at the current moment.

[0105] The above steps S701 - S702 are the same as the above steps S201 - S202.

[0106] Step S703, the target thread module obtains the ready state value stored at the current moment as the target ready state value.

[0107] Step S704, the target thread module compares the target ready state value with the chassis mask.

[0108] In this step, after obtaining the above-mentioned target ready state value, the target thread module determines whether the target ready state value meets the preset matching condition by comparing the target ready state value with the chassis mask it receives.

[0109] In an optional embodiment, the above-mentioned preset matching condition can be expressed as: the ready state value at the current moment (i.e., the target ready state value) matches the chassis mask.

[0110] In the embodiment of the present application, for each thread module included in the central control board, from the moment when the thread module first receives a certain chassis mask to the moment when the thread module generates the first trigger signal, the chassis masks received by the thread module are the same. That is, during this period, the chassis masks in the ready instruction packets carrying the same thread identifier received by the thread module are the same, and the difference lies in the routing board cards that send the ready instruction packets, that is, the transmission paths for transmitting the ready instruction packets are different.

[0111] Step S705, when the target ready state value is the same as the chassis mask, the target thread module determines that the target ready state value meets the preset matching condition.

[0112] Step S706, when the target ready state value is different from the chassis mask, the target thread module determines that the target ready state value does not meet the preset matching condition.

[0113] In the embodiment of the present application, since the above-mentioned chassis mask is the mask information corresponding to the routing board card required to trigger the execution of the quantum computing task, and each target value in the above-mentioned ready state value is updated after receiving the ready instruction packet sent by the corresponding routing board card, therefore, when the above-mentioned target ready state value is the same as the chassis mask, the target thread module can determine that it has received all the ready instruction packets sent by the routing board card required for the thread corresponding to the above-mentioned thread identifier to execute the quantum computing process; when the above-mentioned target ready state value is different from the chassis mask, the target thread module can determine that it has not received all the ready instruction packets sent by the routing board card required for the thread corresponding to the above-mentioned thread identifier to execute the quantum computing process.

[0114] In an optional embodiment, if the above-mentioned target ready state value is the same as the chassis mask, the target thread module can determine that the target ready state value matches the chassis mask. At this time, the target thread module can determine that the target ready state value meets the above-mentioned preset matching condition. That is, the ready state value at the current moment meets the preset matching condition.

[0115] In another alternative embodiment, if the above-mentioned target ready state value is different from the above-mentioned chassis mask, the target thread module may determine that the target ready state does not match the chassis mask. At this time, the target thread module may determine that the target ready state value does not meet the above-mentioned preset matching condition. That is, the ready state value at the current moment does not meet the preset matching condition.

[0116] For ease of understanding, take the chassis mask in the above-mentioned ready instruction packet as 011 as an example for illustration. Now assume that the data volume and format corresponding to the ready state value stored in the thread module are the same as those of the chassis mask.

[0117] When the ready state value stored in the above-mentioned target thread module is 011, the target thread module may determine that this ready state value meets the above-mentioned preset matching condition. When the ready state value stored in the above-mentioned target thread module is 001 or 010, the target thread module may determine that this ready state value does not meet the preset matching condition.

[0118] In the embodiment of the present application, the target thread module can determine whether the ready state value at the current moment meets the preset matching condition by comparing the ready state value currently stored in itself with the received chassis mask, so as to determine whether the target thread module has received the ready instruction packet sent by each routing board required for the execution of the quantum computing task. This enables the target thread module to generate the first trigger signal only when each routing board required for the execution of the quantum computing task is ready, thereby triggering the operation of the routing board, ensuring the accuracy of the generation of the first trigger signal corresponding to each quantum computing task execution, and further providing guarantee for the parallel execution of multiple quantum computing tasks.

[0119] The above steps S705 and S706 are the steps executed respectively when the comparison result between the target ready state value and the chassis mask is different. Here, the execution of the above steps S705 and S706 is not specifically limited.

[0120] Step S707, when the ready state value of the target thread module at the current moment meets the preset trigger condition, the target thread module generates a first trigger signal, and the preset trigger condition is determined based on the chassis mask.

[0121] The above step S707 is the same as the above step S203.

[0122] In the above Figure 7 In the shown embodiment, the above-mentioned preset matching condition, that is, the ready state value at the current moment and the chassis mask are expressed as: the ready state value at the current moment is the same as the received chassis mask. In addition, according to the different representations of the ready state value stored in the above-mentioned thread module and the above-mentioned chassis mask, the representation of the above-mentioned preset matching condition will also be different.

[0123] For ease of understanding, in combination with the above Figure 3 , taking the updated target ready state value of 011 as an example for illustration. Now assume that the data volume and format corresponding to the ready state value stored in the thread module are different from the chassis mask. For example, the chassis mask is 4-bit binary data, where the lower three bits respectively correspond to Figure 3 the routing board 3, routing board 2, and routing board 1 shown in

[0124] When the chassis mask is 0011, the target thread module can determine that the ready state value meets the above preset matching condition. When the chassis mask is other values than 0011, such as 0001, the target thread module can determine that the ready state value does not meet the above preset matching condition.

[0125] In the embodiments of the present application, the matching situation between the ready state value at the current moment and the chassis mask is not specifically limited.

[0126] In an optional embodiment, according to the method shown in the above Figure 2 , the embodiments of the present application further provide a trigger signal generation method. As shown in Figure 8 , Figure 8 is the fifth process schematic diagram of the trigger signal generation method provided by the embodiments of the present application. The following steps are added to the method shown in Figure 8 , that is, step S204 - step S205.

[0127] Step S204, the target thread module sends a first trigger signal to the processing module.

[0128] In the embodiments of the present application, since the number of ready instruction packets received by the processing module at the same moment can be one or more, therefore, when the processing module receives multiple ready instruction packets at the same moment, the thread identifiers carried in each ready instruction packet can be the same or different. Correspondingly, for each thread module in the central control board, the processing module can send multiple chassis masks to the thread module at the same time, and the values corresponding to each chassis mask are the same, but the ready instruction packets are transmitted from different transmission paths.

[0129] In addition, since the above first trigger signal is generated when the ready state value at the current moment matches the chassis mask, and the update of the ready state value is affected by the ready instruction packets received by the processing module, therefore, the number of thread modules that generate the first trigger signal at the same time can be one or more. Here, the number of thread modules that generate the first trigger signal at the same time is not specifically limited.

[0130] Step S205: The processing module generates a second trigger signal including the mask information corresponding to each thread module based on the first trigger signals received within the same time period, and sends the second trigger signal to multiple routing boards, so that the multiple routing boards trigger the execution of the quantum computing task based on the second trigger signal.

[0131] In the embodiments of the present application, the number of thread modules sending the first trigger signal at the same time can be one or more, and the number of first trigger signals received by the processing module at the same time can be one or more.

[0132] After receiving the first trigger signal sent by the target thread module, the processing module can generate a second trigger signal according to the first trigger signals received within the same time period. The second trigger signal includes the mask information corresponding to each thread module. The mask information can be a sequence composed of a third value and / or a fourth value. Wherein, the third value can be 1, and the fourth value can be 0.

[0133] For ease of understanding, taking Figure 9 as an example for illustration. Figure 9 This is a schematic diagram of the second trigger signal provided by the embodiments of the present application.

[0134] In Figure 9 the second trigger signal shown, it includes the mask information corresponding to each thread in the module, that is, 10011. The mask information includes a 5-bit binary number, which corresponds to the thread modules 1 - 5 shown from low to high bits respectively. Among them, the value 1 (i.e., the above-mentioned third value) indicates that the processing module receives the first trigger signal sent by the corresponding thread module within a time period; the value 0 (i.e., the above-mentioned fourth value) indicates that the processing module does not receive the first trigger signal sent by the corresponding thread module within a time period. Figure 3 In the embodiments of the present application, the above-mentioned each time period can be determined according to the synchronization pulse in the processing module. Here, the duration corresponding to the above time period is not specifically limited.

[0135] After generating the above second trigger signal, the processing module can send the second trigger signal to the above-mentioned multiple routing boards. That is, send the second trigger signal to each routing board.

[0136] After receiving the above second trigger signal, each routing board will generate a third trigger signal according to the mask information in the second trigger signal and its own loading state, and send the third trigger signal to the lower-layer board connected to it. When the lower-layer board receives the third trigger signal, it can generate the pulse signal required for the quantum computing task. The generation process of the third trigger signal is not specifically described here.

[0137] ​

[0138] In an embodiment of the present application, when the mask information corresponding to multiple thread modules in the above first trigger information is a third value, the processing modules in the routing board card that are in the loading state accordingly will generate corresponding third trigger signals, that is, multiple third trigger signals will be generated. Correspondingly, multiple lower-level board cards will generate pulse signals required for the execution of multiple quantum computing tasks, thereby promoting the parallel execution of multiple quantum computing tasks and improving the quantum computing rate.

[0139] Through the above steps S204 - S205, the thread module sends the first trigger signal to the processing module, so that the processing module can generate a second trigger signal including the thread mask corresponding to each thread module according to the multiple first trigger signals received in each time period, thereby enabling the routing board card to trigger the parallel execution of multiple quantum computing tasks according to the received second trigger signal. That is, only by sending one second trigger signal can the parallel execution of multiple quantum computing tasks be triggered, saving the transmission resources of the system.

[0140] In an alternative embodiment, the target thread module is communicatively connected to multiple routing board cards respectively. When the thread module is communicatively connected to multiple routing board cards respectively, according to the above Figure 2 shown method, the embodiment of the present application also provides a trigger signal generation method. As Figure 10 shown, Figure 10 is the sixth process schematic diagram of the trigger signal generation method provided by the embodiment of the present application. The following step, that is, step S206, is added to the method shown in Figure 10 shown.

[0141] Step S206, the target thread module sends the first trigger signal to the second routing board card that matches the chassis mask, so that the second routing board card triggers the execution of the quantum computing task based on the first trigger signal.

[0142] In an embodiment of the present application, since the target thread module is communicatively connected to each routing board card respectively, therefore, after the target thread module generates the above first trigger signal, it can send the first trigger signal to each routing board card respectively. The thread module in the routing board card that matches the target thread module generates a fourth trigger signal in the same time period according to the synchronization pulse, its own loading state, and the received first trigger signal, so that the lower-level board cards that are communicatively connected generate pulse signals.

[0143] Through the above step S206, each thread module in the central control board card is directly communicatively connected to the routing board card. When multiple thread modules in the routing board card receive the first trigger signal in the same time period, the routing board card can trigger multiple lower-level board cards to generate pulse signals, realizing the parallel execution of multiple quantum computing tasks.

[0144] Based on the same inventive concept, according to the trigger signal generation method provided in the embodiments of the present application above, the embodiments of the present application also provide a central control board card. As Figure 11 shown, Figure 11 FIG. 5 is a first schematic structural diagram of the central control board card provided by the embodiment of the present application. The central control board card 1101 includes a thread module 1102 and a plurality of thread modules 1103. The central control board card 1101 and a plurality of routing board cards form a quantum computing measurement and control system. Each routing board card is respectively communicatively connected to the processing module 1102 through different transmission paths;

[0145] The above-mentioned processing module 1102 is configured to, when receiving a ready instruction packet carrying a thread identifier and a chassis mask sent by the first routing board card, send the chassis mask to a target thread module that matches the thread identifier;

[0146] The above-mentioned target thread module is configured to, when receiving the chassis mask, update a target value corresponding to the first routing board card in the ready state value stored in itself. The ready state value is used to indicate the ready state of all routing board cards for the same quantum computing task at the current moment; when the ready state value at the current moment meets a preset trigger condition, generate a first trigger signal, and the preset trigger condition is determined based on the chassis mask.

[0147] Optionally, the above-mentioned quantum computing measurement and control system may further include a plurality of lower-layer board cards, and the lower-layer board cards are communicatively connected to the routing board cards and are in one-to-one correspondence;

[0148] The above-mentioned thread identifier is used to indicate the thread required for the lower-layer board card to execute the quantum computing task, and the above-mentioned chassis mask is the mask information corresponding to the routing board card required to trigger the execution of the quantum computing task.

[0149] Optionally, the above-mentioned processing module 1102 may specifically be configured to receive a ready instruction packet sent by the first routing board card, where the ready instruction packet carries a thread identifier and a chassis mask; select a thread module 1103 whose module identifier matches the thread identifier according to the module identifier corresponding to each thread module 1103 as the target thread module; and send the chassis mask to the target thread module.

[0150] Optionally, the above-mentioned target thread module may specifically be configured to, when receiving the chassis mask, determine the first routing board card that sends the ready instruction packet according to the path identifier of the transmission path corresponding to the ready instruction packet; and update the target value corresponding to the first routing board card in the ready state value stored in itself.

[0151] Optionally, the above-mentioned ready state value includes a target value corresponding to each routing board card, and the initial value corresponding to the target value is a first value;

[0152] The above-mentioned target thread module can be specifically used to update the target value corresponding to the first routing board in the ready state value stored by itself from the first value to the second value.

[0153] Optionally, the above-mentioned target thread module can also obtain the ready state value stored at the current moment as the target ready state value before generating the first trigger signal when the ready state value at the current moment meets the preset trigger condition; compare the target ready state value with the chassis mask; when the target ready state value is the same as the chassis mask, determine that the target ready state value meets the preset matching condition; when the target ready state value is different from the chassis mask, determine that the target ready state value does not meet the preset matching condition.

[0154] Optionally, the above-mentioned target thread module can also be used to send a first trigger signal to the processing module 1102;

[0155] The above-mentioned processing module 1102 can also be used to generate a second trigger signal including the mask information corresponding to each thread module 1103 based on the first trigger signal received within the same time period, and send the second trigger signal to multiple routing boards, so that the multiple routing boards trigger the execution of the quantum computing task based on the second trigger signal.

[0156] Optionally, the above-mentioned target thread module is respectively communicatively connected to multiple routing boards;

[0157] The above-mentioned target thread module can also send a first trigger signal to the second routing board that matches the chassis mask, so that the second routing board triggers the execution of the quantum computing task based on the first trigger signal.

[0158] Through the central control board provided by the embodiment of the present application, for the ready instruction packet sent by each routing board, after receiving the ready instruction packet, the processing module in the central control board can send the chassis mask in the ready instruction packet to the target thread module according to the thread identifier in the ready instruction packet, so that the target thread module determines whether the updated ready state value meets the preset trigger condition determined based on the chassis mask after updating the ready state value stored by itself, and thus generates a first trigger signal when the preset trigger condition is met.

[0159] Compared with the way that the central control board card directly generates a trigger signal when receiving a trigger instruction packet during the execution of a single quantum computing task, considering the situation that a quantum computing task needs to call multiple routing board cards and the lower-level board cards connected by the routing board cards during the parallel execution of multiple quantum computing tasks, each thread module in the above central control board card can generate a first trigger signal only when the ready state value at the current moment meets the preset trigger condition determined according to the received chassis mask. This enables the central control board card to generate a trigger signal only when the ready state of the routing board cards required for the execution of each quantum computing task meets the preset trigger condition, realizing the application of multi-threading technology in the quantum computing measurement and control system. This effectively ensures the effectiveness and accuracy of the generation of the first trigger signal corresponding to each quantum computing task, thus providing a guarantee for the parallel execution of subsequent quantum computing tasks.

[0160] Based on the same inventive concept, according to the trigger signal generation method provided in the above embodiments of the present application, the embodiments of the present application also provide a central control board card, as Figure 12 shown, including a processor 1201, a communication interface 1202, a memory 1203, and a communication bus 1204. Among them, the processor 1201, the communication interface 1202, and the memory 1203 complete mutual communication through the communication bus 1204.

[0161] The memory 1203 is used to store computer programs.

[0162] The processor 1201 is configured to implement the steps of the trigger signal generation method described in any one of the above when executing the program stored on the memory 1203.

[0163] The communication bus mentioned in the above central control board card can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0164] The communication interface is used for the communication between the above central control board card and other devices.

[0165] The memory may include a Random Access Memory (RAM), or may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0166] The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0167] The above-mentioned processor may be the physical device corresponding to the processing module and the thread module in the above-mentioned central control board.

[0168] Based on the same inventive concept, according to the trigger signal generation method provided in the embodiment of the present application above, the embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above trigger signal generation methods are implemented.

[0169] Based on the same inventive concept, according to the trigger signal generation method provided in the embodiment of the present application above, the embodiment of the present application also provides a computer program product containing instructions, which when running on a computer, causes the computer to execute any of the trigger signal generation methods in the above embodiments.

[0170] Based on the same inventive concept, according to the trigger signal generation method provided in the embodiment of the present application above, the embodiment of the present application also provides a quantum computing measurement and control system, the quantum computing measurement and control system includes a central control board, and the central control board executes to implement any of the above trigger signal generation methods.

[0171] Based on the same inventive concept, according to the trigger signal generation method provided in the embodiment of the present application above, the embodiment of the present application also provides a quantum computer, the quantum computer includes the above quantum computing measurement and control system, and the quantum computing measurement and control system executes to implement the steps of any of the above trigger signal generation methods.

[0172] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

[0173] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article, or device that includes the element.

[0174] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for embodiments such as the central control board, computer-readable storage medium, computer program product, quantum computing measurement and control system, quantum computer, etc., since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0175] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. A method for generating a trigger signal, characterized in that, The central control board card applied to the quantum computing measurement and control system, the central control board card includes a processing module and multiple thread modules, the quantum computing measurement and control system further includes multiple routing board cards, and each routing board card is respectively communicatively connected to the processing module through different transmission paths. The method includes: When the processing module receives a ready instruction packet carrying a thread identifier and a chassis mask sent by the first routing board card, it sends the chassis mask to the target thread module matching the thread identifier; When the target thread module receives the chassis mask, it updates the target value corresponding to the first routing board card in the ready state value stored in itself, and the ready state value is used to indicate the ready state of all routing board cards for the same quantum computing task at the current moment; When the ready state value at the current moment of the target thread module meets a preset trigger condition, it generates a first trigger signal, and the preset trigger condition is determined based on the chassis mask.

2. The method according to claim 1, wherein The quantum computing measurement and control system further includes multiple lower-layer board cards, and the lower-layer board cards are communicatively connected to the routing board cards and are in one-to-one correspondence; The thread identifier is used to indicate the thread required for the lower-layer board card to execute the quantum computing task, and the chassis mask is the mask information corresponding to the routing board card required to trigger the execution of the quantum computing task.

3. The method according to claim 1, wherein The step of, when receiving a ready instruction packet carrying a thread identifier and a chassis mask sent by the first routing board card, sending the chassis mask to the target thread module matching the thread identifier includes: Receiving a ready instruction packet sent by the first routing board card, and the ready instruction packet carries a thread identifier and a chassis mask; According to the module identifier corresponding to each thread module, selecting the thread module whose module identifier matches the thread identifier as the target thread module; Sending the chassis mask to the target thread module.

4. The method according to claim 1, wherein The step of, when receiving the chassis mask, updating the target value corresponding to the first routing board card in the ready state value stored in itself includes: When receiving the chassis mask, determining the first routing board card that sent the ready instruction packet according to the path identifier of the transmission path corresponding to the ready instruction packet; Updating the target value corresponding to the first routing board card in the ready state value stored in itself.

5. The method according to claim 4, wherein The ready state value includes target values corresponding to each routing board card, and the initial value corresponding to the target value is a first value; The step of updating the target value corresponding to the first routing board card in the ready state value stored in itself includes: Updating the target value corresponding to the first routing board card in the ready state value stored in itself from the first value to a second value.

6. The method according to claim 1, characterized in that Before generating the first trigger signal when the ready state value at the current moment meets the preset trigger condition, the method further includes: The target thread module obtains the ready state value stored at the current moment as the target ready state value; The target thread module compares the target ready state value with the chassis mask; When the target ready state value is the same as the chassis mask, the target thread module determines that the target ready state value meets the preset matching condition; When the target ready state value is different from the chassis mask, the target thread module determines that the target ready state value does not meet the preset matching condition.

7. The method according to claim 1, characterized in that, The method further includes: The target thread module sends the first trigger signal to the processing module; Based on the first trigger signals received within the same time period, the processing module generates a second trigger signal including mask information corresponding to each thread module, and sends the second trigger signal to the multiple routing boards, so that the multiple routing boards trigger the execution of the quantum computing task based on the second trigger signal.

8. The method according to claim 1, characterized in that The target thread module is respectively communicatively connected to the multiple routing boards; The method further includes: The target thread module sends the first trigger signal to a second routing board that matches the chassis mask, so that the second routing board triggers the execution of the quantum computing task based on the first trigger signal.

9. A central control board, characterized in that, The central control board includes a processing module and multiple thread modules. The central control board and the multiple routing boards form a quantum computing measurement and control system. Each routing board is communicatively connected to the processing module through a different transmission path; The processing module is configured to, when receiving a ready instruction packet carrying a thread identifier and a chassis mask sent by a first routing board, send the chassis mask to a target thread module that matches the thread identifier; The target thread module is configured to, when receiving the chassis mask, update a target value corresponding to the first routing board in a ready state value stored therein, where the ready state value is used to indicate the ready state of all routing boards for the same quantum computing task at the current moment; When the ready state value at the current moment meets a preset trigger condition, a first trigger signal is generated, and the preset trigger condition is determined based on the chassis mask.

10. A central control board, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus; The memory is used to store a computer program; The processor is configured to, when executing the program stored on the memory, implement the method steps described in any one of claims 1-9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the method steps described in any one of claims 1-9 are implemented.

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