Implementation method of quantum circuit braiding

Abstract

The invention discloses an implementation method of quantum circuit weaving. The method comprises the steps that an obtained initial quantum circuit is compiled, a first quantum circuit is determined, and the first quantum circuit comprises a single-bit quantum gate and a double-bit quantum gate. Then, according to the first quantum circuit, determining a second quantum circuit and target double-bit quantum gate information; and finally, according to the target double-bit quantum gate information, determining a target single-bit quantum gate operation set to realize quantum circuit braiding. In this way, the initial quantum circuit is compiled into the first quantum circuit only comprising the single-bit quantum gate and the double-bit quantum gate, and interference of a complex quantum gate structure on follow-up operation is eliminated. And the target single-bit quantum gate operation set equivalent to the target double-bit quantum gate is generated, and the repeated operation is merged and simplified, so that the sampling overhead of quantum hardware is remarkably reduced.

Description

Technical Field

[0001] This application relates to the field of quantum computing, and more particularly, to a method for implementing quantum circuit braiding. Background Art

[0002] Based on the unique physical properties of qubits such as quantum superposition and quantum entanglement, quantum computing exhibits significant theoretical advantages over classical computing paradigms when dealing with specific complex problems. In related technologies, quantum circuits are tools for quantum computing and can transform abstract quantum algorithms into executable sequences of physical operations. However, when processing medium and above-scale quantum circuits, the scale of the quantum circuit often exceeds the performance of the quantum computing hardware, resulting in abnormal execution of the quantum circuit and affecting the user experience. Summary of the Invention

[0003] This application provides a method for implementing quantum circuit braiding.

[0004] An embodiment of this application provides a method for implementing quantum circuit braiding, and the method includes: Compiling the obtained initial quantum circuit to determine a first quantum circuit, where the first quantum circuit includes single-qubit quantum gates and two-qubit quantum gates; Determining a second quantum circuit and target two-qubit quantum gate information according to the first quantum circuit; Determining a target single-qubit quantum gate operation set according to the target two-qubit quantum gate information to implement the quantum circuit braiding.

[0005] In this way, a computer device compiles the obtained initial quantum circuit to determine a first quantum circuit, and the first quantum circuit includes single-qubit quantum gates and two-qubit quantum gates. Then, the computer device determines a second quantum circuit and target two-qubit quantum gate information according to the first quantum circuit. Finally, the computer device determines a target single-qubit quantum gate operation set according to the target two-qubit quantum gate information to implement the quantum circuit braiding. In this way, by compiling the initial quantum circuit into a first quantum circuit that only includes single-qubit quantum gates and two-qubit quantum gates, the interference of complex quantum gate structures on subsequent operations is eliminated. And by generating a target single-qubit quantum gate operation set equivalent to the target two-qubit quantum gate and merging and simplifying repeated operations, the sampling overhead of the quantum hardware is significantly reduced.

[0006] In some embodiments, the determining a second quantum circuit and target two-qubit quantum gate information according to the first quantum circuit includes: Based on the hardware performance, splitting the first quantum circuit to determine the second quantum circuit; Determine the target two-qubit quantum gate information according to the second quantum circuit, where the target two-qubit quantum gate information includes the target two-qubit quantum gate to be cut and the position information of the target two-qubit quantum gate in the first quantum circuit.

[0007] In this way, based on the hardware performance, the computer device splits the first quantum circuit to determine the second quantum circuit. Then, the computer device determines the target two-qubit quantum gate information according to the second quantum circuit, where the target two-qubit quantum gate information includes the target two-qubit quantum gate to be cut and the position information of the target two-qubit quantum gate in the first quantum circuit. In this way, by splitting the first quantum circuit based on the hardware performance, the first quantum circuit that cannot be correctly executed due to the hardware performance is transformed into multiple executable second quantum circuits, enabling complex tasks to run in stages.

[0008] In some embodiments, the determining the second quantum circuit and the target two-qubit quantum gate information according to the first quantum circuit includes: Based on a preset splitting algorithm, split the first quantum circuit to determine the second quantum circuit; Determine the target two-qubit quantum gate information according to the second quantum circuit, where the target two-qubit quantum gate information includes the target two-qubit quantum gate to be cut and the position information of the target two-qubit quantum gate in the first quantum circuit.

[0009] In this way, based on the preset splitting algorithm, the computer device splits the first quantum circuit to determine the second quantum circuit. Then, the computer device determines the target two-qubit quantum gate information according to the second quantum circuit, where the target two-qubit quantum gate information includes the target two-qubit quantum gate to be cut and the position information of the target two-qubit quantum gate in the first quantum circuit. In this way, through the preset splitting algorithm, the first quantum circuit is automatically divided into second quantum circuits that meet the hardware scale without manual grouping. Moreover, the preset algorithm can adjust the splitting strategy according to the connection relationship of the hardware to ensure that the quantum gates in the second quantum circuit meet the physical connection limitations of the hardware.

[0010] In some embodiments, the target two-qubit quantum gate information includes the target two-qubit quantum gate to be cut, and the determining the target single-qubit quantum gate operation set according to the target two-qubit quantum gate information includes: Equivalently disassemble the target two-qubit quantum gate to determine an initial single-qubit quantum gate operation set, where the initial single-qubit quantum gate operation set includes initial single-qubit quantum gate operations, weights corresponding to the initial single-qubit quantum gate operations, and the mapping relationship between the initial single-qubit quantum gate operations and the second quantum circuit; Perform a merging process on the set of initial single-bit quantum gate operations to determine the set of target single-bit quantum gate operations.

[0011] In this way, the computer device performs an equivalent decomposition on the target two-bit quantum gate to determine the set of initial single-bit quantum gate operations. The set of initial single-bit quantum gate operations includes initial single-bit quantum gate operations, weights corresponding to the initial single-bit quantum gate operations, and the mapping relationship between the initial single-bit quantum gate operations and the second quantum circuit. Then, the computer device performs a merging process on the set of initial single-bit quantum gate operations to determine the set of target single-bit quantum gate operations. In this way, the correctness of quantum computing is ensured through equivalent decomposition, facilitating the subsequent restoration of the first quantum circuit. Moreover, through the merging process, the quantum circuits that need to be executed by the quantum hardware are reduced, thereby reducing the hardware execution overhead and improving the quantum simulation efficiency.

[0012] In some embodiments, the method further includes: Determine a target measurement result according to the second quantum circuit and the set of target single-bit quantum gate operations.

[0013] In this way, the computer device determines a target measurement result according to the second quantum circuit and the set of target single-bit quantum gate operations. In this way, by using the set of target single-bit quantum gate operations and the second quantum circuit obtained by the quantum hardware through the merging process to obtain the target measurement result, it is possible to improve the hardware execution efficiency without losing quantum circuit information.

[0014] In some embodiments, the determining a target measurement result according to the second quantum circuit and the set of target single-bit quantum gate operations includes: Determine a first measurement result according to the second quantum circuit and the initial single-bit quantum gate operations; Determine a complete operation result corresponding to the initial single-bit quantum gate operation according to the first measurement result; Determine the target measurement result according to the complete operation result and the weight corresponding to the initial single-bit quantum gate operation.

[0015] In this way, the computer device determines a first measurement result according to the second quantum circuit and the initial single-bit quantum gate operations. Then, the computer device determines a complete operation result corresponding to the initial single-bit quantum gate operation according to the first measurement result. Finally, the computer device determines the target measurement result according to the complete operation result and the weight corresponding to the initial single-bit quantum gate operation. In this way, through mathematical derivation and weight superposition, without losing any quantum information, the calculation result of the original initial quantum circuit is efficiently reproduced, breaking through the existing quantum hardware scale limit, and ensuring the efficiency and accuracy of the actual execution of large-scale quantum circuits.

[0016] In some embodiments, determining the first measurement result according to the second quantum circuit and the initial single-qubit quantum gate operation includes: Determining a target sub-circuit variant according to the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship; Determining a first measurement result corresponding to the target sub-circuit variant according to the target sub-circuit variant.

[0017] In this way, the computer device determines the target sub-circuit variant according to the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship. Then, the computer device determines a first measurement result corresponding to the target sub-circuit variant according to the target sub-circuit variant. In this way, through the combined action of the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship, the deviation of the quantum state evolution caused by the operation mapping error is avoided, and the physical executability and logical correctness of the target sub-circuit variant are ensured.

[0018] In some embodiments, determining the target sub-circuit variant according to the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship includes: Performing a splicing process on the initial single-qubit quantum gate operation and the second quantum circuit according to the mapping relationship to determine the target sub-circuit variant.

[0019] In this way, the computer device performs a splicing process on the initial single-qubit quantum gate operation and the second quantum circuit according to the mapping relationship to determine the target sub-circuit variant. In this way, through the splicing process driven by the mapping relationship, the accuracy of the generation of the target sub-circuit variant is ensured.

[0020] In some embodiments, determining a complete operation result corresponding to the initial single-qubit quantum gate operation according to the first measurement result includes: Determining a complete operation result corresponding to the initial single-qubit quantum gate operation according to the mapping relationship and the first measurement result.

[0021] In this way, the computer device determines a complete operation result corresponding to the initial single-qubit quantum gate operation according to the mapping relationship and the first measurement result. In this way, through the combination of measurement results driven by the mapping relationship, the systematic integration of the local measurement result into the complete operation result is realized.

[0022] In some embodiments, the target two-qubit quantum gate information includes the position information of the target two-qubit quantum gate in the first quantum circuit. Determining the target measurement result according to the complete operation result and the weight corresponding to the initial single-qubit quantum gate operation includes: Multiply the complete operation result by the weight corresponding to the initial single-qubit quantum gate operation to determine a temporary processing result; Determine the target measurement result according to the temporary processing result and the position information.

[0023] In this way, the computer device multiplies the complete operation result by the weight corresponding to the initial single-qubit quantum gate operation to determine a temporary processing result. Then, the computer device determines the target measurement result according to the temporary processing result and the position information. In this way, through the association of the weight distribution and the position information, an accurate mapping from the fragmented target sub-circuit variant measurement result to the original initial quantum circuit global result is realized.

[0024] Additional aspects and advantages of the embodiments of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the embodiments of the present application. Description of the Drawings

[0025] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where: Figure 1 is one of the flow schematic diagrams of the implementation method of quantum circuit braiding according to the embodiment of the present application; Figure 2 is the structural schematic diagram of the quantum circuit C according to the embodiment of the present application; Figure 3 is another flow schematic diagram of the implementation method of quantum circuit braiding according to the embodiment of the present application; Figure 4(a) is the structural schematic diagram of the second quantum circuit C2-1 according to the embodiment of the present application; Figure 4(b) is the structural schematic diagram of the second quantum circuit C2-2 according to the embodiment of the present application; Figure 4(c) is the structural schematic diagram of the second quantum circuit C2-3 according to the embodiment of the present application; Figure 4(d) is the structural schematic diagram of the second quantum circuit C2-4 according to the embodiment of the present application; Figure 4(e) is the structural schematic diagram of the second quantum circuit C2-5 according to the embodiment of the present application; Figure 5(a) is the structural schematic diagram of the second quantum circuit C3-1 according to the embodiment of the present application; Figure 5(b) is the structural schematic diagram of the second quantum circuit C3-2 according to the embodiment of the present application; Figure 5(c) is the structural schematic diagram of the second quantum circuit C3-3 according to the embodiment of the present application; Figure 5(d) is the structural schematic diagram of the second quantum circuit C3-4 according to the embodiment of the present application; Figure 5(e) is a schematic structural diagram of the second quantum circuit C3-5 according to an embodiment of the present application; Figure 6 is the third schematic flow diagram of the implementation method of quantum circuit braiding according to an embodiment of the present application; Figure 7 is the fourth schematic flow diagram of the implementation method of quantum circuit braiding according to an embodiment of the present application; Figure 8 is the fifth schematic flow diagram of the implementation method of quantum circuit braiding according to an embodiment of the present application; Figure 9 is the sixth schematic flow diagram of the implementation method of quantum circuit braiding according to an embodiment of the present application; Figure 10 is the seventh schematic flow diagram of the implementation method of quantum circuit braiding according to an embodiment of the present application; Figure 11 is the eighth schematic flow diagram of the implementation method of quantum circuit braiding according to an embodiment of the present application; Figure 12 is the ninth schematic flow diagram of the implementation method of quantum circuit braiding according to an embodiment of the present application; Figure 13 is the tenth schematic flow diagram of the implementation method of quantum circuit braiding according to an embodiment of the present application; Figure 14 is a schematic structural diagram of the quantum circuit D according to an embodiment of the present application; Figure 15(a) is one of the schematic structural diagrams of the target sub-circuit variant according to an embodiment of the present application; Figure 15(b) is the second of the schematic structural diagrams of the target sub-circuit variant according to an embodiment of the present application; Figure 15(c) is the third of the schematic structural diagrams of the target sub-circuit variant according to an embodiment of the present application. Detailed implementation manners

[0026] The following details the embodiments of the present application. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application and should not be construed as a limitation to the embodiments of the present application.

[0027] Based on the unique physical properties of qubits - quantum superposition and quantum entanglement, quantum computing exhibits significant theoretical advantages over classical computing paradigms when dealing with specific complex problems. Different from classical bits that can only represent two discrete states of 0 or 1, a single qubit can be in and Any superposition state, and the entanglement between multiple qubits can form a high-dimensional correlated state, enabling quantum computing to have a natural parallel information processing ability. For example, the Shor algorithm utilizes quantum Fourier transform and superposition to complete the factorization of large integers, which requires exponential time in classical algorithms, in polynomial time, directly threatening the existing RSA encryption system; the Grover algorithm, on the other hand, through the quantum search amplitude amplification technique, improves the search efficiency of an unsorted database to times (N is the scale of the database). Such characteristics make quantum computing show extremely high potential in fields such as cryptography, combinatorial optimization, and quantum chemistry simulation.

[0028] In related technologies, quantum circuits are important tools for quantum computing. It can transform an abstract quantum algorithm into an executable sequence of physical operations. Just as the circuit schematic diagram in a classical computer guides the operation of electronic components, quantum circuits specify in detail steps such as the preparation, operation, and measurement of qubits.

[0029] However, when dealing with medium and above-scale quantum circuits, the scale of quantum circuits often exceeds the performance of quantum computing hardware. That is to say, at present, the development of quantum computing hardware faces many bottlenecks. The number of qubits has just reached a few hundred qubits, and due to the influence of noise such as decoherence, the current hardware only supports the execution of quantum circuits with a scale of dozens of qubits. When the scale of the quantum circuit to be executed exceeds this limit, it will lead to abnormal execution of the quantum circuit, such as an increase in the calculation result error and a significant extension of the execution time, seriously affecting the user experience.

[0030] Based on the above problems, please refer to Figure 1 This application embodiment provides a method for implementing quantum circuit weaving, and the method includes: 01: Compile the obtained initial quantum circuit to determine the first quantum circuit; 02: Determine the second quantum circuit and the target two-qubit quantum gate information according to the first quantum circuit; 03: Determine the target single-qubit quantum gate operation set according to the target two-qubit quantum gate information to achieve quantum circuit weaving.

[0031] This application embodiment also provides a computer device, including a memory and a processor. The method for implementing quantum circuit weaving in this application embodiment can be implemented by the computer device in this application embodiment. Specifically, a computer program is stored in the memory, and the processor is used to compile the obtained initial quantum circuit to determine the first quantum circuit. And determine the second quantum circuit and the target two-qubit quantum gate information according to the first quantum circuit. And determine the target single-qubit quantum gate operation set according to the target two-qubit quantum gate information to achieve quantum circuit weaving.

[0032] Embodiments of the present application also provide a quantum circuit weaving device. The implementation method of quantum circuit weaving in embodiments of the present application can be implemented by the quantum circuit weaving device in embodiments of the present application. Specifically, the quantum circuit simulation device includes a determination module. The determination module is used to perform compilation processing on the obtained initial quantum circuit to determine a first quantum circuit. And determine a second quantum circuit and target two-bit quantum gate information according to the first quantum circuit. And determine a set of target single-bit quantum gate operations according to the target two-bit quantum gate information to achieve quantum circuit weaving.

[0033] Specifically, quantum circuit weaving (QCW) refers to a quantum circuit optimization or compilation technique that realizes equivalent transformation of a quantum circuit by restructuring, decomposing, or mapping quantum gate operations (especially two-bit gates), so as to adapt to a specific quantum computing hardware architecture (such as a restricted qubit connection topology), reduce gate operation errors, or reduce computational complexity. Quantum circuit weaving converts the original quantum circuit into a sequence of gates executable by quantum computing hardware through mathematical transformations (such as unitary matrix decomposition). For example, decomposing a two-bit quantum gate into a combination of single-bit quantum gates and CNOT gates, or avoiding qubit interactions with too large a span by adjusting the gate order.

[0034] The initial quantum circuit refers to the original, unstandardized quantum circuit directly generated by an abstract quantum algorithm, which may contain quantum gate operations not supported by the quantum computing hardware or two-bit gates with too large a span.

[0035] A quantum circuit is a tool for quantum computing, used to transform an abstract quantum algorithm into a sequence of physical operations executable on quantum computing hardware. Its essence is a graphical model describing the evolution process of qubits (Qubits), similar to the logic circuit in a classical computer, but the operating object is qubits with the characteristics of quantum superposition and quantum entanglement.

[0036] A qubit (Qubit) refers to the basic unit of a quantum circuit and is the carrier of quantum information, which can be in , and its superposition state.

[0037] Quantum gates (Quantum Gates) refer to the basic operation units in quantum computing, which are mathematical operations that perform specific transformations on the states of qubits. Their essence is a unitary transformation acting on quantum states, satisfying reversibility and probability conservation, and are used to construct quantum circuits to realize the logical functions of quantum algorithms.

[0038] The first quantum circuit refers to the standardized quantum circuit obtained after compiling the initial quantum circuit, which only contains single-qubit quantum gates and two-qubit quantum gates that can be directly executed by quantum hardware. The first quantum circuit can be used as the standardized input for subsequent two-qubit quantum gate optimization, thus simplifying the decomposition process of complex quantum gates. The purpose of compilation is to decompose higher-order quantum gates or gates not supported by the hardware into a set of basic gates that can be operated by the hardware. For example, decomposing a three-qubit Toffoli gate (CCNOT gate) into a combination of multiple single-qubit gates and two-qubit CNOT gates.

[0039] Single-qubit quantum gates act on a single qubit, such as Pauli gates (X gate, Y gate, Z gate), Hadamard gate (H gate), and phase gates (S gate, T gate), etc., which are used to control the phase or superposition of the quantum state.

[0040] Two-qubit quantum gates act on two qubits, such as CNOT gate (controlled-NOT gate), CZ gate (controlled-Z gate), SWAP gate, etc., which realize the entanglement or correlation between qubits.

[0041] The second quantum circuit refers to a set of sub-circuits obtained after further processing of the first quantum circuit. After all the second quantum circuits are combined in the original order, it is the first quantum circuit. The second quantum circuit has a smaller scale (fewer number of qubits and quantum gates), and can be directly executed on the existing quantum computing hardware.

[0042] The information of the target two-qubit quantum gate refers to the set of characteristic information of the cut two-qubit quantum gate extracted during the processing of the first quantum circuit.

[0043] The set of target single-qubit quantum gate operations refers to the combination of single-qubit quantum gates and related information used to replace the original two-qubit quantum gate after cutting the target two-qubit quantum gate.

[0044] First, the computer device performs compilation on the obtained initial quantum circuit, converting the abstract initial quantum circuit into the first quantum circuit that only includes single-qubit quantum gates and two-qubit quantum gates.

[0045] Subsequently, the computer device analyzes the first quantum circuit, identifies the target two-qubit quantum gate that needs to be cut, and disassembles the first quantum circuit to determine the second quantum circuit and the information of the target two-qubit quantum gate.

[0046] Finally, according to the information of the target two-qubit quantum gate, the set of target single-qubit quantum gate operations is determined.

[0047] The following takes the quantum circuit C as an example to illustrate the implementation method of quantum circuit weaving provided by the embodiment of the present application. Please refer to Figure 2 , Figure 2It is a circuit schematic diagram of a quantum circuit C, and the quantum circuit C includes an H gate acting on a qubit and a CNOT gate acting on a qubit and a qubit .

[0048] First, compile the quantum circuit C to determine the first quantum circuit C1. It can be found that the quantum circuit C originally only includes single-qubit quantum gates and two-qubit quantum gates, so the first quantum circuit C1 remains unchanged.

[0049] Next, based on the dotted line, disassemble the first quantum circuit C1 into two parts, that is, split the qubit into the first part, and split the qubit into the second part. Then, the first part is the second quantum circuits (C2-1) to (C2-5), and the second part is the second quantum circuits (C3-1) to (C3-5), and the target two-qubit quantum gate information includes the cut CNOT gate.

[0050] Then, the computer device determines a set of target single-qubit quantum gate operations and equivalent to the CNOT gate according to the target two-qubit quantum gate information.

[0051] Finally, the computer device realizes quantum circuit braiding according to the set of target single-qubit quantum gate operations.

[0052] In summary, in the method for realizing quantum circuit braiding provided by the embodiment of the present application, the computer device compiles the obtained initial quantum circuit to determine the first quantum circuit, and the first quantum circuit includes single-qubit quantum gates and two-qubit quantum gates. Next, the computer device determines the second quantum circuit and the target two-qubit quantum gate information according to the first quantum circuit. Finally, the computer device determines a set of target single-qubit quantum gate operations according to the target two-qubit quantum gate information to realize quantum circuit braiding. In this way, by compiling the initial quantum circuit into the first quantum circuit that only includes single-qubit quantum gates and two-qubit quantum gates, the interference of complex quantum gate structures on subsequent operations is eliminated. And by generating a set of target single-qubit quantum gate operations equivalent to the target two-qubit quantum gate and merging and simplifying repeated operations, the sampling overhead of quantum hardware is significantly reduced.

[0053] Please refer to Figure 3 , in some embodiments, step 02 (determining the second quantum circuit and the target two-qubit quantum gate information according to the first quantum circuit) includes: 021: Based on the hardware performance, disassemble the first quantum circuit to determine the second quantum circuit; 022: Determine the target two-qubit quantum gate information according to the second quantum circuit.

[0054] In some embodiments, the determination module is further configured to split the first quantum circuit based on the hardware performance to determine a second quantum circuit, and determine the target two-qubit quantum gate information according to the second quantum circuit.

[0055] In some embodiments, the processor is further configured to split the first quantum circuit based on the hardware performance to determine a second quantum circuit, and determine the target two-qubit quantum gate information according to the second quantum circuit.

[0056] Specifically, the splitting process is an important step in the quantum circuit weaving technology. In some embodiments, the splitting process can be based on the performance limitations of the current quantum computing hardware (such as the number of qubits, coherence time, gate operation error, etc.), and the first quantum circuit is cut into multiple second quantum circuits that can run independently on the quantum computing hardware. That is, by disconnecting the key connections (two-qubit gates) in the first quantum circuit, the scale of a single quantum circuit is reduced, so that the quantum circuit adapts to the execution ability of the quantum computing hardware.

[0057] The hardware performance limitations include the number of qubit limitations, the number of quantum gate limitations, and the quantum gate operation error. The number of qubit limitations means that the number of qubits in a quantum computer is about 50 - 1000, but due to decoherence effects, only quantum circuits with a scale of dozens of qubits can be stably executed. The number of quantum gate limitations means that the coherence time (the time for maintaining the quantum state) of qubits is limited (usually at the microsecond level). If the number of quantum gates in the quantum circuit is too large, the execution time may exceed the coherence time, resulting in too large an error in the result. The quantum gate operation error refers to the error rate of two-qubit gates, which accumulates as the number of gates increases.

[0058] The target two-qubit quantum gate information is the key information determined during the splitting process, including the two-qubit gate itself that is cut and its position information in the first quantum circuit. Its role is to provide precise positioning of the "cutting point" for the splitting operation and provide a basis for replacing the two-qubit gate with single-qubit gates subsequently.

[0059] The target two-qubit quantum gate to be cut refers to the two-qubit gate (such as a certain key CNOT gate, etc.) selected from the first quantum circuit that needs to be cut. These two-qubit quantum gates are usually the "bridges" connecting different second quantum circuits. After cutting, the original circuit can be divided into independent sub-circuits.

[0060] The position information refers to the specific position of the target two-qubit quantum gate in the first quantum circuit. For example, acting on qubit and qubit .

[0061] Continuing with the above example, please refer to FIGS. 4(a)-4(e) and 5(a)-5(e). FIGS. 4(a)-4(e) are respectively schematic structural diagrams of the second quantum circuits (C2-1) to (C2-5), and FIGS. 5(a)-5(e) are respectively schematic structural diagrams of the second quantum circuits (C3-1) to (C3-5). The first quantum circuit C1 is disassembled into two parts, that is, the qubit is split into the first part, and the qubit [[ID=৪]]is split into the second part. Then, the first part includes the second quantum circuits (C2-1) to (C2-5), the second part is the second quantum circuits (C3-1) to (C3-5), and the target two-qubit quantum gate information includes the cut CNOT gate and the position information "acting on the qubit and the qubit ".

[0062] In this way, based on the hardware performance, the computer device disassembles the first quantum circuit to determine the second quantum circuit. Then, the computer device determines the target two-qubit quantum gate information according to the second quantum circuit. The target two-qubit quantum gate information includes the cut target two-qubit quantum gate and the position information of the target two-qubit quantum gate on the first quantum circuit. In this way, by disassembling the first quantum circuit based on the hardware performance, the first quantum circuit that cannot be correctly executed due to the hardware performance is transformed into multiple executable second quantum circuits, enabling complex tasks to be run in stages.

[0063] Please refer to Figure 6 , in some embodiments, step 02 (determining the second quantum circuit and the target two-qubit quantum gate information according to the first quantum circuit) includes: 023: Based on a preset disassembly algorithm, disassemble the first quantum circuit to determine the second quantum circuit; 024: Determine the target two-qubit quantum gate information according to the second quantum circuit.

[0064] In some embodiments, the determination module is further configured to disassemble the first quantum circuit based on a preset disassembly algorithm to determine the second quantum circuit. And determine the target two-qubit quantum gate information according to the second quantum circuit.

[0065] In some embodiments, the processor is further configured to disassemble the first quantum circuit based on a preset disassembly algorithm to determine the second quantum circuit. And determine the target two-qubit quantum gate information according to the second quantum circuit.

[0066] Specifically, the disassembly process is an important step in the quantum circuit weaving technology. In some embodiments, the disassembly process can cut the first quantum circuit into multiple second quantum circuits that can be independently run on the quantum computing hardware through a preset disassembly algorithm.

[0067] The preset splitting algorithm refers to a regularization method in quantum circuit braiding technology for guiding how to split a first quantum circuit into sub - circuits (second quantum circuits) that can run on existing quantum hardware.

[0068] Performing splitting processing through the preset splitting algorithm and performing splitting processing based on hardware performance are two strategies for quantum circuits respectively. When performing splitting processing based on hardware performance, relevant parameters of the quantum computing hardware need to be manually set, and it is mainly restricted by the physical capabilities of the quantum hardware, which can ensure that the second quantum circuit can be executed on the hardware. When performing splitting processing through the preset splitting algorithm, it is usually automatically executed by the algorithm without manual intervention, and there are preset mathematical optimization objectives or rules, which can ensure the optimization of splitting quality. When precise adaptation to specific hardware (such as temporarily using a device with faulty qubits), manual optimization of key quantum paths (such as retaining a certain part of the entangled state), or when the circuit scale is small, splitting based on hardware performance is preferred. When facing large - scale complex circuits, batch - processing tasks, or the need for dynamic adaptation to different hardware topologies (such as multi - model support in a quantum cloud platform), splitting based on the preset splitting algorithm is preferred.

[0069] It should be noted that performing splitting processing through the preset splitting algorithm and performing splitting processing based on hardware performance are not mutually exclusive. In actual applications, they are usually combined. For example, first use the preset algorithm to generate an initial splitting plan, and then manually fine - tune according to the real - time performance of the hardware (such as the current available number of qubits) to balance efficiency and hardware adaptability.

[0070] In this way, based on the preset splitting algorithm, the computer device splits the first quantum circuit to determine the second quantum circuit. Then, the computer device determines the target two - qubit quantum gate information according to the second quantum circuit. The target two - qubit quantum gate information includes the target two - qubit quantum gate to be cut and the position information of the target two - qubit quantum gate in the first quantum circuit. In this way, through the preset splitting algorithm, the first quantum circuit is automatically divided into a second quantum circuit that meets the hardware scale without manual grouping. And the preset algorithm can adjust the splitting strategy according to the connection relationship of the hardware to ensure that the quantum gates in the second quantum circuit meet the physical connection restrictions of the hardware.

[0071] Please refer to Figure 7 , in some embodiments, the target two - qubit quantum gate information includes the target two - qubit quantum gate to be cut. Step 03 (determining the set of target single - qubit quantum gate operations according to the target two - qubit quantum gate information) includes: 031: Equivalently disassemble the target two - qubit quantum gate to determine the initial set of single - qubit quantum gate operations; 032: Perform a merging process on the initial set of single - qubit quantum gate operations to determine the set of target single - qubit quantum gate operations.

[0072] In some embodiments, the determination module is configured to equivalently decompose a target two-bit quantum gate to determine an initial set of single-bit quantum gate operations, and perform a merging process on the initial set of single-bit quantum gate operations to determine a target set of single-bit quantum gate operations.

[0073] In some embodiments, the processor is further configured to equivalently decompose a target two-bit quantum gate to determine an initial set of single-bit quantum gate operations, and perform a merging process on the initial set of single-bit quantum gate operations to determine a target set of single-bit quantum gate operations.

[0074] Specifically, equivalent decomposition means that the target two-bit quantum gate (such as CNOT, CZ gate, etc.) is decomposed into a combination of single-bit quantum gate operations through mathematical transformation or quantum gate identities, so that the overall effect of this set of single-bit operations is exactly equivalent to that of the original two-bit gate. The purpose is to replace the cut two-bit gate with single-bit gates, divide the original circuit into sub-circuits (second quantum circuit) that can be executed on hardware, and at the same time retain the relevant information of the original circuit for subsequent recombination of results through classical computing. For example, The two-bit gate of can be decomposed into where the corresponding weight is where the corresponding weight is where the corresponding weight is where the corresponding weight is where the corresponding weight is where the corresponding weight is

[0075] The initial set of single-bit quantum gate operations refers to the preliminary result after equivalent decomposition, including all single-bit gate operations generated by the decomposition and their supporting information. The initial set of single-bit quantum gate operations includes initial single-bit quantum gate operations, weights corresponding to the initial single-bit quantum gate operations, and the mapping relationship between the initial single-bit quantum gate operations and the second quantum circuit. Among them, the initial single-bit quantum gate operations refer to the sequence of single-bit gates generated after decomposing the two-bit gate, such as Each operation only acts on a single qubit and can be directly executed by quantum hardware. The weight corresponding to the initial single-bit quantum gate operation refers to a complex number or a real number used to quantify the contribution degree of this operation to the effect of the original two-bit gate. The mapping relationship between the initial single-bit quantum gate operation and the second quantum circuit refers to the corresponding relationship between each single-bit gate operation and the cut sub-circuit (second quantum circuit), such as, Act on the second quantum circuits (C2-1) to (C2-5). Act on the second quantum circuits (C3-1) to (C3-5).

[0076] The set of target single-qubit quantum gate operations is the optimized result after merging the initial set of single-qubit quantum gate operations. By merging repeated or equivalent single-qubit gate operations, the number of second quantum circuits and the hardware sampling overhead are reduced, while the computational information of the original circuit is retained. Since the initial set of single-qubit gate operations may contain a large number of repeated operations, these repeated operations will cause a sharp increase in the number of sub-circuits, and the hardware needs to run the same sub-circuit multiple times, increasing the execution cost. Therefore, it is necessary to merge the initial set of single-qubit quantum gate operations.

[0077] Continuing with the above example, the computer device performs an equivalent decomposition process on the target two-qubit quantum gate CNOT gate to determine the initial set of single-qubit quantum gate operations equivalent to the CNOT gate , where has a corresponding weight of 0.5, has a corresponding weight of 0.5, has a corresponding weight of 0.5, has a corresponding weight of -0.5, has a corresponding weight of 0.5, has a corresponding weight of 0.5. And act on the second quantum circuits (C2-1) to (C2-5) (corresponding to Fig. 4(a)-Fig. 4(e)) act on the second quantum circuits (C3-1) to (C3-5) (corresponding to Fig. 5(a)-Fig. 5(e)). It should be noted that means applying the gate first and then performing a measurement.

[0078] Then, the initial set of single-qubit quantum gate operations is merged to determine the set of target single-qubit quantum gate operations and , and the corresponding weights and the mapping relationship between the initial single-qubit quantum gates and the second quantum circuits.

[0079] In this way, the computer device equivalently disassembles the target two-bit quantum gate to determine the initial set of single-bit quantum gate operations. The initial set of single-bit quantum gate operations includes the initial single-bit quantum gate operations, the weights corresponding to the initial single-bit quantum gate operations, and the mapping relationship between the initial single-bit quantum gate operations and the second quantum circuit. Then, the computer device performs a merging process on the initial set of single-bit quantum gate operations to determine the target set of single-bit quantum gate operations. In this way, the correctness of quantum computing is ensured through equivalent disassembly, facilitating the subsequent restoration of the first quantum circuit. Moreover, through the merging process, the quantum circuits that need to be executed by the quantum hardware are reduced, thereby reducing the hardware execution overhead and improving the quantum simulation efficiency.

[0080] Please refer to Figure 8 , in some embodiments, the method further includes: 04: Determine the target measurement result according to the second quantum circuit and the target set of single-bit quantum gate operations.

[0081] In some embodiments, the determination module is further configured to determine the target measurement result according to the second quantum circuit and the target set of single-bit quantum gate operations.

[0082] In some embodiments, the processor is further configured to determine the target measurement result according to the second quantum circuit and the target set of single-bit quantum gate operations.

[0083] Specifically, the target measurement result refers to the measurement result that is equivalent to the original initial quantum circuit finally calculated by running the second quantum circuit on the quantum hardware and combining the weights in the target set of single-bit quantum gate operations.

[0084] The computer device runs the second quantum circuit and the single-bit quantum gates in the target set of single-bit quantum gate operations on the quantum hardware, and combines classical weighted calculation to recombine the split local results into the target measurement result.

[0085] In this way, the computer device determines the target measurement result according to the second quantum circuit and the target set of single-bit quantum gate operations. In this way, by executing the target set of single-bit quantum gate operations and the second quantum circuit obtained through the merging process on the quantum hardware to obtain the target measurement result, it is possible to improve the hardware execution efficiency without losing the quantum circuit information.

[0086] Please refer to Figure 9 , in some embodiments, step 04 (determine the target measurement result according to the second quantum circuit and the target set of single-bit quantum gate operations) includes: 041: Determine the first measurement result according to the second quantum circuit and the initial single-bit quantum gate operations; 042: Determine the complete operation result corresponding to the initial single-bit quantum gate operation according to the first measurement result; 043: Determine the target measurement result based on the complete operation result and the weight corresponding to the initial single-bit quantum gate operation.

[0087] In some embodiments, the determination module is further configured to determine a first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation; determine a complete operation result corresponding to the initial single-bit quantum gate operation based on the first measurement result; and determine a target measurement result based on the complete operation result and a weight corresponding to the initial single-bit quantum gate operation.

[0088] In some embodiments, the processor is further configured to determine a first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation; determine a complete operation result corresponding to the initial single-bit quantum gate operation based on the first measurement result; and determine a target measurement result based on the complete operation result and a weight corresponding to the initial single-bit quantum gate operation.

[0089] Specifically, the first measurement result refers to the original probability distribution corresponding to each initial single-bit quantum gate operation in the target single-bit quantum gate operation set, determined by actually running and measuring the second quantum circuit obtained through quantum hardware. For example, using the six groups of initial single-bit quantum gate operations in the CNOT gate decomposition as an example, there are a total of ten first measurement results. Please refer to Figure 4(a), which shows the data obtained after running the quantum circuit shown in Figure 4(a) as one of the first measurement results.

[0090] The complete operation result is the set of the first measurement results corresponding to all initial single-bit gate operations, that is, the measurement results covering all possible single-bit operation combinations, ensuring that the calculation results of the original quantum circuit can be fully restored after weighted recombination. Taking the 6 groups of initial single-bit quantum gate operations disassembled by the CNOT gate as an example, the complete operation result includes a set of 6 elements, namely The corresponding measurement results.

[0091] First, each initial single-bit gate operation is applied to the subcircuit, running the hardware and measuring to obtain the original probability distribution corresponding to each operation. Next, all first measurement results are aggregated into a single set to ensure coverage of all initial operations. Finally, through classical calculation, each probability distribution in the complete operation result is multiplied by the weight (squared modulus) of the corresponding initial operation and then summed to obtain the equivalent measurement result of the original circuit.

[0092] In this way, the computer device determines the first measurement result based on the second quantum circuit and the initial single-qubit quantum gate operation. Then, the computer device determines the complete operation result corresponding to the initial single-qubit quantum gate operation according to the first measurement result. Finally, the computer device determines the target measurement result based on the complete operation result and the weight corresponding to the initial single-qubit quantum gate operation. In this way, through mathematical derivation and weight superposition, without losing any quantum information, the calculation result of the original initial quantum circuit is efficiently reproduced, breaking through the existing quantum hardware scale limitation, and ensuring the efficiency and accuracy of the actual execution of large-scale quantum circuits.

[0093] Please refer to Figure 10 , in some embodiments, step 041 (determining the first measurement result according to the second quantum circuit and the initial single-qubit quantum gate operation) includes: 0411: Determine the target sub-circuit variant according to the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship; 0412: Determine the first measurement result corresponding to the target sub-circuit variant according to the target sub-circuit variant.

[0094] In some embodiments, the determination module is further configured to determine the target sub-circuit variant according to the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship, and determine the first measurement result corresponding to the target sub-circuit variant according to the target sub-circuit variant.

[0095] In some embodiments, the processor is further configured to determine the target sub-circuit variant according to the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship, and determine the first measurement result corresponding to the target sub-circuit variant according to the target sub-circuit variant.

[0096] Specifically, the target sub-circuit variant refers to an executable sub-circuit version generated by modifying the second quantum circuit (original sub-circuit) according to the initial single-qubit quantum gate operation in the quantum circuit braiding technology, that is, injecting the initial single-qubit gate operation into the second quantum circuit to generate multiple variants (sub-circuits with different operation versions), and each variant needs to run independently on the quantum hardware, and finally the calculation output of the original circuit is restored through the weighted recombination of the measurement results. For example, please refer to FIGS. 4(a)-4(e), and FIGS. 4(a)-4(e) are the target sub-circuit variants obtained after respectively adding the first part of the quantum circuit (i.e., the qubit ).

[0097] After determining the target sub-circuit variant, the quantum measurement data (the first measurement result) is obtained by running the generated sub-circuit variant, providing an experimental basis for subsequent result recombination.

[0098] In this way, the computer device determines the target sub-circuit variant according to the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship. Then, the computer device determines the first measurement result corresponding to the target sub-circuit variant according to the target sub-circuit variant. In this way, through the combined action of the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship, the deviation of quantum state evolution caused by incorrect operation mapping is avoided, and the physical executability and logical correctness of the target sub-circuit variant are ensured.

[0099] Please refer to Figure 11 , in some embodiments, step 0411 (determining the target sub-circuit variant according to the initial single-qubit quantum gate operation, the second quantum circuit, and the mapping relationship) includes: 04111: According to the mapping relationship, splice the initial single-qubit quantum gate operation and the second quantum circuit to determine the target sub-circuit variant.

[0100] In some embodiments, the determining module is further configured to splice the initial single-qubit quantum gate operation and the second quantum circuit according to the mapping relationship to determine the target sub-circuit variant.

[0101] In some embodiments, the processor is further configured to splice the initial single-qubit quantum gate operation and the second quantum circuit according to the mapping relationship to determine the target sub-circuit variant.

[0102] Specifically, taking the quantum circuit C as an example, the quantum circuit C includes an H gate acting on the qubit and a CNOT gate acting on the qubit and the qubit . After splitting the quantum circuit C, two second quantum circuits C2 and C3 are generated. The second quantum circuit C2 includes the qubit and all operations acting on the qubit (excluding the CNOT gate). The second quantum circuit C3 includes the qubit and all operations acting on the qubit (excluding the CNOT gate).

[0103] Then, according to the initial single-qubit quantum gate operation obtained by disassembling and merging the CNOT gate, it is respectively added to the second quantum circuit C2 to obtain the corresponding target sub-circuit variant. According to the initial single-qubit quantum gate operation obtained by disassembling and merging the CNOT gate, it is respectively added to the second quantum circuit C3 to obtain the corresponding target sub-circuit variant. Among them, the mapping relationship is used to determine the corresponding relationship between the initial single-qubit quantum gate operation and the second quantum circuit, that is, to determine which second quantum circuit the initial single-qubit quantum gate operation should be spliced with.

[0104] In this way, the computer device splices the initial single-bit quantum gate operation and the second quantum circuit according to the mapping relationship to determine the target sub-circuit variant. In this way, through the splicing process driven by the mapping relationship, the accuracy of generating the target sub-circuit variant is ensured.

[0105] Please refer to Figure 12 , in some embodiments, step 042 (determining the complete operation result corresponding to the initial single-bit quantum gate operation according to the first measurement result) includes: 0421: Determine the complete operation result corresponding to the initial single-bit quantum gate operation according to the mapping relationship and the first measurement result.

[0106] In some embodiments, the confirmation module is further configured to determine the complete operation result corresponding to the initial single-bit quantum gate operation according to the mapping relationship and the first measurement result.

[0107] In some embodiments, the processor is further configured to determine the complete operation result corresponding to the initial single-bit quantum gate operation according to the mapping relationship and the first measurement result.

[0108] Specifically, the mapping relationship refers to the correspondence rule between the initial single-bit quantum gate operation and the second quantum circuit, and the mapping relationship can bind the first measurement result measured by the quantum hardware to the theoretical initial single-bit gate operation one by one, forming a complete data set covering all operations, ensuring no information omission when reconstructing the original circuit result later. For example, if the set of initial single-bit gate operations is {initial single-bit quantum gate operation 1, initial single-bit quantum gate operation 2,..., initial single-bit quantum gate operation n}, and the corresponding first measurement results are {result 1; result 2;...; result n}, then the complete operation result can be expressed as: {operation 1: result 1; operation 2: result 2;...; operation n: result n}.

[0109] Continuing with the above example, if in the second quantum circuit C2 the first measurement result of the corresponding target sub-circuit variant is M1, in the second quantum circuit C2 the first measurement result of the corresponding target sub-circuit variant is M2, in the second quantum circuit C2 the first measurement result of the corresponding target sub-circuit variant is M3, in the second quantum circuit C2 the first measurement result of the corresponding target sub-circuit variant is M4, in the second quantum circuit C2 the first measurement result of the corresponding target sub-circuit variant is M5. In the second quantum circuit C3 the first measurement result of the corresponding target sub-circuit variant is M6, in the second quantum circuit C3 The first measurement result of the corresponding target sub-circuit variant is M7, in the second quantum circuit C3 The first measurement result of the corresponding target sub-circuit variant is M8, in the second quantum circuit C3 The first measurement result of the corresponding target sub-circuit variant is M9, in the second quantum circuit C3 The first measurement result of the corresponding target sub-circuit variant is M10.

[0110] Then, according to the mapping relationship, it is determined that the complete operation result includes the result of 、 the result of 、 the result of 、 the result of 、 the result of 、 the result of 。

[0111] In this way, the computer device determines the complete operation result corresponding to the initial single-qubit quantum gate operation according to the mapping relationship and the first measurement result. In this way, through the combination of measurement results driven by the mapping relationship, the systematic integration of local measurement results into complete operation results is achieved.

[0112] Please refer to Figure 13 , in some embodiments, the target two-qubit quantum gate information includes the position information of the target two-qubit quantum gate in the first quantum circuit. Step 043 (determining the target measurement result according to the complete operation result and the weight corresponding to the initial single-qubit quantum gate operation) includes: 0431: Multiply the complete operation result by the weight corresponding to the initial single-qubit quantum gate operation to determine the temporary processing result; 0432: Determine the target measurement result according to the temporary processing result and the position information.

[0113] In some embodiments, the determining module is further configured to multiply the complete operation result by the weight corresponding to the initial single-qubit quantum gate operation to determine the temporary processing result, and determine the target measurement result according to the temporary processing result and the position information.

[0114] In some embodiments, the processor is further configured to multiply the complete operation result by the weight corresponding to the initial single-qubit quantum gate operation to determine the temporary processing result, and determine the target measurement result according to the temporary processing result and the position information.

[0115] Specifically, the temporary processing result is the product of each complete operation result and the corresponding weight modulus squared, reflecting the contribution of each initial operation to the result of the original circuit.

[0116] The position information determines the integration method of the temporary processing results. If the target two-bit quantum gate is at the end of the original quantum circuit (i.e., its action is the last operation), the target measurement result is the weighted sum of all temporary processing results (because there are no other subsequent operations to affect). If the target two-bit quantum gate is in the middle of the original quantum circuit, the quantum state evolution of the operations before and after it needs to be considered, and it may be necessary to perform temporal convolution or state update on the temporary processing results.

[0117] Continuing with the above example, according to the result of 、 the result of 、 the result of 、 the result of 、 the result of 、 the result of , and the weights {0.5, 0.5, 0.5, -0.5, 0.5, -0.5} corresponding to the above complete operation results, determine the temporary processing results.

[0118] Subsequently, sum up all the temporary processing results to determine the target measurement result. And according to the position information, determine the integration method of the temporary processing results.

[0119] In this way, the computer device multiplies the complete operation result and the weight corresponding to the initial single-bit quantum gate operation to determine the temporary processing result. Then, the computer device determines the target measurement result according to the temporary processing result and the position information. In this way, through the association of the weight distribution and the position information, an accurate mapping from the fragmented target sub-circuit variant measurement result to the global result of the original initial quantum circuit is realized.

[0120] The following uses a complete example to illustrate the above implementation method of quantum circuit weaving. Please refer to Figure 14 , Figure 14 which is a schematic structural diagram of quantum circuit D. Quantum circuit D includes a CNOT gate acting on qubit and qubit . The processing flow is as follows: First, check whether quantum circuit D has been compiled into a form with only single-bit gates and two-bit gates. If the compilation is not completed, recompile quantum circuit D into a form with only single-bit gates and two-bit gates. If the compilation is completed, decompose it into two parts according to the dotted line. The first part includes qubit and qubit and the qubits in the original circuit and qubits For all operations of, the second part includes qubits and qubits and the qubits in the original circuit and qubits and all operations thereof. In this decomposition method, the two CNOT gates between qubits and qubits will be cut.

[0121] Next, a set of single - qubit quantum gate operations are used to equivalently replace the cut two - qubit quantum gates, generating an equivalent set of single - qubit quantum gate operations and corresponding weights. After the two CNOT gates are cut, the two sub - circuits will respectively generate 6^2 = 36 initial single - qubit quantum gate operations.

[0122] Then, the 36 initial single - qubit quantum gate operations are merged and simplified, that is, the repeated initial single - qubit quantum gate operations are merged and simplified, obtaining 5^2 = 25 non - repeated initial single - qubit quantum gate operations (which is the set of target single - qubit quantum gate operations).

[0123] Subsequently, these non - repeated initial single - qubit quantum gate operations are respectively spliced with the attributed second quantum circuit to determine the target sub - circuit variants. Please refer to FIGS. 15(a) - 15(c). FIG. 15(a) shows the first sub - circuit variant, the second sub - circuit variant, and the 25th sub - circuit variant, where the single - qubit quantum operations used to replace the two CNOTs are shown in the dashed box.

[0124] Then, these sub - circuit variants are respectively run on the hardware to collect measurement results (i.e., the first measurement results).

[0125] Next, the complete quantum operation is restored to the inner product set of 36 complete variants (i.e., the complete operation results).

[0126] Finally, the properties of the original circuit are restored by combining weight calculation, that is, the local results of the sub - circuits are recombined through classical calculation to restore the global properties of the original circuit.

[0127] This application also provides a computer - readable storage medium containing a computer program. When the computer program is executed by one or more processors, one or more processors are caused to execute the method of this application.

[0128] It can be understood that a computer program includes computer program code. The computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable storage medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution medium, etc.

[0129] In the description of this specification, the descriptions referring to terms such as "specifically", "furthermore", "specially", "understandably", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0130] Any process or method description shown in the flowchart or described in other ways herein can be understood to represent a module, segment or part of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a manner that is not shown or discussed in sequence, including in a substantially simultaneous manner or in a reverse order according to the functions involved, which should be understood by those skilled in the technical field of the embodiments of the present application.

[0131] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application.

Claims

1. A method for implementing quantum circuit braiding, characterized in that The method includes: Compiling the obtained initial quantum circuit to determine a first quantum circuit, where the first quantum circuit includes single-qubit quantum gates and two-qubit quantum gates; Determining a second quantum circuit and target two-qubit quantum gate information according to the first quantum circuit; Determining a target single-qubit quantum gate operation set according to the target two-qubit quantum gate information to implement quantum circuit braiding.

2. The method according to claim 1, characterized in that The determining the second quantum circuit and target two-qubit quantum gate information according to the first quantum circuit includes: Based on the hardware performance, splitting the first quantum circuit to determine the second quantum circuit; Determining the target two-qubit quantum gate information according to the second quantum circuit, where the target two-qubit quantum gate information includes the cut target two-qubit quantum gate and the position information of the target two-qubit quantum gate in the first quantum circuit.

3. The method according to claim 1, characterized in that, The determining the second quantum circuit and target two-qubit quantum gate information according to the first quantum circuit includes: Based on a preset splitting algorithm, splitting the first quantum circuit to determine the second quantum circuit; Determining the target two-qubit quantum gate information according to the second quantum circuit, where the target two-qubit quantum gate information includes the cut target two-qubit quantum gate and the position information of the target two-qubit quantum gate in the first quantum circuit.

4. The method according to claim 1, wherein The target two-qubit quantum gate information includes the cut target two-qubit quantum gate. The determining the target single-qubit quantum gate operation set according to the target two-qubit quantum gate information includes: Equivalently disassembling the target two-qubit quantum gate to determine an initial single-qubit quantum gate operation set, where the initial single-qubit quantum gate operation set includes initial single-qubit quantum gate operations, weights corresponding to the initial single-qubit quantum gate operations, and the mapping relationship between the initial single-qubit quantum gate operations and the second quantum circuit; Performing a merging process on the initial single-qubit quantum gate operation set to determine the target single-qubit quantum gate operation set.

5. The method according to claim 4, wherein The method further includes: Determining a target measurement result according to the second quantum circuit and the target single-qubit quantum gate operation set.

6. The method according to claim 5, wherein The determining the target measurement result according to the second quantum circuit and the target single-qubit quantum gate operation set includes: Determining a first measurement result according to the second quantum circuit and the initial single-qubit quantum gate operations; Determining a complete operation result corresponding to the initial single-qubit quantum gate operations according to the first measurement result; Determining the target measurement result according to the complete operation result and the weights corresponding to the initial single-qubit quantum gate operations.

7. The method according to claim 6, characterized in that, The determining the first measurement result according to the second quantum circuit and the initial single-qubit quantum gate operations includes: Determining a target sub-circuit variant according to the initial single-qubit quantum gate operations, the second quantum circuit, and the mapping relationship; Determining a first measurement result corresponding to the target sub-circuit variant according to the target sub-circuit variant.

8. The method according to claim 7, wherein The determining the target sub-circuit variant according to the initial single-qubit quantum gate operations, the second quantum circuit, and the mapping relationship includes: According to the mapping relationship, splice the initial single-bit quantum gate operation and the second quantum circuit to determine the target sub-circuit variant.

9. The method according to claim 6, wherein The determining of the complete operation result corresponding to the initial single-bit quantum gate operation according to the first measurement result includes: Determine the complete operation result corresponding to the initial single-bit quantum gate operation according to the mapping relationship and the first measurement result.

10. The method according to claim 6, characterized in that, The target two-bit quantum gate information includes the position information of the target two-bit quantum gate in the first quantum circuit. The determining of the target measurement result according to the complete operation result and the weight corresponding to the initial single-bit quantum gate operation includes: Multiply the complete operation result and the weight corresponding to the initial single-bit quantum gate operation to determine an intermediate processing result; Determine the target measurement result according to the intermediate processing result and the position information.

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