Display substrate, display panel and display terminal

Abstract

The invention relates to a display substrate, a display panel and a display terminal. The display substrate comprises a substrate and a protection unit, wherein the protection unit comprises a first signal line, a second signal line, a connecting part and a discharge module; one of the first signal line and the second signal line is connected to the discharge module through the connecting part, and the distance between the other one of the first signal line and the second signal line and the connecting part is larger than the distance between one of the first signal line and the second signal line and the connecting part. The distance between the other one of the first signal line and the second signal line and the connecting part is larger than the distance between one of the first signal line and the second signal line and the connecting part, so that the minimum distance between the connecting part and the first signal line or the second signal line which is not connected can be increased; and the electric field intensity formed between the connecting part and the first signal line or the second signal line which is not connected is reduced, so that the risk of electrochemical corrosion of the connecting part, the first signal line or the second signal line is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display substrate, a display panel, and a display terminal. Background Art

[0002] To avoid damage to the display substrate caused by Electrostatic Discharge (ESD), an ESD protection circuit is usually provided in the display substrate. The protection circuit can conduct away the static electricity and reduce the risk of damage to the components in the circuit caused by static electricity.

[0003] However, with the requirements of higher resolution and narrower borders for the display substrate, the space for setting the ESD protection circuit is reduced. Especially for small-sized display products, such as watches, the pitch of the traces in the ESD protection circuit is further compressed, resulting in easy occurrence of electrochemical corrosion between adjacent traces. Summary of the Invention

[0004] Embodiments of the present application provide a display substrate, a display panel, and a display terminal, which improve the technical problem that the pitch of the traces in the ESD protection circuit of the display substrate is further compressed, resulting in easy occurrence of electrochemical corrosion between adjacent traces.

[0005] To achieve the above object, according to the first aspect of the present application, a display substrate is provided, including a substrate and a protection unit disposed on one side of the substrate. The protection unit includes:

[0006] A first signal line and a second signal line are disposed in the same layer. The first signal line and the second signal line extend along a first direction and are arranged along a second direction, and the second direction is different from the first direction;

[0007] A connection part is disposed in the same layer as the first signal line and the second signal line;

[0008] A discharge module is disposed between the first signal line and the second signal line. The second signal line is connected to the first signal line through the discharge module, and one of the first signal line and the second signal line is connected to the discharge module through the connection part to control the discharge module, so that the second signal line is communicated with or disconnected from the first signal line through the discharge module;

[0009] Wherein, in the second direction, the distance between the other one of the first signal line and the second signal line and the connection part is greater than the distance between one of the first signal line and the second signal line and the connection part.

[0010] Optionally, the discharging module includes a plurality of thin film transistors arranged along the first direction. The thin film transistors include gates, and adjacent gates are connected to form a gate line. The first signal line is disposed on a side of the gate away from the substrate;

[0011] The protection unit further includes a resistor portion, and the one of the first signal line and the second signal line is connected to the connection portion through the resistor portion;

[0012] Wherein, the connection portion and the resistor portion are connected through a via hole, and the connection portion and the gate line are connected through another via hole. The two via holes are arranged along the first direction.

[0013] Optionally, the thin film transistor includes an active portion, a drain, and a source. The active portion and the resistor portion are arranged on the same layer and the active portion extends along the second direction; the drain and the source are arranged on the same layer as the first signal line. The first signal line is connected to one end of the active portion through the drain, and the second signal line is connected to the other end of the active portion through the source.

[0014] Optionally, two adjacent active portions are connected and arranged in the first direction. The drain is integrally provided with the first signal line, and the source is integrally provided with the second signal line.

[0015] Optionally, there are a plurality of discharging modules, and the plurality of discharging modules are arranged along the second direction. The first signal line or the second signal line is disposed between two adjacent discharging modules.

[0016] Optionally, the first signal line includes a first sub-line configured to input a low gate voltage, and the voltage of the first sub-line is less than the voltage of the second signal line;

[0017] Wherein, the second signal line is connected to the discharging module through the connection portion, and the distance between the first sub-line and the connection portion is greater than the distance between the second signal line and the connection portion.

[0018] Optionally, the display substrate further includes a first voltage line extending along the second direction. The first sub-line is connected to the first voltage line. The first sub-line includes a connected first main segment and a first connection segment. The first main segment is connected to the discharging module, and the first connection segment is located between the first main segment and the first voltage line. The width of the first connection segment is less than the width of the first main segment.

[0019] Optionally, the first main segment is connected to the discharging module on one side through a via hole, and the first main segment is connected to the discharging module on the other side through another via hole. The two via holes are arranged along the second direction.

[0020] Optionally, the first signal line includes a second sub-line configured to input a high gate voltage, and the voltage of the second sub-line is greater than the voltage of the second signal line;

[0021] Wherein, the second sub-line is connected to the discharge module through the connection portion, and the distance between the second signal line and the connection portion is greater than the distance between the second sub-line and the connection portion.

[0022] Optionally, the display substrate further includes a second voltage line extending in the second direction, the second sub-line is connected to the second voltage line, the second sub-line includes a connected second main segment and a second connection segment, the second main segment is connected to the discharge module, the second connection segment is located between the second main segment and the second voltage line, and the width of the second connection segment is smaller than the width of the second main segment.

[0023] Optionally, the second main segment is connected to the discharge module on one side through a via hole, and the second main segment is connected to the discharge module on the other side through another via hole, and the two via holes are arranged along the second direction.

[0024] According to a second aspect of the present application, there is provided a display panel including the above-mentioned display substrate.

[0025] According to a third aspect of the present application, there is provided a display terminal including the above-mentioned display panel.

[0026] In the display substrate of the embodiment of the present application, by making the distance between the other one of the first signal line and the second signal line and the connection portion greater than the distance between the one of the first signal line and the second signal line and the connection portion, the minimum distance between the connection portion and the unconnected first signal line or second signal line can be increased, and the electric field strength formed between the connection portion and the unconnected first signal line or second signal line can be reduced, thereby reducing the risk of electrochemical corrosion of the connection portion, the first signal line or the second signal line.

[0027] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0029] To more fully understand the present application and its beneficial effects, the following description will be made in conjunction with the accompanying drawings, where like reference numerals in the following description denote like parts.

[0030] Figure 1 is a top view structural schematic diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0031] Figure 2 is Figure 1 an enlarged structural schematic diagram at position C in

[0032] Figure 3 is Figure 2 a sectional structural schematic diagram in

[0033] Figure 4 is a schematic diagram of the working principle of a protection unit provided in an exemplary embodiment of the present disclosure;

[0034] Figure 5 is a structural schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure;

[0035] Figure 6 is a structural schematic diagram of a display terminal provided in an exemplary embodiment of the present disclosure.

[0036] Description of reference numerals:

[0037] 1 - Display substrate; AA - Display area; NA - Non - display area;

[0038] 10 - Substrate;

[0039] 20 - Protection unit; 20a - Discharge module;

[0040] 211 - First signal line;

[0040] 211a - First sub - line;

[0040] 2111 - First main segment;

[0040] 2112 - First connection segment;

[0040] 211b - Second sub - line;

[0040] 2113 - Second main segment; <[]

[0040] 2114 - Second connection segment; 212 - Second signal line;

[0041] 213 - Bridging part; 214 - Connection part;

[0041] 221 - Gate line; 222 - First voltage line; 223 - Second voltage line;

[0042] 231 - Resistance part;

[0043] 241 - Via;

[0044] 250 - Thin - film transistor; 251 - Gate; 252 - Active part; 253 - Drain; 254 - Source;

[0045] s1 - Spacing between the other one of the first signal line 211 and the second signal line 212 and the connection part 214; It should be noted that there seems to be an error in the "[]0000091" in the original text for item 43. It should probably be just "0000091". This has been translated as accurately as possible based on the provided text.

[0046] s2 - The distance between one of the first signal line 211 and the second signal line 212 and the connection part 214;

[0047] s3 - The distance between the other of the first signal line 211 and the second signal line 212 and the bridging part 213;

[0048] w1 - The width of the first connection segment 2112; w2 - The width of the first main body segment 2111;

[0049] w3 - The width of the second connection segment 2114; w4 - The width of the second main body segment 2113;

[0050] D1 - The first direction; D2 - The second direction;

[0051] 2 - Display panel; 3 - Display terminal; 4 - Terminal body. Detailed implementation manners

[0052] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0053] To achieve the above object, according to the first aspect of the present application, as shown in FIGS. 1 to Figure 3 A display substrate 1 is provided, including a substrate 10 and a protection unit 20 disposed on one side of the substrate 10. The protection unit 20 includes a first signal line 211, a second signal line 212, a connection part 214, and a discharge module 20a. The first signal line 211 and the second signal line 212 are arranged in the same layer. The first signal line 211 and the second signal line 212 extend along the first direction D1 and are arranged along the second direction D2. The second direction D2 is different from the first direction D1. The discharge module 20a is disposed between the first signal line 211 and the second signal line 212. The second signal line 212 is connected to the first signal line 211 through the discharge module 20a. One of the first signal line 211 and the second signal line 212 is connected to the discharge module 20a through the connection part 214 to control the discharge module 20a, so that the second signal line 212 is connected or disconnected from the first signal line 211 through the discharge module 20a. The connection part 214 is arranged in the same layer as the first signal line 211 and the second signal line 212. Among them, the distance s1 between the other of the first signal line 211 and the second signal line 212 and the connection part 214 is greater than the distance s2 between one of the first signal line 211 and the second signal line 212 and the connection part 214.

[0054] In some embodiments, the display substrate 1 may be the array substrate 10 in the display panel 2, etc.

[0055] The substrate 10 may be a rigid material or a flexible material. The rigid material may be glass, quartz, or a silicon wafer. The flexible material is one of polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET), etc.

[0056] The protection unit 20 is disposed on the substrate 10, and the protection unit 20 is formed by laminating multiple film layers. The protection unit 20 is used for electrostatic protection to protect the display substrate 1 from being damaged by static electricity. The protection unit 20 can conduct the static electricity into the ground wire or the power supply wire, thereby preventing the static electricity from damaging the components in the display substrate 1.

[0057] In the embodiments of the present application, the same-layer setting means using the same material and being formed through the same patterning process. The patterning process includes steps such as coating photoresist, exposure and development, etching, and removing photoresist.

[0058] Both the first signal line 211 and the second signal line 212 are made of conductive materials. For example, the first signal line 211 and the second signal line 212 are formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0059] The first signal line 211 and the second signal line 212 extend along the first direction D1. That is to say, the connection line between one end and the other end of the first signal line 211 is parallel to the first direction D1, and the connection line between one end and the other end of the second signal line 212 is parallel to the first direction D1. The first signal line 211 and the second signal line 212 are arranged along the second direction D2, and the first direction D1 is different from the second direction D2. That is to say, the extension line of the first signal line 211 in the extension direction does not coincide with the extension line of the second signal line 212 in the extension direction, that is, the first signal line 211 and the second signal line 212 are arranged in a staggered manner.

[0060] In the embodiments of the present application, the different-layer setting means not being formed through the same patterning process. For example, other film layers are formed between two layers of materials by other film-forming processes.

[0061] As Figure 2 shown, the connection portion 214 is set on the same layer as the first signal line 211. The connection portion 214 can be formed through the same patterning process as the first signal line 211, thereby simplifying the manufacturing process of the display substrate 1.

[0062] The first signal line 211 and the second signal line 212 are configured to input different voltage signals. For example, the first signal line 211 may be a constant voltage signal, such as a gate high voltage (VGH), a gate low voltage (VGL), etc. The second signal line 212 may be an alternating current signal that alternates between a low level and a high level. For example, the second signal line 212 may be a scan signal, a clock signal, an electroluminescent signal (EM), etc.

[0063] The discharge module 20a may include components such as a thin film transistor 250 and a diode. For example, when the discharge module 20a includes the thin film transistor 250, the working principle of the discharge module 20a is to utilize the switching characteristics of the thin film transistor 250. When static electricity is generated, the thin film transistor 250 is quickly turned on, enabling the second signal line 212 to be connected to the first signal line 211 through the discharge module 20a to form a low-resistance static electricity discharge path, and quickly guiding the static electricity charge to the first signal line 211. When no static electricity is generated, the thin film transistor 250 is not turned on, so that the second signal line 212 is disconnected from the first signal line 211 through the discharge module 20a, thus not affecting the signal transmission of the second signal line 212.

[0064] Since one of the first signal line 211 and the second signal line 212 is connected to the discharge module 20a through the connection portion 214, the potential of the connection portion 214 is consistent with the potential of one of the first signal line 211 and the second signal line 212, and no electric field is generated between the connection portion 214 and one of the first signal line 211 and the second signal line 212. While the potential of the other of the first signal line 211 and the second signal line 212 is inconsistent with the potential of the connection portion 214. Since the connection portion 214 and the other of the first signal line 211 and the second signal line 212 are arranged on the same layer, when the distance between the connection portion 214 and the other of the first signal line 211 and the second signal line 212 is relatively small, the electric field intensity is relatively large. When the display substrate 1 is in a humid environment, the connection portion 214 and the other of the first signal line 211 and the second signal line 212 are prone to electrochemical corrosion under the action of the electric field, resulting in the failure of the protection unit 20. Therefore, the distance s1 between the other of the first signal line 211 and the second signal line 212 and the connection portion 214 is set to be greater than the distance s2 between one of the first signal line 211 and the second signal line 212 and the connection portion 214, so as to increase the distance s1 between the other of the first signal line 211 and the second signal line 212 and the connection portion 214, reduce the electric field intensity between the other of the first signal line 211 and the second signal line 212 and the connection portion 214, and reduce the risk of electrochemical corrosion.

[0065] In some embodiments, the distance s1 between the other one of the first signal line 211 and the second signal line 212 and the connection portion 214 is greater than 5 microns. For example, s1 is 6 microns, 7 microns, 8 microns, 9 microns, 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, 15 microns, etc.

[0066] In some embodiments, the distance s2 between one of the first signal line 211 and the second signal line 212 and the connection portion 214 can be as small as possible according to the process capability, so as to avoid increasing the distance between the first signal line 211 and the second signal line 212 and avoid increasing the occupied area of the protection unit 20. The distance s2 between one of the first signal line 211 and the second signal line 212 and the connection portion 214 is 2 microns to 5 microns. For example, s2 is 2 microns, 3 microns, 4 microns, 5 microns, etc.

[0067] Optionally, the discharge module 20a includes a plurality of thin film transistors 250 arranged along the first direction D1. The thin film transistor 250 includes a gate 251, and adjacent gates 251 are connected to form a gate line 221. The first signal line 211 is disposed on a side of the gate 251 away from the substrate 10; the protection unit 20 further includes a resistor portion 231, and one of the first signal line 211 and the second signal line 212 is connected to the connection portion 214 through the resistor portion 231; wherein, the connection portion 214 and the resistor portion 231 are connected through a via 241, and the connection portion 214 and the gate line 221 are connected through another via 241, and the two vias 241 are arranged along the first direction D1.

[0068] As Figure 2 shown, the positive projection of the gate line 221 on the substrate 10 is located in the middle region of the active portion 252, and the overlapping region between the gate line 221 and the active portion 252 is the channel region of the thin film transistor 250.

[0069] The material of the gate line 221 is a conductive material. For example, the gate line 221 is formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0070] As Figure 1 shown, the positive projection of the gate line 221 on the substrate 10 is located between the positive projections of the first signal line 211 and the second signal line 212 on the substrate 10, which means that the gate line 221 does not overlap with the first signal line 211 and the second signal line 212.

[0071] The material of the resistor portion 231 is a semiconductor material, such as amorphous silicon, polycrystalline silicon, metal oxide semiconductor, etc.

[0072] In some embodiments, as Figure 2As shown, the resistor portion 231 is in a zigzag shape, which means that the extending direction of the resistor portion 231 is not a straight line but has multiple extending directions. For example, a part of the resistor portion 231 can extend along the first direction D1, and another part can extend along the second direction D2. Through the above arrangement, the length of the resistor portion 231 can be extended within as small a space as possible, thereby increasing the impedance of the resistor portion 231. By increasing the impedance of the resistor portion 231, it is less likely for the resistor portion 231 to be broken down by static electricity.

[0073] In some embodiments, as Figure 2 shown, the orthographic projection of the resistor portion 231 on the substrate 10 is located between the first signal line 211, the second signal line 212, and the gate line 221. The orthographic projections of the first signal line 211, the second signal line 212, and the gate line 221 on the substrate 10 do not overlap with the orthographic projection of the resistor portion 231 on the substrate 10, thereby avoiding the electric field generated by the first signal line 211, the second signal line 212, and the gate line 221 from affecting the impedance of the resistor portion 231.

[0074] Since the resistor portion 231, the second signal line 212, and the gate line 221 are all located in different film layers, and the different film layers are separated by an insulating layer. Therefore, in order to realize the connection between the resistor portion 231 and the gate line 221, a connection portion 214 needs to be provided.

[0075] Specifically, as Figure 2 and Figure 3 shown, the gate line 221 and the resistor portion 231 are both provided on the side of the first signal line 211 close to the substrate 10. The connection portion 214 is connected to the resistor portion 231 through a via 241, and the via 241 penetrates the insulating layer between the connection portion 214 and the resistor portion 231, and the connection portion 214 is deposited in the via 241. The connection portion 214 is connected to the gate line 221 through another via 241, and the via 241 penetrates the insulating layer between the connection portion 214 and the gate line 221, and the connection portion 214 is deposited in the via 241.

[0076] It should be understood that in the embodiments of the present application, when it is necessary to electrically connect conductive materials or semiconductor materials in different film layers, it can be achieved through the via 241.

[0077] As Figure 2 shown, the two vias 241 are arranged along the first direction D1, which means that the connection line of the centers of the two vias 241 extends along the first direction D1. Through the above arrangement, the length direction of the connection portion 214 can be parallel to the first direction D1, thereby reducing the dimension of the connection portion 214 in the direction perpendicular to the first direction D1, that is, reducing the width of the connection portion 214, increasing the minimum distance between the connection portion 214 and the other one of the first signal line 211 and the second signal line 212, and further reducing the risk of electrochemical corrosion.

[0078] Optionally, as Figure 2 and Figure 3 shown, one end of the resistor portion 231 away from the connection portion 214 is connected to one of the first signal line 211 and the second signal line 212.

[0079] In some embodiments, a bridging portion 213 is continuously provided at an edge of one of the first signal line 211 and the second signal line 212. The bridging portion 213 is connected to the resistor portion 231 through a via 241. The distance s3 between the other of the first signal line 211 and the second signal line 212 and the bridging portion 213 is greater than the distance s1 between the other of the first signal line 211 and the second signal line 212 and the connection portion 214.

[0080] The bridging portion 213 is continuously provided with one of the first signal line 211 and the second signal line 212, that is to say, the bridging portion 213 is provided on the same layer and continuously with one of the first signal line 211 and the second signal line 212.

[0081] The distance s3 between the other of the first signal line 211 and the second signal line 212 and the bridging portion 213 is greater than the distance s1 between the other of the first signal line 211 and the second signal line 212 and the connection portion 214. That is to say, the bridging portion 213 is located on the side of the connection portion 214 close to one of the first signal line 211 and the second signal line 212. Through the above settings, the bridging portion 213 can be made as close as possible to one of the first signal line 211 and the second signal line 212, avoiding the bridging portion 213 occupying a large area, thereby leaving a larger layout space for the resistor portion 231 and ensuring that the resistor portion 231 has sufficient length to increase the impedance of the resistor portion 231.

[0082] Optionally, as Figure 2 and Figure 3 shown, the thin film transistor 250 includes an active portion 252, a drain 253 and a source 254. The active portion 252 is provided on the same layer as the resistor portion 231 and the active portion 252 extends along the second direction D2; the drain 253 and the source 254 are provided on the same layer as the first signal line 211. The first signal line 211 is connected to one end of the active portion 252 through the drain 253, and the second signal line 212 is connected to the other end of the active portion 252 through the source 254.

[0083] In some embodiments, the active portion 252 is provided on the same layer as the resistor portion 231, so that the active portion 252 and the resistor portion 231 can be formed by the same patterning process, simplifying the manufacturing process of the display substrate 1. That is to say, the active portion 252 and the resistor portion 231 are made of the same material.

[0084] In some embodiments, the first signal line 211 is on the same layer as and continuous with the drain 253, and the first signal line 211 is used to provide the drain 253 signal for the thin film transistor 250. The second signal line 212 is on the same layer as and continuous with the source 254, and the second signal line 212 is used to provide the source 254 signal for the thin film transistor 250.

[0085] As Figure 4 shown, the protection unit 20 utilizes the conduction characteristic of the thin film transistor 250 to control the discharge of electrostatic charges. The electrostatic protection principle of the protection unit 20 will be described below. As shown in (a), when no electrostatic discharge occurs, the thin film transistor 250 is in the cut-off state, that is, the thin film transistor 250 is not conducting. At this time, the thin film transistor 250 does not affect the signal transmission of the second signal line 212. As shown in (b) and (c), when an electrostatic discharge occurs, by controlling the gate 251 voltage of the thin film transistor 250, the thin film transistor 250 is turned on, forming an electrostatic discharge path from the second signal line 212 to the first signal line 211. The first signal line 211 can conduct the static electricity to one of the VGL signal trace or the VGH signal trace.

[0086] Specifically, in one embodiment, please refer to Figure 2 and Figure 4 , connect the drain 253 of the thin film transistor 250 to the first signal line 211, connect the source 254 to the second signal line 212, and connect the gate 251 to one of the first signal line 211 and the second signal line 212 through the resistor portion 231. When an electrostatic discharge pulse appears on the second signal line 212, the voltage of the source 254 rises rapidly, and the resistor portion 231 has a current limiting effect, so that the voltage of the gate 251 does not rise rapidly, making the thin film transistor 250 meet the conduction condition and thus turning on the thin film transistor 250, discharging the electrostatic charges to the first signal line 211, and the first signal line 211 discharges the electrostatic charges to other structures.

[0087] In some embodiments, the thin film transistor 250 can be a PMOS (P-channel Metal-Oxide-Semiconductor). The conduction condition of the PMOS is Vgs < Vth, where Vgs is the gate-source voltage, that is, the voltage difference between the gate 251 and the source 254 of the PMOS, that is, Vgs = VG - VS. Vth is the threshold voltage, that is, the absolute value of the minimum gate-source voltage required for the PMOS to start conducting.

[0088] As Figure 4As shown, G corresponds to the gate 251 of the thin film transistor 250, S corresponds to the source 254 of the thin film transistor 250, and D corresponds to the drain 253 of the thin film transistor 250. INPUT corresponds to the signal connected to the second signal line 212, and VGH and VGL correspond to the signals connected to the first signal line 211. VG is the voltage at point G, and VS is the voltage at point S.

[0089] As Figure 4 shown in (a) of [], when electrostatic discharge does not occur, the thin film transistor 250 is configured to satisfy Vgs > Vth, and the thin film transistor 250 is in the cut-off state.

[0090] As Figure 4 shown in (b) of [], when INPUT is a positive voltage, after electrostatic discharge occurs, the VS voltage increases rapidly. Since Vgs = VG - VS, Vgs decreases, satisfying Vgs < Vth, and the thin film transistor 250 is in the on state. The static electricity is discharged along the second signal line 212 to the first signal line 211, so that the second signal line 212 is protected from electrostatic damage. The arrow in (b) is the path of the electrostatic discharge.

[0091] As Figure 4 shown in (c) of [], when INPUT is a negative voltage, after electrostatic discharge occurs, the VS voltage increases rapidly. Since a resistance portion 231 is provided between the source 254 and the gate 251 of the thin film transistor 250, the resistance portion 231 limits the static electricity current, so that the current flowing to the gate 251 does not become very large instantaneously, thereby slowing down the rising speed of the voltage of the gate 251. That is to say, at the moment of electrostatic discharge, VG remains unchanged. Since Vgs = VG - VS, Vgs decreases, satisfying Vgs < Vth, and the thin film transistor 250 is in the on state. The static electricity is discharged along the second signal line 212 to the first signal line 211, so that the second signal line 212 is protected from electrostatic damage. The arrow in (c) is the path of the electrostatic discharge.

[0092] Optionally, as Figure 1 and Figure 2 shown, two adjacent active portions 252 are connected and arranged in the first direction D1. The drain 253 is integrally provided with the first signal line 211, and the source 254 is integrally provided with the second signal line 212. Through the above settings, the number of thin film transistors 250 can be increased without increasing the floor area of the thin film transistor 250, thereby increasing the electrostatic discharge path and further improving the electrostatic protection effect.

[0093] Optionally, as Figure 1 and Figure 2 shown, there are multiple discharge modules 20a. The multiple discharge modules 20a are arranged along the second direction D2, and a first signal line 211 or a second signal line 212 is provided between two adjacent discharge modules 20a.

[0094] Optionally, as Figure 1 and Figure 2 shown, the protection unit 20 includes two first signal lines 211 and a second signal line 212 disposed between the two first signal lines 211; wherein, thin film transistors 250 are disposed on both sides of the second signal line 212, and the gate lines 221 on both sides of the second signal line 212 are connected. Through the above arrangement, a plurality of thin film transistors 250 can be disposed on both sides of the second signal line 212, thereby further increasing the number of thin film transistors 250, increasing the electrostatic discharge path, and further improving the electrostatic protection effect.

[0095] Optionally, as Figure 1 shown, the first signal line 211 includes a first sub-line 211a, and the voltage of the first sub-line 211a is less than the voltage of the second signal line 212; wherein, the second signal line 212 is connected to the discharge module 20a through a connection portion 214, and the distance s1 between the first sub-line 211a and the connection portion 214 is greater than the distance s2 between the second signal line 212 and the connection portion 214.

[0096] As Figure 4 shown in (c) of

[0097] Optionally, as Figure 1 shown, the display substrate 1 further includes a first voltage line 222 extending along the second direction D2, the first sub-line 211a is connected to the first voltage line 222, the first sub-line 211a includes a connected first main segment 2111 and a first connection segment 2112, the first main segment 2111 is connected to the discharge module 20a, the first connection segment 2112 is located between the first main segment 2111 and the first voltage line 222, and the width w1 of the first connection segment 2112 is less than the width w2 of the first main segment 2111.

[0098] The first main segment 2111 is connected to the drain 253 of the thin film transistor 250. The first connection segment 2112 connects the first main segment 2111 and the first voltage line 222. The first connection segment 2112 corresponds to the connection portion 214 and the resistance portion 231, that is to say, the resistance portion 231 is disposed on one side in the width w1 direction of the first connection segment 2112.

[0099] Optionally, the first signal line 211 includes a second sub-line 211b, and the voltage of the second sub-line 211b is greater than the voltage of the second signal line 212; wherein, the second sub-line 211b is connected to the discharge module 20a through a connection portion 214, and the distance between the second signal line 212 and the connection portion 214 is greater than the distance between the second sub-line 211b and the connection portion 214.

[0100] As Figure 4 As shown in (b) therein, the second sub-line 211b can input a VGH signal. The second signal line 212 can input an INPUT signal. During electrostatic discharge, Vgs < Vth, the thin film transistor 250 is in the on state, and the static electricity is discharged along the second signal line 212 to the second sub-line 211b, so that the second signal line 212 is protected from electrostatic damage. The arrow in (b) is the path of static electricity discharge.

[0101] The width w1 of the first connection segment 2112 is smaller than the width w2 of the first main segment 2111. By the above setting, the width w1 of the first connection segment 2112 can be reduced, the distance between the first connection segment 2112 and the connection portion 214 can be increased, and the risk of electrochemical corrosion can be further reduced.

[0102] Optionally, the first main segment 2111 is connected to the discharge module 20a on one side through a via 241, and the first main segment 2111 is connected to the discharge module 20a on the other side through another via 241. The two vias 241 are arranged along the second direction D2. Since the width of the first main segment 2111 is relatively wide, the part of the width of the first main segment 2111 that exceeds the first connection segment 2112 can be used to overlap with the via to realize the electrical connection between the first main segment 2111 and the discharge module 20a.

[0103] Optionally, the display substrate 1 further includes a second voltage line 223 extending along the second direction D2. The second sub-line 211b is connected to the second voltage line 223. The second sub-line 211b includes a connected second main segment 2113 and a second connection segment 2114. The second main segment 2113 is connected to the discharge module 20a. The second connection segment 2114 is located between the second main segment 2113 and the second voltage line 223. The width w3 of the second connection segment 2114 is smaller than the width w4 of the second main segment 2113.

[0104] The second main segment 2113 is connected to the drain 253 of the thin film transistor 250. The second connection segment 2114 connects the second main segment 2113 and the second voltage line 223. The second connection segment 2114 corresponds to the connection portion 214 and the resistor portion 231. That is to say, the resistor portion 231 is provided on one side in the width w3 direction of the second connection segment 2114.

[0105] The width w3 of the second connecting section 2114 is smaller than the width w4 of the second main section 2113. With the above arrangement, the width w3 of the second connecting section 2114 can be reduced, increasing the distance between the second connecting section 2114 and the connecting portion 214, and further reducing the risk of electrochemical corrosion.

[0106] Optionally, the second main section 2113 is connected to the discharge module 20a on one side through a via 241, and the second main section 2113 is connected to the discharge module 20a on the other side through another via 241. The two vias 241 are arranged along the second direction D2. Since the width of the second main section 2113 is relatively wide, the part of the width of the second main section 2113 that exceeds the second connecting section 2114 can be used to overlap with the via 241 to achieve the electrical connection between the second main section 2113 and the discharge module 20a.

[0107] In some embodiments, both the first voltage line 222 and the second voltage line 223 are configured to input a constant voltage signal, and the voltage value of the first voltage line 222 is less than the voltage value of the second voltage line 223.

[0108] In some embodiments, the first voltage line 222 and the second voltage line 223 are arranged on the same layer. For example, the first voltage line 222, the second voltage line 223, and the gate line 221 are all arranged on the same layer. With the above arrangement, the first voltage line 222, the second voltage line 223, and the gate line 221 can be formed by the same patterning process, thus simplifying the manufacturing process of the display substrate 1.

[0109] In some embodiments, the first voltage line 222 is configured to input a VGL voltage, and the second voltage line 223 is configured to input a VGH voltage. The VGL voltage can be between -5 volts and -10 volts, but is not limited thereto. The VGH voltage can be between 20 volts and 35 volts, but is not limited thereto. The second signal line 212 is configured to input an AC signal.

[0110] As Figure 4 shown in (c) of [], when INPUT is a negative voltage, that is, the AC signal of the second signal line 212 is at a low level. After electrostatic discharge, the VS voltage increases rapidly. Since a resistance portion is provided between the source 254 and the gate 251 of the thin film transistor 250, the resistance portion limits the static electricity, so that the current flowing to the gate 251 will not become very large instantaneously, thereby slowing down the rising speed of the voltage of the gate 251. That is to say, at the moment of electrostatic discharge, VG remains unchanged. Since Vgs = VG - VS, then Vgs decreases, satisfying Vgs < Vth, and the thin film transistor 250 is in the on state. The static electricity is discharged to the first sub-line 211a through the thin film transistor 250, and then conducted to the first voltage line 222 via the first sub-line 211a, so that the second signal line 212 is protected from electrostatic damage.

[0111] AsFigure 4 As shown in (b), when INPUT is a positive voltage, that is, the AC signal of the second signal line 212 is at a high level, after electrostatic discharge occurs, the VS voltage increases rapidly. Since a resistor portion is provided between the source 254 and the gate 251 of the thin film transistor 250, the resistor portion limits the electrostatic current, so that the current flowing to the gate 251 will not become very large instantaneously, thereby slowing down the rising speed of the voltage of the gate 251. That is to say, at the moment of electrostatic discharge, VG remains unchanged. Since Vgs = VG - VS, then Vgs decreases, satisfying Vgs < Vth, and the thin film transistor 250 is in an on state. The static electricity is discharged along the thin film transistor 250 to the second sub-line 211b, and then conducted to the second voltage line 223 via the second sub-line 211b, so that the second signal line 212 for transmitting the AC signal is protected from electrostatic damage. Through the above arrangement, the voltage of the second signal line 212 for transmitting the AC signal can be maintained between VGL + Vth and VGH - Vth, preventing the voltage of the second signal line 212 for transmitting the AC signal from being too high or too low to cause electrostatic damage.

[0112] Since the first sub-line 211a is electrically connected to the first voltage line 222 and the second sub-line 211b is electrically connected to the second voltage line 223, therefore, the first sub-line 211a and the second sub-line 211b need to be arranged at intervals to ensure their insulation; at the same time, arranging the first sub-line 211a and the second sub-line 211b in a common line can make the structure of the protection unit 20 compact and reduce the space occupied by the protection unit 20.

[0113] Among them, arranging in a common line means that the extension lines of the central axes of the two traces coincide. It should be noted that arranging in a common line means coincidence within the allowable range of process errors. When the extension lines of the central axes of the two traces deviate and do not coincide due to process errors, it should also be understood as arranging in a common line.

[0114] Optionally, as Figure 1 shown, since the first voltage line 222 and the second voltage line 223 are configured to input different voltages and the first voltage line 222 and the second voltage line 223 are arranged on the same layer, in order to avoid forming an electric field between them due to too close a distance and causing electrochemical corrosion, the discharge module 20a can be arranged between the first voltage line 222 and the second voltage line 223, so that the distance between the first voltage line 222 and the second voltage line 223 is larger.

[0115] According to the second aspect of the present application, as Figure 5 shown, a display panel 2 is provided, including the above-mentioned display substrate 1.

[0116] In this embodiment, as Figure 5As shown, the display panel 2 includes a display substrate 1. The display panel 2 can be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0117] As Figure 5 shown, the display panel 2 includes a display area AA and a non-display area NA disposed around the display area AA. The display area AA can be provided with a plurality of sub-pixels, and the sub-pixels can include red sub-pixels, green sub-pixels, and blue sub-pixels, so as to achieve color display. The non-display area NA can be provided with a driving circuit, such as a gate driving circuit, etc., and the driving circuit can provide driving signals for the sub-pixels.

[0118] The non-display area NA is provided with a bonding portion for bonding and connecting with a bonding member or the like. The bonding member includes a driving chip, a chip-on-film, a flexible circuit board, etc. The bonding member is used to input driving signals to the display panel 2 to control the display of the sub-pixels.

[0119] The display substrate 1 can be a driving substrate of the display panel 2. The protection unit 20 can be located in the display area AA or the non-display area NA. For example, Figure 5 the case where the protection unit 20 is located in the display area AA is taken as an example for illustration. The protection unit 20 can be located between the bonding portion and the display area AA, or the protection unit 20 can be located on the side of the bonding portion away from the display area AA.

[0120] According to the third aspect of the present application, as Figure 6 shown, a display terminal 3 is provided, including the above-mentioned display panel 2.

[0121] In some embodiments, the display terminal 3 includes a display panel 2 and a terminal body 4, and the display panel 2 and the terminal body 4 are combined into one.

[0122] In some embodiments, the display terminal 3 is a wearable device, such as a watch, glasses, etc.

[0123] In this embodiment, the display terminal 3 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. Figure 6 The case of a watch is taken as an example for illustration, but it should not be construed as a limitation to the present application.

[0124] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0125] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0126] Among the embodiments, implementation manners and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0127] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display substrate (1), characterized in that, The invention comprises a substrate (10) and a protection unit (20) arranged on one side of the substrate (10), wherein the protection unit (20) comprises: A first signal line (211) and a second signal line (212) are arranged in the same layer, the first signal line (211) and the second signal line (212) extend along a first direction (D1) and are arranged along a second direction (D2), the second direction (D2) being different from the first direction (D1); A connecting portion (214) is provided on the same layer as the first signal line (211) and the second signal line (212); a discharge module (20a) disposed between the first signal line (211) and the second signal line (212); the second signal line (212) being connected to the first signal line (211) through the discharge module (20a); and one of the first signal line (211) and the second signal line (212) being connected to the discharge module (20a) through the connection portion (214) to control the discharge module (20a) so that the second signal line (212) is connected to or disconnected from the first signal line (211) through the discharge module (20a); Wherein, in the second direction (D2), the distance between the other of the first signal line (211) and the second signal line (212) and the connecting portion (214) is greater than the distance between the one of the first signal line (211) and the second signal line (212) and the connecting portion (214).

2. The display substrate (1) according to claim 1, wherein The discharge module (20a) comprises a plurality of thin film transistors (250) arranged along the first direction (D1), the thin film transistors (250) comprising gate electrodes (251), adjacent gate electrodes (251) being connected to form a gate line (221), and the first signal line (211) being arranged on a side of the gate electrodes (251) facing away from the substrate (10); The protection unit (20) further includes a resistor portion (231), wherein the one of the first signal line (211) and the second signal line (212) is connected to the connection portion (214) via the resistor portion (231); The connecting portion (214) is connected to the resistor portion (231) via a via hole (241), and the connecting portion (214) is connected to the gate line (221) via another via hole (241), and the two via holes (241) are arranged along the first direction (D1).

3. The display substrate (1) according to claim 2, characterized in that, The thin film transistor (250) includes an active portion (252), a drain electrode (253) and a source electrode (254); the active portion (252) is arranged in the same layer as the resistor portion (231) and the active portion (252) extends along the second direction (D2); the drain electrode (253) and the source electrode (254) are arranged in the same layer as the first signal line (211); the first signal line (211) is connected to one end of the active portion (252) through the drain electrode (253), and the second signal line (212) is connected to the other end of the active portion (252) through the source electrode (254).

4. The display substrate (1) according to claim 3, characterized in that, Two adjacent ones of the active parts (252) are connected and arranged in the first direction (D1). The drain electrode (253) is integrally provided with the first signal line (211), and the source electrode (254) is integrally provided with the second signal line (212).

5. The display substrate (1) according to claim 1, characterized in that, There are multiple discharge modules (20a). The multiple discharge modules (20a) are arranged along the second direction (D2). The first signal line (211) or the second signal line (212) is arranged between two adjacent discharge modules (20a).

6. The display substrate (1) according to any one of claims 1 to 5, characterized in that, The first signal line (211) includes a first sub-line (211a). The first sub-line (211a) is configured to input a low gate voltage. The voltage of the first sub-line (211a) is less than the voltage of the second signal line (212). Among them, the second signal line (212) is connected to the discharge module (20a) through the connection part (214). The distance between the first sub-line (211a) and the connection part (214) is greater than the distance between the second signal line (212) and the connection part (214).

7. The display substrate (1) according to claim 6, characterized in that, The display substrate (1) further includes a first voltage line (222) extending along the second direction (D2). The first sub-line (211a) is connected to the first voltage line (222). The first sub-line (211a) includes a connected first main segment (2111) and a first connection segment (2112). The first main segment (2111) is connected to the discharge module (20a). The first connection segment (2112) is located between the first main segment (2111) and the first voltage line (222). The width (w1) of the first connection segment (2112) is less than the width (w2) of the first main segment (2111).

8. The display substrate (1) according to claim 7, characterized in that, The first main segment (2111) is connected to the discharge module (20a) on one side through a via hole (241). The first main segment (2111) is connected to the discharge module (20a) on the other side through another via hole (241). The two via holes (241) are arranged along the second direction (D2).

9. The display substrate (1) according to any one of claims 1 to 5, characterized in that, The first signal line (211) includes a second sub-line (211b). The second sub-line (211b) is configured to input a high gate voltage. The voltage of the second sub-line (211b) is greater than the voltage of the second signal line (212). Among them, the second sub-line (211b) is connected to the discharge module (20a) through the connection part (214). The distance between the second signal line (212) and the connection part (214) is greater than the distance between the second sub-line (211b) and the connection part (214).

10. The display substrate (1) according to claim 9, characterized in that, The display substrate (1) further includes a second voltage line (223) extending along the second direction (D2). The second sub-line (211b) is connected to the second voltage line (223). The second sub-line (211b) includes a connected second main section (2113) and a second connection section (2114). The second main section (2113) is connected to the discharge module (20a). The second connection section (2114) is located between the second main section (2113) and the second voltage line (223). The width (w3) of the second connection section (2114) is smaller than the width (w4) of the second main section (2113).

11. The display substrate (1) according to claim 10, characterized in that, The second main section (2113) is connected to the discharge module (20a) on one side through a via hole (241), and the second main section (2113) is connected to the discharge module (20a) on the other side through another via hole (241). The two via holes (241) are arranged along the second direction (D2).

12. A display panel (2), characterized in that, A display substrate (1) according to any one of claims 1 to 11 is included.

13. A display terminal (3), characterized in that, A display panel (2) according to claim 12 is included.

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