OLED (Organic Light Emitting Diode) pixel driving circuit based on MRAM (Magnetic Random Access Memory)

Abstract

The invention discloses an MRAM (Magnetic Random Access Memory)-based OLED (Organic Light Emitting Diode) pixel driving circuit, and relates to the technical field of liquid crystal display, the MRAM-based OLED pixel driving circuit comprises a signal input module, a reset compensation module, a control module and a driving module which are adaptively connected, the driving module comprises an MRAM and a driving tube connected with the output end of the MRAM, and the driving tube is connected with a light emitting device; the OLED pixel driving circuit based on the MRAM comprises a reset stage, a compensation stage, a transmitting stage and a closing stage which are carried out in sequence in a working period, a data signal is input to a reset compensation module by a signal input module in the compensation stage, and the reset compensation module provides compensation voltage for a control module according to the data signal; a scanning signal is input to the control module through the signal input module in the emission stage, the control module controls the magnetic moment state of the MRAM according to the scanning signal and the compensation voltage, and the MRAM is used for controlling the conduction state of the driving tube so as to control the light-emitting state of the light-emitting device. The circuit effectively improves the driving linearity and reduces the power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal display, and in particular to an MRAM-based OLED pixel driving circuit. Background Art

[0002] As a new generation of display technology, organic light-emitting diodes (OLEDs) are widely used in smartphones, wearable devices and micro-display fields due to their self-luminescence, high contrast, ultra-thinness and flexibility.

[0003] Figure 1 The structure of a typical traditional OLED pixel driving circuit (2T-1C pixel driving circuit) is shown. It consists of a switching transistor, a driving transistor, and a capacitor. Its operating principle is: the control voltage (WL) turns on the switching transistor in the circuit and stores the data voltage (VDATA) in the capacitor. The capacitor is used to set the bias voltage between the gate and source of the driving transistor. At this time, the driving transistor converts the voltage level stored in the capacitor into a driving current. The drain or source of the driving transistor is connected to the OLED, and the OLED light intensity is controlled by controlling the magnitude of the driving current. When the switching transistor is turned off, the driving current can still be maintained by the capacitor. This circuit has the following defects:

[0004] (1) The linear range is narrow and the grayscale control accuracy is limited

[0005] Figure 2 The simulation image of the driving current in the above 2T-1C pixel driving circuit changes with the data voltage (0-5V) is shown. Figure 2 As can be seen, when VDATA is in the 0-2.5V range, the drive current is very low, and the pixel driver circuit is not turned on. When VDATA is in the 3-4V range, the relationship between the drive current and VDATA can be roughly classified as linear. When VDATA is in the 2.5V-3V and 4V-4.15V ranges, the drive current varies nonlinearly with VDATA. When VDATA is higher than 4.15V, the drive current varies linearly with VDATA, but the rate of change is significantly different from that of 3V-4V. In summary, the above-mentioned 2T-1C pixel driver circuit can only achieve a good linear response when VDATA is between 3V and 4V, which limits the grayscale control accuracy when using the 2T-1C pixel driver circuit to drive OLEDs.

[0006] (2) High power consumption

[0007] Because the capacitor still maintains the driving current when the switching transistor of the above-mentioned 2T-1C pixel driving circuit is turned off, the OLED driven by the 2T-1C pixel driving circuit will continue to emit light after being illuminated and cannot be turned off by itself, resulting in a large amount of circuit power consumption.

[0008] As an example, Figure 3 The simulation results of driving a 4×4 pixel array by using the above-mentioned 2T-1C pixel driving circuit are shown. The 4×4 pixel array includes 4 pixel rows, each pixel row includes 4 pixel modules, and each pixel module is driven by a 2T-1C pixel driving circuit. The pixel driving circuits within the same pixel row are controlled by the same control signal. Figure 3 From top to bottom in the figure respectively represent the control signal WL1 of the first pixel row, the driving currents I0-I3 output by each pixel driving circuit within the first pixel row, the control signal WL2 of the second pixel row, the driving currents I4-I7 output by each pixel driving circuit within the second pixel row, the control signal WL3 of the third pixel row, the driving currents I8-I11 output by each pixel driving circuit within the third pixel row, the control signal WL4 of the fourth pixel row, and the driving currents I12-I15 output by each pixel driving circuit within the fourth pixel row.

[0009] As Figure 3 shown, the four pixel rows are sequentially controlled to be lit by the control signal. Once the pixel modules within a pixel row have been lit, then that pixel row will continue to emit light throughout the cycle. For example, after the pixel modules within the first pixel row are controlled by the control signal WL1 to be lit, they will still continue to emit light when the pixel modules within the second pixel row are controlled by the control signal WL2 to be lit. This results in a relatively high power consumption of the circuit when applying the above-mentioned pixel driving circuit. Taking the power supply voltage VDD as 5V, the charging and discharging current I of the capacitor in the pixel driving circuit as 50nA, the light-emitting cycle T of a single pixel module as 1ms, the driving current I1 as 25μA (the median value), and the duty cycle D of the pixel module as 0.5 as an example, calculate the power consumption P of a single 2T-1C pixel driving circuit in the 4×4 pixel array 2TIC =P static +P dynamic =VDD×I + VDD×I1×D×f = 5V×50nA + 5V×25μA×0.5×250Hz ≈ 15mW, where P static represents the static power consumption, and P dynamic represents the dynamic power consumption, and f represents the frequency.

[0010] (3) There are crosstalk and leakage problems

[0011] There will be crosstalk and leakage problems between adjacent pixel driving circuits in the pixel array, thus affecting the display effect of the pixel array. Summary of the Invention

[0012] In view of the above problems and technical requirements, the inventor of the present invention has proposed an OLED pixel driving circuit based on MRAM. The technical solution of the present invention is as follows:

[0013] An OLED pixel driving circuit based on MRAM, comprising a signal input module, a reset compensation module, a control module and a driving module which are adaptively connected. Among them,

[0014] The driving module includes an MRAM and a driving transistor connected to the output end of the MRAM, and the driving transistor is connected to a light-emitting device;

[0015] The OLED pixel driving circuit based on MRAM includes a reset stage, a compensation stage, an emission stage and a shutdown stage that are sequentially performed within one working cycle. Among them,

[0016] A data signal is input from the signal input module to the reset compensation module during the compensation stage, and the reset compensation module provides a compensation voltage for the control module according to the data signal;

[0017] A scan signal is input from the signal input module to the control module during the emission stage, and the control module controls the magnetic moment state of the MRAM according to the scan signal and the compensation voltage, and uses the MRAM to control the conduction state of the driving transistor so as to control the light-emitting state of the light-emitting device.

[0018] A further technical solution thereof is that the driving transistor includes an NMOS transistor T1, and the driving module further includes a capacitor C2, a PMOS transistor T2 and an NMOS transistor T3. Among them,

[0019] The free layer of the MRAM is connected to a reference voltage VREF, the fixed layer of the MRAM is connected to the drains of the PMOS transistor T2 and the NMOS transistor T3, the source of the PMOS transistor T2 is connected to a power supply voltage VDD, the source of the NMOS transistor T3 is grounded, and the gates of the PMOS transistor T2 and the NMOS transistor T3 are connected together to form a first node;

[0020] The output end of the MRAM is connected to the gate of the NMOS transistor T1 and one end of the capacitor C2, the other end of the capacitor C2 and the drain of the NMOS transistor T1 are connected to the power supply voltage VDD, the source of the NMOS transistor T1 is connected to the positive electrode of the light-emitting device, and the negative electrode of the light-emitting device is grounded.

[0021] A further technical solution thereof is that the MRAM includes an STT-MRAM, and the control module controls the current direction flowing through the STT-MRAM by controlling the voltage of the first node, thereby controlling the magnetic moment state of the STT-MRAM.

[0022] A further technical solution thereof is that the reset compensation module includes a capacitor C1, an NMOS transistor T4, an NMOS transistor T8 and an NMOS transistor T9;

[0023] The drain of the NMOS transistor T8 is connected to the source of the NMOS transistor T9 to form a second node. The drain of the NMOS transistor T9 is connected to its gate, and the second node is grounded through a capacitor C1.

[0024] The source of the NMOS transistor T4 is connected to the first node, and the drain of the NMOS transistor T4 is grounded.

[0025] The gates of the NMOS transistors T8 and T9 are connected to a first control signal, and the gate of the NMOS transistor T4 is connected to the light-emitting signal receiving node.

[0026] A further technical solution is that the control module includes a PMOS transistor T6. The source of the PMOS transistor T6 is connected to the second node, and the drain of the PMOS transistor T6 is connected to the first node.

[0027] A further technical solution is that the signal input module includes a PMOS transistor T5 and an NMOS transistor T7. Among them,

[0028] The drain of the PMOS transistor T5 is connected to the source of the NMOS transistor T7 to form a third node. The third node is connected to the gate of the PMOS transistor T6 and the source of the NMOS transistor T8.

[0029] The drain of the PMOS transistor T5 is connected to a scan signal, the drain of the NMOS transistor T7 is connected to a data signal, the gate of the PMOS transistor T5 is connected to the light-emitting signal receiving node, and the gate of the NMOS transistor T7 is connected to a second control signal.

[0030] A further technical solution is that it further includes an electromagnetic suppression module. The light-emitting signal receiving node is connected to the electromagnetic suppression module.

[0031] The electromagnetic suppression module is used to control the light-emitting signal to be input to the light-emitting signal receiving node when the drive control signal is valid.

[0032] The electromagnetic suppression module includes a PMOS transistor T10 and an NMOS transistor T11. The light-emitting signal receiving node is connected to the source of the PMOS transistor T10 and the drain of the NMOS transistor T11. The drain of the PMOS transistor T10 is connected to the power supply voltage VDD, the source of the NMOS transistor T10 is connected to the light-emitting signal, and the gates of the PMOS transistor T10 and the NMOS transistor T11 are connected to the drive control signal.

[0033] A further technical solution is that in the reset stage, the reset compensation module resets the voltage of the first node to the ground potential and resets the voltages of the second node and the third node according to the voltage of the first control signal.

[0034] In a further technical solution, during the compensation phase, the reset compensation module compensates the second node voltage to a compensation voltage, which is the sum of the absolute value of the threshold voltage of PMOS transistor T6 and the data signal voltage.

[0035] In a further technical solution, during the reset phase, the light emitting signal and the first control signal are at the second level, and the second control signal is at the first level;

[0036] During the compensation phase, the light emitting signal and the second control signal are at the second level, and the first control signal is at the first level;

[0037] During the emission phase, the light emitting signal, the first control signal, and the second control signal are all at the first level;

[0038] During the off phase, the light emitting signal is at the second level, and the first control signal and the second control signal are at the first level.

[0039] The beneficial technical effects of the present invention are as follows:

[0040] A pixel driving circuit for OLED based on MRAM is proposed. By utilizing the non-volatile storage characteristics of MRAM, persistent storage of grayscale data is achieved. Combining the scanning signal and the data signal can realize PWM constant current driving of OLED, improving the linearity of driving and solving the problem of narrow linear range of traditional pixel driving circuits, which is beneficial to constructing multi-level grayscale pixel circuits. At the same time, OLED can be self-turned off by MRAM, thus saving unnecessary circuit power consumption. In addition, an electromagnetic suppression module is designed, which can control the input state of the emission signal (EM signal) and eliminate crosstalk and leakage phenomena in the application of the pixel driving circuit in matrix displays. Brief Description of the Drawings

[0041] Figure 1 is the circuit schematic diagram of the traditional 2T-1C pixel driving circuit provided by the present invention.

[0042] Figure 2 is the simulation curve of the driving current varying with the data voltage in the 2T-1C pixel driving circuit.

[0043] Figure 3 is the simulation result diagram of driving a 4×4 pixel array using the 2T-1C pixel driving circuit.

[0044] Figure 4 is the circuit schematic diagram of an embodiment of the pixel driving circuit for OLED based on MRAM provided by the present invention.

[0045] Figure 5 is the circuit schematic diagram of an embodiment of the electromagnetic suppression module provided by the present invention.

[0046] Figure 6 It is a schematic diagram of the current flow and voltage transfer direction of the pixel driving circuit provided by the present invention during the reset stage.

[0047] Figure 7 It is a schematic diagram of the current flow and voltage transfer direction of the pixel driving circuit provided by the present invention during the compensation stage.

[0048] Figure 8 It is a schematic diagram of the current flow and voltage transfer direction of the pixel driving circuit provided by the present invention during the emission stage.

[0049] Figure 9 It is a schematic diagram of the current flow and voltage transfer direction of the pixel driving circuit provided by the present invention during the off stage.

[0050] Figure 10 It is a schematic diagram of the change of each signal voltage of the pixel driving circuit provided by the present invention during the working cycle.

[0051] Figure 11 It is a simulation result diagram of the OLED pixel driving circuit based on MRAM provided by the present invention.

[0052] Figure 12 It is a simulation curve of the turn-on time of the OLED in the OLED pixel driving circuit based on MRAM provided by the present invention changing with VDATA. Detailed implementation manners

[0053] The following further describes the detailed implementation manners of the present invention with reference to the accompanying drawings. It can be understood that the detailed implementation manners described herein are only used to explain the relevant content and are not intended to limit the present disclosure.

[0054] The present invention provides an OLED pixel driving circuit based on MRAM (Magnetic Random Access Memory), which includes a signal input module, a reset compensation module, a control module, and a driving module that are adaptively connected. Among them,

[0055] The driving module includes an MRAM and a driving transistor connected to the output end of the MRAM, and the driving transistor is connected to the light-emitting device;

[0056] The OLED pixel driving circuit based on MRAM includes a reset stage, a compensation stage, an emission stage, and an off stage that are sequentially performed during a working cycle. Among them,

[0057] During the compensation stage, the data signal is input from the signal input module to the reset compensation module, and the reset compensation module provides a compensation voltage for the control module according to the data signal;

[0058] During the emission stage, a scan signal is input from a signal input module to a control module. The control module controls the magnetic moment state of the MRAM according to the scan signal and a compensation voltage, and controls the on-state of a driving transistor by using the MRAM, so as to control the light-emitting state of a light-emitting device.

[0059] Please refer to Figure 4 In the pixel driving circuit provided by the present invention, a signal input module, a reset compensation module, a control module, and a driving module are adaptively connected. Specifically, it means that the signal input module is connected to the control module and the reset compensation module, and the control module is connected to the reset compensation module and the driving module.

[0060] The MRAM is a random access memory that stores data based on magnetoresistive properties. The MRAM operates based on MTJ (Magnetic Tunnel Junction). The MTJ generally consists of two ferromagnetic layers and a non-magnetic insulating layer. The two ferromagnetic layers are a fixed layer and a free layer respectively, and the non-magnetic insulating layer is disposed between the fixed layer and the free layer. The MRAM stores data by changing the magnitude of the magnetoresistance by changing the magnetic moment state (i.e., the magnetic moment state of the MTJ). The magnetic moment state is defined by the magnetic moment directions of the two ferromagnetic layers in the MTJ, including a parallel state and an anti-parallel state. Specifically, when the magnetic moment directions of the free layer and the fixed layer are the same, the MRAM is in the parallel state, and at this time, the MRAM exhibits a low-resistance state; when the magnetic moment directions of the free layer and the fixed layer are opposite, the MRAM is in the anti-parallel state, and at this time, the MRAM exhibits a high-resistance state.

[0061] In the present invention, the control module controls the magnetic moment state of the MRAM according to the scan signal and the compensation voltage, and controls the on-state of the driving transistor by using the change of the magnetoresistance of the MRAM. The controlling the light-emitting state of the light-emitting device by the on-state of the driving transistor specifically means that when the driving transistor is turned on, the light-emitting device is powered on and lit; on the contrary, when the driving transistor is turned off, the light-emitting device is turned off. Moreover, the magnitude of the current flowing through the light-emitting device each time the driving transistor controlled by the MRAM is turned on remains unchanged, so that constant current driving of the light-emitting device can be realized. By controlling the on-time of the driving transistor, the light-emitting brightness of the light-emitting device can be controlled, that is, the longer the on-time of the driving transistor, the longer the light-emitting time of the light-emitting device, and the higher the brightness of the light-emitting device. The light-emitting device includes but is not limited to an OLED. Compared with the scheme of controlling a driving transistor by using a capacitor voltage in a traditional pixel driving circuit, the pixel driving circuit provided by the present invention has a wider linear range, that is, the range in which a data signal and the light-emitting brightness have a linear relationship is larger, and can control the opening and closing of the light-emitting device by itself, reducing the power consumption of the circuit. The specific working principle of the OLED pixel driving circuit based on the MRAM can be referred to the following description.

[0062] Further, the driving transistor includes an NMOS transistor T1, and the driving module further includes a capacitor C2, a PMOS transistor T2, and an NMOS transistor T3, where

[0063] The free layer of the MRAM is connected to a reference voltage VREF, the fixed layer of the MRAM is connected to the drains of the PMOS transistor T2 and the NMOS transistor T3, the source of the PMOS transistor T2 is connected to a power supply voltage VDD, the source of the NMOS transistor T3 is grounded, and the gates of the PMOS transistor T2 and the NMOS transistor T3 are connected to form a first node;

[0064] The output terminal of the MRAM is connected to the gate of the NMOS transistor T1 and one end of the capacitor C2, the other end of the capacitor C2 and the drain of the NMOS transistor T1 are connected to the power supply voltage VDD, the source of the NMOS transistor T1 is connected to the positive electrode of the light-emitting device, and the negative electrode of the light-emitting device is grounded. The power supply voltage VDD > the reference voltage VREF > the ground potential GND.

[0065] In this embodiment, the MRAM used is specifically STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory), which is a type of MRAM that utilizes the spin-transfer torque effect to change the magnetic moment state by changing the direction of the current flowing through the magnetic tunnel junction. Specifically, when the current flows from the fixed layer to the free layer, the STT-MRAM is in the parallel state; when the current flows from the free layer to the fixed layer, the STT-MRAM is in the anti-parallel state.

[0066] The control module controls the voltage of the first node ( Figure 4 represented by point C in the figure) to control the direction of the current flowing through the STT-MRAM, thereby controlling the magnetic moment state of the STT-MRAM. Please refer to Figure 4 , the PMOS transistor T2 and the NMOS transistor T3 form an inverter. When the voltage of the first node is at a low level, the PMOS transistor T2 is turned on, and the current flows from the fixed layer to the free layer. The STT-MRAM is in the parallel state and presents a low-resistance state. The STT-MRAM outputs a low-level voltage from the output terminal to the gate of the NMOS transistor T1, and the NMOS transistor T1 is not turned on; when the voltage of the first node is at a high level, the NMOS transistor T3 is turned on, and the current flows from the free layer to the fixed layer. The STT-MRAM is in the anti-parallel state and presents a high-resistance state. The STT-MRAM outputs a high-level voltage from the output terminal to the gate of the NMOS transistor T1, and the NMOS transistor T1 is turned on, and the light-emitting device is powered on and lit.

[0067] It should be noted that the capacitor C2 in the driving module is used to reduce the current spike when the NMOS transistor T1 is turned on. Although the capacitor C2 will also store a certain voltage when the STT-MRAM outputs a high-level voltage to the gate of the NMOS transistor T1, since the capacitor C2 in the present invention is not used to store data signals, its capacitance value is generally small. After the STT-MRAM stops outputting a high-level voltage to the gate of the NMOS transistor T1, the stored voltage is difficult to turn on the NMOS transistor T1, and its influence on the on-state of the NMOS transistor T1 can be ignored.

[0068] Further, the reset compensation module includes a capacitor C1, an NMOS transistor T4, an NMOS transistor T8, and an NMOS transistor T9;

[0069] The drain of the NMOS transistor T8 is connected to the source of the NMOS transistor T9 to form a second node ( Figure 4 represented by point E in the figure), the drain of the NMOS transistor T9 is connected to the gate, and the second node is grounded through the capacitor C1; the source of the NMOS transistor T4 is connected to the first node, and the drain of the NMOS transistor T4 is grounded; the gates of the NMOS transistor T8 and the NMOS transistor T9 are connected to a first control signal ( Figure 4 represented by S1 in the figure), and the gate of the NMOS transistor T4 is connected to the light-emitting signal receiving node.

[0070] The control module includes a PMOS transistor T6, the source of the PMOS transistor T6 is connected to the second node, and the drain of the PMOS transistor T6 is connected to the first node.

[0071] The signal input module includes a PMOS transistor T5 and an NMOS transistor T7. Among them,

[0072] The drain of the PMOS transistor T5 is connected to the source of the NMOS transistor T7 to form a third node ( Figure 4 represented by point D in the figure), and the third node is connected to the gate of the PMOS transistor T6 and the source of the NMOS transistor T8;

[0073] The drain of the PMOS transistor T5 is connected to a scan signal ( Figure 4 represented by V sweep in the figure), the drain of the NMOS transistor T7 is connected to a data signal ( Figure 4 represented by VDATA in the figure), the gate of the PMOS transistor T5 is connected to the light-emitting signal receiving node, and the gate of the NMOS transistor T7 is connected to a second control signal ( Figure 4 represented by S2 in the figure). The specific working principles of the reset compensation module, the control module, and the signal input module can be referred to the following description.

[0074] To solve the problems of crosstalk and leakage existing in adjacent pixel driving circuits in a pixel array, an electromagnetic suppression module is provided in the pixel driving circuit, and the light-emitting signal receiving node is connected to the electromagnetic suppression module. As Figure 5 shown, the electromagnetic suppression module is used to control the input of the light-emitting signal to the light-emitting signal receiving node when the driving control signal ( Figure 5 represented by WL in

[0075] ) is valid.

[0076] The electromagnetic suppression module includes a PMOS transistor T10 and an NMOS transistor T11. The light-emitting signal receiving node is connected to the source of the PMOS transistor T10 and the drain of the NMOS transistor T11. The drain of the PMOS transistor T10 is connected to the power supply voltage VDD. The source of the NMOS transistor T10 is connected to the light-emitting signal. The gates of the PMOS transistor T10 and the NMOS transistor T11 are connected to the driving control signal.

[0077] Figures 6 - 9 Successively shown are the current flow and voltage transfer directions in the circuit of the OLED pixel driving circuit provided by the present invention during the reset stage, compensation stage, emission stage, and shutdown stage. Figure 10 Shown are the voltage change conditions of the light-emitting signal, first control signal, second control signal, and first to third node voltages during the reset stage, compensation stage, and emission stage. Figure 9 In Figures 6 - 10 each voltage waveform from top to bottom successively represents the light-emitting signal (EM), first control signal (S1), second control signal (S2), first node voltage (D), second node voltage (E), and third node voltage (C). Next, under the condition that the driving control signal is valid, the working principle of the OLED pixel driving circuit provided by the present invention will be specifically described according to

[0078] As Figure 10 shown, during the reset stage, the light-emitting signal and the first control signal are at the second level, and the second control signal is at the first level; in this embodiment, the first level is a low level, and the second level is a high level.

[0079] Specifically, the high level of the light-emitting signal, the first control signal, and the second control signal is defined as 8V, and the low level is defined as -3V. During the reset phase, the light-emitting signal and the first control signal are set to 8V, and the second control signal is set to -3V. As Figure 6 shown, at this time, the NMOS transistor T4 is turned on, discharging the voltage of the first node to a low level, that is, the voltage of the first node is at a low level. From the above description, it can be seen that at this time, the current flows from the fixed layer to the free layer, and the STT-MRAM is in the parallel state. The NMOS transistor T1 is not turned on, and the light-emitting device remains in the off state. At the same time, the NMOS transistors T8 and T9 are turned on. In the ideal state without considering the conduction loss of the NMOS transistors, the voltage of the second node and the voltage of the third node will be charged to the voltage of the first control signal, that is, the voltages of the second node and the third node are equal to the voltage of the first control signal and are both 8V. It should be noted that Figure 10 is the simulation result considering the conduction loss of the NMOS transistors T8 and T9. As Figure 10 shown, the voltage of the second node is the value obtained by subtracting the conduction loss of the NMOS transistor T9 from the voltage of the first control signal, which is 5.73V. The voltage of the third node is the value obtained by subtracting the conduction loss of the NMOS transistor T8 from the voltage of the second node, which is 5.7V. Among them, the difference in the conduction loss of the NMOS transistors T8 and T9 is caused by the different connection methods of the NMOS transistors T8 and T9. The gate and drain of the NMOS transistor T9 are connected to form a diode connection, and its conduction loss is greater than that of the NMOS transistor T8.

[0080] The threshold voltage of the PMOS transistor T6 may change during application. To ensure that the threshold voltage of the PMOS transistor T6 does not affect the conduction state of the PMOS transistor T6 during the emission phase, the threshold voltage of the PMOS transistor T6 is compensated during the compensation phase. Specifically, during the compensation phase, the light-emitting signal and the second control signal are at the second level, and the first control signal is at the first level. In this embodiment, that is, during the compensation phase, the light-emitting signal and the second control signal are set to 8V, and the first control signal is set to -3V. As Figure 7As shown, NMOS transistor T7 and NMOS transistor T4 are turned on. The data signal (VDATA) is input from NMOS transistor T7 to the third node, and thus loaded to the gate of PMOS transistor T6, causing PMOS transistor T6 to turn on and form a source follower. After the voltage of the second node is discharged through PMOS transistor T6 and NMOS transistor to the sum of the data signal voltage and the absolute value of the threshold voltage of PMOS transistor T6, PMOS transistor T6 turns off. At this time, the voltage of the second node is the compensation voltage, and the capacitor C1 stores the compensation voltage at the second node. The compensation voltage can be expressed as VDATA + |VTH|, where VTH is the threshold voltage of PMOS transistor T6. At the same time, since NMOS transistor T4 is turned on, the first node is discharged to the ground potential, causing PMOS transistor T2 to turn on. The current still flows from the fixed layer to the free layer, and the STT-MRAM is in the parallel state. NMOS transistor T1 is not turned on, and the light-emitting device remains off.

[0081] In the emission stage, the light-emitting signal, the first control signal, and the second control signal are all at the first level. In this embodiment, that is, in the emission stage, the light-emitting signal, the first control signal, and the second control signal are all -3V. As Figure 8 shown, PMOS transistor T5 is turned on, and the scan signal (V sweep ) is input from PMOS transistor T5 to the third node. In this embodiment, the scan signal is a voltage signal that linearly decreases within the range of 5.5V to -2.5V within one working cycle. The conduction condition of PMOS transistor T6 is: V sweep - (VDATA + |VTH|) < VTH. After simplification, it can be obtained that when V sweep < VDATA, PMOS transistor T6 is turned on. The capacitance value of capacitor C1 is usually greater than the parasitic capacitance value of the first node. The voltage of the first node is charged to the voltage of the second node, and the voltage of the second node will not drop. At this time, NMOS transistor T3 is turned on, and the current flows from the free layer to the fixed layer. The STT-MRAM is in the anti-parallel state, and NMOS transistor T1 is turned on, and the light-emitting device is lit.

[0082] In the off stage, the light-emitting signal is at the second level, and the first control signal and the second control signal are at the first level. In this embodiment, that is, in the off stage, the light-emitting signal is 8V, and the first control signal and the second control signal are both -3V. As Figure 9 shown, NMOS transistor T4 is turned on, and the first node is discharged to the ground potential, causing PMOS transistor T2 to turn on. The current flows from the fixed layer to the free layer, and the STT-MRAM is in the parallel state. NMOS transistor T1 is not turned on, and the light-emitting device is turned off.

[0083] Figure 11 This is the simulation result of the OLED pixel driving circuit based on MRAM provided by the present invention. Figure 11Among them, the waveforms of pink, green, blue, purple, and red respectively represent the data signal, the scan signal, the voltage at the output terminal of the STT-MRAM, the current flowing through the light-emitting device (OLED), and the source voltage of the NMOS transistor T1. From Figure 11 it can be seen that when V sweep < VDATA, the voltage at the output terminal of the STT-MRAM changes from low level to high level, the driving transistor conducts, and there is a current of 8.6 μA flowing through the OLED. During one working cycle, at different VDATA voltages, the current flowing through the OLED is the same, but the conduction time of the driving transistor is different. The higher the VDATA voltage, the longer the conduction time of the driving transistor within one working cycle, the longer the conduction time of the OLED, and the higher the brightness of the OLED, and vice versa. Therefore, the conduction time of the driving transistor can be controlled by the voltage of VDATA, the conduction time of the OLED can be controlled, and thus the brightness of the OLED can be controlled, and the PWM constant current driving of the OLED can be realized.

[0084] Figure 12 is the curve of the conduction time of the OLED in the pixel driving circuit provided by the present invention changing with VDATA (0 - 5V). As Figure 12 it can be seen that when VDATA is between 0.8V and 5V, the conduction time of the OLED increases linearly therewith. The range of the linear change of the conduction time of the OLED with VDATA is relatively wide, which is beneficial to constructing a pixel circuit with multiple gray levels.

[0085] To verify the power consumption reduction effect of the pixel driving circuit provided by the present invention, it is assumed that the 4×4 pixel array described in the background art is driven by this pixel driving circuit, and it is assumed that it operates at full power under the same parameters (VDATA = 5V, I1 = 25 μA, OLED conduction time Time_on = 954 μs). The power consumption P of a single pixel driving circuit MRAM = VDD × I1 × D × f = 5V × 25 μA × 954 μs / 4000 μs × 250 Hz ≈ 7.5 mW. (P 2T1C - P MRAM ) / P 2T1C × 100% = 50%. It can be seen that the power consumption of the pixel driving circuit provided by the present invention is still reduced by 50% compared with the traditional 2T1C pixel driving circuit even under the full power operation condition, effectively reducing the circuit power consumption.

[0086] It should be noted that the words "first" and "second" used in the above description are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0087] The above are only the preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention shall be considered to be included within the protection scope of the present invention.

Claims

1. An OLED pixel driving circuit based on MRAM, characterized in that It includes a signal input module, a reset compensation module, a control module, and a driving module that are adaptively connected. Among them, the driving module includes an MRAM and a driving transistor connected to the output terminal of the MRAM, and the driving transistor is connected to a light-emitting device; the OLED pixel driving circuit based on MRAM includes a reset stage, a compensation stage, an emission stage, and a shutdown stage that are sequentially performed within one working cycle. Among them, a data signal is input from the signal input module to the reset compensation module during the compensation stage, and the reset compensation module provides a compensation voltage for the control module according to the data signal; a scan signal is input from the signal input module to the control module during the emission stage, and the control module controls the magnetic moment state of the MRAM according to the scan signal and the compensation voltage, and uses the MRAM to control the conduction state of the driving transistor to control the light-emitting state of the light-emitting device.

2. The OLED pixel driving circuit based on MRAM according to claim 1, wherein the driving transistor includes an NMOS transistor T1, and the driving module further includes a capacitor C2, a PMOS transistor T2, and an NMOS transistor T3. Among them, the free layer of the MRAM is connected to a reference voltage VREF, the fixed layer of the MRAM is connected to the drains of the PMOS transistor T2 and the NMOS transistor T3, the source of the PMOS transistor T2 is connected to a power supply voltage VDD, the source of the NMOS transistor T3 is grounded, and the gates of the PMOS transistor T2 and the NMOS transistor T3 are connected to form a first node; the output terminal of the MRAM is connected to the gate of the NMOS transistor T1 and one end of the capacitor C2, the other end of the capacitor C2 and the drain of the NMOS transistor T1 are connected to the power supply voltage VDD, the source of the NMOS transistor T1 is connected to the positive electrode of the light-emitting device, and the negative electrode of the light-emitting device is grounded.

3. The OLED pixel driving circuit based on MRAM according to claim 2, wherein the MRAM includes an STT-MRAM, and the control module controls the current direction flowing through the STT-MRAM by controlling the voltage of the first node, thereby controlling the magnetic moment state of the STT-MRAM.

4. The OLED pixel driving circuit based on MRAM according to claim 2, wherein the reset compensation module includes a capacitor C1, an NMOS transistor T4, an NMOS transistor T8, and an NMOS transistor T9; the drain of the NMOS transistor T8 is connected to the source of the NMOS transistor T9 to form a second node, the drain of the NMOS transistor T9 is connected to the gate, and the second node is grounded through the capacitor C1; the source of the NMOS transistor T4 is connected to the first node, and the drain of the NMOS transistor T4 is grounded; the gates of the NMOS transistor T8 and the NMOS transistor T9 are connected to a first control signal, and the gate of the NMOS transistor T4 is connected to a light-emitting signal receiving node.

5. The OLED pixel driving circuit based on MRAM according to claim 4, characterized in that, the control module includes a PMOS transistor T6, the source of the PMOS transistor T6 is connected to the second node, and the drain of the PMOS transistor T6 is connected to the first node.

6. The OLED pixel driving circuit based on MRAM according to claim 4, wherein, the signal input module includes a PMOS transistor T5 and an NMOS transistor T7. Among them, the drain of the PMOS transistor T5 is connected to the source of the NMOS transistor T7 to form a third node, and the third node is connected to the gate of the PMOS transistor T6 and the source of the NMOS transistor T8; The drain of the PMOS transistor T5 is connected to the scan signal, the drain of the NMOS transistor T7 is connected to the data signal, the gate of the PMOS transistor T5 is connected to the light-emitting signal receiving node, and the gate of the NMOS transistor T7 is connected to the second control signal.

7. The MRAM-based OLED pixel driving circuit according to claim 6, wherein It further includes an electromagnetic suppression module, and the light-emitting signal receiving node is connected to the electromagnetic suppression module; The electromagnetic suppression module is used to control the light-emitting signal to be input to the light-emitting signal receiving node when the drive control signal is valid; The electromagnetic suppression module includes a PMOS transistor T10 and an NMOS transistor T11. The light-emitting signal receiving node is connected to the source of the PMOS transistor T10 and the drain of the NMOS transistor T11. The drain of the PMOS transistor T10 is connected to the power supply voltage VDD, the source of the NMOS transistor T10 is connected to the light-emitting signal, and the gates of the PMOS transistor T10 and the NMOS transistor T11 are connected to the drive control signal.

8. The MRAM-based OLED pixel driving circuit according to claim 6, wherein In the reset stage, the reset compensation module resets the voltage of the first node to the ground potential and resets the voltages of the second node and the third node according to the voltage of the first control signal.

9. The MRAM-based OLED pixel driving circuit according to claim 6, wherein In the compensation stage, the reset compensation module compensates the voltage of the second node to the compensation voltage, and the compensation voltage is the sum of the absolute value of the threshold voltage of the PMOS transistor T6 and the data signal voltage.

10. The OLED pixel driving circuit based on MRAM according to claim 7, wherein, In the reset stage, the light-emitting signal and the first control signal are at the second level, and the second control signal is at the first level; In the compensation stage, the light-emitting signal and the second control signal are at the second level, and the first control signal is at the first level; In the emission stage, the light-emitting signal, the first control signal, and the second control signal are all at the first level; In the shutdown stage, the light-emitting signal is at the second level, and the first control signal and the second control signal are at the first level.

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