Pixel driving circuit, display device and method for driving display device

Abstract

The invention relates to a display device, a pixel driving circuit and a method for driving the display device. The display device includes a pixel driving circuit including: a first transistor including a gate electrode connected to a first node, a first electrode electrically connected to a first voltage line, and a second electrode connected to a second node; a second transistor including a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the first node; a sixth transistor including a gate electrode connected to the second emission line, a first electrode connected to the second node, and a second electrode connected to the third node; and a fourth transistor including a gate electrode connected to the second scan line, a first electrode connected to the third node, and a second electrode connected to the second voltage line, and an inactive period of the second emission control signal overlaps an active period of the second scan signal.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0016166, filed on February 1, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a pixel driving circuit capable of preventing deterioration of display quality. In addition, the present disclosure relates to a display device including the pixel driving circuit and a method for driving the display device. Background Art

[0004] Various display devices (such as televisions (TVs), cellular phones, tablet computers, navigation systems, and game consoles) have been developed. Notably, since portable display devices are battery-operated, many efforts have been made to reduce their power consumption.

[0005] One method of reducing power consumption is to reduce the operating frequency of the display device. For example, reducing the operating frequency when the display device is displaying a still image can help reduce its power consumption.

[0006] There is a need for a technology that can reduce the power consumption of a display device while maintaining high display quality. Summary of the Invention

[0007] Embodiments of the present disclosure provide a pixel driving circuit capable of preventing deterioration of display quality, a display device including the pixel driving circuit, and a method for driving the display device.

[0008] According to an embodiment of the present disclosure, a display device is provided, including: a display panel including a plurality of pixels; and a driving controller configured to drive the plurality of pixels in units of frames. Each of the plurality of pixels includes: a light-emitting diode and a pixel driving circuit connected to the light-emitting diode. The pixel driving circuit includes: a first transistor including a gate electrode connected to a first node, a first electrode electrically connected to a first voltage line for applying a first driving voltage, and a second electrode connected to a second node; a second transistor including a gate electrode connected to a first scan line for applying a first scan signal, a first electrode connected to a data line, and a second electrode connected to the first node; a first capacitor connected between the first node and the second node; a sixth transistor including a gate electrode connected to a second emission line for applying a second emission control signal, a first electrode connected to the second node, and a second electrode connected to a third node; and a fourth transistor including a gate electrode connected to a second scan line for applying a second scan signal different from the first scan signal, a first electrode connected to the third node, and a second electrode connected to a second voltage line for applying an initialization voltage. The frame includes a driving period and a scanning period, and during the scanning period, a non-effective period of the second emission control signal overlaps with an effective period of the second scan signal.

[0009] The pixel driving circuit further includes: a fifth transistor including a gate electrode connected to a first emission line for applying a first emission control signal, a first electrode connected to the first voltage line, and a second electrode connected to the first electrode of the first transistor, and during the scanning period, the first emission control signal is in an effective state.

[0010] The pixel driving circuit further includes: a third transistor including a gate electrode connected to a third scan line for applying a third scan signal different from the first scan signal and the second scan signal, a first electrode connected to a third voltage line for applying a reference voltage, and a second electrode connected to the first node.

[0011] During the scanning period, the third scan signal is in a non-effective state.

[0012] The driving period includes an effective period of the first scan signal.

[0013] During the scanning period, a first width of the effective period of the second scan signal is less than a second width of the non-effective period of the second emission control signal.

[0014] During the driving period, the active period of the second scan signal has a third width different from the first width.

[0015] During the driving period, the inactive period of the second emission control signal has a fourth width equal to the second width.

[0016] During the scanning period, the first scan signal is in an inactive state.

[0017] During the scanning period, the active period of the second scan signal and the inactive period of the second emission control signal occur simultaneously.

[0018] A plurality of the scanning periods are included in the frame.

[0019] According to an embodiment of the present disclosure, there is provided a pixel driving circuit, including: a first transistor including a gate electrode connected to a first node, a first electrode electrically connected to a first voltage line for applying a first driving voltage, and a second electrode connected to a second node; a second transistor including a gate electrode connected to a first scan line for applying a first scan signal, a first electrode connected to a data line, and a second electrode connected to the first node; a first capacitor connected between the first node and the second node; a sixth transistor including a gate electrode connected to a second emission line for applying a second emission control signal, a first electrode connected to the second node, and a second electrode connected to a third node; and a fourth transistor including a gate electrode connected to a second scan line for applying a second scan signal different from the first scan signal, a first electrode connected to the third node, and a second electrode connected to a second voltage line for applying an initialization voltage, and wherein, during a scanning period of holding a data voltage, the inactive period of the second emission control signal overlaps with the active period of the second scan signal.

[0020] The pixel driving circuit further includes: a fifth transistor including a gate electrode connected to a first emission line for applying a first emission control signal, a first electrode connected to the first voltage line, and a second electrode connected to the first electrode of the first transistor, wherein, during the scanning period, the fifth transistor is in a conducting state.

[0021] The pixel driving circuit further includes: a third transistor including a gate electrode connected to a third scan line for applying a third scan signal different from the first scan signal and the second scan signal, a first electrode connected to a third voltage line for applying a reference voltage, and a second electrode connected to the first node.

[0022] During the scan period, the third transistor is in an off state.

[0023] During the scan period, a first width of an active period of the second scan signal is less than a second width of an inactive period of the second emission control signal.

[0024] During the scan period, the second transistor is in an off state.

[0025] According to an embodiment of the present disclosure, a method for driving a display device is provided. The display device includes a display panel, the display panel includes a driving controller, a light-emitting diode, and a pixel driving circuit. The pixel driving circuit includes a driving transistor, a switching transistor for receiving a data voltage, an initialization transistor connected to an initialization voltage line, a first light-emitting transistor, and a second light-emitting transistor. The method includes: driving the display panel by the driving controller in units of frames including a driving period and a scan period; keeping the first light-emitting transistor in an on state during the scan period; providing a first period during the scan period, during which the second light-emitting transistor is off; providing a second period during the period when the second light-emitting transistor is off, during which the initialization transistor is on, and wherein the first period overlaps with the second period.

[0026] The first period overlaps with the entire second period.

[0027] The method further includes: providing a third period during the driving period, during which the switching transistor is on; and causing the light-emitting diode to emit light during the driving period.

[0028] A first width of the first period is greater than a second width of the second period.

[0029] A plurality of the driving periods and a plurality of the scan periods are provided alternately.

[0030] The method further includes: keeping the switching transistor in an off state during the scan period. Description of the Drawings

[0031] The above and other features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the drawings.

[0032] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0033] Figure 2 is a block diagram of a display device according to an embodiment of the present disclosure.

[0034] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0035] Figure 4 is a cross-sectional view of a display panel taken along line I-I' according to an embodiment of the present disclosure. Figure 1 of the display panel.

[0036] Figure 5 shows a driving frequency generated by a driving operation of a display device according to an embodiment of the present disclosure.

[0037] Figure 6 is a waveform diagram of a driving signal during a driving period according to an embodiment of the present disclosure.

[0038] Figure 7 is a waveform diagram of a driving signal during a scanning period according to an embodiment of the present disclosure.

[0039] Figure 8 is a photograph of a display panel according to a comparative example of the present disclosure.

[0040] Figure 9 is a graph measuring the brightness of a display panel according to a comparative example of the present disclosure.

[0041] Figure 10 is a photograph of a display panel according to an embodiment of the present disclosure.

[0042] Figure 11 is a graph measuring the brightness of a display panel according to an embodiment of the present disclosure. Detailed Description

[0043] In the specification, the expression that a first component (or region, layer, part, portion, etc.) is "on" a second component, "connected to" the second component, or "coupled to" the second component means that the first component is directly on the second component, the first component is directly connected to the second component, or the first component is directly coupled to the second component, or a third component is interposed between the first component and the second component.

[0044] The same reference numerals will be assigned to the same components. Additionally, in the drawings, the thickness, ratio, and size of components may be exaggerated for effective description of technical features. The term "and / or" includes any combination and all combinations of one or more related components.

[0045] Although terms such as "first", "second", etc. may be used to describe various components, these terms should not be construed as restrictive. The terms are only used to distinguish one component from another. For example, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0046] In addition, the terms "below", "lower", "above", and "upper" are used to describe the relationships between components shown in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0047] It will be further understood that the terms "include", "including", "comprises", "comprising", "has", "have", or "having" specify the presence of the stated features, numbers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, and / or combinations thereof.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In addition, unless explicitly defined herein, terms defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their context in the relevant art and shall not be interpreted in an idealized or overly formal sense.

[0049] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0050] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0051] Reference Figure 1 , according to an embodiment of the present disclosure, the display device DD may have a shape having a shorter side extending in a first direction DR1 and a longer side extending in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited thereto; various display devices DD having different shapes may be provided.

[0052] According to the present disclosure, the display device DD may include a large display device such as a television or a monitor, or a small and medium-sized display device such as a cellular phone, a tablet computer, a vehicle navigation system, or a game console. These examples are provided for illustrative purposes only, and it is obvious that the display device DD can be applied to other electronic devices without departing from the scope of the present disclosure.

[0053] As Figure 1As shown, the display device DD can display an image IM in a third direction DR3 intersecting the first direction DR1 and the second direction DR2 in a display surface FS parallel to the first direction DR1 and the second direction DR2, respectively. The display surface FS in which the image IM is displayed can correspond to the front surface of the display device DD.

[0054] The display surface FS of the display device DD can be divided into a plurality of regions. The display surface FS of the display device DD can be divided into a display region DA and a non-display region NDA.

[0055] The display region DA is a region where the image IM is displayed. The user can view the image IM through the display region DA. The shape of the display region DA can be defined by the non-display region NDA. However, this structure is provided for illustrative purposes. For example, the non-display region NDA can be adjacent to only one side of the display region DA, or can be completely omitted. The display device DD according to an embodiment of the present disclosure can include various configurations, and the present disclosure is not limited to any specific embodiment.

[0056] The non-display region NDA adjacent to the display region DA is a region where the image IM is not displayed. The border region of the display device DD can be defined by the non-display region NDA.

[0057] The non-display region NDA can surround the display region DA. However, this structure is provided for illustrative purposes. For example, the non-display region NDA can be adjacent to only a part of the edge of the display region DA, and is not limited to any specific embodiment.

[0058] Figure 2 is a block diagram of a display device according to an embodiment of the present disclosure.

[0059] Referring to Figure 2 , the display device DD can include a display panel DP and a driving controller DC.

[0060] According to an embodiment of the present disclosure, the display panel DP can be an emissive display panel, but the present disclosure is not limited thereto. For example, the display panel DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro light-emitting diode (LED) display panel, or a nano-LED display panel. The light-emitting layer of the organic light-emitting display panel can include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel can include quantum dots or quantum rods. The light-emitting layer of the micro-LED display panel can include micro-LEDs. The light-emitting layer of the nano-LED display panel can include nano-LEDs. Hereinafter, the display panel DP is referred to as an organic light-emitting display panel.

[0061] The driving controller DC can include a timing controller TC, a scan driving circuit SDC, and a data driving circuit DDC.

[0062] The timing controller TC can receive an image signal and a control signal from an external source. The timing controller TC can transform the data format of the image signal to match the interface specification with the data driving circuit DDC to generate image data D-RGB. The timing controller TC can generate a scan control signal SCS and a data control signal DCS by transforming the control signal. The timing controller TC outputs the image data D-RGB, the data control signal DCS, and the scan control signal SCS.

[0063] The scan driving circuit SDC can receive the scan control signal SCS from the timing controller TC. The scan control signal SCS can include a vertical start signal for starting the operation of the scan driving circuit SDC and a clock signal for determining the output timing of the signal. The scan driving circuit SDC can generate a plurality of first scan signals, a plurality of second scan signals, and a plurality of third scan signals. The scan driving circuit SDC can output the plurality of first scan signals to a plurality of first scan lines GWL1 to GWLn corresponding to the plurality of first scan signals, can output the plurality of second scan signals to a plurality of second scan lines GIL1 to GILn corresponding to the plurality of second scan signals, and can output the plurality of third scan signals to a plurality of third scan lines GRL1 to GRLn corresponding to the plurality of third scan signals. Herein, n can be a natural number greater than 0.

[0064] The scan driving circuit SDC can generate a plurality of first emission control signals and a plurality of second emission control signals in response to the scan control signal SCS. The scan driving circuit SDC can output the plurality of first emission control signals to a plurality of first emission lines EML1 to EMLn corresponding to the plurality of first emission control signals, and can output the plurality of second emission control signals to a plurality of second emission lines EMBL1 to EMBLn corresponding to the plurality of second emission control signals.

[0065] Although Figure 2 it is shown that a plurality of first scan signals to a plurality of third scan signals and a plurality of first emission control signals and a plurality of second emission control signals are output from a single scan driving circuit SDC, the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the display device DD may include a plurality of scan driving circuits SDC. The plurality of scan driving circuits SDC can output a plurality of scan driving signals in the form of the first scan signal to the third scan signal and the first emission control signal and the second emission control signal. Additionally, according to an embodiment of the present disclosure, the scan driving circuit SDC may include a driving circuit that generates and outputs the first scan signal to the third scan signal and a driving circuit that generates and outputs the first emission control signal and the second emission control signal.

[0066] The data driving circuit DDC can receive a data control signal DCS and image data D-RGB from a timing controller TC. The data driving circuit DDC can transform the image data D-RGB into a data voltage and output the data voltage to a plurality of data lines DL1 to DLm, which will be described below. Herein, m can be a natural number greater than 0. The data voltage can be an analog voltage corresponding to the gray level value of the image data D-RGB.

[0067] The display panel DP can include first scan lines GWL1 to GWLn, second scan lines GIL1 to GILn, third scan lines GRL1 to GRLn, first emission lines EML1 to EMLn, second emission lines EMBL1 to EMBLn, data lines DL1 to DLm, a first voltage line PL, a second voltage line VL, a third voltage line VRL, and a plurality of pixels PX11 to PXnm. The first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, the third scan lines GRL1 to GRLn, the first emission lines EML1 to EMLn, and the second emission lines EMBL1 to EMBLn can extend in a first direction DR1 and be arranged in a second direction DR2 intersecting the first direction DR1.

[0068] The data lines DL1 to DLm can cross and be insulated from the first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, the third scan lines GRL1 to GRLn, the first emission lines EML1 to EMLn, and the second emission lines EMBL1 to EMBLn. The plurality of pixels PX11 to PXnm can be connected to corresponding ones of the scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn among the scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn. The connection relationship between the pixels PX11 to PXnm and the scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn can vary according to the configuration of the driving circuits of the plurality of pixels PX11 to PXnm.

[0069] The first voltage line PL can receive a first driving voltage ELVDD. The second voltage line VL can receive an initialization voltage Vint. The third voltage line VRL can receive a reference voltage Vref. The initialization voltage Vint can have a level lower than the level of the first driving voltage ELVDD. A second driving voltage ELVSS can be applied to the display panel DP. The second driving voltage ELVSS can have a level lower than the first driving voltage ELVDD.

[0070] Although the display device DD has been described above with reference to Figure 2 , the display device DD according to an embodiment of the present disclosure is not limited to this configuration. The display device DD may include scan lines GWL1 to GWLn, GIL1 to GILn, and GRL1 to GRLn, or these scan lines may be omitted. In addition, the connection relationship between each of the plurality of pixels PX11 to PXnm and the scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn may vary.

[0071] The plurality of pixels PX11 to PXnm may include multiple groups of pixels, and each group of pixels includes light-emitting diodes OLEDs (see Figure 3 ) that emit light of different colors. For example, these groups may include red pixels that emit red light, green pixels that emit green light, and blue pixels that emit blue light. The light-emitting diodes of the red pixels, green pixels, and blue pixels may include light-emitting layers made of different materials.

[0072] Each of the plurality of pixels PX11 to PXnm may include a plurality of transistors and at least one capacitor electrically connected to the transistors. Details thereof will be described later. At least one of the scan driving circuit SDC and the data driving circuit DDC may include a plurality of transistors formed by the same process as the pixel driving circuit.

[0073] The above scan lines GWL1 to GWLn, GIL1 to GILn, and GRL1 to GRLn, the plurality of pixels PX11 to PXnm, the scan driving circuit SDC, and the data driving circuit DDC may be formed on a substrate by multiple photolithography processes.

[0074] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure. Figure 3 The pixel PXij shown in Figure 2 may correspond to each of the plurality of pixels PX11 to PXnm shown in

[0075] Refer to Figure 2 and Figure 3, the pixel PXij can be connected to the j-th data line DLj (also referred to as the data line DLj) among the data lines DL1 to DLm, the i-th first scan line GWLi (also referred to as the first scan line GWLi) among the first scan lines GWL1 to GWLn, the i-th second scan line GILi (also referred to as the second scan line GILi) among the second scan lines GIL1 to GILn, the i-th third scan line GRLi (also referred to as the third scan line GRLi) among the third scan lines GRL1 to GRLn, the i-th first emission line EMLi (also referred to as the first emission line EMLi) among the first emission lines EML1 to EMLn, and the i-th second emission line EMBLi (also referred to as the second emission line EMBLi) among the second emission lines EMBL1 to EMBLn. In this case, "i" is a natural number greater than 0 and less than or equal to n, and "j" is a natural number greater than 0 and less than or equal to m.

[0076] The pixel PXij can be connected to the first scan line GWLi for transmitting the first scan signal GW, the second scan line GILi for transmitting the second scan signal GI, the third scan line GRLi for transmitting the third scan signal GR, the first emission line EMLi for transmitting the first emission control signal EM, the second emission line EMBLi for transmitting the second emission control signal EMB, and the data line DLj for transmitting the data voltage Vdata. Additionally, the pixel PXij can be connected to the first voltage line PL for transmitting the first driving voltage ELVDD, the second voltage line VL for transmitting the initialization voltage Vint, and the third voltage line VRL for transmitting the reference voltage Vref.

[0077] The pixel PXij can include a light-emitting diode OLED and a pixel driving circuit PC. For example, the light-emitting diode OLED can be an organic light-emitting diode including an organic light-emitting layer. The pixel driving circuit PC can be connected to the light-emitting diode OLED to control the amount of current flowing through the light-emitting diode OLED. The light-emitting diode OLED can generate light with a specific brightness according to the amount of current provided.

[0078] The pixel driving circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. The first electrode (first terminal) of each of the first transistor T1 to the sixth transistor T6 may be a source or a drain, and the second electrode (second terminal) of each of the first transistor T1 to the sixth transistor T6 may be an electrode different from the first electrode. For example, when the first electrode is a drain, the second electrode may be a source. The node connected to the gate electrode of the first transistor T1 may be a first node N1, and the node connected to the second electrode of the first transistor T1 may be defined as a second node N2. The node connected to the anode AE of the light-emitting diode OLED (see Figure 4 ) may be a third node N3.

[0079] The pixel PXij according to an embodiment of the present disclosure may be referred to as having a 6T2C structure.

[0080] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be an N-type transistor having an oxide semiconductor as a semiconductor layer. However, this is provided for illustrative purposes only. For example, the semiconductor layer according to an embodiment of the present disclosure is not limited to such a composition and may include amorphous silicon, low-temperature polycrystalline silicon (LTPS), or single-crystalline silicon. The N-type transistors for the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may exhibit less variation in device characteristics and have a lower instantaneous afterimage generation probability. However, this is also for illustrative purposes only. For example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be P-type transistors. In another embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 is an N-type transistor, and the remaining transistors are P-type transistors.

[0081] The first transistor T1 can be electrically connected between the first voltage line PL and the second node N2. The first transistor T1 can include a first gate electrode connected to the first node N1, a first electrode electrically connected to the first voltage line PL for receiving the first driving voltage ELVDD, and a second electrode connected to the second node N2. The first electrode can be connected to the first voltage line PL via the fifth transistor T5. The second electrode can be connected to the third node N3 via the sixth transistor T6. The first transistor T1 can further include a second gate electrode connected to the second node N2. The first gate electrode and the second gate electrode can face each other at different layers. The first transistor T1 can receive the data voltage Vdata according to the switching operation of the second transistor T2 and can control the amount of the driving current Id flowing through the light-emitting diode OLED. The first transistor T1 can be referred to as a driving transistor.

[0082] The second transistor T2 can be connected between the data line DLj and the first node N1. The second transistor T2 can include a gate electrode connected to the first scan line GWLi for receiving the first scan signal GW, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can be turned on in response to the first scan signal GW to electrically connect the data line DLj to the first node N1 and transmit the data voltage Vdata from the data line DLj to the first node N1. The second transistor T2 can be referred to as a switching transistor.

[0083] The third transistor T3 can be connected between the first gate electrode of the first transistor T1 and the third voltage line VRL. The third transistor T3 can include a gate electrode connected to the third scan line GRLi for receiving the third scan signal GR, a first electrode connected to the third voltage line VRL for receiving the reference voltage Vref, and a second electrode connected to the first node N1. The third transistor T3 can be turned on in response to the third scan signal GR received through the third scan line GRLi to transmit the reference voltage Vref from the third voltage line VRL to the first node N1. The third transistor T3 can be referred to as a reset transistor.

[0084] The fourth transistor T4 can be connected between the second voltage line VL and the third node N3. The fourth transistor T4 can include a gate electrode connected to the second scan line GILi for providing the second scan signal GI, a first electrode connected to the third node N3, and a second electrode connected to the second voltage line VL for providing the initialization voltage Vint. The fourth transistor T4 can be turned on in response to the second scan signal GI received through the second scan line GILi to transmit the initialization voltage Vint from the second voltage line VL to the third node N3. The fourth transistor T4 can be referred to as an initialization transistor.

[0085] The fifth transistor T5 can be connected between the first voltage line PL and the first transistor T1. The fifth transistor T5 can include a gate electrode connected to a first emission line EMLi for providing a first emission control signal EM, a first electrode connected to the first voltage line PL, and a second electrode connected to the first electrode of the first transistor T1. The fifth transistor T5 can be turned on or off in response to the first emission control signal EM received through the first emission line EMLi. The fifth transistor T5 can be referred to as a first light-emitting transistor.

[0086] The sixth transistor T6 can be connected between the first transistor T1 and the light-emitting diode OLED. The sixth transistor T6 can include a gate electrode connected to a second emission line EMBLi for providing a second emission control signal EMB, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The sixth transistor T6 can be turned on or off in response to the second emission control signal EMB received through the second emission line EMBLi. The sixth transistor T6 can be referred to as a second light-emitting transistor.

[0087] The first capacitor C1 can be connected between the first node N1 and the second node N2. The first capacitor C1 can include a first electrode and a second electrode. The first electrode can be connected to the first gate electrode of the first transistor T1, and the second electrode can be connected to the second electrode of the first transistor T1. The first capacitor C1 can store a threshold voltage and a voltage corresponding to the data signal. The first capacitor C1 can be referred to as a storage capacitor.

[0088] The second capacitor C2 can be connected between the first voltage line PL and the second node N2. The second capacitor C2 can include a first electrode and a second electrode. The first electrode can be connected to the first voltage line PL. The second electrode can be connected to the second gate electrode and the second electrode of the first transistor T1. The capacitance of the second capacitor C2 can be smaller than the capacitance of the first capacitor C1. The second capacitor C2 can be referred to as a holding capacitor.

[0089] The light-emitting diode OLED can be electrically connected to the first transistor T1. The light-emitting diode OLED can include an anode AE (see Figure 4 ) connected to the third node N3 and a cathode CE (see Figure 4 ) facing the pixel electrode. The cathode CE (see Figure 4 ) can receive a second driving voltage ELVSS. The cathode CE (see Figure 4 ) can be a common electrode shared by a plurality of pixels PX (see Figure 2 ).

[0090] Figure 4 is shown along an embodiment according to the present disclosure Figure 1Cross-sectional view of the display panel taken along line I-I'.

[0091] Reference Figure 4 , the display panel DP may include a substrate layer 110, a circuit layer 120 disposed on the substrate layer 110, a light-emitting element layer 130, and a packaging layer 140.

[0092] The substrate layer 110 may have a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide-based resin layer, and the material is not specifically limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a silicone resin, a polyamide resin, and a perylene resin. Additionally, the substrate layer may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0093] At least one inorganic layer may be disposed on the top surface of the substrate layer 110. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may have a multilayer structure. The inorganic layers in the multilayer structure may include a barrier layer BRL and / or a buffer layer BFL described later. The barrier layer BRL and the buffer layer BFL may be selectively disposed.

[0094] The barrier layer BRL prevents foreign substances from infiltrating from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may include a plurality of silicon oxide layers, the silicon nitride layer may include a plurality of silicon nitride layers, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0095] A blocking pattern BML may be disposed on the barrier layer BRL. According to an embodiment, the barrier layer BRL may be omitted. In this case, the blocking pattern BML may be disposed on the top surface of the substrate layer 110.

[0096] The blocking pattern BML may overlap with the first transistor T1. The blocking pattern BML may overlap with the channel portion A1 to prevent deterioration of the electrical characteristics of the channel portion A1. Additionally, in the manufacturing process of the display device DD (see Figure 1 ), the blocking pattern BML may protect the first transistor T1 from the influence of light or moisture introduced from the lower part of the substrate layer 110. The blocking pattern BML may include a material having a low light transmittance. For example, the blocking pattern BML may be a metal pattern including molybdenum (Mo). The light incident on the blocking pattern BML may be reflected from the top surface or the bottom surface of the blocking pattern BML.

[0097] Although Figure 4A blocking pattern BML is shown below the first transistor T1, but the layout relationship of the blocking pattern BML according to an embodiment of the present disclosure is not limited to this configuration. For example, the blocking pattern BML may be disposed below at least one of a plurality of transistors including the first transistor T1 and the third transistor T3 to overlap with the channel portion of the transistor.

[0098] A buffer layer BFL may be disposed on the barrier layer BRL while covering the blocking pattern BML. The buffer layer BFL may improve the bonding force between the substrate layer 110 and the semiconductor pattern and / or the conductive pattern. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0099] A semiconductor pattern is disposed on the buffer layer BFL. Hereinafter, the semiconductor pattern directly disposed on the buffer layer BFL is described as a first semiconductor pattern. The first semiconductor pattern may include an oxide semiconductor.

[0100] The first semiconductor pattern may have electrical properties that vary according to the doping state. The first semiconductor pattern may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant.

[0101] The doped region may have greater conductivity than the undoped region, and the doped region may be used as an electrode or a signal line. The undoped region substantially corresponds to the active (or channel) region of the transistor. In other words, a first portion of the first semiconductor pattern may be the active region of the transistor, a second portion of the first semiconductor pattern may be the source region or the drain region of the transistor, and a third portion of the first semiconductor pattern may be a connection electrode or a connection signal line. Figure 4 The first transistor T1 is shown as an example of the first semiconductor pattern.

[0102] The first electrode S1, the channel portion A1, and the second electrode D1 of the first transistor T1 may be formed from the first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 may extend from the channel portion A1 in opposite directions.

[0103] Figure 4 A part of the connection signal line CSL formed from the semiconductor pattern is shown. Although not shown separately, when observed in a plan view, the connection signal line CSL may be connected to the second electrode of the sixth transistor T6 (see Figure 3 ).

[0104] The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 may be associated with the pixel PX (seeFigure 2 ) overlap to cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. According to an embodiment, the first insulating layer 10 may be a single silicon oxide layer. In addition to the first insulating layer 10, the insulating layer of the circuit layer 120 to be described later may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0105] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 may be a part of a metal pattern. The third electrode G1 of the first transistor T1 may overlap with the channel portion A1 of the first transistor T1. In the process of doping the first semiconductor pattern, the third electrode G1 of the first transistor T1 may be used as a mask. The third electrode G1 may be the first gate electrode of the first transistor T1.

[0106] The second insulating layer 20 is disposed on the first insulating layer 10 to cover the third electrode G1. The second insulating layer 20 may overlap with a plurality of pixels PX. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. According to an embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0107] The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap with the third electrode G1. The upper electrode UE may be a part of a metal pattern or a part of a doped semiconductor pattern. The upper electrode UE overlapping with a part of the third electrode G1 may be the second gate electrode of the first transistor T1.

[0108] According to an embodiment of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern. The upper electrode UE is disposed on the insulating pattern. The upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0109] The third insulating layer 30 is disposed on the second insulating layer 20 to cover the upper electrode UE. According to an embodiment, the third insulating layer 30 may be a single silicon oxide layer. A semiconductor pattern is disposed on the third insulating layer 30. Hereinafter, the semiconductor pattern directly disposed on the third insulating layer 30 may be a second semiconductor pattern.

[0110] The second semiconductor pattern may include an oxide semiconductor. Figure 4The third transistor T3 is illustrated by an example of a second semiconductor pattern. A first electrode S3, a channel portion A3, and a second electrode D3 of the third transistor T3 are formed from the second semiconductor pattern. The first electrode S3 and the second electrode D3 of the third transistor T3 may extend from the channel portion A3 in opposite directions.

[0111] A fourth insulating layer 40 is disposed on the third insulating layer 30 to cover the second semiconductor pattern. According to an embodiment, the fourth insulating layer 40 may be a single silicon oxide layer. A third electrode G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The third electrode G3 may be a part of a metal pattern. The third electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3. The third electrode G3 may be a gate electrode of the third transistor T3.

[0112] According to an embodiment of the present disclosure, the fourth insulating layer 40 may be replaced with an insulating pattern. The third electrode G3 of the third transistor T3 is disposed on the insulating pattern. According to an embodiment, when observed in a plan view, the third electrode G3 may have the same shape as the shape of the insulating pattern.

[0113] A fifth insulating layer 50 is disposed on the fourth insulating layer 40 to cover the third electrode G3. According to an embodiment, the fifth insulating layer 50 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxynitride layers and silicon nitride layers stacked alternately with each other.

[0114] At least one insulating layer is further disposed on the fifth insulating layer 50. According to an embodiment, a sixth insulating layer 60 and a seventh insulating layer 70 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers, and may have a single-layer structure or a multi-layer structure. The sixth insulating layer 60 and the seventh insulating layer 70 may be single-layer polyimide-based resin layers. The present disclosure is not limited thereto, and the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a silicone resin, a polyamide resin, and a perylene resin.

[0115] A first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to a connection signal line CSL through a first contact hole CH1 formed through the first insulating layer 10 to the fifth insulating layer 50, and a second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a contact hole CH-60 formed through the sixth insulating layer 60. According to an embodiment of the present disclosure, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 may be omitted.

[0116] The light-emitting element layer 130 includes a light-emitting diode OLED and a pixel defining layer PDL. The anode AE of the light-emitting diode OLED can be disposed on the seventh insulating layer 70. The anode AE of the light-emitting diode OLED can be connected to the second connection electrode CNE20 through a contact hole CH-70 formed through the seventh insulating layer 70. The light-emitting diode OLED can include an organic light-emitting diode.

[0117] The opening OP of the pixel defining layer PDL can expose at least a portion of the anode AE of the light-emitting diode OLED. The opening OP of the pixel defining layer PDL can define a light-emitting region PXA. For example, when viewed in a plan view of the display panel DP, a plurality of pixels PX (see Figure 2 ) can be arranged in a consistent pattern. The region including the plurality of pixels PX can be a pixel region, and each pixel region includes a light-emitting region PXA and a non-light-emitting region NPXA adjacent to the light-emitting region PXA. The non-light-emitting region NPXA can surround the light-emitting region PXA.

[0118] The hole control layer HCL can be commonly disposed in both the light-emitting region PXA and the non-light-emitting region NPXA. A common layer such as the hole control layer HCL can be formed across a plurality of pixels PX (see Figure 2 ). The hole control layer HCL can include a hole transport layer and a hole injection layer.

[0119] The light-emitting layer EML is disposed on the hole control layer HCL. The light-emitting layer EML can be disposed only in a region corresponding to the opening OP. The light-emitting layer EML can be separately formed on each of the plurality of pixels PX (see Figure 2 ).

[0120] Although a patterned light-emitting layer EML is shown according to an embodiment, the light-emitting layer EML can also be commonly disposed across a plurality of pixels PX (see Figure 2 ). In this case, the light-emitting layer EML can generate white light or blue light and can have a multilayer structure.

[0121] The electron control layer ECL is disposed on the light-emitting layer EML. The electron control layer ECL can include an electron transport layer and an electron injection layer. The cathode CE of the light-emitting diode OLED is disposed on the electron control layer ECL. The electron control layer ECL and the cathode CE can be commonly disposed across a plurality of pixels PX.

[0122] The encapsulation layer 140 is disposed on the cathode CE. The encapsulation layer 140 can cover a plurality of pixels PX (see Figure 2)。According to an embodiment, the encapsulation layer 140 may directly cover the cathode CE. In other words, the encapsulation layer 140 may be in direct contact with the cathode CE. According to an embodiment of the present disclosure, the encapsulation layer 140 may further include a cover layer that directly covers the cathode CE. According to an embodiment of the present disclosure, compared with the structure shown in Figure 4 , the stacked structure of the light-emitting diode OLED may have an inverted structure.

[0123] The encapsulation layer 140 may be disposed on the light-emitting element layer 130. The encapsulation layer 140 may include an inorganic layer, an organic layer, and an inorganic layer that are sequentially stacked, and the layers constituting the encapsulation layer 140 are not limited thereto.

[0124] The inorganic layer may protect the light-emitting element layer 130 from moisture and oxygen, while the organic layer may protect the light-emitting element layer 130 from foreign substances such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic layer may include, but is not limited to, an acrylic organic layer, but the present disclosure is not limited thereto.

[0125] Figure 5 The driving frequency generated by the driving operation of the display device according to an embodiment of the present disclosure is shown.

[0126] Referring to Figure 2 , Figure 3 and Figure 5 , the driving controller DC may drive a plurality of pixels PX in units of frames. One frame may include a driving period A and a scanning period B.

[0127] The driving period A and the scanning period B may be referred to as a first period and a second period, respectively. The first period may be a period for performing data writing, while the second period may be a period for refreshing during which data writing is not performed.

[0128] During the driving period A, the data voltage Vdata of the first transistor T1 may be initialized. The initialization and update speed of the data voltage Vdata may be controlled according to circumstances, and the deterioration of the first transistor T1 and the light-emitting diode OLED may be prevented by changing the period of the driving period A. For example, when displaying a still image that does not require rapid updating of the data voltage Vdata, low-speed driving may be performed to reduce power consumption by extending the frame period of the first transistor T1.

[0129] During low-speed driving, the length of the period of the first frame may increase. Therefore, the number of scanning periods B during which the input data voltage Vdata is held may increase. During the scanning period B, the driving current Id may be supplied to the light-emitting diode OLED while the first emission control signal EM remains in the on state.

[0130] The driving controller DC can adjust the driving frequency of the display panel DP by repeating the scanning period B.

[0131] The display device DD can synchronize the frame generation of the graphics processing device included in the display device DD with the frame output timing of the display panel DP. In other words, the display panel DP can operate at a variable scanning rate. For example, when the operating frequency of the display panel DP is reduced under specific operating conditions (such as displaying a still image), the power consumption of the display device DD can be reduced.

[0132] Each of the driving period A and the scanning period B can be a period having a time of 2.1 milliseconds (ms). In other words, each of the driving period A and the scanning period B can have a frequency of 240 Hz (Hertz). However, this is only provided for exemplary purposes, and the duration of each of the driving period A and the scanning period B according to an embodiment of the present disclosure is not limited to these examples. For example, each of the driving period A and the scanning period B can be a period having a time of 4.2 ms.

[0133] When the graphics processing device generates a frame having a scanning rate of 120 Hz, the scanning driving circuit SDC can control the driving period A and the scanning period B to be driven once per frame, so that the display panel DP operates at a frequency of 120 Hz. A plurality of driving periods A and a plurality of scanning periods B can be provided respectively. A plurality of driving periods A and a plurality of scanning periods B can be provided alternately.

[0134] When the graphics processing device generates a frame having a scanning rate of 80 Hz, the scanning driving circuit SDC can be driven to have one driving period A and two scanning periods B in one frame.

[0135] When the graphics processing device generates a frame having a scanning rate of 60 Hz, the scanning driving circuit SDC can be driven to have one driving period A and three scanning periods B in one frame.

[0136] When the graphics processing device generates a frame having a scanning rate of 48 Hz, the scanning driving circuit SDC can be driven to have one driving period A and four scanning periods B in one frame.

[0137] When the graphics processing device generates a frame having a scanning rate of 40 Hz, the scanning driving circuit SDC can be driven to have one driving period A and five scanning periods B in one frame.

[0138] When the graphics processing device generates a frame having a scanning rate of 34 Hz, the scanning driving circuit SDC can be driven to have one driving period A and six scanning periods B in one frame.

[0139] When the graphics processing device generates a frame with a scanning rate of 30 Hz, the scan drive circuit SDC can be driven to have one drive period A and seven scan periods B in one frame.

[0140] Figure 6 is a waveform diagram of a drive signal during a drive period according to an embodiment of the present disclosure.

[0141] Reference Figure 3 and Figure 6 , each of the drive signals EM, EMB, GR, GI, and GW can have a high level for some periods and a low level for some periods. When the relevant signal is at a high level, the N-type transistor having a gate electrically connected to the scan lines GRLi, GILi, and GWLi and the emission lines EMLi and EMBLi can be turned on, and when the relevant signal is at a low level, the P-type transistor can be turned on. The drive signals EM, EMB, GR, GI, and GW can include a first emission control signal EM, a second emission control signal EMB, a third scan signal GR, a second scan signal GI, and a first scan signal GW.

[0142] The drive period A can include a first period P1 (also referred to as an active period P1), a second period P2, a third period P3, a fourth period P4, and a fifth period P5.

[0143] During the first period P1, the second scan signal GI in an active state can be provided to the second scan line GILi. The third scan signal GR in an active state can be provided to the third scan line GRLi. The first scan signal GW can be in an inactive state.

[0144] The fourth transistor T4 can be turned on by the second scan signal GI. The third node N3, which is the anode AE of the light-emitting diode OLED (see Figure 4 ), can be initialized to the initialization voltage Vint by the fourth transistor T4 when the fourth transistor T4 is turned on.

[0145] The third transistor T3 can be turned on by the third scan signal GR. The first node N1, which is the first gate electrode of the first transistor T1, can be initialized to the reference voltage Vref by the third transistor T3 when the third transistor T3 is turned on.

[0146] The second period P2 can be executed after the first period P1. During the second period P2, the third scan signal GR in an active state can be provided to the third scan line GRLi. The first emission control signal EM in an active state can be provided to the first emission line EMLi. Each of the first scan signal GW, the second scan signal GI, and the second emission control signal EMB can be in an inactive state.

[0147] The third transistor T3 can be turned on by a third scan signal GR. A first node N1, which is a first gate electrode of the first transistor T1, can be initialized by the third transistor T3 to a reference voltage Vref when the third transistor T3 is turned on.

[0148] The fifth transistor T5 can be turned on by a first emission control signal EM. A first driving voltage ELVDD can be provided by the fifth transistor T5 to a first electrode of the first transistor T1 when the fifth transistor T5 is turned on.

[0149] The reference voltage Vref can be provided to the first gate electrode of the first transistor T1, and the first driving voltage ELVDD can be supplied to the first electrode of the first transistor T1 to turn on the first transistor T1. When the voltage of the second electrode of the first transistor T1 decreases to less than the difference "Vref - Vth" between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off. Additionally, a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the first capacitor C1 to compensate for the threshold voltage (Vth) of the first transistor T1.

[0150] A third period P3 can be executed after the second period P2. During the third period P3, a first scan signal GW in an active state can be provided to a first scan line GWLi. A second scan signal GI in an active state can be provided to a second scan line GILi. The third scan signal GR, the first emission control signal EM, and the second emission control signal EMB can be in an inactive state.

[0151] The second transistor T2 can be turned on by the first scan signal GW. A data voltage Vdata can be transferred from a data line DLj through the second transistor T2 to the first node N1, which is the first gate electrode of the first transistor T1, when the second transistor T2 is turned on. Accordingly, the voltage of the first node N1 can be changed from the reference voltage Vref to a voltage corresponding to the data voltage Vdata. In this case, the voltage of the second node N2 can also change in response to the change in the voltage across the first node N1. The voltage at the second node N2 can be expressed as "Vref - Vth + a×(Vdata - Vref)", which varies according to the capacitance ratio a = C1 / (C1 + C2) of the first capacitor C1 and the second capacitor C2. Thus, the gate-source voltage Vgs of the first transistor T1 (the voltage between the first node N1 and the second node N2) can be as shown in Equation 1 below.

[0152] Formula 1

[0153]

[0154] The fourth transistor T4 can be turned on by the second scan signal GI. As the anode AE of the light-emitting diode OLED (see Figure 4 ), the third node N3 can be initialized to the initialization voltage Vint by the fourth transistor T4 when the fourth transistor T4 is turned on. In this case, the gate-source voltage Vgs of the first transistor T1 can be as shown in Equation 2 below.

[0155] Formula 2

[0156]

[0157] Different from the present disclosure, due to the residual voltage in the light-emitting diode OLED, a change in brightness may occur. In the case of driving at a low gray level, the visibility of this change in brightness increases. Therefore, the light-emitting diode OLED that displays black at the black gray level emits light with a brightness higher than the expected black brightness. However, according to the present disclosure, by initializing the anode AE (see Figure 4 ) with the initialization voltage Vint through the fourth transistor T4 before the light-emitting diode OLED emits light, the phenomenon that the light-emitting diode OLED emits light slowly when at the black gray level can be prevented. Therefore, the change in the brightness of the light-emitting diode OLED at a low gray level can be minimized, thereby further improving the display quality. Therefore, a pixel driving circuit PC that prevents deterioration of the display quality and a display device DD including the pixel driving circuit PC (see Figure 1 ) can be provided.

[0158] The fourth period P4 can be executed after the third period P3. During the fourth period P4, the first emission control signal EM in the active state can be provided to the first emission line EMLi. The second emission control signal EMB in the active state can be provided to the second emission line EMBLi. The first scan signal GW, the second scan signal GI, and the third scan signal GR can be in the inactive state.

[0159] The fifth transistor T5 can be turned on by the first emission control signal EM. The sixth transistor T6 can be turned on by the second emission control signal EMB.

[0160] When the fifth transistor T5 and the sixth transistor T6 are turned on, a current path can be formed along the first voltage line PL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting diode OLED. In other words, the drive current Id can flow through the first voltage line PL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting diode OLED.

[0161] From the display panel DP (see Figure 2) The data-driven circuit DDC (see Figure 2 ) The data voltage Vdata output is written so that the light-emitting diode OLED emits light. The drive current Id can be expressed by the following equation.

[0162] Formula 3

[0163]

[0164] Formula 4

[0165]

[0166] Formula 5

[0167]

[0168] Formula 6

[0169]

[0170] In the above equation, "μ" represents the field mobility, "Cox" indicates the capacitance of the gate insulating layer, "W" and "L" are the width and length of the first transistor T1, and "Vgs" is the gate-source voltage of the first transistor T1. "μ" and "Cox" are constants. In other words, "α" is a constant.

[0171] The gate-source voltage of the first transistor T1 is the voltage difference obtained by subtracting the voltage across the second node N2 from the voltage across the third node N3.

[0172] Equation 5 is a generalization of Equations 2 to 4. Equation 6 is a generalization of Equation 5.

[0173] The threshold voltage (Vth) of the first transistor T1 included in each of the multiple pixels PX (refer to Figure 2 ) can vary according to the characteristics of the first transistor T1. However, according to the present disclosure, the threshold voltage (Vth) of the first transistor T1 does not affect the drive current Id flowing through the light-emitting diode OLED during the first period P1, the second period P2, the third period P3, and the fourth period P4. Referring to Equation 6, the drive current Id flowing through the light-emitting diode OLED during the fourth period P4 is not affected by the threshold voltage (Vth) of the first transistor T1. The drive current Id of the light-emitting diode OLED is proportional to the square of the difference between the data voltage Vdata, the reference voltage Vref, and the initialization voltage Vint, and is independent of the characteristics of the first transistor T1. Therefore, the image IM output from the display panel DP (refer to Figure 2 ) (refer to Figure 1) The luminance is uniformly maintained. Therefore, a pixel driving circuit PC with improved display quality and a display device DD including the pixel driving circuit PC can be provided (refer to Figure 1 )

[0174] The fifth period P5 can be executed after the fourth period P4. During the fifth period P5, the first emission control signal EM can be in an active state. The first scan signal GW, the second scan signal GI, and the third scan signal GR can be in an inactive state. The second emission control signal EMB can be in an inactive state.

[0175] During the fifth period P5, the width W3 of the inactive period of the second emission control signal EMB can be the same as the width W1 of the inactive period of the second emission control signal EMB during a part of the first period P1 and the second and third periods P2 and P3. When the second emission control signal EMB is in an active state, a current path can be formed along the first voltage line PL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting diode OLED. Therefore, the drive current Id can be applied to the light-emitting diode OLED. The drive current Id can be controlled and applied by the second emission control signal EMB during the fifth period P5.

[0176] Different from the present disclosure, when the first emission control signal EM is switched and the second emission control signal EMB remains in an active state, in other words, when the drive current Id is controlled by the first emission control signal EM, the first transistor T1 can operate every time the first emission control signal EM is activated, thereby increasing power consumption. However, according to the present disclosure, the first emission control signal EM can be not switched during the scan period B. The fifth transistor T5 can always be turned on during the scan period B. Therefore, the fifth transistor T5, the first transistor T1, and the second node N2 can be kept electrically connected. Therefore, a pixel driving circuit PC with reduced power consumption and a display device DD including the pixel driving circuit PC can be provided (see Figure 1 )

[0177] Figure 7 is a waveform diagram of drive signals during a scan period according to an embodiment of the present disclosure.

[0178] Refer to Figure 3 and Figure 7 , the first emission control signal EM can be in an active state during the scan period B. The first scan signal GW and the third scan signal GR can be in an inactive state.

[0179] The second emission control signal EMB may include an active period and an inactive period. The scanning period B may include a sixth period P6. The sixth period P6 may be the inactive period P6 of the second emission control signal EMB.

[0180] The width W4 of the inactive period P6 of the second emission control signal EMB may be equal to the width W1 of the inactive period of the second emission control signal EMB during the driving period A (see Figure 6 ) and the width W3 of the inactive period of the second emission control signal EMB during the driving period A (see Figure 6 ).

[0181] When the second emission control signal EMB is in the active state, a current path may be formed along the first voltage line PL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting diode OLED. Accordingly, the drive current Id may be applied to the light-emitting diode OLED. In other words, in the scanning period B, the supply of the drive current Id may be controlled and applied by the second emission control signal EMB.

[0182] During the scanning period B, the first emission control signal EM may be maintained in the active state.

[0183] Different from the present disclosure, when the first emission control signal EM is switched and the second emission control signal EMB is maintained in the active state, in other words, when the application of the drive current Id is controlled by the first emission control signal EM, the first transistor T1 may operate whenever the first emission control signal EM is activated, thereby increasing power consumption. However, according to the present disclosure, the first emission control signal EM may not be switched during the scanning period B. The fifth transistor T5 may always be turned on during the scanning period B. Accordingly, the fifth transistor T5, the first transistor T1, and the second node N2 may be maintained in electrical connection. Accordingly, a pixel driving circuit PC with reduced power consumption and a display device DD including the pixel driving circuit PC may be provided (see Figure 1 ).

[0184] The second scanning signal GI may include an active period and an inactive period. The scanning period B may further include a seventh period P7. The seventh period P7 may be the active period P7 of the second scanning signal GI.

[0185] The width W5 of the active period P7 of the second scanning signal GI may be less than the width W4 of the inactive period P6 of the second emission control signal EMB.

[0186] The width W5 of the active period P7 of the second scanning signal GI may be different from the width W2 of the active period P1 of the second scanning signal GI during the driving period A (see Figure 6)。For example, the width W5 of the active period P7 of the second scan signal GI may be greater than the width W2 of the active period P1 of the second scan signal GI during the driving period A (see Figure 6 )。

[0187] The scan period B may further include an eighth period P8. The eighth period P8 may be an inactive period P8 of the second emission control signal EMB.

[0188] The width W6 of the inactive period P8 of the second emission control signal EMB may be equal to the width W1 of the inactive period of the second emission control signal EMB in the driving period A (see Figure 6 )。In other words, the eighth period P8 may be substantially equal to the fifth period P5 of the driving period A (see Figure 6 )。

[0189] The inactive period P6 of the second emission control signal EMB may overlap with the active period P7 of the second scan signal GI. The active period P7 of the second scan signal GI may overlap with the inactive period P6 of the second emission control signal EMB. In other words, the active period of the second emission control signal EMB does not overlap with the active period P7 of the second scan signal GI. Therefore, during the scan period B, the fourth transistor T4 and the sixth transistor T6 may not be turned on simultaneously.

[0190] The active period P7 of the second scan signal GI may be referred to as an anode reset period. In other words, the scan period B may include at least one anode reset period during low-speed driving performed at a lower frame frequency.

[0191] The fourth transistor T4 may be turned on during the active period P7 of the second scan signal GI. The initialization voltage Vint may be provided to the third node N3. In other words, the anode AE of the light-emitting diode OLED (see Figure 4 ) may be reset to the initialization voltage Vint.

[0192] The third node N3 may be periodically reset to the initialization voltage Vint to reduce the flicker phenomenon that occurs as the scan period B within a frame increases during low-speed driving.

[0193] Different from the present disclosure, during driving period A, the luminance may decrease as the data voltage Vdata is initialized. When the duration of driving period A increases, the decrease in luminance may become apparent to the user. Additionally, when the driving current is low even after driving period A ends in a low gray level state, a charging delay phenomenon may occur, increasing the time required for the data voltage Vdata to return to its original state. Due to the recognized luminance decrease and charging delay, this may cause a flicker phenomenon. However, according to the present disclosure, an anode reset driving can be performed during scanning period B in low-speed driving at a low gray level, where the anode AE of the light-emitting diode OLED (see Figure 4 ) is periodically reset to the initialization voltage Vint. Therefore, the flicker phenomenon can be improved. Thus, a display device DD (see Figure 1 ) with improved display quality can be provided.

[0194] Figure 8 is a photograph of a display panel according to a comparative example of the present disclosure, Figure 9 is a graph measuring the luminance of a display panel according to a comparative example of the present disclosure, Figure 10 is a photograph of a display panel according to an embodiment of the present disclosure, and Figure 11 is a graph measuring the luminance of a display panel according to an embodiment of the present disclosure.

[0195] As Figure 9 and Figure 11 shown, the horizontal axes respectively represent the vertical axis coordinates of the images IM1 and IM2 of Figure 8 and Figure 10 in the range of 0 to 1200, and the vertical axis represents the luminance profile in the range of -10% to 10%.

[0196] Referring to Figure 8 and Figure 10 , the images IM1 and IM2 can be obtained by photographing the display panel DP using an external photographing unit. When the data voltage corresponds to 255 gray levels and when the data voltage provided to the pixel PXij corresponds to 10 nits, each of the images IM1 and IM2 is obtained by photographing the display panel DP showing a black image.

[0197] Referring to Figure 3 , Figure 8 and Figure 9 , the first image IM1 can be obtained by driving and measuring the display panel DP using an existing method for driving pixels according to a comparative example of the present disclosure. In other words, according to the comparative example, during the scanning period of the pixel PXij, the first emission control signal EM is not always in an active state, and the active period of the second emission control signal EMB can overlap with the active period of the second scanning signal GI.

[0198] The fourth transistor T4 and the sixth transistor T6 can be turned on simultaneously during the scanning period. Since the first capacitor C1, the second capacitor C2, and the capacitor of the light-emitting diode OLED are all discharged during this period, the amount of current flowing to the second voltage line VL to apply the initialization voltage Vint increases. Therefore, a voltage drop (referred to as IR Drop) may occur at the first driving voltage ELVDD of the first voltage line PL connected to the second capacitor C2. The voltage level of the first driving voltage ELVDD changes due to the voltage drop phenomenon in the first voltage line PL. Therefore, in the display panel of the comparative example, a defect of Mura that appears as a horizontal or vertical line on the display panel may occur due to insufficient driving current.

[0199] The first graph GP1 can represent the brightness profile for each vertical axis coordinate of the first image IM1. The brightness profile can be the average value of the brightness during the period corresponding to the vertical axis coordinate in the first image IM1.

[0200] Referring to the vicinity of 220 and 730 on the horizontal axis in the first graph GP1, an average brightness value close to -10% is observed. This indicates that a brightness deviation occurs in this area. Therefore, in the display panel DP using the pixel driving method according to the comparative example (see Figure 2 ), a Mura defect that may cause line contamination may occur.

[0201] In addition, when driving the display panel DP using the pixel driving method according to the comparative example (see Figure 2 ), the first emission control signal EM is repeatedly switched during the scanning period. Therefore, the power consumption of the display panel DP (see Figure 2 ) may increase. For example, the pixel driving method according to the comparative example may result in a power consumption ranging from 0.90 W (watts) to 1 W.

[0202] However, referring to Figure 3 , Figure 8 , ​ and ​ , the second image IM2 can be obtained by driving the display panel DP via the method of driving the pixel PXij according to the embodiments of the present disclosure and measuring the display panel DP. In other words, during the scanning period B of the pixel PXij, the first emission control signal EM is always in an active state, and the active period of the second emission control signal EMB may not overlap with the active period of the second scanning signal GI. In other words, the non-active period of the second emission control signal EMB can cover the active period of the second scanning signal GI. For example, the non-active period of the second emission control signal EMB may occur simultaneously with the active period of the second scanning signal GI.

[0203] According to the present disclosure, the fourth transistor T4 and the sixth transistor T6 can be driven such that they are not simultaneously turned on during the scanning period B. A current path may not be defined along the first voltage line PL, the second capacitor C2, the second node N2, the sixth transistor T6, the third node N3, the fourth transistor T4, and the second voltage line VL. Accordingly, a voltage drop phenomenon of the first driving voltage ELVDD can be prevented or eliminated, and a burn-in defect can be prevented or eliminated. Accordingly, a pixel driving circuit PC that prevents deterioration of display quality, a display device DD including the pixel driving circuit PC (see ​ ) and a method for driving the display device DD can be provided.

[0204] The second graph GP2 may represent a luminance profile for each vertical axis coordinate of the second image IM2. The luminance profile may be an average value of luminance during a period corresponding to the vertical axis coordinate in the second image IM2.

[0205] According to the present disclosure, the luminance deviation in the second graph GP2 may be less than the luminance deviation in the first graph GP1 (see ​ ). Accordingly, a pixel driving circuit PC having improved display quality compared to a comparative example, a display device DD including the pixel driving circuit PC (see ​ ) and a method for driving the display device DD can be provided.

[0206] In addition, according to the present disclosure, the first emission control signal EM may not be switched during the scanning period B. With the pixel driving method according to an embodiment of the present disclosure, due to the scanning period B, the power consumption may be about 0.6W. Accordingly, a pixel driving circuit PC having reduced power consumption, a display device DD including the pixel driving circuit PC (see ​ ) and a method for operating the display device DD can be provided.

[0207] As described above, the sixth transistor and the fourth transistor can be driven to prevent them from being simultaneously turned on. A current path may not be defined through the first voltage line, the second capacitor, the fourth transistor, the sixth transistor, and the second voltage line. Accordingly, a voltage drop of the first driving voltage can be prevented or eliminated, and a burn-in defect can be prevented or eliminated. Accordingly, a pixel driving circuit that prevents deterioration of display quality, a display device including the pixel driving circuit, and a method for driving the display device can be provided.

[0208] Although the present disclosure has been described with reference to specific embodiments, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein, The display device includes: a display panel including a plurality of pixels; a driving controller configured to drive the plurality of pixels in units of frames, wherein each of the plurality of pixels includes: a light-emitting diode and a pixel driving circuit connected to the light-emitting diode, wherein the pixel driving circuit includes: a first transistor including a gate electrode connected to a first node, a first electrode electrically connected to a first voltage line for applying a first driving voltage, and a second electrode connected to a second node; a second transistor including a gate electrode connected to a first scan line for applying a first scan signal, a first electrode connected to a data line, and a second electrode connected to the first node; a first capacitor connected between the first node and the second node; a sixth transistor including a gate electrode connected to a second emission line for applying a second emission control signal, a first electrode connected to the second node, and a second electrode connected to a third node; and a fourth transistor including a gate electrode connected to a second scan line for applying a second scan signal different from the first scan signal, a first electrode connected to the third node, and a second electrode connected to a second voltage line for applying an initialization voltage, wherein the frame includes a driving period and a scanning period, and wherein, during the scanning period, a non-effective period of the second emission control signal overlaps with an effective period of the second scan signal.

2. The display device according to claim 1, wherein, The pixel driving circuit further includes: a fifth transistor including a gate electrode connected to a first emission line for applying a first emission control signal, a first electrode connected to the first voltage line, and a second electrode connected to the first electrode of the first transistor, and wherein, during the scanning period, the first emission control signal is in an effective state.

3. The display device according to claim 2, wherein, The pixel driving circuit further includes: a third transistor including a gate electrode connected to a third scan line for applying a third scan signal different from the first scan signal and the second scan signal, a first electrode connected to a third voltage line for applying a reference voltage, and a second electrode connected to the first node.

4. The display device according to claim 3, wherein, During the scanning period, the third scan signal is in a non-effective state.

5. The display device according to claim 1, wherein, The driving period includes an effective period of the first scan signal.

6. The display device according to claim 1, wherein, During the scanning period, a first width of the effective period of the second scan signal is smaller than a second width of the non-effective period of the second emission control signal.

7. The display device according to claim 6, wherein, During the driving period, the effective period of the second scan signal has a third width different from the first width.

8. The display device according to claim 6, wherein, During the driving period, the non-effective period of the second emission control signal has a fourth width equal to the second width.

9. The display device according to claim 1, wherein, During the scanning period, the first scan signal is in a non-effective state.

10. The display device according to claim 1, wherein, During the scanning period, the effective period of the second scan signal and the non-effective period of the second emission control signal occur simultaneously.

11. The display device according to claim 1, wherein, A plurality of the scanning periods are included in the frame.

12. A pixel driving circuit, wherein, The pixel driving circuit includes: A first transistor, comprising a gate electrode connected to a first node, a first electrode electrically connected to a first voltage line for applying a first driving voltage, and a second electrode connected to a second node; A second transistor, comprising a gate electrode connected to a first scan line for applying a first scan signal, a first electrode connected to a data line, and a second electrode connected to the first node; A first capacitor, connected between the first node and the second node; A sixth transistor, comprising a gate electrode connected to a second emission line for applying a second emission control signal, a first electrode connected to the second node, and a second electrode connected to a third node; and A fourth transistor, comprising a gate electrode connected to a second scan line for applying a second scan signal different from the first scan signal, a first electrode connected to the third node, and a second electrode connected to a second voltage line for applying an initialization voltage, and wherein, during a scan period for holding a data voltage, a non-effective period of the second emission control signal overlaps with an effective period of the second scan signal.

13. The pixel driving circuit according to claim 12, wherein, The pixel driving circuit further comprises: A fifth transistor, comprising a gate electrode connected to a first emission line for applying a first emission control signal, a first electrode connected to the first voltage line, and a second electrode connected to the first electrode of the first transistor, wherein, during the scan period, the fifth transistor is in an on state.

14. The pixel driving circuit according to claim 13, wherein, The pixel driving circuit further comprises: A third transistor, comprising a gate electrode connected to a third scan line for applying a third scan signal different from the first scan signal and the second scan signal, a first electrode connected to a third voltage line for applying a reference voltage, and a second electrode connected to the first node.

15. The pixel driving circuit according to claim 14, wherein, During the scan period, the third transistor is in an off state.

16. The pixel driving circuit according to claim 12, wherein, During the scan period, a first width of the effective period of the second scan signal is less than a second width of the non-effective period of the second emission control signal.

17. The pixel driving circuit according to claim 12, wherein, During the scan period, the second transistor is in an off state.

18. A method for driving a display device, wherein, The display device includes a display panel, the display panel includes a driving controller, a light-emitting diode, and a pixel driving circuit, the pixel driving circuit includes a driving transistor, a switching transistor for receiving a data voltage, an initialization transistor connected to an initialization voltage line, a first light-emitting transistor, and a second light-emitting transistor, the method includes: Driving the display panel by the driving controller in units of frames including a driving period and a scan period; Keeping the first light-emitting transistor in an on state during the scan period; Providing a first period during the scan period, during which the second light-emitting transistor is off; Providing a second period during the period when the second light-emitting transistor is off, during which the initialization transistor is on, and wherein the first period overlaps with the second period.

19. The method according to claim 18, wherein, The first period overlaps with the entire second period.

20. The method according to claim 18, wherein, [[ID= Providing a third period during the driving period, during which the switching transistor is turned on; and Causing the light emitting diode to emit light during the driving period.

21. The method according to claim 18, wherein A first width of the first period is greater than a second width of the second period.

22. The method according to claim 18, wherein Alternately providing a plurality of the driving periods and a plurality of the scanning periods.

23. The method according to claim 18, wherein The method further includes: Keeping the switching transistor in an off state during the scanning period.

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