Wafer bonding edge collapse optimization method and semiconductor device

Abstract

The application provides a wafer bonding edge collapse optimization method and a semiconductor device, and relates to the technical field of semiconductor manufacturing. The wafer bonding edge collapse optimization method comprises the following steps: sequentially manufacturing a sacrificial layer and a seed layer on a substrate to obtain an upper wafer; manufacturing a groove penetrating through the sacrificial layer in the up-down direction on the upper wafer, and enabling the sacrificial layer to form a channel connected with the outside after being removed; manufacturing a first bonding layer on the upper wafer and sealing the groove through the first bonding layer, so that a hollow structure is formed in the groove; hot-press bonding the first bonding layer on a second bonding layer of a lower wafer and removing the sacrificial layer before or during the hot-press bonding; thinning the substrate and removing the peripheral structure including the groove. The wafer bonding edge collapse optimization method solves the problem that the prior art solution causes the bonding quality to be reduced when used in a specific application scenario, and achieves the effects of ensuring the bonding quality and improving the device quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a wafer bonding edge collapse optimization method and a semiconductor device. BACKGROUND

[0002] Referring to the Chinese invention patent with the authorization announcement number CN117276099B, the patent technology discloses that by setting a groove at the edge of the wafer, the cracks and edge collapses generated in the bonding interface during the thinning process are prevented from continuing to expand towards the center of the device, thereby protecting the internal devices of the wafer. However, the application scenario of this technical solution has limitations. When this technical solution is applied to a non-vacuum environment under normal pressure and the wafer adopts a hot-press bonding process, the hollow structure inside the technical solution contains gas, and the gas expands when heated, causing the associated structure to bulge, thereby reducing the bonding quality of the wafer. For example, the local position of the wafer fails to be tightly bonded, and even causes the wafer to warp or tilt, which seriously affects the quality of the device. Figure 3

[0003] At present, there is no effective technical solution to the above problems. SUMMARY

[0004] The purpose of the present application is to provide a wafer bonding edge collapse optimization method and a semiconductor device, which solves the problem of reduced bonding quality when the prior art solution is used in a bonding scenario under normal pressure and non-vacuum, and achieves the effects of ensuring bonding quality and improving device quality.

[0005] In a first aspect, the present application provides a wafer bonding edge collapse optimization method, comprising the following steps:

[0006] S1. A sacrificial layer and a seed layer are sequentially made on a substrate to obtain an upper wafer; the sacrificial layer is located at the edge of the substrate;

[0007] S2. A groove is made on the upper wafer, which penetrates the sacrificial layer in the up-down direction and forms a channel that connects the groove and the outside after the sacrificial layer is removed;

[0008] S3. Based on the non-vacuum environment under normal pressure, a first bonding layer is made on the upper wafer, and the groove is sealed by the first bonding layer, so that a hollow structure is formed in the groove;

[0009] S4. The first bonding layer is hot-pressed on the second bonding layer of the lower wafer, and the sacrificial layer is removed before or during hot-pressing, so that a thin wall appears in the hollow structure during hot-pressing, and the gas in the hollow structure expands due to heating and breaks through the thin wall, causing the hollow structure to communicate with the outside, thereby reducing the internal pressure of the hollow structure;

[0010] ​S5. Thinning the substrate and removing a peripheral structure including the groove.

[0011] The wafer bonding edge collapse optimization method provided by the application utilizes a sacrificial layer to manufacture a thin-walled gas breakthrough hollow structure. Through this active control of gas release, the internal pressure of the hollow structure can be effectively reduced, thereby avoiding quality defects such as bulging of the wafer, and further improving the quality of the device.

[0012] Further, in step S2, the downward projection of the groove covers the edge of the sacrificial layer away from the outside, so that after the groove is completed, the inner edge of the sacrificial layer is fully exposed on the sidewall of the groove.

[0013] The remaining sacrificial layer can be avoided to remain in the inner structure, thereby further ensuring the integrity of the edge of the finished device and ensuring the performance of the device.

[0014] Further, the first bonding layer and the second bonding layer are made of copper, aluminum or gold material.

[0015] Further, the specific steps in step S4 include:

[0016] S41. When the sacrificial layer is made of a material that is not thermally volatile and not thermally decomposable, the sacrificial layer is removed before thermal pressure bonding.

[0017] Further, the non-thermally volatile and non-thermally decomposable material includes polymethyl methacrylate, hydrogen silane silane, photoresist or polyether ether ketone.

[0018] Further, the specific steps in step S4 include:

[0019] S42. When the sacrificial layer is made of a material that is thermally volatile or thermally decomposable, the sacrificial layer is removed by heat during thermal pressure bonding.

[0020] The thermal pressure bonding process is fully utilized, and additional processes are avoided, which is conducive to improving production efficiency.

[0021] Further, the thermally volatile or thermally decomposable material includes parylene, polydimethylsiloxane, polypropylene, polystyrene, polyurethane or silicon carbide.

[0022] In a second aspect, the application provides a semiconductor device manufactured by the wafer bonding edge collapse optimization method described above.

[0023] In a third aspect, the application provides a semiconductor device, comprising:

[0024] An upper wafer, the upper wafer comprising a substrate, a sacrificial layer and a seed layer in sequence; the sacrificial layer is located at the edge of the substrate;

[0025] a groove, which penetrates the sacrificial layer along the up-down direction and enables a channel to be formed after the sacrificial layer is removed, the channel connecting the groove with the outside world;

[0026] a first bonding layer, which is arranged on the upper wafer and seals the groove under the condition of normal pressure in a non-vacuum environment, so that a hollow structure is formed in the groove;

[0027] a lower wafer, which comprises a second bonding layer, the second bonding layer being hot-pressed and bonded on the first bonding layer; the sacrificial layer is used to form a thin wall after being removed, the thin wall being able to be broken by the gas in the hollow structure so as to connect the hollow structure with the outside world, thereby reducing the internal pressure of the hollow structure; the groove is used to block the edge collapse of the peripheral structure from spreading to the inner structure surrounded by the groove.

[0028] Further, the groove is arranged at a position whose downward projection covers the side edge of the sacrificial layer away from the outside world, and the inner side edge of the sacrificial layer is entirely exposed on the side wall of the groove.

[0029] As can be seen from the above, the wafer bonding edge collapse optimization method provided by the present application increases the sacrificial layer at the edge of the wafer and removes the sacrificial layer before or during bonding, so that a thin wall that can be broken is formed in the hollow structure, thereby actively controlling the gas to break through the thin wall of the hollow structure, so as to release the internal pressure of the hollow structure, and further avoid the associated structure from bulging, which not only ensures the bonding quality, but also ensures the device quality.

[0030] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application according to the embodiments. The objects and other advantages of the present application will be achieved by means of the structure particularly pointed out in the written description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A flow chart of the wafer bonding edge collapse optimization method provided by the embodiments of the present application.

[0032] Figure 2 A preparation process schematic diagram of a semiconductor device provided by the embodiments of the present application.

[0033] Figure 3 A structure schematic diagram of a device bulging in the prior art.

[0034] Figure 4 A structure schematic diagram of a semiconductor device provided by the embodiments of the present application.

[0035] Figure 5A schematic view of a structure after a thin wall is broken and a channel is formed in an embodiment of the present application.

[0036] Figure 6 A schematic view of a partial structure in which a projection of the groove in the up-down direction covers a part of the end of the sacrificial layer away from the outside in an embodiment of the present application.

[0037] Figure 7 A schematic view of a partial structure in which a projection of the groove in the up-down direction covers only between the two ends of the width direction of the sacrificial layer in an embodiment of the present application.

[0038] Figure 8 A schematic view of a structure in which an annular sacrificial layer is arranged on a substrate in an embodiment of the present application.

[0039] Figure 9 A schematic view of a structure in which a plurality of strip-shaped sacrificial layers are arranged on a substrate in an embodiment of the present application.

[0040] Figure 10 A schematic view of a structure in which a strip-shaped sacrificial layer is arranged on a substrate in an embodiment of the present application.

[0041] Label explanation:

[0042] 100, upper wafer; 110, substrate; 120, sacrificial layer; 130, seed layer; 200, groove; 210, hollow structure; 211, thin wall; 300, first bonding layer; 400, lower wafer; 410, second bonding layer. DETAILED DESCRIPTION

[0043] Embodiments of the present application are described in detail below with reference to the accompanying drawings. The embodiments described below are examples for explaining the present application and should not be construed as limiting the present application.

[0044] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0045] In the description of the application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0046] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "upper", "above" and "on" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The "under", "below" and "under" of the first feature to the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0047] The following disclosure provides many different embodiments or examples for implementing different structures of the application. In order to simplify the disclosure of the application, the components and arrangements of specific examples are described in the following. Of course, they are only examples, and the purpose is not to limit the application. In addition, the application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0048] The technical solutions in the embodiments of the application will be described clearly and completely in the following with reference to the accompanying drawings of the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, not all the embodiments. The components of the embodiments of the application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the application. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0049] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Also, in the description of this invention, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0050] It should be noted that the "up and down direction" mentioned below refers to... Figure 1 The arrows are for reference.

[0051] Reference Appendix Figure 1 Appendix Figure 2 Appendix Figure 4 and attached Figure 5 This invention provides a method for optimizing wafer bonding edge breakage, comprising the following steps:

[0052] S1. A sacrificial layer and a seed layer are sequentially fabricated on the substrate to obtain the upper wafer; the sacrificial layer is located at the edge of the substrate;

[0053] S2. A groove is made on the upper wafer that penetrates the sacrificial layer in the vertical direction, and a channel connecting the groove and the outside can be formed after the sacrificial layer is removed;

[0054] S3. Under normal pressure and non-vacuum conditions, a first bonding layer is fabricated on the upper wafer and the groove is sealed by the first bonding layer to form a hollow structure inside the groove;

[0055] S4. The first bonding layer is hot-pressed onto the second bonding layer of the lower wafer, and the sacrificial layer is removed before or during hot-pressing, so that the hollow structure has a thin wall during hot-pressing and the gas inside the hollow structure breaks through the thin wall due to thermal expansion, causing the hollow structure to connect with the outside, thereby reducing the internal pressure of the hollow structure.

[0056] S5. Thin the substrate and remove the peripheral structure, including the groove.

[0057] In this embodiment, the manufacturing conditions are lowered to a non-vacuum environment at atmospheric pressure. Although this may reduce the quality of the layer structure, it effectively reduces costs. As a result of the reduced costs, the finished devices can be sold at a lower price to meet the supply needs of the low-end market.

[0058] In practical applications, after the first bonding layer seals the groove, the hollow structure formed inside the groove will seal a certain amount of gas. During the thermal pressure bonding, the sealed gas expands under heat, causing the hollow structure to expand outward and form an outward bulging bump. This bump often affects the flatness of the first bonding layer, making it impossible for the first bonding layer to be tightly connected to the second bonding layer, resulting in problems such as separation of the upper wafer from the lower wafer or tilting of the upper wafer relative to the lower wafer.

[0059] To this end, the present embodiment proposes a technical solution of providing a sacrificial layer at the edge of the upper wafer. By removing the sacrificial layer before or during thermal pressure bonding, a thin wall that is easily broken is formed at a designated position of the hollow structure, thereby artificially controlling the gas to break through the thin wall, allowing the hollow structure to communicate with the outside world, and finally releasing the internal pressure of the hollow structure, achieving the effect of internal and external pressure balance. This avoids the formation of a bulging bump, which is beneficial to ensure that the upper wafer and the lower wafer are tightly bonded everywhere, effectively avoiding the problem of wafer warping or tilting, and achieving the effect of improving the quality of finished devices.

[0060] It should be noted that the design of the groove is the same as the prior art, and the hollow structure formed by the groove blocks the cracks or edge collapse generated at the bonding interface between the upper wafer and the lower wafer during thinning from continuing to expand into the wafer (i.e., the inner structure surrounded by the groove).

[0061] After step S5 is performed, the substrate will be thinned (the thickness of the remaining substrate after thinning is less than the depth of the groove extending into the substrate) and the peripheral structure (including the groove and the peripheral part of the groove) will be removed. At the same time, since the sacrificial layer is provided at the edge of the upper wafer, when the gas breaks through the thin wall, the gap will only appear on the peripheral structure. Therefore, even if the gap forms irregular structural fragments or cracks, they will eventually be removed like the cracks and edge collapse generated at the bonding interface, so they will not affect the integrity of the finished device edge, which is beneficial to ensure the regularity of the wafer appearance and the quality of the devices inside the wafer.

[0062] In some embodiments, reference is made to the accompanying drawings Figure 6 and the accompanying drawings Figure 7 In step S2, the downward projection of the groove opening position covers the side edge of the sacrificial layer away from the outside world, so that after the groove is completed, the inside edge of the remaining part of the sacrificial layer (the sacrificial layer is in a complete state before the groove is made, and after the groove is made, part of the sacrificial layer is cut off by the groove, and the remaining part is the remaining part) is completely exposed on the side wall of the groove (here, it is emphasized that the remaining part of the sacrificial layer only remains on the peripheral structure and not in the inner structure).

[0063] In actual application, if the downward projection of the groove opening position only covers between the two ends of the width direction of the sacrificial layer (i.e. the groove cuts the sacrificial layer from between the two ends of the width direction of the sacrificial layer), it will cause part of the remaining sacrificial layer to remain in the inner structure. When the sacrificial layer is removed, it will cause the edge of the inner structure to be incomplete, thereby affecting the integrity of the edge of the finished device, or when step S5 is performed, part of the inner structure needs to be further removed, resulting in more material loss, and even affecting the performance of the device.

[0064] In contrast, the downward projection of the groove opening position of the present embodiment covers the side edge of the sacrificial layer away from the outside (i.e. the groove cuts the sacrificial layer from the end of the sacrificial layer away from the outside), which can avoid the remaining sacrificial layer remaining in the inner structure, thereby further ensuring the integrity of the edge of the finished device and ensuring the performance of the device.

[0065] In some embodiments, the first bonding layer and the second bonding layer are made of copper, aluminum or gold material.

[0066] In some preferred embodiments, the first bonding layer and the second bonding layer are made of gold material. In actual application, Cu, Al and Au are suitable for thermal compression bonding due to their high diffusion rate. Among the three metals, Cu and Al have good ductility, but Cu and Al require a bonding temperature of 400°C to ensure bonding quality. At the same time, the surface of copper and aluminum is easily oxidized, and the oxidation layer needs to be treated before bonding to ensure the bonding effect. Compared with Cu and Al, Au-Au thermal compression bonding requires a bonding temperature of about 300°C, and the surface of Au does not form an oxide, and the surface treatment before bonding is relatively easy, and is more suitable for thermal compression bonding. The mechanism of Au-Au thermal compression bonding is that Au-Au is in contact with each other, and is combined together by diffusion and melting under a certain pressure and temperature. The surface roughness of sputtered Au is low, which is conducive to achieving good bonding effect.

[0067] In some embodiments, the specific steps in step S4 include:

[0068] S41. When the sacrificial layer is made of a material that is not thermally volatile and not thermally decomposable, the sacrificial layer is removed before thermal compression bonding.

[0069] Further, the material that is not thermally volatile and not thermally decomposable includes polymethyl methacrylate, hydrogen silane silane, photoresist or polyether ether ketone.

[0070] In the actual application, the sacrificial layer made of polymethyl methacrylate needs to be removed by dissolving with solvents such as methyl ethyl ketone, ethyl acetate, acetone, etc. The sacrificial layer made of hydrosilane needs to be removed by dissolving with solvents such as hydrogen fluoride. The sacrificial layer made of photoresist needs to be removed by dissolving with solvents such as acetone, isopropyl alcohol, etc. The sacrificial layer made of polyether ether ketone needs to be removed by dissolving with solvents such as dichloromethane, N-methyl pyrrolidone, etc.

[0071] In some embodiments, the specific steps in step S4 include:

[0072] S42. When the sacrificial layer is made of a material that volatilizes or decomposes under heat, the sacrificial layer is removed during thermal compression bonding by using the heat generated during thermal compression bonding.

[0073] Further, the material that volatilizes or decomposes under heat includes poly-p-xylylene, polydimethylsiloxane, polypropylene, polystyrene, polyurethane, or silicon carbide.

[0074] In the actual application, the material that volatilizes or decomposes under heat synchronously converts the sacrificial layer into gaseous products by using the heat generated during thermal compression bonding, which not only removes the sacrificial layer without residue, but also ensures the appearance of the exposed thin wall of the hollow structure, and fully utilizes the thermal compression bonding process, avoiding the addition of extra processes and improving the production efficiency.

[0075] Reference is made to the accompanying drawings Figure 4 and the accompanying drawings Figure 5 , the present application provides a semiconductor device manufactured by the wafer bonding edge collapse optimization method in the above embodiments.

[0076] The present application provides a semiconductor device, comprising:

[0077] The upper wafer 100 sequentially comprises a substrate 110, a sacrificial layer 120, and a seed layer 130; the sacrificial layer 120 is located at the edge of the substrate 110.

[0078] The recess 200 penetrates the sacrificial layer 120 in the up-down direction and forms a channel that connects the recess 200 with the outside after the sacrificial layer 120 is removed.

[0079] The first bonding layer 300 is arranged on the upper wafer 100 and seals the recess 200 under the condition of normal pressure in a non-vacuum environment, so as to form a hollow structure 210 in the recess 200.

[0080] The lower wafer 400 includes a second bonding layer 410, which is thermocompression bonded on the first bonding layer 300; the sacrificial layer 120 is used to form the thin wall 211 after being removed, the thin wall 211 can be broken by the gas in the hollow structure 210 to make the hollow structure 210 communicate with the outside, thereby reducing the internal pressure of the hollow structure 210; the groove 200 is used to block the edge collapse of the peripheral structure from spreading to the inner structure surrounded by the groove 200.

[0081] In some embodiments, reference is made to the accompanying drawings that form a part of this specification Figure 8 , the accompanying drawings Figure 9 , and the accompanying drawings Figure 10 , the sacrificial layer 120 can be arranged in a ring shape at the edge of the substrate 110, or in a plurality of strip structures extending towards the center of the substrate 110, and the plurality of strip structures are arranged circumferentially along the edge of the substrate 110, or only one strip structure extending towards the center of the substrate 110, and the strip structure is arranged at the edge of the substrate 110.

[0082] In some embodiments, reference is made to the accompanying drawings Figure 6 , and the accompanying drawings Figure 7 , the projection of the opening position of the groove 200 downward covers the side edge of the sacrificial layer 120 away from the outside and the inner side edge of the remaining part of the sacrificial layer 120 is exposed on the sidewall of the groove 200.

[0083] In this document, the terms "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0084] The description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0085] The above only describes the embodiments of the present application and does not limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for optimizing wafer bonding edge breakage, characterized in that, Includes the following steps: S1. A sacrificial layer and a seed layer are sequentially fabricated on a substrate to obtain an upper wafer; the sacrificial layer is located at the edge of the substrate; S2. A groove is formed on the upper wafer that penetrates the sacrificial layer in the vertical direction, and after the sacrificial layer is removed, a channel is formed that connects the groove to the outside. S3. Under normal pressure and non-vacuum conditions, a first bonding layer is fabricated on the upper wafer and the groove is sealed with the first bonding layer to form a hollow structure inside the groove; S4. The first bonding layer is hot-pressed onto the second bonding layer of the lower wafer, and the sacrificial layer is removed before or during hot-pressing, so that the hollow structure has a thin wall during hot-pressing and the gas inside the hollow structure expands due to heat and breaks through the thin wall, causing the hollow structure to communicate with the outside, thereby reducing the internal pressure of the hollow structure; the specific steps include: S41. When the sacrificial layer is made of a material that is not thermally volatile and does not thermally decompose, the sacrificial layer is removed before hot-press bonding; S42. When the sacrificial layer is made of a material that volatilizes or decomposes upon heating, the sacrificial layer is removed during hot-press bonding using the heat generated during the hot-press bonding process; S5. Thin the substrate and remove the peripheral structure including the groove.

2. The wafer bonding edge breakage optimization method according to claim 1, characterized in that, In step S2, the downward projection of the groove covers the side edge of the sacrificial layer away from the outside, so that after the groove is made, the inner edge of the sacrificial layer is fully exposed on the side wall of the groove.

3. The wafer bonding edge breakage optimization method according to claim 1, characterized in that, The first bonding layer and the second bonding layer are made of copper, aluminum or gold.

4. The wafer bonding edge breakage optimization method according to claim 1, characterized in that, The materials that are not thermally volatile and not thermally decomposed include polymethyl methacrylate, hydrosilyl silane, photoresist, or polyetheretherketone.

5. The wafer bonding edge breakage optimization method according to claim 1, characterized in that, The materials that volatilize or decompose upon heating include parylene, polydimethylsiloxane, polypropylene, polystyrene, polyurethane, or silicon carbide.

6. A semiconductor device, characterized in that, Manufactured using the wafer bonding edge breakage optimization method as described in any one of claims 1-5.

7. A semiconductor device, characterized in that, include: The upper wafer (100) comprises a substrate (110), a sacrificial layer (120), and a seed layer (130) in sequence; the sacrificial layer (120) is located at the edge of the substrate (110); The groove (200) penetrates the sacrificial layer (120) in the vertical direction and forms a channel connecting the groove (200) to the outside after the sacrificial layer (120) is removed; A first bonding layer (300) is disposed on the upper wafer (100) and the groove (200) is sealed under normal pressure non-vacuum environment conditions to form a hollow structure (210) inside the groove (200). The lower wafer (400) includes a second bonding layer (410) that is hot-pressed onto the first bonding layer (300). The sacrificial layer (120) is used to remove the hollow structure (210) so that a thin wall (211) appears in the hollow structure (210). The thin wall (211) can be broken by the gas inside the hollow structure (210) to make the hollow structure (210) communicate with the outside, thereby reducing the internal pressure of the hollow structure (210). The groove (200) is used to prevent the edge breakage generated by the outer structure from extending to the inner structure surrounded by the groove (200). When the sacrificial layer is made of a material that is not thermally volatile and not thermally decomposed, the sacrificial layer is removed before hot-pressing. When the sacrificial layer is made of a material that is thermally volatile or thermally decomposed, the sacrificial layer is removed during hot-pressing using the heat generated during hot-pressing.

8. The semiconductor device according to claim 7, characterized in that, The downward projection of the groove (200) covers the side edge of the sacrificial layer (120) away from the outside, and the inner edge of the sacrificial layer (120) is fully exposed on the side wall of the groove (200).

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