Self-adaptive dual-redundancy system merging unit automatic switching device and method

Abstract

The invention discloses a merging unit automatic switching device and method of a self-adaptive dual-redundancy system. The merging unit automatic switching device comprises a switching system 1, a switching system 2 and an MUX, an FPGA (Field Programmable Gate Array) 1 is arranged in the switching system 1, and an FPGA 2 is arranged in the switching system 2. The switching system 1 and the switching system 2 receive data of the bus merging unit A and the bus merging unit B at the same time; the switching system 1 and the switching system 2 determine a selection mode according to respective received input signals; the FPGA1 and the FPGA2 respectively process the data of the A set of bus merging unit and the B set of bus merging unit; the FPGA1 and the FPGA2 are used for sending the selected data to the MUX and the respective switching systems of the MUX and the MUX; the data selected by the FPGA 1 and the data selected by the FPGA A2 are monitored by the switching system 1 and the switching system 2 respectively; and the MUX outputs the corresponding data C1 or the data C2 to each sending optical port according to the output logic.

Description

Technical Field

[0001] The present invention belongs to the technical field of intelligent substations, and particularly relates to an automatic switching device and method for an adaptive dual-redundancy system merging unit. Background Art

[0002] For a typical 220 kV intelligent substation, the voltage acquisition of each interval protection of 110 kV and the A set of main transformer protection all need to pass through the 110 kV bus merging unit A. For the 110 kV double-bus connection situation, when the bus merging unit A is abnormal, it will affect the voltage acquisition of the 110 kV bus protection, the A set of main transformer protection, and all line protections, causing the distance and directional zero-sequence functions of each line protection and the backup protection in the main transformer to exit. Only the PT breakover current protection remains in each line interval, and the bus differential protection has no voltage locking guarantee. In extreme cases, it may lead to misoperation of the protection and expand the fault range. Currently, to solve this problem, different methods are adopted for newly built substations and renovated old substations.

[0003] For newly built substation line intervals, a voltage seamless selection and integration device is configured, which collects the voltages of Bus I and Bus II from both the bus merging unit A and the bus merging unit B, and by default, adopts the voltage of the bus merging unit A, as Figure 1 shown. When the optical fiber of the bus merging unit A is disconnected, frames are lost, or the data is abnormal, the voltage seamless selection and integration device automatically identifies and selects to adopt the voltage of the bus merging unit B, and automatically re-selects the voltage of A after the data of the bus merging unit A is normal, thus solving the problem of voltage loss of each interval protection when the bus merging unit is abnormal.

[0004] For the renovation scheme adopted for old substations, Chinese Patent Application CN109660020 discloses a bus voltage intelligent selection and switching device and method. This scheme proposes to connect both the A / B bus merging units to this device. When data is invalid, the bus voltage intelligent selection and switching device will select and send the data of the effective bus merging unit, as Figure 2As shown. This solution does save a large amount of optical cables and improve work efficiency, but there are still the following problems. When the bus voltage intelligent selection and switching device fails, it will still cause the bus protection, the main transformer protection of set A, and all line protections to lose voltage, unable to solve the N-1 problem like that of a single merging unit failure, nor can it ensure the solution of the voltage loss problem of each interval protection. The communication protocol for the analog quantity sampling in the process layer of many old substations is the IEC60044-8 protocol, and the existing bus voltage intelligent selection and switching device only supports the IEC61850-9-2 protocol, and these substations cannot be transformed either. In addition, for the case where different manufacturers' devices are configured for the dual bus merging units, the channel sequence of the voltage sampling data output by the dual bus merging units may be inconsistent at this time. The existing bus voltage intelligent selection and switching device can only switch the sampling voltage data as a whole and does not support the case of different manufacturers' devices configured for the dual bus merging units.

[0005] In view of the above problems, the present invention proposes an adaptive dual-redundancy system merging unit automatic switching device and method. When the bus merging unit A is abnormal, the voltage data of the bus merging unit B is selected and sent out, so that the voltage acquisition of the 110kV bus protection, the main transformer protection of set A, and all line protections remains normal, and the distance, directional zero-sequence functions of each line protection and the backup protection in the main transformer, as well as the bus differential protection, remain normal. Summary of the Invention

[0006] In order to achieve the above object, the technical solution of the present application is proposed as follows:

[0007] A merging unit automatic switching device for an adaptive dual-redundancy system includes a switching system 1, a switching system 2, and a MUX.

[0008] The switching system 1 includes an FPGA1, a DSP1, an input module 1, and a power supply 1.

[0009] The switching system 2 includes an FPGA2, a DSP2, an input module 2, and a power supply 2.

[0010] The MUX is a hardware selector that selects and sends the received data.

[0011] Further, the power supply 1 supplies power to the FPGA1, the DSP1, the input module 1, and the MUX; the power supply 2 supplies power to the FPGA2, the DSP2, the input module 2, and the MUX.

[0012] Further, the input module 1 and the input module 2 collect the same set of input signals; the input signals include an automatic selection input and a forced selection input; the forced selection input includes a forced selection input for set A bus merging unit and a forced selection input for set B bus merging unit.

[0013] Further, the FPGA1 and the FPGA2 have two selection modes, namely the automatic selection mode and the forced selection mode; the forced selection mode includes forced selection of the bus merging unit of set A and forced selection of the bus merging unit of set B.

[0014] Further, the input module 1 controls the FPGA1 to enter the corresponding selection mode; the input module 2 controls the FPGA2 to enter the corresponding selection mode.

[0015] Further, the switching system 1 and the switching system 2 simultaneously receive data A sent by the bus merging unit of set A and data B sent by the bus merging unit of set B;

[0016] The FPGA1 processes the data A and the data B to obtain data C1, and sends it to the MUX and the DSP1;

[0017] The FPGA2 processes the data SV1 and the data SV2 to obtain data C2, and sends it to the MUX and the DSP2;

[0018] The MUX outputs the corresponding data C1 or data C2 to each transmitting optical port according to the output logic.

[0019] Further, for the processing, it is judged the modes of the FPGA1 and the FPGA2. If it is the automatic selection mode, the FPGA1 and the FPGA2 select data according to the automatic switching logic; if it is the forced selection mode, the FPGA1 and the FPGA2 select the data of the bus merging unit in the corresponding forced mode.

[0020] Specifically, the automatic switching logic is that when both the data A and the data B are normal, the FPGA1 and the FPGA2 select the data A; when the data A is normal and the data B is abnormal, the FPGA1 and the FPGA2 select the data A; when the data A is abnormal and the data B is normal, the FPGA1 and the FPGA2 select the data B; when both the data A and the data B are abnormal, the FPGA1 and the FPGA2 maintain the current selection state.

[0021] Further, the DSP1 receives the data A and the data B through the FPGA1, and simultaneously receives the data C1 processed by the FPGA1; the DSP2 receives the data A and the data B through the FPGA2, and simultaneously receives the data C2 processed by the FPGA2.

[0022] Further, the data C1 and the data C2 are determined according to an automatic switching logic or a forced selection mode. If the data C1 and the data C2 are the data A, the DSP1 checks the received data C1 against the data A. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally. If they are inconsistent, the signal SEL1 of the FPGA1 is set to 0, and the switching system 1 issues an alarm and locks the transmission.

[0023] The DSP2 checks the received data C2 against the data A. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally. If they are inconsistent, the signal SEL1 of the FPGA2 is set to 0, and the switching system 2 issues an alarm and locks the transmission.

[0024] If the data C1 and the data C2 are the data B, the DSP1 checks the received data C1 against the data B. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally. If they are inconsistent, the signal SEL1 of the FPGA1 is set to 0, and the switching system 1 issues an alarm and locks the transmission.

[0025] The DSP2 checks the received data C2 against the data B. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally. If they are inconsistent, the signal SEL1 of the FPGA2 is set to 0, and the switching system 2 issues an alarm and locks the transmission.

[0026] Further, the output logic is selected according to the signal SEL1 and the signal SEL2. When the signal SEL1 is set to 1 and the signal SEL2 is set to 1, the MUX selects the data C1 sent by the FPGA1 for output.

[0027] When the signal SEL1 is set to 1 and the signal SEL2 is set to 0, the MUX selects the data C1 sent by the FPGA1 for output.

[0028] When the signal SEL1 is set to 0 and the signal SEL2 is set to 1, the MUX selects the data C2 sent by the FPGA1 for output.

[0029] When the signal SEL1 is set to 0 and the signal SEL2 is set to 0, the MUX does not output.

[0030] Furthermore, the device has two independent switching systems; the device has an independent dual power supply system, and the two do not affect each other; the device is provided with a dual input module, and the input module can receive input signals; the MUX is powered by an independent dual power supply system.

[0031] Furthermore, the two switching systems each output monitoring signals for busbar merging unit A and busbar merging unit B through GOOSE, so that if any abnormal situation occurs, the operation and maintenance personnel can be notified in time for processing;

[0032] The two switching systems receive binary input signals via the CAN bus, and the binary input signals are collected and received by the binary input modules. When any one of the binary input modules is abnormal, it does not affect the collection and reception of the binary input signals by the other binary input module.

[0033] The device is provided with a dual power supply system to independently power the two switching systems, and the overall function of the device is not affected when either power supply is cut off;

[0034] The MUX is powered by the dual power supply system, and the MUX function is not affected when any one of the switching systems is powered off.

[0035] Furthermore, the device adaptively supports the IEC60044-8 and IEC61850-9-2 protocol cascade bus voltage data types by configuring the cascade bus voltage protocol with a fixed value, that is, the format of the data A and the data B is IEC60044-8 or IEC61850-9-2.

[0036] Furthermore, when the voltage channel sequence of the bus merging unit A and the bus merging unit B are inconsistent, the device configures the voltage channel sequence through a human-machine interface. When the bus merging unit A is abnormal, the device switches to the bus merging unit B and can quickly and automatically match the voltage data channel sequence of the A / B bus merging units.

[0037] Furthermore, the device has a non-delay forwarding function, and the time from when the device receives the data A and the data B to when the optical port of the device sends the data after the logical selection is negligible.

[0038] A method for automatically switching a merging unit of an adaptive dual-redundancy system comprises the following steps:

[0039] Step 1: The switching system 1 and the switching system 2 simultaneously receive data A sent by bus merging unit set A and data B sent by bus merging unit set B;

[0040] Step 2: The FPGA1 processes the data A and the data B to obtain data C1, and sends it to the MUX and the DSP1; the FPGA2 processes the data SV1 and the data SV2 to obtain data C2, and sends it to the MUX and the DSP2;

[0041] Step 3: The MUX outputs the corresponding data C1 or data C2 to each transmitting optical port according to the output logic.

[0042] Further, the specific steps of the processing in Step 2 are as follows:

[0043] Step 2.1: The device judges the modes of the FPGA1 and the FPGA2; there are two selection modes for the FPGA1 and the FPGA2, namely the automatic selection mode and the forced selection mode

[0044] Step 2.2: In the automatic selection mode, the FPGA1 and the FPGA2 make selections according to the automatic switching logic;

[0045] Step 2.3: In the forced selection mode, the FPGA1 and the FPGA2 select the bus merging unit under the corresponding forced mode.

[0046] Further, the specific manner of the automatic switching logic in Step 2.2 is as follows:

[0047] When the data A is normal and the data B is normal, the FPGA1 and the FPGA2 select the data A;

[0048] When the data A is normal and the data B is abnormal, the FPGA1 and the FPGA2 select the data A;

[0049] When the data A is abnormal and the data B is normal, the FPGA1 and the FPGA2 select the data B;

[0050] When both the data A and the data B are abnormal, the FPGA1 and the FPGA2 maintain the current selection state.

[0051] Further, in the forced selection mode of Step 2.3, there are forced selections of the bus merging unit of set A and the bus merging unit of set B;

[0052] When the FPGA1 and the FPGA2 are in the forced selection of the bus merging unit of set A, the FPGA1 and the FPGA2 select the data A;

[0053] When the FPGA1 and the FPGA2 are in the forced selection of the bus merging unit B set, the FPGA1 and the FPGA2 select the data B.

[0054] Further, in step 2, the DSP1 receives the data A and the data B through the FPGA1, and at the same time receives the data C1 processed by the FPGA1; the DSP2 receives the data A and the data B through the FPGA2, and at the same time receives the data C2 processed by the FPGA2;

[0055] The data C1 and the data C2 are determined according to the automatic switching logic or the forced selection mode. If the data C1 and the data C2 are the data A, the DSP1 verifies the received data C1 with the data A. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally; if they are inconsistent, the signal SEL1 of the FPGA1 is set to 0, and the switching system 1 gives an alarm and locks the transmission;

[0056] The DSP2 verifies the received data C2 with the data A. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally; if they are inconsistent, the signal SEL1 of the FPGA2 is set to 0, and the switching system 2 gives an alarm and locks the transmission;

[0057] If the data C1 and the data C2 are the data B, the DSP1 verifies the received data C1 with the data B. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally; if they are inconsistent, the signal SEL1 of the FPGA1 is set to 0, and the switching system 1 gives an alarm and locks the transmission;

[0058] The DSP2 verifies the received data C2 with the data B. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally; if they are inconsistent, the signal SEL1 of the FPGA2 is set to 0, and the switching system 2 gives an alarm and locks the transmission.

[0059] Further, the output logic in step 3 is as follows:

[0060] When the signal SEL1 is set to 1 and the signal SEL2 is set to 1, the MUX selects the data C1 sent by the FPGA1 for output;

[0061] When the signal SEL1 is set to 1 and the signal SEL2 is set to 0, the MUX selects the data C1 sent by the FPGA1 for output;

[0062] When the signal SEL1 is set to 0 and the signal SEL2 is set to 1, the MUX selects the data C2 sent by the FPGA1 for output;

[0063] When the signal SEL1 is set to 0 and the signal SEL2 is set to 0, the MUX does not output.

[0064] Compared with the prior art, the present invention provides an automatic switching device and method for an adaptive dual-redundancy system merging unit, having the following advantages:

[0065] 1. Two sets of independent switching systems are adopted to process the data of the merging unit of busbar set A and the merging unit of busbar set B simultaneously. The two systems are independently powered and operate independently. One system is on duty and the other is in standby. When the on-duty system loses power or malfunctions, the standby system switches to the on-duty state, ensuring that the overall function of the device is not affected, improving the reliable operation level of the substation protection device, avoiding the bad situation of expanding a point fault into a surface fault, and solving the problem that the current intelligent bus voltage selection and switching device causes the loss of voltage for each interval protection due to the device's own fault.

[0066] 2. The present invention adaptively supports the cascaded bus voltage data types of IEC60044-8 and IEC61850-9-2 protocols, solving the problem that some old substations cannot be renovated. In addition, for the situation where the voltage channel sequences of the dual bus merging units are inconsistent, the present invention supports automatically matching the voltage data channel sequences of the A / B set bus merging units, solving the problem that the substation cannot be renovated when the voltage channels of the two bus merging units are inconsistent. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 Schematic diagram of cascading of dual bus merging units;

[0068] Figure 2 Voltage switching scheme for renovated substations;

[0069] Figure 3 System architecture diagram of an automatic switching device for a merging unit of an adaptive dual-redundancy system;

[0070] Figure 4 Data processing steps for FPGA1 and FPGA2 to receive data;

[0071] Figure 5 Automatic switching logic table of an automatic switching device for a merging unit of an adaptive dual-redundancy system;

[0072] Figure 6 Output logic table of an automatic switching device for a merging unit of an adaptive dual-redundancy system. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0073] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0074] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0075] It should also be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0076] It should be further understood that the term "and / or" used in the specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0077] Embodiment 1

[0078] An automatic switching device for a merging unit of an adaptive dual-redundancy system includes a switching system 1, a switching system 2, and a MUX; the switching system 1 includes an FPGA 1, a DSP 1, an input module 1, and a power supply 1; the switching system 2 includes an FPGA 2, a DSP 2, an input module 2, and a power supply 2; the MUX is a hardware selector that selects and sends the received data.

[0079] The power supply 1 supplies power to the FPGA 1, the DSP 1, the input module 1, and the MUX; the power supply 2 supplies power to the FPGA 2, the DSP 2, the input module 2, and the MUX.

[0080] The input module 1 and the input module 2 collect the same set of input signals; the input signals include an automatic selection input and a forced selection input; the forced selection input includes a forced selection input for the merging unit of bus set A and a forced selection input for the merging unit of bus set B.

[0081] The FPGA 1 and the FPGA 2 have two selection modes, namely an automatic selection mode and a forced selection mode; the forced selection mode includes a forced selection of the merging unit of bus set A and a forced selection of the merging unit of bus set B.

[0082] The input module 1 controls the FPGA1 to enter the corresponding selection mode; the input module 2 controls the FPGA2 to enter the corresponding selection mode.

[0083] The switching system 1 and the switching system 2 simultaneously receive the data A sent by the set A bus merging unit and the data B sent by the set B bus merging unit;

[0084] The FPGA1 processes the data A and the data B to obtain the data C1, and sends it to the MUX and the DSP1;

[0085] The FPGA2 processes the data SV1 and the data SV2 to obtain the data C2, and sends it to the MUX and the DSP2;

[0086] The MUX outputs the corresponding data C1 or data C2 to each transmitting optical port according to the output logic.

[0087] For the above processing, judge the modes of the FPGA1 and the FPGA2. If it is the automatic selection mode, the FPGA1 and the FPGA2 select data according to the automatic switching logic; if it is the forced selection mode, the FPGA1 and the FPGA2 select the data of the bus merging unit in the corresponding forced mode.

[0088] If the input module 1 and the input module 2 collect the automatic selection input signals, the input module 1 controls the FPGA1 to enter the automatic selection mode, and the input module 2 controls the FPGA2 to enter the automatic selection mode;

[0089] The FPGA1 and the FPGA2 synchronously receive the data A of the set A bus merging unit and the data B of the set B bus merging unit;

[0090] The automatic switching logic is triggered in the automatic selection mode, as specifically shown in Table 1,

[0091] When the data A is normal and the data B is normal, the FPGA1 and the FPGA2 select the data A;

[0092] When the data A is normal and the data B is abnormal, the FPGA1 and the FPGA2 select the data A;

[0093] When the data A is abnormal and the data B is normal, the FPGA1 and the FPGA2 select the data B;

[0094] When the data A is abnormal and the data B is abnormal, the FPGA1 and the FPGA2 maintain the current selection state.

[0095] The input module 1 and the input module 2 collect the input signals for forcibly selecting the merging unit of busbar set A. Then, the input module 1 controls the FPGA1 to forcibly select the merging unit of busbar set A, and the input module 2 controls the FPGA2 to forcibly select the merging unit of busbar set A;

[0096] The FPGA1 and the FPGA2 synchronously receive data A from the merging unit of busbar set A and data B from the merging unit of busbar set B, and select to send data A.

[0097] The input module 1 and the input module 2 collect the input signals for forcibly selecting the merging unit of busbar set B. Then, the input module 1 controls the FPGA1 to forcibly select the merging unit of busbar set B, and the input module 2 controls the FPGA2 to forcibly select the merging unit of busbar set B;

[0098] The FPGA1 and the FPGA2 synchronously receive data A from the merging unit of busbar set A and data B from the merging unit of busbar set B, and select to send data B.

[0099] The DSP1 receives data A and data B through the FPGA1, and simultaneously receives the processed data C1 from the FPGA1; the DSP2 receives data A and data B through the FPGA2, and simultaneously receives the processed data C2 from the FPGA2.

[0100] The data C1 and the data C2 are determined according to the automatic switching logic or the forced selection mode;

[0101] If the data C1 and the data C2 are data A, the DSP1 checks the received data C1 against the data A. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally; if they are inconsistent, the signal SEL1 of the FPGA1 is set to 0, and the switching system 1 issues an alarm and blocks the transmission;

[0102] The DSP2 checks the received data C2 against the data A. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally; if they are inconsistent, the signal SEL1 of the FPGA2 is set to 0, and the switching system 2 issues an alarm and blocks the transmission;

[0103] If the data C1 and the data C2 are the data B, the DSP1 checks the received data C1 against the data B. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally. If they are inconsistent, the signal SEL1 of the FPGA1 is set to 0, and the switching system 1 issues an alarm and locks the transmission.

[0104] The DSP2 checks the received data C2 against the data B. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally. If they are inconsistent, the signal SEL1 of the FPGA2 is set to 0, and the switching system 2 issues an alarm and locks the transmission.

[0105] The output logic performs the execution output according to the signal SEL1 and the signal SEL2, as shown in Table 2 specifically:

[0106] When the signal SEL1 is set to 1 and the signal SEL2 is set to 1, the MUX selects the data C1 sent by the FPGA1 for output;

[0107] When the signal SEL1 is set to 1 and the signal SEL2 is set to 0, the MUX selects the data C1 sent by the FPGA1 for output;

[0108] When the signal SEL1 is set to 0 and the signal SEL2 is set to 1, the MUX selects the data C2 sent by the FPGA2 for output;

[0109] When the signal SEL1 is set to 0 and the signal SEL2 is set to 0, the MUX does not output.

[0110] Embodiment 2

[0111] An automatic switching device for a merging unit of an adaptive dual-redundancy system, as Figure 3 shown, has two independent switching systems; the device has an independent dualized power supply system, and the two do not affect each other; the device is provided with a dualized input module, and the input module can receive input signals; the MUX is powered by an independent dualized power supply system.

[0112] The two switching systems respectively output monitoring signals for the merging unit of busbar set A and the merging unit of busbar set B through GOOSE. If an abnormal situation occurs, it can promptly notify the operation and maintenance for handling;

[0113] The two switching systems receive input signals through the CAN bus, and the input signals are collected and received by the input module. When any one of the input modules is abnormal, it does not affect the other input module's collection and reception of the input signals;

[0114] The device is provided with a dual - power supply system to independently supply power to the two sets of switching systems, and the overall function of the device is not affected when any one set of power supply is cut off.

[0115] The MUX is powered by the dual - power supply system, and the MUX function is not affected when any one set of the switching systems is cut off.

[0116] The device adaptively supports the IEC60044 - 8 and IEC61850 - 9 - 2 protocol - cascaded bus voltage data types by configuring the cascaded bus voltage protocol with fixed values, that is, the formats of the data A and the data B are IEC60044 - 8 or IEC61850 - 9 - 2.

[0117] When the voltage channel sequences of the A - set bus merging unit and the B - set bus merging unit of the device are inconsistent, the voltage channel sequence is configured through the human - machine interface. When the A - set bus merging unit is abnormal, after the device switches to the B - set bus merging unit, it can quickly and automatically match the voltage data channel sequences of the A / B - set bus merging units.

[0118] The device has a non - delay forwarding function, and the time from receiving the data A and the data B by the device to sending the logically selected data from the optical port of the device can be ignored.

[0119] Embodiment III

[0120] An automatic switching method for a merging unit of an adaptive dual - redundant system, comprising the following steps:

[0121] Step 1: The switching system 1 and the switching system 2 simultaneously receive the data A sent by the A - set bus merging unit and the data B sent by the B - set bus merging unit.

[0122] Step 2: The FPGA1 processes the data A and the data B to obtain data C1, and sends it to the MUX and the DSP1; the FPGA2 processes the data SV1 and the data SV2 to obtain data C2, and sends it to the MUX and the DSP2.

[0123] Step 3: The MUX outputs the corresponding data C1 or data C2 to each sending optical port according to the output logic.

[0124] Specifically, the specific steps of the processing in the step 2 are as Figure 4 shown:

[0125] Step 2.1: The device determines the modes of the FPGA1 and the FPGA2; there are two selection modes for the FPGA1 and the FPGA2, namely, the automatic selection mode and the forced selection mode

[0126] Step 2.2: In the automatic selection mode, the FPGA1 and the FPGA2 are selected according to the automatic switching logic;

[0127] Step 2.3: In the forced selection mode, the FPGA1 and the FPGA2 select the bus merging units in the corresponding forced modes.

[0128] The automatic switching logic in the said Step 2.2 is shown in Table 1:

[0129] When the data A is normal and the data B is normal, the FPGA1 and the FPGA2 select the data A;

[0130] When the data A is normal and the data B is abnormal, the FPGA1 and the FPGA2 select the data A;

[0131] When the data A is abnormal and the data B is normal, the FPGA1 and the FPGA2 select the data B;

[0132] When the data A is abnormal and the data B is abnormal, the FPGA1 and the FPGA2 maintain the current selection state.

[0133] In the forced selection mode of the said Step 2.3, there are forced selections of the set A bus merging unit and the set B bus merging unit;

[0134] When the FPGA1 and the FPGA2 are in the forced selection of the set A of the bus merging unit, the FPGA1 and the FPGA2 select the data A;

[0135] When the FPGA1 and the FPGA2 are in the forced selection of the set B of the bus merging unit, the FPGA1 and the FPGA2 select the data B.

[0136] In the said Step 2, the DSP1 receives the data A and the data B through the FPGA1, and at the same time receives the data C1 processed by the FPGA1; the DSP2 receives the data A and the data B through the FPGA2, and at the same time receives the data C2 processed by the FPGA2;

[0137] The data C1 and the data C2 are determined according to the automatic switching logic or the forced selection mode. If the data C1 and the data C2 are the data A, the DSP1 checks the received data C1 against the data A. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally. If they are inconsistent, the signal SEL1 of the FPGA1 is set to 0, and the switching system 1 issues an alarm and locks the transmission.

[0138] The DSP2 checks the received data C2 against the data A. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally. If they are inconsistent, the signal SEL1 of the FPGA2 is set to 0, and the switching system 2 issues an alarm and locks the transmission.

[0139] If the data C1 and the data C2 are the data B, the DSP1 checks the received data C1 against the data B. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally. If they are inconsistent, the signal SEL1 of the FPGA1 is set to 0, and the switching system 1 issues an alarm and locks the transmission.

[0140] The DSP2 checks the received data C2 against the data B. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally. If they are inconsistent, the signal SEL1 of the FPGA2 is set to 0, and the switching system 2 issues an alarm and locks the transmission.

[0141] The specific method of the output logic in step 3 is shown in Table 2:

[0142] When the signal SEL1 is set to 1 and the signal SEL2 is set to 1, the MUX selects the data C1 sent by the FPGA1 for output.

[0143] When the signal SEL1 is set to 1 and the signal SEL2 is set to 0, the MUX selects the data C1 sent by the FPGA1 for output.

[0144] When the signal SEL1 is set to 0 and the signal SEL2 is set to 1, the MUX selects the data C2 sent by the FPGA1 for output.

[0145] When the signal SEL1 is set to 0 and the signal SEL2 is set to 0, the MUX does not output.

[0146] Those of ordinary skill in the art can realize that the units of each example described in combination with the embodiments disclosed in this embodiment can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0147] In the embodiments provided in this application, it should be understood that the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units can be combined into one unit, one unit can be split into multiple units, or some features can be ignored, etc.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered by the scope of the claims and the description of the present invention.

Claims

1. An automatic switching device for a merging unit of an adaptive dual-redundancy system, comprising a switching system 1, a switching system 2, and a MUX; The switching system 1 includes an FPGA1, a DSP1, an input module 1, and a power supply 1; The switching system 2 includes an FPGA2, a DSP2, an input module 2, and a power supply 2; The MUX is a hardware selector that selects and sends the received data.

2. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 1, characterized in that, The power supply 1 supplies power to the FPGA1, the DSP1, the input module 1, and the MUX; the power supply 2 supplies power to the FPGA2, the DSP2, the input module 2, and the MUX.

3. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 1, characterized in that, The input module 1 and the input module 2 collect the same set of input signals; the input signals include automatic selection input and forced selection input; the forced selection input includes forced selection input for the merging unit of bus set A and forced selection input for the merging unit of bus set B.

4. The merging unit automatic switching device of the adaptive dual-redundancy system according to claim 1, characterized in that: The FPGA1 and the FPGA2 have two selection modes, namely, automatic selection mode and forced selection mode; the forced selection mode includes forced selection of the merging unit of bus set A and forced selection of the merging unit of bus set B.

5. The automatic switching device of the merging unit of an adaptive dual-redundancy system according to claim 1, characterized in that, The input module 1 controls the FPGA1 to enter the corresponding selection mode; the input module 2 controls the FPGA2 to enter the corresponding selection mode.

6. The automatic switching device of the merging unit of an adaptive dual-redundancy system according to claim 1, characterized in that The switching system 1 and the switching system 2 simultaneously receive data A sent by the merging unit of bus set A and data B sent by the merging unit of bus set B; The FPGA1 processes the data A and the data B to obtain data C1, and sends it to the MUX and the DSP1; The FPGA2 processes the data SV1 and the data SV2 to obtain data C2, and sends it to the MUX and the DSP2; The MUX outputs the corresponding data C1 or data C2 to each transmitting optical port according to the output logic.

7. The automatic switching device of the merging unit of an adaptive dual-redundancy system according to claim 6, characterized in that, For the processing, specifically judge the modes of the FPGA1 and the FPGA2. If it is the automatic selection mode, the FPGA1 and the FPGA2 select data according to the automatic switching logic; if it is the forced selection mode, the FPGA1 and the FPGA2 select the data of the bus merging unit in the corresponding forced mode. The automatic switching logic is that when both the data A and the data B are normal, the FPGA1 and the FPGA2 select the data A; When the data A is normal and the data B is abnormal, the FPGA1 and the FPGA2 select the data A; When the data A is abnormal and the data B is normal, the FPGA1 and the FPGA2 select the data B; when both the data A and the data B are abnormal, the FPGA1 and the FPGA2 maintain the current selection state.

8. The automatic switching device for the merging unit of an adaptive dual-redundancy system according to claim 6, characterized in that, The DSP1 receives the data A and the data B through the FPGA1, and simultaneously receives the data C1 processed by the FPGA1; the DSP2 receives the data A and the data B through the FPGA2, and simultaneously receives the data C2 processed by the FPGA2.

9. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 8, characterized in that, The data C1 and the data C2 are determined according to the automatic switching logic or the forced selection mode. If the data C1 and the data C2 are the data A, the DSP1 checks the received data C1 against the data A. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally; otherwise, it is set to 0, and the switching system 1 issues an alarm and locks the transmission. The DSP2 checks the received data C2 against the data A. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally; otherwise, it is set to 0, and the switching system 2 issues an alarm and locks the transmission. If the data C1 and the data C2 are the data B, the DSP1 checks the received data C1 against the data B. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally; otherwise, it is set to 0, and the switching system 1 issues an alarm and locks the transmission. The DSP2 checks the received data C2 against the data B. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally; otherwise, it is set to 0, and the switching system 2 issues an alarm and locks the transmission.

10. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 6, characterized in that, The output logic is selected according to the signal SEL1 and the signal SEL2. When the signal SEL1 is set to 1 and the signal SEL2 is set to 1, the MUX selects the data C1 sent by the FPGA1 for output. When the signal SEL1 is set to 1 and the signal SEL2 is set to 0, the MUX selects the data C1 sent by the FPGA1 for output. When the signal SEL1 is set to 0 and the signal SEL2 is set to 1, the MUX selects the data C2 sent by the FPGA1 for output. When the signal SEL1 is set to 0 and the signal SEL2 is set to 0, the MUX does not output.

11. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 2, characterized in that, The device has two independent switching systems. The device is equipped with an independent dualized power supply system, and the two do not affect each other. The device is provided with a dualized input module, and the input module can receive input signals. The MUX is powered by an independent dualized power supply system.

12. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 11, characterized in that, The two switching systems respectively output monitoring signals for the A set of bus coupler units and the B set of bus coupler units through GOOSE. If an abnormal situation occurs, it can notify the operation and maintenance in time for processing. The two switching systems receive input signals through the CAN bus. The input signals are collected and received by the input module. When any one of the input modules is abnormal, it does not affect the other input module's collection and reception of the input signals. The device is provided with a dual power supply system to independently supply power to the two switching systems. When any one set of power is cut off, it does not affect the overall function of the device. The MUX is powered by the dual power supply system. When any one set of the switching systems is powered off, it does not affect the MUX function.

13. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 1, characterized in that, The device adaptively supports the cascaded bus voltage data types of IEC60044-8 and IEC61850-9-2 protocols by configuring the cascaded bus voltage protocol with fixed values, that is, the formats of the data A and the data B are IEC60044-8 or IEC61850-9-2.

14. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 1, characterized in that, When the voltage channel sequences of the A set of bus merging units and the B set of bus merging units of the device are inconsistent, the voltage channel sequence is configured through the human-machine interface. When the A set of bus merging units is abnormal, the device can quickly and automatically match the voltage data channel sequences of the A / B set of bus merging units after switching to the B set of bus merging units.

15. The merging unit automatic switching device of an adaptive dual-redundancy system according to claim 1, characterized in that, The device has a function of forwarding without delay, and the time from the device receiving the data A and the data B to the device sending the logically selected data from the optical port can be ignored.

16. A method for automatically switching a merging unit of an adaptive dual-redundancy system, comprising the following steps: Step 1: The switching system 1 and the switching system 2 simultaneously receive the data A sent by the A set of bus merging units and the data B sent by the B set of bus merging units. Step 2: The FPGA1 processes the data A and the data B to obtain data C1, and sends it to the MUX and the DSP1; the FPGA2 processes the data SV1 and the data SV2 to obtain data C2, and sends it to the MUX and the DSP2. Step 3: The MUX outputs the corresponding data C1 or data C2 to each sending optical port according to the output logic.

17. The automatic switching method of the merging unit of an adaptive dual-redundancy system according to claim 16, characterized in that The specific steps of the processing in the step 2 are as follows: Step 2.1: The device judges the modes of the FPGA1 and the FPGA2; the FPGA1 and the FPGA2 have two selection modes, namely the automatic selection mode and the forced selection mode. Step 2.2: In the automatic selection mode, the FPGA1 and the FPGA2 follow the automatic switching logic for selection. Step 2.3: In the forced selection mode, the FPGA1 and the FPGA2 select the data of the bus merging unit selected in the corresponding forced mode.

18. The method for automatic switching of merging units in an adaptive dual-redundancy system according to claim 17, wherein: The specific manner of the automatic switching logic in the step 2.2 is as follows: When the data A is normal and the data B is normal, the FPGA1 and the FPGA2 select the data A. When the data A is normal and the data B is abnormal, the FPGA1 and the FPGA2 select the data A. When the data A is abnormal and the data B is normal, the FPGA1 and the FPGA2 select the data B. When both the data A and the data B are abnormal, the FPGA1 and the FPGA2 maintain the current selection state.

19. The automatic switching method of the merging unit of an adaptive dual-redundancy system according to claim 17, characterized in that, In the forced selection mode of the step 2.3, there are forced selections of the A set of bus merging units and the B set of bus merging units. When the FPGA1 and the FPGA2 are in the forced selection of the A set of bus merging units, the FPGA1 and the FPGA2 select the data A. When the FPGA1 and the FPGA2 are in the state of forcibly selecting the bus merging unit B set, the FPGA1 and the FPGA2 select the data B.

20. The automatic switching method of the merging unit of an adaptive dual-redundancy system according to claim 16, characterized in that, In step 2, the DSP1 receives the data A and the data B through the FPGA1, and simultaneously receives the data C1 processed by the FPGA1; the DSP2 receives the data A and the data B through the FPGA2, and simultaneously receives the data C2 processed by the FPGA2; The data C1 and the data C2 are determined according to the automatic switching logic or the forced selection mode. If the data C1 and the data C2 are the data A, the DSP1 verifies the received data C1 and the data A. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally; otherwise, it is set to 0, and the switching system 1 issues an alarm and blocks transmission. The DSP2 verifies the received data C2 and the data A. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally; otherwise, it is set to 0, and the switching system 2 issues an alarm and blocks transmission. If the data C1 and the data C2 are the data B, the DSP1 verifies the received data C1 and the data B. If they are consistent, the signal SEL1 of the FPGA1 is set to 1, and the switching system 1 operates normally; otherwise, it is set to 0, and the switching system 1 issues an alarm and blocks transmission. The DSP2 verifies the received data C2 and the data B. If they are consistent, the signal SEL2 of the FPGA2 is set to 1, and the switching system 2 operates normally; otherwise, it is set to 0, and the switching system 2 issues an alarm and blocks transmission.

21. The method for automatic switching of merging units in an adaptive redundant system according to claim 16, wherein: The output logic in step 3 is as follows: When the signal SEL1 is set to 1 and the signal SEL2 is set to 1, the MUX selects the data C1 sent by the FPGA1 for output; When the signal SEL1 is set to 1 and the signal SEL2 is set to 0, the MUX selects the data C1 sent by the FPGA1 for output; When the signal SEL1 is set to 0 and the signal SEL2 is set to 1, the MUX selects the data C2 sent by the FPGA1 for output; When the signal SEL1 is set to 0 and the signal SEL2 is set to 0, the MUX does not output.

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